Dell Inspiron 7380 Schematic

5

4

3

2

1

D

KR CS MLK 13" Schematics Whiskey Lake-U

C

2018-07-19 REV : A00

C

B

A

DY : None Installed UMA: UMA only installed

5

4

B

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page

Size Document Number Rev

A4

Thursday, July 19, 2018

Date: Sheet

3

2

Cover Page

KR CS MLK 13"

1 106

of

1 106

of

1 106

of

1

A00

A

5

Project code: 4PD0EZ010001???

4

3

2

1

D

DDR4 X16 Memory Down

HDMI CONN.

C

B

12

HDMI2.0

WHL-U 13" CPU 15W Block Diagram

1Rx16

1Rx16 Channel B

USB2.0 LANE5

Intel CPU

Whiskey Lake U 15W (UMA) WHL PCH-LP

10 USB 2.0/1.1 ports 6 USB 3.0 ports High Definition Audio 3 SATA ports 6 PCIE ports LPC I/F ACPI 5.0

DP

USB3.0

USB3.0 LANE4

USB2.0

USB2.0 LANE4

PCIE

USB2.0

USB2.0 LANE7

USB3.0

USB3.0 LANE1

USB2.0

USB2.0 LANE1

HDA

MUX and Redriver

TUSB546

I2C1

DDR4 X16 Memory Down

13.3" FHD

Touch panel

LPSCON

PS175HDM

M.2 SSD

Finger Printer

LID SENSOR

ALPS HGDEDM013A

USB 3.0 CONN. Type-A

eSPI debug port

Channel A

13

eDP

55

I2C

DDI1

57

63

92

PCIE/SATA

USB2.0

I2C

70

USB3.0

USB3.0 LANE2

USB2.0 LANE2

USB2.0

eSPI

35

68

PCB P/N: 17945 Revision: SA

DP/USB 3.0

71

PD

TI TPS65982DC

NGFF WLAN

CardReader SD 3.0

Realtak RTS5176E

USB 3.0 re-driver

Parade PS8713B

HDA CODEC

Realtek ALC3254

CC1/CC2

SMBUS

USB 2.0

USB3.0

MIC_IN/AGND

HP_R/L

27

USB3.0 Type-C Port1

IO Board

Micro SD Card Slot

USB3.0 CONN.

Type-A

Universal Jack

2CH SPEAKER (2CH 2W/4ohm)

D

7372

LPS

C

B

Thermal

NUVOTON NCT7718W

A

Fan Control

PWM

26

SMBUS

FAN DETECT

KBC

KB SCAN INTERFACE

Int.

FAN

5

KB

MICROCHIP MEC1416

Touch PAD

Image sensor

PS2

4

USB2.0 x 1

USB2.0 LANE6

24

SPI

I2C

Flash ROM

16MB Quad Read

3

25

TPM

NUVOTON NPCT750

91

Camera (HD) D-MIC

2

55

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Block Diagram

KR CS MLK 13"

1

of

2 106Thursday, July 19, 2018

of

2 106Thursday, July 19, 2018

of

2 106Thursday, July 19, 2018

A00

A

5

4

3

2

1

SSID = CPU

PECI_CPU[24]

PROCHOT#_CPU[24,44,46]

D

C

TP_WAKE_KBC#[24,65]

H_CPUPWRGD[17]

TOUCH_PANEL_INTR#[55]

TOUCH_PANEL_PD#[55]

(#543016) PROCHOT# Routing Guidelines

1V_VCCSTG

Rb

PROCHOT#_CPU

[PECI] and [PROCHOT#] Impedance control: 50 ohm

3D3V_S5_PCH

1

R303 Do Not Stuff

DY

TP_WAKE_KBC#

2

1

R301 1KR2J-1-GP

2

R302 499R2F-2-GP

Ra

1

R304 49D9R2F-GP

R305 49D9R2F-GP

2

TP309Do Not Stuff

TP302Do Not Stuff

TP303Do Not Stuff

TP304Do Not Stuff

TP307Do Not Stuff

TP308Do Not Stuff

1

2

TP301 Do Not Stuff

1

CATERR#_CPU

PECI_CPU

PROCHOT#_CPU_R

THERMTRIP#_CPU

BPM_CPU_N0

BPM_CPU_N1

BPM_CPU_N2

BPM_CPU_N3

GPP_E3/CPU_GP0

TOUCH_PANEL_INTR#

TOUCH_PANEL_PD#

CPU_POPIRCOMP

PCH_POPIRCOMP

20180412 Follow RO

XDP_TDO_CPU

XDP_TCLK

CPU1D

AA4

CATERR#

AR1

PECI

Y4

PROCHOT#

BJ1

THRMTRIP#

U1

BPM#0

U2

BPM#1

U3

BPM#2

U4

BPM#3

CE9

GPP_E3/CPU_GP0

CN3

GPP_E7/CPU_GP1

CB34

GPP_B3/CPU_GP2

CC35

GPP_B4/CPU_GP3

BP27

PROC_POPIRCOMP

BW25

PCH_OPIRCOMP

WHISKEY-LAKE-GP

1

R310 51R2J-2-GP

1

R317 51R2J-2-GP

2

PROC_PREQ#

PROC_PRDY#

1V_VCCSTG

4 OF 20

PROC_TCK

PROC_TDI

PROC_TDO

PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

PCH_TRST#

PCH_JTAGX

20180412 Follow RO13

T6

U6

Y5

T5

AB6

W6

U5

W5

P5

Y6

P6

XDP_PREQ#

W2

XDP_PRDY#

W1

XDP_TCLK

XDP_TDI

XDP_TDO_CPU

XDP_TMS

XDP_TRST#

PCH_JTAG_TCK

1V_VCCST_CPU

#544669 CRB Rev0.52

1

R308 1KR2J-1-GP

1

TP311 Do Not Stuff

1

TP313 Do Not Stuff

1

TP314 Do Not Stuff

1

TP315 Do Not Stuff

1

TP305 Do Not Stuff

1

TP306 Do Not Stuff

D

C

B

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 inches Mt <0.3 mils

A

Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

5

THERMTRIP#_CPU

H_CPUPWRGD

Title

Size Document Number Rev

A4

Date: Sheet

4

3

Date: Sheet

(Reserved)

2

KR CS MLK 13"

2

RO13_20171001

1

2

ED301

DY

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Do Not Stuff

3 106Thursday, July 19, 2018

of

3 106Thursday, July 19, 2018

of

3 106Thursday, July 19, 2018

of

1

A00

B

A

5

4

3

2

1

SSID = CPU

DP to HDMI2.0

HDMI_DDI_TX_N0[57]

HDMI_DDI_TX_P0[57]

HDMI_DDI_TX_N1[57]

HDMI_DDI_TX_P1[57]

D

HDMI_DDI_TX_N2[57]

HDMI_DDI_TX_P2[57]

HDMI_DDI_TX_N3[57]

HDMI_DDI_TX_P3[57]

DP1_AUX_CPU_N[57]

DP1_AUX_CPU_P[57]

HDMI_HPD_CPU[57]

DP for Type-C Mux

DP2_DDI_TX_N0[71]

DP2_DDI_TX_P0[71]

DP2_DDI_TX_N1[71]

DP2_DDI_TX_P1[71]

DP2_DDI_TX_N2[71]

C

DP2_DDI_TX_P2[71]

DP2_DDI_TX_N3[71]

DP2_DDI_TX_P3[71]

DP2_AUX_CPU_N[71]

DP2_AUX_CPU_P[71]

eDP_TX_CPU_N0[55]

eDP_TX_CPU_P0[55]

eDP_TX_CPU_N1[55]

eDP_TX_CPU_P1[55]

eDP_TX_CPU_N2[55]

eDP_TX_CPU_P2[55]

eDP_TX_CPU_N3[55]

eDP_TX_CPU_P3[55]

eDP_AUX_CPU_N[55]

eDP_AUX_CPU_P[55]

B

eDP_HPD_CPU[55]

DP1_HPD_CPU[71,72]

L_BKLT_EN[24]

L_BKLT_CTRL[55]

EDP_VDD_EN[55]

GPP_H17_STRAP[15]

3D3V_S0

RN401

1

2

SRN2K2J-1-GP

RN403

1

2

SRN2K2J-1-GP

1

R402 10KR2J-3-GP

Add RTC Gen 9 reset circuit_20170814 leakage issue

3D3V_S5_PCH

1

R406 10KR2J-3-GP

RTC_RST

2

CPU_DP_HPD_P

PCH side Device side

DP1_HPD_CPU_R

CPU_DP1_CTRL_DATA

4

CPU_DP1_CTRL_CLK

3

CPU_DP2_CTRL_CLK

4

CPU_DP2_CTRL_DATA

3

SIO_EXT_SMI#

2

Q401

1

2

RTC_RST

3

2N7002KDW-1-GP

75.27002.F7C

20170814 RTC Gen 9 reset circuit

NON_RTC_RST

1

R404 Do Not Stuff

1

R403 100KR2J-1-GP

2

3D3V_S5_PCH

Note:ZZ.27002.F7C01

6

5

4

2

1

R405 10KR2J-3-GP

RTC_RST

2

DP1_HPD_CPU_R

DP1_HPD_CPU

DP to HDMI2.0

DP for Type-C Mux

1V_VCCIO

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

PU to 3.3 V with 2.2-k ±5% resistor

NC

HDMI_DDI_TX_N0

HDMI_DDI_TX_P0

HDMI_DDI_TX_N1

HDMI_DDI_TX_P1

HDMI_DDI_TX_N2

HDMI_DDI_TX_P2

HDMI_DDI_TX_N3

HDMI_DDI_TX_P3

DP2_DDI_TX_N0

DP2_DDI_TX_P0

DP2_DDI_TX_N1

DP2_DDI_TX_P1

DP2_DDI_TX_N2

DP2_DDI_TX_P2

DP2_DDI_TX_N3

DP2_DDI_TX_P3

CHECK WHL design guide: DISP_RCOMP

Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

eDP_RCOMP_CPU

2

1

R401 24D9R2F-L-GP

TP402 Do Not Stuff

1

CPU_DP1_CTRL_CLK

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK

CPU_DP2_CTRL_DATA

GPP_E23_STRAP

GPP_H17_STRAP

AL5

DDI1_TXN0

AL6

DDI1_TXP0

AJ5

DDI1_TXN1

AJ6

DDI1_TXP1

AF6

DDI1_TXN2

AF5

DDI1_TXP2

AE5

DDI1_TXN3

AE6

DDI1_TXP3

AC4

DDI2_TXN0

AC3

DDI2_TXP0

AC1

DDI2_TXN1

AC2

DDI2_TXP1

AE4

DDI2_TXN2

AE3

DDI2_TXP2

AE1

DDI2_TXN3

AE2

DDI2_TXP3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHISKEY-LAKE-GP

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

Isolation Spacing

1 OF 20CPU1A

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_TXN2

EDP_TXP2

EDP_TXN3

EDP_TXP3

EDP_AUX_N

EDP_AUX_P

DISP_UTILS

DDI1_AUX_N

DDI1_AUX_P

DDI2_AUX_N

DDI2_AUX_P

DDI3_AUX_N

DDI3_AUX_P

GPP_E13/DDPB_HPD0/DISP_MISC0

GPP_E14/DDPC_HPD1/DISP_MISC1

GPP_E15/DPPD_HPD2/DISP_MISC2

GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

Resistor Value

Length

Max = 100 mils

AG4

AG3

AG2

AG1

AJ4

AJ3

AJ2

AJ1

AH4

AH3

AM7

AC7

AC6

AD4

AD3

AG7

AG6

CN6

CM6

CP7

CP6

CM7

CK11

CG11

CH11

eDP_TX_CPU_N0

eDP_TX_CPU_P0

eDP_TX_CPU_N1

eDP_TX_CPU_P1

eDP_TX_CPU_N2

eDP_TX_CPU_P2

eDP_TX_CPU_N3

eDP_TX_CPU_P3

eDP_AUX_CPU_N

eDP_AUX_CPU_P

DP1_AUX_CPU_N

DP1_AUX_CPU_P

DP2_AUX_CPU_N

DP2_AUX_CPU_P

HDMI_HPD_CPU

DP1_HPD_CPU_R

SIO_EXT_SMI#

eDP_HPD_CPU

L_BKLT_EN

EDP_VDD_EN

L_BKLT_CTRL

20180208 Follow RO NC

for HDMI2.0

for Type-C Mux

D

C

B

A00

A

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

CPU_(JTAG/CPU SIDE BAND)

Custom

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

KR CS MLK 13"

4 106Thursday, July 19, 2018

1

of

SSID = CPU

M_A_DQS_DN[7: 0][12]

M_A_DQS_DP[7:0][12]

D

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[16:23]

M_A_DQ[24:31]

C

M_A_DQ[32:39]

M_A_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_CLK#0[13]

M_B_CLK0[13]

M_B_CKE0[13]

M_B_CS#0[13]

M_B_ODT0[13]

B

M_B_ACT_N[13]

M_B_BG0[13]

M_B_BG1[13]

M_B_BA0[13]

M_B_BA1[13]

M_B_ALERT_N[13]

M_B_PARITY[13]

V_SM_VREF_CN TA[12]

V_SM_VREF_CN TB[13]

VTT_CNTL[51]

SM_DRAMRST #[12,13]

1D2V_S3

1

R505 470R2F-GP

2

1

R504 Do Not Stuff

D

C

SM_DRAMRST #

2

1

C501

DY

Do Not Stuff

2

B

2

CPU1C

DDR1_DQ0/DDR0_DQ16

DDR1_DQ1/DDR0_DQ17

DDR1_DQ2/DDR0_DQ18

DDR1_DQ3/DDR0_DQ19

DDR1_DQ4/DDR0_DQ20

DDR1_DQ5/DDR0_DQ21

DDR1_DQ6/DDR0_DQ22

DDR1_DQ7/DDR0_DQ23

DDR1_DQ8/DDR0_DQ24

DDR1_DQ9/DDR0_DQ25

DDR1_DQ10/DDR0_DQ26

DDR1_DQ11/DDR0_DQ27

DDR1_DQ12/DDR0_DQ28

DDR1_DQ13/DDR0_DQ29

DDR1_DQ14/DDR0_DQ30

DDR1_DQ15/DDR0_DQ31

DDR1_DQ16/DDR0_DQ48

DDR1_DQ17/DDR0_DQ49

DDR1_DQ18/DDR0_DQ50

DDR1_DQ19/DDR0_DQ51

DDR1_DQ20/DDR0_DQ52

DDR1_DQ21/DDR0_DQ53

DDR1_DQ22/DDR0_DQ54

DDR1_DQ23/DDR0_DQ55

DDR1_DQ24/DDR0_DQ56

DDR1_DQ25/DDR0_DQ57

DDR1_DQ26/DDR0_DQ58

DDR1_DQ27/DDR0_DQ59

DDR1_DQ28/DDR0_DQ60

DDR1_DQ29/DDR0_DQ61

DDR1_DQ30/DDR0_DQ62

DDR1_DQ31/DDR0_DQ63

DDR1_DQ32/DDR1_DQ16

DDR1_DQ33/DDR1_DQ17

DDR1_DQ34/DDR1_DQ18

DDR1_DQ35/DDR1_DQ19

DDR1_DQ36/DDR1_DQ20

DDR1_DQ37/DDR1_DQ21

DDR1_DQ38/DDR1_DQ22

DDR1_DQ39/DDR1_DQ23

DDR1_DQ40/DDR1_DQ24

DDR1_DQ41/DDR1_DQ25

DDR1_DQ42/DDR1_DQ26

DDR1_DQ43/DDR1_DQ27

DDR1_DQ44/DDR1_DQ28

DDR1_DQ45/DDR1_DQ29

DDR1_DQ46/DDR1_DQ30

DDR1_DQ47/DDR1_DQ31

DDR1_DQ48/DDR1_DQ48

DDR1_DQ49/DDR1_DQ49

DDR1_DQ50/DDR1_DQ50

DDR1_DQ51/DDR1_DQ51

DDR1_DQ52/DDR1_DQ52

DDR1_DQ53/DDR1_DQ53

DDR1_DQ54/DDR1_DQ54

DDR1_DQ55/DDR1_DQ55

DDR1_DQ56/DDR1_DQ56

DDR1_DQ57/DDR1_DQ57

DDR1_DQ58/DDR1_DQ58

DDR1_DQ59/DDR1_DQ59

DDR1_DQ60/DDR1_DQ60

DDR1_DQ61/DDR1_DQ61

DDR1_DQ62/DDR1_DQ62

DDR1_DQ63/DDR1_DQ63

WHISKEY-LAKE- GP

20180409 Follow RO13

SM_PGCNTL

3 OF 20

DDR1_CKN0/DDR1_CKN0

DDR1_CKP0/DDR1_CKP0

DDR1_CKN1/DDR1_CKN1

DDR1_CKP1/DDR1_CKP1

DDR1_CKE0/DDR1_CKE0

DDR1_CKE1/DDR1_CKE1

DDR1_CKE2/NC

DDR1_CKE3/NC

DDR1_CS#0/DDR1_CS#0

DDR1_CS#1/DDR1_CS#1

DDR1_ODT0/DDR1_ODT0

NC/DDR1_ODT1

DDR1_CAB9/DDR1_MA0

DDR1_CAB8/DDR1_MA1

DDR1_CAB5/DDR1_MA2

NC/DDR1_MA3

NC/DDR1_MA4

DDR1_CAA0/DDR1_MA5

DDR1_CAA2/DDR1_MA6

DDR1_CAA4/DDR1_MA7

DDR1_CAA3/DDR1_MA8

DDR1_CAA1/DDR1_MA9

DDR1_CAB7/DDR1_MA10

DDR1_CAA7/DDR1_MA11

DDR1_CAA6/DDR1_MA12

DDR1_CAB0/DDR1_MA13

DDR1_CAB2/DDR1_MA14

DDR1_CAB1/DDR1_MA15

DDR1_CAB3/DDR1_MA16

DDR1_CAB4/DDR1_BA0

DDR1_CAB6/DDR1_BA1

DDR1_CAA5/DDR1_BG0

DDR1_CAA9/DDR1_BG1

DDR1_CAA8/DDR1_ACT#

DDR1_DQSN0/DDR0_DQSN2

DDR1_DQSP0/DDR0_DQSP2

DDR1_DQSN1/DDR0_DQSN3

DDR1_DQSP1/DDR0_DQSP3

DDR1_DQSN2/DDR0_DQSN6

DDR1_DQSP2/DDR0_DQSP6

DDR1_DQSN3/DDR0_DQSN7

DDR1_DQSP3/DDR0_DQSP7

DDR1_DQSN4/DDR1_DQSN2

DDR1_DQSP4/DDR1_DQSP2

DDR1_DQSN5/DDR1_DQSN3

DDR1_DQSP5/DDR1_DQSP3

DDR1_DQSN6/DDR1_DQSN6

DDR1_DQSP6/DDR1_DQSP6

DDR1_DQSN7/DDR1_DQSN7

DDR1_DQSP7/DDR1_DQSP7

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_RCOMP0

DDR_RCOMP1

DDR_RCOMP2

3D3V_S5

Q501

G

PJA138KA-GP

D

S

084.00138.0A31

M_B_CLK#0

AF28

M_B_CLK0

AF29

AE28

AE29

M_B_CKE0

T28

T29

V28

V29

M_B_CS#0

AL37

AL35

M_B_ODT0

AL36

AL34

M_B_A0

AG36

M_B_A1

AG35

M_B_A2

AF34

M_B_A3

AG37

M_B_A4

AE35

M_B_A5

AF35

M_B_A6

AE37

M_B_A7

AC29

M_B_A8

AE36

M_B_A9

AB29

M_B_A10

AG34

M_B_A11

AC28

M_B_A12

AB28

M_B_A13

AK35

M_B_A14

AJ35

M_B_A15

AK34

M_B_A16

AJ34

M_B_BA0

AJ37

M_B_BA1

AJ36

M_B_BG0

W29

M_B_BG1

Y28

M_B_ACT_N

W28

M_A_DQS_DN2

H24

M_A_DQS_DP2

G24

M_A_DQS_DN3

C23

M_A_DQS_DP3

D23

M_A_DQS_DN6

G30

M_A_DQS_DP6

H30

M_A_DQS_DN7

L30

M_A_DQS_DP7

N30

M_B_DQS_DN2

AL31

M_B_DQS_DP2

AL30

M_B_DQS_DN3

AU31

M_B_DQS_DP3

AU30

M_B_DQS_DN6

BC31

M_B_DQS_DP6

BC30

M_B_DQS_DN7

BH31

M_B_DQS_DP7

BH30

M_B_ALERT_N

Y29

M_B_PARITY

AE34

SM_DRAMRST #_CPU

BU31

SM_RCOMP_0

BN28

SM_RCOMP_1

BN27

SM_RCOMP_2

BN29

R501 (RO13)(20170911)(DEL: R507) DDP: 121 ohm (64.12105.6DL) SDP: 200 ohm (64.20005.6DL)

1

R506 10KR2F-2-DL- GP

Q502_G

Q502

G

S

Notice:ZZ.2N70 2.J3101

2N7002K-2-GP

84.2N702.J31

2

M_A_DQS2 M_A_DQS3 M_A_DQS6 M_A_DQS7 M_B_DQS2 M_B_DQS3 M_B_DQS6 M_B_DQS7

2

1

R501 121R2F-GP

DDP/SDP

2

1

R502 80D6R2F-L-G P

2

1

R503 100R2F-L1-GP- U

Layout Note:

#543016 Design Guideline: SM_RCOMP keep routing length less than 500 mils.

3D3V_S0

1

R507 10KR2F-2-DL- GP

2

VTT_CNTL

D

M_A_DQ0

M_A_DQ1

M_A_DQ2

M_A_DQ3

M_A_DQ4

M_A_DQ5

M_A_DQ6

M_A_DQ7

M_A_DQ8

M_A_DQ9

M_A_DQ10

M_A_DQ11

M_A_DQ12

M_A_DQ13

M_A_DQ14

M_A_DQ15

M_A_DQ32

M_A_DQ33

M_A_DQ34

M_A_DQ35

M_A_DQ36

M_A_DQ37

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_A_DQ41

M_A_DQ42

M_A_DQ43

M_A_DQ44

M_A_DQ45

M_A_DQ46

M_A_DQ47

M_B_DQ0

M_B_DQ1

M_B_DQ2

M_B_DQ3

M_B_DQ4

M_B_DQ5

M_B_DQ6

M_B_DQ7

M_B_DQ8

M_B_DQ9

M_B_DQ10

M_B_DQ11

M_B_DQ12

M_B_DQ13

M_B_DQ14

M_B_DQ15

M_B_DQ32

M_B_DQ33

M_B_DQ34

M_B_DQ35

M_B_DQ36

M_B_DQ37

M_B_DQ38

M_B_DQ39

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ43

M_B_DQ44

M_B_DQ45

M_B_DQ46

M_B_DQ47

4

CPU1B

A26

DDR0_DQ0/DDR0_DQ0

D26

DDR0_DQ1/DDR0_DQ1

D28

DDR0_DQ2/DDR0_DQ2

C28

DDR0_DQ3/DDR0_DQ3

B26

DDR0_DQ4/DDR0_DQ4

C26

DDR0_DQ5/DDR0_DQ5

B28

DDR0_DQ6/DDR0_DQ6

A28

DDR0_DQ7/DDR0_DQ7

B30

DDR0_DQ8/DDR0_DQ8

D30

DDR0_DQ9/DDR0_DQ9

B33

DDR0_DQ10/DDR0_DQ10

D32

DDR0_DQ11/DDR0_DQ11

A30

DDR0_DQ12/DDR0_DQ12

C30

DDR0_DQ13/DDR0_DQ13

B32

DDR0_DQ14/DDR0_DQ14

C32

DDR0_DQ15/DDR0_DQ15

H37

DDR0_DQ16/DDR0_DQ32

H34

DDR0_DQ17/DDR0_DQ33

K34

DDR0_DQ18/DDR0_DQ34

K35

DDR0_DQ19/DDR0_DQ35

H36

DDR0_DQ20/DDR0_DQ36

H35

DDR0_DQ21/DDR0_DQ37

K36

DDR0_DQ22/DDR0_DQ38

K37

DDR0_DQ23/DDR0_DQ39

N36

DDR0_DQ24/DDR0_DQ40

N34

DDR0_DQ25/DDR0_DQ41

R37

DDR0_DQ26/DDR0_DQ42

R34

DDR0_DQ27/DDR0_DQ43

N37

DDR0_DQ28/DDR0_DQ44

N35

DDR0_DQ29/DDR0_DQ45

R36

DDR0_DQ30/DDR0_DQ46

R35

DDR0_DQ31/DDR0_DQ47

AN35

DDR0_DQ32/DDR1_DQ0

AN34

DDR0_DQ33/DDR1_DQ1

AR35

DDR0_DQ34/DDR1_DQ2

AR34

DDR0_DQ35/DDR1_DQ3

AN37

DDR0_DQ36/DDR1_DQ4

AN36

DDR0_DQ37/DDR1_DQ5

AR36

DDR0_DQ38/DDR1_DQ6

AR37

DDR0_DQ39/DDR1_DQ7

AU35

DDR0_DQ40/DDR1_DQ8

AU34

DDR0_DQ41/DDR1_DQ9

AW35

DDR0_DQ42/DDR1_DQ10

AW34

DDR0_DQ43/DDR1_DQ11

AU37

DDR0_DQ44/DDR1_DQ12

AU36

DDR0_DQ45/DDR1_DQ13

AW36

DDR0_DQ46/DDR1_DQ14

AW37

DDR0_DQ47/DDR1_DQ15

BA35

DDR0_DQ48/DDR1_DQ32

BA34

DDR0_DQ49/DDR1_DQ33

BC35

DDR0_DQ50/DDR1_DQ34

BC34

DDR0_DQ51/DDR1_DQ35

BA37

DDR0_DQ52/DDR1_DQ36

BA36

DDR0_DQ53/DDR1_DQ37

BC36

DDR0_DQ54/DDR1_DQ38

BC37

DDR0_DQ55/DDR1_DQ39

BE35

DDR0_DQ56/DDR1_DQ40

BE34

DDR0_DQ57/DDR1_DQ41

BG35

DDR0_DQ58/DDR1_DQ42

BG34

DDR0_DQ59/DDR1_DQ43

BE37

DDR0_DQ60/DDR1_DQ44

BE36

DDR0_DQ61/DDR1_DQ45

BG36

DDR0_DQ62/DDR1_DQ46

BG37

DDR0_DQ63/DDR1_DQ47

WHISKEY-LAKE- GP

DDR4 ball type: Non-Interleaved Type

2 OF 20

DDR0_CKE2/NC

DDR0_CKE3/NC

NC/DDR0_ODT1

NC/DDR0_MA3

NC/DDR0_MA4

NC/DDR0_PAR

DDR_VREF_CA

DDR_VTT_CTL

V32

V31

T32

T31

U36

U37

U34

U35

AE32

AF32

AE31

AF31

AC37

AC36

AC34

AC35

AA35

AB35

AA37

AA36

AB34

W36

Y31

W34

AA34

AC32

AC31

AB32

Y32

W32

AB31

V34

V35

W35

C27

D27

D31

C31

J35

J34

P34

P35

AP35

AP34

AV34

AV35

BB35

BB34

BF34

BF35

W37

W31

F36

D35

D37

E36

C35

DDR0_CKN0/DDR0_CKN0

DDR0_CKP0/DDR0_CKP0

DDR0_CKN1/DDR0_CKN1

DDR0_CKP1/DDR0_CKP1

DDR0_CKE0/DDR0_CKE0

DDR0_CKE1/DDR0_CKE1

DDR0_CS#0/DDR0_CS#0

DDR0_CS#1/DDR0_CS#1

DDR0_ODT0/DDR0_ODT0

DDR0_CAB9/DDR0_MA0

DDR0_CAB8/DDR0_MA1

DDR0_CAB5/DDR0_MA2

DDR0_CAA0/DDR0_MA5

DDR0_CAA2/DDR0_MA6

DDR0_CAA4/DDR0_MA7

DDR0_CAA3/DDR0_MA8

DDR0_CAA1/DDR0_MA9

DDR0_CAB7/DDR0_MA10

DDR0_CAA7/DDR0_MA11

DDR0_CAA6/DDR0_MA12

DDR0_CAB0/DDR0_MA13

DDR0_CAB2/DDR0_MA14

DDR0_CAB1/DDR0_MA15

DDR0_CAB3/DDR0_MA16

DDR0_CAB4/DDR0_BA0

DDR0_CAB6/DDR0_BA1

DDR0_CAA5/DDR0_BG0

DDR0_CAA8/DDR0_ACT#

DDR0_CAA9/DDR0_BG1

DDR0_DQSN0/DDR0_DQSN0

DDR0_DQSP0/DDR0_DQSP0

DDR0_DQSN1/DDR0_DQSN1

DDR0_DQSP1/DDR0_DQSP1

DDR0_DQSN2/DDR0_DQSN4

DDR0_DQSP2/DDR0_DQSP4

DDR0_DQSN3/DDR0_DQSN5

DDR0_DQSP3/DDR0_DQSP5

DDR0_DQSN4/DDR1_DQSN0

DDR0_DQSP4/DDR1_DQSP0

DDR0_DQSN5/DDR1_DQSN1

DDR0_DQSP5/DDR1_DQSP1

DDR0_DQSN6/DDR1_DQSN4

DDR0_DQSP6/DDR1_DQSP4

DDR0_DQSN7/DDR1_DQSN5

DDR0_DQSP7/DDR1_DQSP5

NC/DDR0_ALERT#

DDR0_VREF_DQ0

DDR0_VREF_DQ1

DDR1_VREF_DQ

5

M_A_DQS_DN0

M_A_DQS_DN1

M_A_DQS_DN2

M_A_DQS_DN3

M_A_DQS_DN4

M_A_DQS_DN5

M_A_DQS_DN6

M_A_DQS_DN7

M_A_DQS_DP0

M_A_DQS_DP1

M_A_DQS_DP2

M_A_DQS_DP3

M_A_DQS_DP4

M_A_DQS_DP5

M_A_DQS_DP6

M_A_DQS_DP7

M_A_DQ0[12]

M_A_DQ1[12]

M_A_DQ2[12]

M_A_DQ3[12]

M_A_DQ4[12]

M_A_DQ5[12]

M_A_DQ6[12]

M_A_DQ7[12]

M_A_DQ8[12]

M_A_DQ9[12]

M_A_DQ10[12]

M_A_DQ11[12]

M_A_DQ12[12]

M_A_DQ13[12]

M_A_DQ14[12]

M_A_DQ15[12]

M_A_DQ16[12]

M_A_DQ17[12]

M_A_DQ18[12]

M_A_DQ19[12]

M_A_DQ20[12]

M_A_DQ21[12]

M_A_DQ22[12]

M_A_DQ23[12]

M_A_DQ24[12]

M_A_DQ25[12]

M_A_DQ26[12]

M_A_DQ27[12]

M_A_DQ28[12]

M_A_DQ29[12]

M_A_DQ30[12]

M_A_DQ31[12]

M_A_DQ32[12]

M_A_DQ33[12]

M_A_DQ34[12]

M_A_DQ35[12]

M_A_DQ36[12]

M_A_DQ37[12]

M_A_DQ38[12]

M_A_DQ39[12]

M_A_DQ40[12]

M_A_DQ41[12]

M_A_DQ42[12]

M_A_DQ43[12]

M_A_DQ44[12]

M_A_DQ45[12]

M_A_DQ46[12]

M_A_DQ47[12]

M_A_DQ48[12]

M_A_DQ49[12]

M_A_DQ50[12]

M_A_DQ51[12]

M_A_DQ52[12]

M_A_DQ53[12]

M_A_DQ54[12]

M_A_DQ55[12]

M_A_DQ56[12]

M_A_DQ57[12]

M_A_DQ58[12]

M_A_DQ59[12]

M_A_DQ60[12]

M_A_DQ61[12]

M_A_DQ62[12]

M_A_DQ63[12]

M_B_A0[13]

M_B_A1[13]

M_B_A2[13]

M_B_A3[13]

M_B_A4[13]

M_B_A5[13]

M_B_A6[13]

M_B_A7[13]

M_B_A8[13]

M_B_A9[13]

M_B_A10[13]

M_B_A11[13]

M_B_A12[13]

M_B_A13[13]

M_B_A14[13]

M_B_A15[13]

M_B_A16[13]

M_B_DQS_DN[7: 0][13]

M_B_DQS_DP[7:0][13]

M_A_CLK#0[12]

M_A_CLK0[12]

M_A_CKE0[12]

M_A_CS#0[12]

M_A_ODT0[12]

M_A_ACT_N[12]

M_A_BG0[12]

M_A_BG1[12]

M_A_BA0[12]

M_A_BA1[12]

M_A_ALERT_N[12]

M_A_PARITY[12]

M_A_A0[12]

M_A_A1[12]

M_A_A2[12]

M_A_A3[12]

M_A_A4[12]

M_A_A5[12]

M_A_A6[12]

M_A_A7[12]

M_A_A8[12]

M_A_A9[12]

M_A_A10[12]

M_A_A11[12]

M_A_A12[12]

M_A_A13[12]

M_A_A14[12]

M_A_A15[12]

M_A_A16[12]

M_B_DQS_DN0

M_B_DQS_DN1

M_B_DQS_DN2

M_B_DQS_DN3

M_B_DQS_DN4

M_B_DQS_DN5

M_B_DQS_DN6

M_B_DQS_DN7

M_B_DQS_DP0

M_B_DQS_DP1

M_B_DQS_DP2

M_B_DQS_DP3

M_B_DQS_DP4

M_B_DQS_DP5

M_B_DQS_DP6

M_B_DQS_DP7

M_B_DQ0[13]

M_B_DQ1[13]

M_B_DQ2[13]

M_B_DQ3[13]

M_B_DQ4[13]

M_B_DQ5[13]

M_B_DQ6[13]

M_B_DQ7[13]

M_B_DQ8[13]

M_B_DQ9[13]

M_B_DQ10[13]

M_B_DQ11[13]

M_B_DQ12[13]

M_B_DQ13[13]

M_B_DQ14[13]

M_B_DQ15[13]

M_B_DQ16[13]

M_B_DQ17[13]

M_B_DQ18[13]

M_B_DQ19[13]

M_B_DQ20[13]

M_B_DQ21[13]

M_B_DQ22[13]

M_B_DQ23[13]

M_B_DQ24[13]

M_B_DQ25[13]

M_B_DQ26[13]

M_B_DQ27[13]

M_B_DQ28[13]

M_B_DQ29[13]

M_B_DQ30[13]

M_B_DQ31[13]

M_B_DQ32[13]

M_B_DQ33[13]

M_B_DQ34[13]

M_B_DQ35[13]

M_B_DQ36[13]

M_B_DQ37[13]

M_B_DQ38[13]

M_B_DQ39[13]

M_B_DQ40[13]

M_B_DQ41[13]

M_B_DQ42[13]

M_B_DQ43[13]

M_B_DQ44[13]

M_B_DQ45[13]

M_B_DQ46[13]

M_B_DQ47[13]

M_B_DQ48[13]

M_B_DQ49[13]

M_B_DQ50[13]

M_B_DQ51[13]

M_B_DQ52[13]

M_B_DQ53[13]

M_B_DQ54[13]

M_B_DQ55[13]

M_B_DQ56[13]

M_B_DQ57[13]

M_B_DQ58[13]

M_B_DQ59[13]

M_B_DQ60[13]

M_B_DQ61[13]

M_B_DQ62[13]

M_B_DQ63[13]

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[0:7]

M_B_DQ[8:15]

M_B_DQ[32:39]

M_B_DQ[40:47]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_CLK#0

M_A_CLK0

M_A_CKE0

M_A_CS#0

M_A_ODT0

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

M_A_BA0

M_A_BA1

M_A_BG0

M_A_ACT_N

M_A_BG1

M_A_DQS_DN0

M_A_DQS_DP0

M_A_DQS_DN1

M_A_DQS_DP1

M_A_DQS_DN4

M_A_DQS_DP4

M_A_DQS_DN5

M_A_DQS_DP5

M_B_DQS_DN0

M_B_DQS_DP0

M_B_DQS_DN1

M_B_DQS_DP1

M_B_DQS_DN4

M_B_DQS_DP4

M_B_DQS_DN5

M_B_DQS_DP5

M_A_ALERT_N

M_A_PARITY

V_SM_VREF_CN TA

V_SM_VREF_CN TB

SM_PGCNTL

3

M_A_DQS0 M_A_DQS1 M_A_DQS4 M_A_DQS5 M_B_DQS0 M_B_DQS1 M_B_DQS4 M_B_DQS5

M_A_DQ[16:23]

M_A_DQ[24:31]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[48:55]

M_B_DQ[56:63]

M_A_DQ16

M_A_DQ17

M_A_DQ18

M_A_DQ19

M_A_DQ20

M_A_DQ21

M_A_DQ22

M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ31

M_A_DQ48

M_A_DQ49

M_A_DQ50

M_A_DQ51

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60

M_A_DQ61

M_A_DQ62

M_A_DQ63

M_B_DQ16

M_B_DQ17

M_B_DQ18

M_B_DQ19

M_B_DQ20

M_B_DQ21

M_B_DQ22

M_B_DQ23

M_B_DQ24

M_B_DQ25

M_B_DQ26

M_B_DQ27

M_B_DQ28

M_B_DQ29

M_B_DQ30

M_B_DQ31

M_B_DQ48

M_B_DQ49

M_B_DQ50

M_B_DQ51

M_B_DQ52

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ56

M_B_DQ57

M_B_DQ58

M_B_DQ59

M_B_DQ60

M_B_DQ61

M_B_DQ62

M_B_DQ63

AJ29

AJ30

AM32

AM31

AM30

AM29

AJ31

AJ32

AR31

AR32

AV30

AV29

AR30

AR29

AV32

AV31

BA32

BA31

BD31

BD32

BA30

BA29

BD29

BD30

BG31

BG32

BK32

BK31

BG29

BG30

BK30

BK29

J22

H25

G22

H22

F25

J25

G25

F22

D22

C22

C24

D24

A22

B22

A24

B24

G31

G32

H29

H28

G28

G29

H31

H32

L31

L32

N29

N28

L28

L29

N31

N32

A00

A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

A2

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C .

CPU_(DDR)

KR CS MLK 13"

1

5 106Thursday, July 19, 2018

of

5 106Thursday, July 19, 2018

of

5 106Thursday, July 19, 2018

of

5

SSID = CPU

CFG3[15]

CFG4[15]

D

C

B

PCH strap pin:

CFG3 CFG4

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG[3]

(#543016)

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

DISPLAY PORT PRESENCE STRAP

CFG[4]

A

0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

0 : ENABLED An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

5

4

2

1

R601 49D9R2F-GP

TP618Do Not Stuff

4

1

CFG3

CFG4

CFG_RCOMP

ITP_PMODE

T4

CFG0

R4

CFG1

T3

CFG2

R3

CFG3

J4

CFG4

M4

CFG5

J3

CFG6

M3

CFG7

R2

CFG8

N2

CFG9

R1

CFG10

N1

CFG11

J2

CFG12

L2

CFG13

J1

CFG14

L1

CFG15

L3

CFG16

N3

CFG18

L4

CFG17

N4

CFG19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD#CG2

CG1

RSVD#CG1

H4

RSVD#H4

H3

RSVD#H3

BV24

RSVD#BV24

BV25

RSVD#BV25

BK36

RSVD#BK36

BK35

RSVD#BK35

W3

RSVD#W3

AM4

RSVD#AM4

AM3

RSVD_TP#AM3

WHISKEY-LAKE-GP

3

WHL QS/CFL/WHL_ES1_CNL U

RSVD_TP#F37

RSVD_TP#F34

RSVD_TP#CN36

RSVD_TP#BJ36

RSVD_TP#BJ34

RSVD_TP#BT9

RSVD_TP#BT8

RSVD_TP#BP8

RSVD_TP#BP9

RSVD#CR4

RSVD#CP3

RSVD#CR3

RSVD_TP#AT3

RSVD_TP#AU3

RSVD#AN1

RSVD#AN2

RSVD#AN4

RSVD#AN3

RSVD_TP#CR35

3

17 OF 20CPU1Q

IST_TRIG

TP#BK34

TP#BR18

IST_TP0

IST_TP1

IST_TRIG0

IST_TRIG1

TP#BP34

VSS

TP#BP35

SKTOCC#

F37

F34

CP36

CN36

BJ36

BJ34

BK34

BR18

BT9

BT8

BP8

BP9

CR4

CP3

CR3

AT3

AU3

AN1

AN2

AN4

AN3

AL2

AL1

AL4

AL3

BP34

BP36

BP35

CR35

E1

IST_TRIG

SKTOCC#

1

TP620 Do Not Stuff

1

TP619 Do Not Stuff

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RESERVED)

Size Document Number Rev

Custom

Date: Sheet

2

CPU_(RESERVED)

KR CS MLK 13"

1

6 106Thursday, July 19, 2018

1

D

C

B

A

A00

of

A00

5

SSID = CPU

VCCCORE_SENSE[46]

D

C

B

VSSCORE_SENSE[46]

SVID_CLK_CPU[46]

SVID_ALERT#_CPU[46]

SVID_DATA_CPU[46]

1V_CPU_CORE

1

R719 100R2F-L1-GP-U

2

1

R720 100R2F-L1-GP-U

2

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCCORE_SENSE

VSSCORE_SENSE

1V_CPU_CORE

AW10

AN9

AN10

AN24

AN26

AN27

AP2

AP9

AP24

AP26

AR5

AR6

AR7

AR8

AR10

AR25

AR27

AT9

AT24

AT26

AU5

AU6

AU7

AU8

AU9

AU24

AU25

AU26

AU27

AV2

AV5

AV7

AV10

AV27

AW5

AW6

AW7

AW8

AW9

BB9

BC24

AY9

BB24

4

VCCCORE

RSVD#BB9

RSVD#BC24

RSVD#AY9

RSVD#BB24

12 OF 20CPU1L

VCCCORE

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

RSVD#Y3

VCCSTG

1V_CPU_CORE

AW24

AW25

AW26

AW27

AY24

AY26

BA5

BA7

BA8

BA25

BA27

BB2

BB26

BC5

BC6

BC7

BC9

BC10

BC26

BC27

BD5

BD8

BD10

BD25

BD27

BE9

BE24

BE25

BE26

BE27

BF2

BF9

BF24

BF26

BG27

VCCCORE_SENSE

AN6

VSSCORE_SENSE

AN5

SVID_ALERT#_CPU_R

AA3

SVID_CLK_CPU_R

AA1

SVID_DATA_CPU_R

AA2

Y3

BG3

3

1V_VCCSTG

2

1

SVID_543016:

Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals.

1V_VCCST_CPU

SVID DATA

SVID_DATA_CPU_R

SVID CLOCK

SVID_CLK_CPU_R

SVID ALERT

SVID_ALERT#_CPU_R

1

R726 100R2F-L1-GP-U

2

R709 Do Not Stuff

1

R732 Do Not Stuff

R728 220R2F-GP

1

1V_VCCST_CPU

1

#544669 CLOSE TO CPU

SVID_DATA_CPU

2

1

R723 Do Not Stuff

DY

2

1

2

SVID_CLK_CPU

R727 56R2F-1-GP

SVID_ALERT#_CPU

2

1V_VCCST_CPU

#544669 CLOSE TO VR

20180208 R727, R728 change to 1%

#544669 CLOSE TO CPU

D

C

B

WHISKEY-LAKE-GP

Wistron Corporation

A

Title

CPU(VCC_CORE)

Size Document Number Rev

A4

Thursday, July 19, 2018

Date: Sheet

5

4

3

2

CPU(VCC_CORE)

KR CS MLK 13"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

7 106

of

7 106

of

7 106

of

1

A00

A

5

SSID = CPU

VCCGT_SENSE[46]

VSSGT_SENSE[46]

VSSSA_SENSE[46]

VCCSA_SENSE[46]

D

1V_VCCGT

1

R807 100R2F-L1-GP-U

2

VCCGT_SENSE

VSSGT_SENSE

1

R808 100R2F-L1-GP-U

C

B

A

2

VCCSA_SENSE

VSSSA_SENSE

1V_VCCSA

5

1

R810 100R2F-L1-GP-U

2

1

R809 100R2F-L1-GP-U

2

1V_VCCGT

WHL QS/CFL/WHL_ES1_CNL U

A5

VCCGT

A6

VCCGT

A8

VCCGT

A11

VCCGT

A12

VCCGT

A14

VCCGT

A15

VCCGT

A17

VCCGT

A18

VCCGT

A20

VCCGT

B3

VCCGT

B4

VCCGT

B6

VCCGT

B8

VCCGT

B11

VCCGT

B14

VCCGT

B17

VCCGT

B20

VCCGT

C2

VCCGT

C3

VCCGT

C6

VCCGT

C7

VCCGT

C8

VCCGT

C11

VCCGT

C12

VCCGT

C14

VCCGT

C15

VCCGT

C17

VCCGT

C18

VCCGT

C20

VCCGT

D4

VCCGT

D7

VCCGT

D11

VCCGT

D12

VCCGT

D14

VCCGT

D15

VCCGT

D17

VCCGT

D18

VCCGT

D20

VCCGT

E4

VCCGT

F5

VCCGT

F6

VCCGT

F7

VCCGT

F8

VCCGT

F11

VCCGT

F14

VCCGT

F17

VCCGT

F20

VCCGT

G11

VCCGT

G12

VCCGT

G14

VCCGT

G15

VCCGT

G17

VCCGT

G18

VCCGT

G20

VCCGT

H5

VCCGT

H6

VCCGT

H7

VCCGT

H8

VCCGT

H11

VCCGT

WHISKEY-LAKE-GP

4

13 OF 20CPU1M

VCCGT

VCCCORE

VCCGT_SENSE

VSSGT_SENSE

1V_VCCGT

H12

H14

H15

H17

H18

H20

J7

J8

J11

J14

J17

J20

K2

K11

L7

L8

L10

M9

N7

N8

N9

N10

P2

P8

R9

T8

T9

T10

U8

U10

V9

W8

W9

AA9

AB2

AB8

AB9

AB10

AC8

AD9

AE8

AE9

AE10

AF2

AF8

AF10

AG8

AG9

AH9

AJ8

AJ10

AK2

AK9

AL8

AL9

AL10

AM8

V2

Y8

Y10

E3

D2

1V_GT_CORE

VCCGT_SENSE

VSSGT_SENSE

3

1D2V_S3

1

C804

DY

Do Not Stuff

2

1V_VCCST_CPU

2

1

C801 SC1U10V2KX-1DLGP

1V_VCCSTG

2

1

C802 SC1U10V2KX-1DLGP

1D2V_VCCSFR_OC

2

1

C803 SC1U10V2KX-1DLGP

1V_VCCST_CPU

0.12 A

1

C805

SCD1U25V2KX-1-DL-GP

2

1V_CPU_CORE

3

2

AD36

VDDQ

AH32

VDDQ

AH36

VDDQ

AM36

VDDQ

AN32

VDDQ

AW32

VDDQ

AY36

VDDQ

BE32

VDDQ

BH36

VDDQ

R32

VDDQ

Y36

VDDQ

BC28

0.04 A

1

C806

2

SC1U10V2KX-1DLGP

RSVD#BC28

BP11

VCCST

BP2

VCCST

BG1

VCCSTG

BG2

VCCSTG

BL27

VCCPLL_OC

BM26

VCCPLL_OC

BR11

VCCPLL

BT11

VCCPLL

WHISKEY-LAKE-GP

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

RO13_CFLU_20171225

1V_GT_CORE

RO13_CFLU_20171227(ES2 used)

ES2

2

1

R811 D0002R5J-2-GP

1

R813 D0002R5J-2-GP

1

R814 D0002R5J-2-GP

ES2

Title

Size Document Number Rev

A4

Date: Sheet

2

14 OF 20CPU1N

VCCIO_OUT

VCCSA

RO13_CFLU_20171227(ES0/ES1 used)

R812 Do Not Stuff

R815 Do Not Stuff

1V_VCCIO

AK24

AK26

AL24

AL25

AL26

AL27

AM25

AM27

BH24

BH25

BH26

BH27

BJ24

BJ26

BP16

BP18

BG8

BG10

BH9

BJ8

BJ9

BJ10

BK8

BK25

BK27

BL8

BL9

BL10

BL24

BL26

BM24

BN25

BP28

BP29

VSSSA_SENSE

BE7

VCCSA_SENSE

BG7

1

ES0/ES1

1

+VCCIO(ICCMAX.=2.73A

1V_VCCSA

2

ES0/ES1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(DISPLAY)

KR CS MLK 13"

1

D

C

B

1V_VCCGT

A

A00

8 106Thursday, July 19, 2018

of

8 106Thursday, July 19, 2018

of

8 106Thursday, July 19, 2018

of

1

5

4

3

2

1

D

C

D

C

(Blanking)

A00

B

A

B

Wistron Corporation

A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

(Reserved)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

KR CS MLK 13"

9 106Thursday, July 19, 2018

1

of

SSID = CPU

1V_CPU_CORE

PC1002

1

2

D

2

SC22U6D3V3MX-1-DL-GP

PC1014

1

2

5

1V_CPU_CORE

PC1004

PC1003

1

2

PC1015

PC1016

1

2

PC1006

PC1005

1

2

SC22U6D3V3MX-1-DL-GP

PC1017

1

2

1

2

PC1018

1

2

22U 0603 x 39 (7DY)

PC1007

PC1019

PC1009

PC1008

1

2

SC22U6D3V3MX-1-DL-GP

PC1020

1

2

1

2

PC1021

1

2

PC1011

PC1010

1

2

SC22U6D3V3MX-1-DL-GP

PC1022

PC1023

1

2

4

PC1013

PC1012

1

2

PC1024

PC1025

1

2

3

2

1

D

SC22U6D3V3MX-1-DL-GP

PC1027

PC1026

1

2

C

B

1V_VCCGT

SC22U6D3V3MX-1-DL-GP

PC1037

1

DY

2

Do Not Stuff

SC22U6D3V3MX-1-DL-GP

PC1052

1

2

SC22U6D3V3MX-1-DL-GP

PC1063

1

DY

2

SC22U6D3V3MX-1-DL-GP

PC1028

PC1029

1

2

SC22U6D3V3MX-1-DL-GP

1V_VCCGT

PC1039

PC1038

1

DY

2

Do Not Stuff

SC22U6D3V3MX-1-DL-GP

PC1053

PC1054

1

2

SC22U6D3V3MX-1-DL-GP

PC1064

PC1065

1

DY

2

SC22U6D3V3MX-1-DL-GP

PC1031

PC1032

PC1030

1

2

DY

2

1

2

Do Not Stuff

DY

PC1034

1

2

DY

PC1036

1

2

SC22U6D3V3MX-1-DL-GP

PC1080

PC1079

1

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

1

DY

2

PC1081

1

DY

2

Do Not Stuff

PC1082

DY

1

DY

2

C

PC1084

PC1083

22U 0603 x 35 (9 DY)

PC1049

PC1045

PC1040

PC1055

PC1066

PC1042

PC1041

1

2

PC1057

PC1056

1

2

1

2

DY

2

PC1067

PC1068

1

DY

2

PC1044

PC1043

1

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

PC1058

1

2

Do Not Stuff

SC22U6D3V3MX-1-DL-GP

PC1069

1

2

1

DY

2

PC1059

1

2

PC1070

1

2

PC1046

1

2

SC22U6D3V3MX-1-DL-GP

PC1061

PC1060

1

2

SC22U6D3V3MX-1-DL-GP

PC1001

PC1048

PC1047

1

2

PC1062

1

2

PC1050

1

DY

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

PC1051

B

A

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

1V_VCCSA

PC1071

1

2

SC22U6D3V3MX-1-DL-GP

VCCSA

PC1073

PC1072

1

2

SC22U6D3V3MX-1-DL-GP

22U 0603 x 8 (2DY)

PC1075

PC1074

1

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

5

Do Not Stuff

SC22U6D3V3MX-1-DL-GP

PC1077

PC1076

1

DY

2

PC1078

1

DY

2

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(Power CAP1)

Size Document Number Rev

A3

Date: Sheet

CPU_(Power CAP1)

KR CS MLK 13"

10 106Thursday, July 19, 2018

1

of

A00

A

5

SSID = CPU

PCH Power

D

1D0V_S5

1

C1112 SC22U6D3V3MX-1-DL-GP

2

RO13_20171110 KR EC list

4

3

CPU Power

1V_VCCIO

VCCIO

C1133

1

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

C1134

1

DY

2

+VCCIO(ICCMAX.=2.73A)

C1135

C1108

1

DY

2

Do Not Stuff

SC1U10V2KX-1DLGP

C1109

1

2

C1111

C1110

1

2

SSID

1V_VCCGT

C1102

1

DY

2

Do Not Stuff

UNSLICED GT

DY

C1103

1

2

DY

C1104

1

2

1U 0402 x 6

C1105

1

DY

2

SC1U10V2KX-1DLGP

Do Not Stuff

SC1U10V2KX-1DLGP

1

C1107

C1106

1

2

D

3D3V_S5_PCH

1

R1103 Do Not Stuff

RO13_20171020

C

1D8V_S5

2

R1104 Do Not Stuff

RO13_20171020

B

1D0V_S5

C1128

1

2

3D3V_VCCPRIM

2

1D8V_VCCPRIM

1

C1129

1

2

C1113

1

DY

2

C1122

1

DY

2

3D3V_VCCPRIM

DY

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

Do Not Stuff

1D0V_S5

C1115

Do Not Stuff

1

DY

2

Do Not Stuff

1D2V_S3

C1130

1

DY

2

C1123

Do Not Stuff

1

2

SC22U6D3V3MX-1-DL-GP

Do Not Stuff

C1114

SC1U10V2KX-1DLGP

1

2

C1131

1

DY

2

1D0V_S5

C1132

1

2

SC10U6D3V3MX-DL-GP

C1116

SC1U10V2KX-1DLGP

C1117

1

2

C1136

1

2

SC1U10V2KX-1DLGP

1

2

C1138

C1137

1

2

1D0V_S5

C1118

SC22U6D3V3MX-1-DL-GP

1

2

C1139

1

2

SCD1U25V2KX-1-DL-GP

1

2

C1140

1

2

C1119

C1141

1

2

RO13_20171030 +VCCMPHYGTAON_1P0_LS_SIP change to 1D0V_S5.

1D0V_S5

C1121

C1120

SC1U10V2KX-1DLGP

C1142

1

2

1

DY

2

RO13_20170717

DY

Do Not Stuff

1

2

Do Not Stuff

SC1U10V2KX-1DLGP

1

2

DY

FC1103

1

2

FC1102

C

B

SC22U6D3V3MX-1-DL-GP

A

5

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(Power CAP2)

Size Document Number Rev

A4

Date: Sheet

2

CPU_(Power CAP2)

KR CS MLK 13"

11 106Thursday, July 19, 2018

1

of

A00

A

SSID = MEMORY

M_A_DQS_DN[7: 0][5]

M_A_DQS_DP[7:0][5]

D

M_A_DQ0[5]

M_A_DQ1[5]

M_A_DQ2[5]

M_A_DQ3[5]

M_A_DQ4[5]

M_A_DQ5[5]

M_A_DQ6[5]

M_A_DQ7[5]

M_A_DQ8[5]

M_A_DQ9[5]

M_A_DQ10[5]

M_A_DQ11[5]

M_A_DQ12[5]

M_A_DQ13[5]

M_A_DQ14[5]

M_A_DQ15[5]

M_A_DQ16[5]

M_A_DQ17[5]

M_A_DQ18[5]

M_A_DQ19[5]

M_A_DQ20[5]

M_A_DQ21[5]

M_A_DQ22[5]

M_A_DQ23[5]

M_A_DQ24[5]

M_A_DQ25[5]

M_A_DQ26[5]

M_A_DQ27[5]

M_A_DQ28[5]

M_A_DQ29[5]

M_A_DQ30[5]

C

B

M_A_DQ31[5]

M_A_DQ32[5]

M_A_DQ33[5]

M_A_DQ34[5]

M_A_DQ35[5]

M_A_DQ36[5]

M_A_DQ37[5]

M_A_DQ38[5]

M_A_DQ39[5]

M_A_DQ40[5]

M_A_DQ41[5]

M_A_DQ42[5]

M_A_DQ43[5]

M_A_DQ44[5]

M_A_DQ45[5]

M_A_DQ46[5]

M_A_DQ47[5]

M_A_DQ48[5]

M_A_DQ49[5]

M_A_DQ50[5]

M_A_DQ51[5]

M_A_DQ52[5]

M_A_DQ53[5]

M_A_DQ54[5]

M_A_DQ55[5]

M_A_DQ56[5]

M_A_DQ57[5]

M_A_DQ58[5]

M_A_DQ59[5]

M_A_DQ60[5]

M_A_DQ61[5]

M_A_DQ62[5]

M_A_DQ63[5]

M_A_A0[5]

M_A_A1[5]

M_A_A2[5]

M_A_A3[5]

M_A_A4[5]

M_A_A5[5]

M_A_A6[5]

M_A_A7[5]

M_A_A8[5]

M_A_A9[5]

M_A_A10[5]

M_A_A11[5]

M_A_A12[5]

M_A_A13[5]

M_A_A14[5]

M_A_A15[5]

M_A_A16[5]

V_SM_VREF_CN TA[5]

M_A_ODT0[5]

M_A_BG0[5]

M_A_PARITY[5]

M_A_CLK0[5]

M_A_CLK#0[5]

M_A_CKE0[5]

M_A_CS#0[5]

SM_DRAMRST #[5 ,13]

M_A_ACT_N[5]

M_A_ALERT_N[5]

M_A_BA0[5]

M_A_BA1[5]

M_A_BG1[5]

M_A_DQS_DN0

M_A_DQS_DN1

M_A_DQS_DN2

M_A_DQS_DN3

M_A_DQS_DN4

M_A_DQS_DN5

M_A_DQS_DN6

M_A_DQS_DN7

M_A_DQS_DP0

M_A_DQS_DP1

M_A_DQS_DP2

M_A_DQS_DP3

M_A_DQS_DP4

M_A_DQS_DP5

M_A_DQS_DP6

M_A_DQS_DP7

2

M_A_BG1_M9_R

2

DDP/SDP

2

DDP/SDP

2

DDP/SDP

2

DDP/SDP

CLK

C1290

C1291

1

DY

2

C1278

C1276

C1277

1

DY

2

VDDQ/VDD 1uF x32

C1206

C1208

C1207

1

2

1

2

C1223

1

2

SC1U10V2KX-1D LGP

C1224

1

2

SC1U10V2KX-1D LGP

DY

2

C1222

1

DY

2

1D2V_S3

1

R1222 1K8R2F-GP

2

M_VREF_CA_D IMMA

2

R1223 1K8R2F-GP

1

close to CPU

M_A_CLK0

R1225 33R2F-3-GP

M_A_CLK#0

R1226 33R2F-3-GP

C1210

C1209

1

2

C1225

C1226

1

2

M_A_CLK0

2016/11/25 DY

ALERT

M_A_ALERT_N

1

C1211

1

2

C1227

1

DY

2

C1285

Do Not Stuff

1

DY

2

C1212

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1228

1

2

Do Not Stuff

SC1U10V2KX-1D LGP

R1202

1

2D7R2F-1-G P

M_A_CLK#0

2

R1208

1

49D9R2F-GP

C1213

C1229

1

2

???

2

M_A_CLK

C1214

1

DY

2

C1230

1

2

V_SM_VREF_CN TA

1

C1202 SCD022U16V2KX -3DLGP

2

+V_VREF_PATH 1

1

R1203 24D9R2F-L-G P

2

1D2V_S3

C1247

2

1

SCD01U50V2KX- 1DLGP

C1216

C1215

1

2

SC1U10V2KX-1D LGP

C1231

C1232

1

DY

2

Do Not Stuff

SC1U10V2KX-1D LGP

1

2

1

2

M_A_DQ42

G2

M_A_DQ41

F7

M_A_DQ46

H3

M_A_DQ44

H7

M_A_DQ43

H2

M_A_DQ40

H8

M_A_DQ47

J3

M_A_DQ45

J7

M_A_DQ37

A3

M_A_DQ36

B8

M_A_DQ34

C3

M_A_DQ38

C7

M_A_DQ32

C2

M_A_DQ33

C8

M_A_DQ39

D3

M_A_DQ35

D7

M_A_DQS_DP4

B7

M_A_DQS_DN4

A7

M_A_DQS_DP5

G3

M_A_DQS_DN5

F3

E2

E7

M_A_ODT0

K3

A_ZQ_RAM2

F9

M_VREF_CA_D IMMA

M1

M_A_BG0

M2

TEST_MODE_4

N9

M_A_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

M_A_DQ11

G2

M_A_DQ13

F7

M_A_DQ15

H3

M_A_DQ12

H7

M_A_DQ10

H2

M_A_DQ8

H8

M_A_DQ14

J3

M_A_DQ9

J7

M_A_DQ4

A3

M_A_DQ5

B8

M_A_DQ6

C3

M_A_DQ3

C7

M_A_DQ0

C2

M_A_DQ1

C8

M_A_DQ7

D3

M_A_DQ2

D7

M_A_DQS_DP0

B7

M_A_DQS_DN0

A7

M_A_DQS_DP1

G3

M_A_DQS_DN1

F3

E2

E7

M_A_ODT0

K3

A_ZQ_RAM4

F9

M_VREF_CA_D IMMA

M1

M_A_BG0

M2

TEST_MODE_1

N9

M_A_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

3

M_A_BG1_E9_4

M_A_BG1_M9_R

M_A_BG1_E9_1

M_A_BG1_M9_R

1D2V_S3

1

R1234 240R2D-GP

1

C1286 SCD047U25V2KX -4-GP

2

1D2V_S3

1

R1201 240R2D-GP

1

C1201 SCD047U25V2KX -4-GP

2

SDP & DDP SETTING

M_A_BG1

1

R1220 0R2J-L-GP

DDP

1

R1221 Do Not Stuff

SDP

R1212~R1215 (RO13)(20170911)(DEL: R1216~R1219) DDP: 240 ohm (64.24005.6DL) SDP: 0 ohm (63.R0034.L0L)

M_A_BG1_E9_1

M_A_BG1_E9_2

M_A_BG1_E9_3

M_A_BG1_E9_4

2

TEST_MODE_1

TEST_MODE_2

TEST_MODE_3

TEST_MODE_4

2

1D2V_S3

1

R1212 240R2F-1-GP

1

R1213 240R2F-1-GP

1

R1214 240R2F-1-GP

1

R1215 240R2F-1-GP

1

TP1201 Do Not Stuff

1

TP1202 Do Not Stuff

1

TP1203 Do Not Stuff

1

TP1204 Do Not Stuff

0D6V_VREF_S0

VTT 10uF x4

C1289

C1288

1

DY

2

SC10U6D3V3MX- DL-GP

Do Not Stuff

SC10U6D3V3MX- DL-GP

Do Not Stuff

2D5V_S3

VPP 10uF x5

C1275

C1279

1

DY

2

SC10U6D3V3MX- DL-GP

Do Not Stuff

SC10U6D3V3MX- DL-GP

Do Not Stuff

C1204

C1205

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1221

C1220

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

5

1D2V_S3

2D5V_S3

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

M_A_CS#0

SM_DRAMRST #

M_A_ACT_N

M_A_ALERT_N

M_A_CLK0

M_A_CLK#0

M_A_CKE0

M_A_BA0

M_A_BA1

2D5V_S3

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

M_A_CS#0

SM_DRAMRST #

M_A_ACT_N

M_A_ALERT_N

M_A_CLK0

M_A_CLK#0

M_A_CKE0

M_A_BA0

M_A_BA1

RAM1

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

1D2V_S3

RAM3

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

VDD

VDDQ

VPP

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

VDD

VDDQ

VPP

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

UDQS_T

UDQS_C

LDQS_T

LDQS_C

VREFCA

NC#T7

VSSQ

UDQS_T

UDQS_C

LDQS_T

LDQS_C

VREFCA

NC#T7

VSSQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

BG0

TEN

PAR

VSS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

BG0

TEN

PAR

VSS

ZQ

M_A_DQ59

G2

M_A_DQ61

F7

M_A_DQ62

H3

M_A_DQ56

H7

M_A_DQ58

H2

M_A_DQ57

H8

M_A_DQ63

J3

M_A_DQ60

J7

M_A_DQ53

A3

M_A_DQ50

B8

M_A_DQ48

C3

M_A_DQ54

C7

M_A_DQ52

C2

M_A_DQ51

C8

M_A_DQ49

D3

M_A_DQ55

D7

M_A_DQS_DP6

B7

M_A_DQS_DN6

A7

M_A_DQS_DP7

G3

M_A_DQS_DN7

F3

E2

E7

M_A_ODT0

K3

A_ZQ_RAM1

F9

M_VREF_CA_D IMMA

M1

M_A_BG0

M2

TEST_MODE_2

N9

M_A_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

M_A_DQ17

G2

M_A_DQ19

F7

M_A_DQ22

H3

M_A_DQ23

H7

M_A_DQ21

H2

M_A_DQ18

H8

M_A_DQ20

J3

M_A_DQ16

J7

M_A_DQ25

A3

M_A_DQ29

B8

M_A_DQ27

C3

M_A_DQ31

C7

M_A_DQ28

C2

M_A_DQ24

C8

M_A_DQ26

D3

M_A_DQ30

D7

M_A_DQS_DP3

B7

M_A_DQS_DN3

A7

M_A_DQS_DP2

G3

M_A_DQS_DN2

F3

E2

E7

M_A_ODT0

K3

A_ZQ_RAM3

F9

M_VREF_CA_D IMMA

M1

M_A_BG0

M2

TEST_MODE_3

N9

M_A_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

M_A_BG1_E9_3

M_A_BG1_M9_R

M_A_BG1_E9_2

M_A_BG1_M9_R

4

1D2V_S3

2

1

R1205 240R2D-GP

1

C1236 SCD047U25V2KX -4-GP

2

1D2V_S3

2

1

R1204 240R2D-GP

1

C1203 SCD047U25V2KX -4-GP

2

2D5V_S3

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

M_A_CS#0

SM_DRAMRST #

M_A_ACT_N

M_A_ALERT_N

M_A_CLK0

M_A_CLK#0

M_A_CKE0

M_A_BA0

M_A_BA1

2D5V_S3

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

M_A_CS#0

SM_DRAMRST #

M_A_ACT_N

M_A_ALERT_N

M_A_CLK0

M_A_CLK#0

M_A_CKE0

M_A_BA0

M_A_BA1

1D2V_S3

RAM2

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

1D2V_S3

RAM4

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

VDD

VDDQ

VPP

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

VDD

VDDQ

VPP

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQS_T

UDQS_C

LDQS_T

LDQS_C

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

VREFCA

NC#T7

VSSQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQS_T

UDQS_C

LDQS_T

LDQS_C

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

VREFCA

NC#T7

VSSQ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

ZQ

BG0

TEN

PAR

VSS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

ZQ

BG0

TEN

PAR

VSS

1

M_A_BG1_M9_R

R1224 36R2F-1-GPDDP

M_A_A16

R1211 36R2F-1-GP

M_A_A10

M_A_A14

M_A_BG0

M_A_CS#0

M_A_A8

M_A_A11

M_A_A0

M_A_A2

M_A_PARITY

M_A_A13

M_A_A7

M_A_A9

M_A_A6

M_A_A5

M_A_BA1

M_A_A1

M_A_BA0

M_A_A4

M_A_A3

M_A_A12

M_A_CKE0

M_A_A15

M_A_ACT_N

M_A_ODT0

C1217

C1219

C1218

1

2

C1234

C1235

C1233

1

2

1

RN1202

1

2

3

4

SRN36J-GP

RN1203

1

2

3

4

SRN36J-GP

RN1204

1

2

3

4

SRN36J-GP

RN1205

1

2

3

4

SRN36J-GP

RN1206

1

2

3

4

SRN36J-GP

RN1207

1

2

3

4

SRN36J-GP

2

8

7

6

5

8

7

6

5

8

7

6

5

8

7

6

5

8

7

6

5

8

7

6

5

0D6V_VREF_S0

D

C

B

A00

A

2D5V_S3

1

2

C1259

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1260

DY

C1261

1

2

VPP 1uF x16

C1264

C1262

C1263

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

Do Not Stuff

5

C1270

DY

C1271

1

DY

2

Do Not Stuff

SC1U10V2KX-1D LGP

C1272

1

2

C1266

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

C1268

1

DY

2

C1265

1

DY

2

C1269

C1267

0D6V_VREF_S0

C1255

C1274

C1273

1

2

4

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

C1257

1

2

VTT 1uF x16

C1258

1

DY

2

C1280

C1281

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

1

DY

2

1

2

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

C1292

C1283

C1282

C1284

1

C1295

C1293

1

DY

2

C1296

C1294

1

DY

1

DY

2

Do Not Stuff

3

C1299

C1298

C1297

1

DY

2

1D2V_S3

1

DY

2

C1237

VDDQ/VDD 10uF x10

C1239

C1240

C1238

1

2

Do Not Stuff

SC10U6D3V3MX- DL-GP

C1244

C1245

C1242

1

DY

2

SC10U6D3V3MX- DL-GP

Do Not Stuff

SC10U6D3V3MX- DL-GP

C1243

1

DY

2

C1246

1

2

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

Taipei Hsie n 221, Taiwan, R.O.C .

Title

DDR3-SODIMM1

Size Document Num ber Rev

A2

Thursday, July 19, 2018

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C .

KR CS MLK 13"

1

12 106

of

12 106

of

12 106

of

C1241

1

2

SSID = MEMORY

M_B_DQS_DN[7: 0][5]

M_B_DQS_DP[7:0][5]

D

M_B_DQ0[5]

M_B_DQ1[5]

M_B_DQ2[5]

M_B_DQ3[5]

M_B_DQ4[5]

M_B_DQ5[5]

M_B_DQ6[5]

M_B_DQ7[5]

M_B_DQ8[5]

M_B_DQ9[5]

M_B_DQ10[5]

M_B_DQ11[5]

M_B_DQ12[5]

M_B_DQ13[5]

M_B_DQ14[5]

M_B_DQ15[5]

M_B_DQ16[5]

M_B_DQ17[5]

M_B_DQ18[5]

M_B_DQ19[5]

M_B_DQ20[5]

M_B_DQ21[5]

M_B_DQ22[5]

M_B_DQ23[5]

M_B_DQ24[5]

M_B_DQ25[5]

M_B_DQ26[5]

M_B_DQ27[5]

M_B_DQ28[5]

M_B_DQ29[5]

M_B_DQ30[5]

2D5V_S3

1

2

V_SM_VREF_CN TB[5]

C1337

M_B_DQ31[5]

M_B_DQ32[5]

M_B_DQ33[5]

M_B_DQ34[5]

M_B_DQ35[5]

M_B_DQ36[5]

M_B_DQ37[5]

M_B_DQ38[5]

M_B_DQ39[5]

M_B_DQ40[5]

M_B_DQ41[5]

M_B_DQ42[5]

M_B_DQ43[5]

M_B_DQ44[5]

M_B_DQ45[5]

M_B_DQ46[5]

M_B_DQ47[5]

M_B_DQ48[5]

M_B_DQ49[5]

M_B_DQ50[5]

M_B_DQ51[5]

M_B_DQ52[5]

M_B_DQ53[5]

M_B_DQ54[5]

M_B_DQ55[5]

M_B_DQ56[5]

M_B_DQ57[5]

M_B_DQ58[5]

M_B_DQ59[5]

M_B_DQ60[5]

M_B_DQ61[5]

M_B_DQ62[5]

M_B_DQ63[5]

M_B_A0[5]

M_B_A1[5]

M_B_A2[5]

M_B_A3[5]

M_B_A4[5]

M_B_A5[5]

M_B_A6[5]

M_B_A7[5]

M_B_A8[5]

M_B_A9[5]

M_B_A10[5]

M_B_A11[5]

M_B_A12[5]

M_B_A13[5]

M_B_A14[5]

M_B_A15[5]

M_B_A16[5]

M_B_ODT0[5]

M_B_BG0[5]

M_B_PARITY[5]

M_B_CLK0[5]

M_B_CLK#0[5]

M_B_CKE0[5]

M_B_CS#0[5]

SM_DRAMRST #[5,12]

M_B_ALERT_N[5]

M_B_ACT_N[5]

M_B_BA0[5]

M_B_BA1[5]

M_B_BG1[5]

C1338

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1339

C

B

A

1D2V_S3

R1304 240R2D-GP

1

2

1D2V_S3

R1306 240R2D-GP

1

2

C1353

C1352

1

2

4

2

1

C1303 SCD047U25V2KX -4-GP

2

1

C1336 SCD047U25V2KX -4-GP

0D6V_VREF_S0

DY

4

C1354

1

2

Do Not Stuff

SC1U10V2KX-1D LGP

1D2V_S3

RAM6

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

1D2V_S3

1

2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

C1358

C1357

1

DY

2

VDDQ

VPP

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

RAM8

VDD

VDDQ

VPP

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

C1359

1

DY

2

Do Not Stuff

2D5V_S3

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_A16

M_B_CS#0

SM_DRAMRST #

M_B_ACT_N

M_B_ALERT_N

M_B_CLK0

M_B_CLK#0

M_B_CKE0

M_B_BA0

M_B_BA1

2D5V_S3

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_A16

M_B_CS#0

SM_DRAMRST #

M_B_ACT_N

M_B_ALERT_N

M_B_CLK0

M_B_CLK#0

M_B_CKE0

M_B_BA0

M_B_BA1

C1355

C1356

1

2

5

1D2V_S3

RAM5

B3

VDD

B9

1D2V_S3

1

DY

2

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

B3

B9

D1

G7

J1

J9

L1

L9

R1

T9

A1

A9

C1

D9

F2

F8

G1

G9

J2

J8

B1

R9

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

L7

P1

L3

P9

K7

K8

K2

N2

N8

C1345

1

2

VDD

VDDQ

VPP

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

RAM7

VDD

VDDQ

VPP

NF#E2/UDM#/UDBI#

NF#E7/LDM#/LDBI#

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC#

A13

WE#/A14

CAS#/A15

RAS#/A16

CS#

RESET#

ACT#

ALERT#

CK_T

CK_C

CKE

BA0

BA1

MT40A256M16GE-083E- B-COLAY1-GP

ZZ.00PAD.0Q2

C1348

C1346

C1347

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

Do Not Stuff

M_B_DQS_DN0

M_B_DQS_DN1

M_B_DQS_DN2

M_B_DQS_DN3

M_B_DQS_DN4

M_B_DQS_DN5

M_B_DQS_DN6

M_B_DQS_DN7

M_B_DQS_DP0

M_B_DQS_DP1

M_B_DQS_DP2

M_B_DQS_DP3

M_B_DQS_DP4

M_B_DQS_DP5

M_B_DQS_DP6

M_B_DQS_DP7

VPP 1uF x16 VTT 1uF x16

C1340

1

2

C1341

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

Do Not Stuff

5

C1342

2D5V_S3

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_A16

M_B_CS#0

SM_DRAMRST #

M_B_ACT_N

M_B_ALERT_N

M_B_CLK0

M_B_CLK#0

M_B_CKE0

M_B_BA0

M_B_BA1

2D5V_S3

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_A16

M_B_CS#0

SM_DRAMRST #

M_B_ACT_N

M_B_ALERT_N

M_B_CLK0

M_B_CLK#0

M_B_CKE0

M_B_BA0

M_B_BA1

C1344

1

2

UDQS_T

UDQS_C

LDQS_T

LDQS_C

VREFCA

UDQS_T

UDQS_C

LDQS_T

LDQS_C

VREFCA

1

DY

2

NC#T7

VSSQ

NC#T7

VSSQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

ZQ

BG0

TEN

PAR

VSS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

ODT

ZQ

BG0

TEN

PAR

VSS

C1349

DY

M_B_DQ27

G2

M_B_DQ29

F7

M_B_DQ30

H3

M_B_DQ28

H7

M_B_DQ26

H2

M_B_DQ25

H8

M_B_DQ31

J3

M_B_DQ24

J7

M_B_DQ23

A3

M_B_DQ17

B8

M_B_DQ18

C3

M_B_DQ20

C7

M_B_DQ22

C2

M_B_DQ16

C8

M_B_DQ19

D3

M_B_DQ21

D7

M_B_DQS_DP2

B7

M_B_DQS_DN2

A7

M_B_DQS_DP3

G3

M_B_DQS_DN3

F3

E2

E7

M_B_ODT0

K3

B_ZQ_RAM1

F9

M_VREF_CA_D IMMB

M1

M_B_BG0

M2

TEST_MODE_7

N9

M_B_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

M_B_DQ63

G2

M_B_DQ60

F7

M_B_DQ59

H3

M_B_DQ56

H7

M_B_DQ62

H2

M_B_DQ61

H8

M_B_DQ58

J3

M_B_DQ57

J7

M_B_DQ53

A3

M_B_DQ49

B8

M_B_DQ51

C3

M_B_DQ55

C7

M_B_DQ52

C2

M_B_DQ48

C8

M_B_DQ50

D3

M_B_DQ54

D7

M_B_DQS_DP6

B7

M_B_DQS_DN6

A7

M_B_DQS_DP7

G3

M_B_DQS_DN7

F3

E2

E7

M_B_ODT0

K3

B_ZQ_RAM3

F9

M_VREF_CA_D IMMB

M1

M_B_BG0

M2

TEST_MODE_8

N9

M_B_PARITY

T3

T7

B2

E1

E9

G8

K1

K9

M9

N1

T1

A2

A8

C9

D2

D8

E3

E8

F1

H1

H9

C1350

1

2

Do Not Stuff

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

M_B_BG1_E9_2

M_B_BG1_M9_R

M_B_BG1_E9_4

M_B_BG1_M9_R

C1351

DY

3

M_B_DQ14

G2

DQ0

M_B_DQ11

F7

DQ1

M_B_DQ15

H3

DQ2

M_B_DQ13

H7

DQ3

M_B_DQ10

H2

DQ4

M_B_DQ9

H8

DQ5

M_B_DQ12

J3

DQ6

M_B_DQ8

J7

DQ7

M_B_DQ0

A3

DQ8

M_B_DQ1

B8

DQ9

M_B_DQ3

C3

DQ10

M_B_DQ7

C7

DQ11

M_B_DQ5

C2

DQ12

M_B_DQ4

C8

DQ13

M_B_DQ6

D3

DQ14

M_B_DQ2

D7

DQ15

M_B_DQS_DP0

B7

UDQS_T

M_B_DQS_DN0

A7

UDQS_C

M_B_DQS_DP1

G3

LDQS_T

M_B_DQS_DN1

F3

LDQS_C

E2

E7

K3

ODT

F9

ZQ

M1

VREFCA

M2

BG0

N9

TEN

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

G2

DQ0

F7

DQ1

H3

DQ2

H7

DQ3

H2

DQ4

H8

DQ5

J3

DQ6

J7

DQ7

A3

DQ8

B8

DQ9

C3

DQ10

C7

DQ11

C2

DQ12

C8

DQ13

D3

DQ14

D7

DQ15

B7

UDQS_T

A7

UDQS_C

G3

LDQS_T

F3

LDQS_C

E2

E7

K3

ODT

F9

ZQ

M1

VREFCA

M2

BG0

N9

TEN

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

C1361

C1362

C1360

1

DY

2

Do Not Stuff

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

M_B_ODT0

B_ZQ_RAM2

M_VREF_CA_D IMMB

M_B_BG0

TEST_MODE_5

M_B_PARITY

M_B_BG1_E9_1

M_B_BG1_M9_R

M_B_DQ46

M_B_DQ41

M_B_DQ47

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ43

M_B_DQ40

M_B_DQ35

M_B_DQ36

M_B_DQ39

M_B_DQ34

M_B_DQ32

M_B_DQ37

M_B_DQ38

M_B_DQ33

M_B_DQS_DP4

M_B_DQS_DN4

M_B_DQS_DP5

M_B_DQS_DN5

M_B_ODT0

B_ZQ_RAM4

M_VREF_CA_D IMMB

M_B_BG0

TEST_MODE_6

M_B_PARITY

M_B_BG1_E9_3

M_B_BG1_M9_R

C1363

C1364

1

DY

2

3

1D2V_S3

1

R1301 240R2D-GP

1

C1301 SCD047U25V2KX -4-GP

2

1D2V_S3

1

R1305 240R2D-GP

1

C1343 SCD047U25V2KX -4-GP

2

C1366

C1365

1

DY

2

Do Not Stuff

SC1U10V2KX-1D LGP

2

C1367

SDP & DDP SETTING

M_B_BG1

1

R1339 0R2J-L-GP

DDP

1

R1340 Do Not Stuff

SDP

R1331~R1334 (RO13)(20170911)(DEL: R1335~R1338) DDP: 240 ohm (64.24005.6DL) SDP: 0 ohm (63.R0034.L0L)

M_B_BG1_E9_1

R1331 240R2F-1-GP

M_B_BG1_E9_2

R1332 240R2F-1-GP

M_B_BG1_E9_3

R1333 240R2F-1-GP

M_B_BG1_E9_4

R1334 240R2F-1-GP

TEST_MODE_5

1

0D6V_VREF_S0

VTT 10uF x4

C1376

1

2

SC10U6D3V3MX- DL-GP

Do Not Stuff

2D5V_S3

C1371

1

2

SC10U6D3V3MX- DL-GP

Do Not Stuff

SC10U6D3V3MX- DL-GP

1D2V_S3

1

2

1

2

1D2V_S3

C1390

1

DY

2

TP1301 Do Not Stuff

TP1303 Do Not Stuff

TP1304 Do Not Stuff

TP1302 Do Not Stuff

C1377

1

2

VPP 10uF x5

C1372

1

2

C1304

DY

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1320

DY

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1391

1

2

Do Not Stuff

SC10U6D3V3MX- DL-GP

TEST_MODE_7

TEST_MODE_8

TEST_MODE_6

C1369

C1368

1

DY

2

1

C1378

1

2

C1373

1

2

VDDQ/VDD 1uF x32

C1305

1

2

C1321

1

2

C1392

1

DY

2

M_B_BG1_M9_R

2

DDP/SDP

2

DDP/SDP

2

DDP/SDP

2

DDP/SDP

CLK

M_B_CLK0

M_B_CLK#0

C1379

1

DY

2

C1374

C1375

1

DY

2

C1308

C1306

C1307

1

DY

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

C1324

C1323

C1322

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

VDDQ/VDD 10uF x10

C1394

C1395

C1393

1

DY

2

1D2V_S3

1

R1320 1K8R2F-GP

2

M_VREF_CA_D IMMB

2

R1321 1K8R2F-GP

1

close to CPU

M_B_CLK0

??? Check with RO

ALERT

M_B_ALERT_N

1

R1313 33R2F-3-GP

1

R1314 33R2F-3-GP

C1310

C1309

1

2

C1325

C1326

1

DY

2

C1397

C1396

1

2

Do Not Stuff

SC10U6D3V3MX- DL-GP

Do Not Stuff

SC10U6D3V3MX- DL-GP

1

DY

2

DY

Do Not Stuff

1

49D9R2F-GP

2

C1311

C1327

DY

C1398

C1388

2

1

DY

R1330

2

C1312

1

2

SC1U10V2KX-1D LGP

C1328

1

2

Do Not Stuff

SC1U10V2KX-1D LGP

C1399

1

2

R1302

1

2D7R2F-1-G P

M_B_CLK#0

M_B_CLK

C1313

1

2

C1329

1

2

V_SM_VREF_CN TB

2

1

C1302 SCD022U16V2KX -3DLGP

2

+V_VREF_PATH 2

1

R1303 24D9R2F-L-G P

2

1D2V_S3

C1370

2

1

SCD01U50V2KX- 1DLGP

C1315

C1314

C1316

1

2

C1330

1

2

1

2

SC1U10V2KX-1D LGP

C1331

C1332

1

2

SC1U10V2KX-1D LGP

Do Not Stuff

SC1U10V2KX-1D LGP

Title

Size Document Num ber Rev

A2

Thursday, July 19, 2018

Date: Sheet

1

M_B_BG1_M9_R

R1312 36R2F-1-G PDDP

M_B_ODT0

R1311 36R2F-1-G P

M_B_BG0

M_B_A14

M_B_A15

M_B_CS#0

M_B_A6

M_B_A5

M_B_A4

M_B_BA1

M_B_PARITY

M_B_A13

M_B_A9

M_B_A0

M_B_CKE0

M_B_A10

M_B_A16

M_B_ACT_N

M_B_BA0

M_B_A1

M_B_A12

M_B_A3

M_B_A8

M_B_A11

M_B_A2

M_B_A7

C1319

C1317

C1318

1

2

C1334

C1335

C1333

1

DY

2

DDR3-SODIMM1

KR CS MLK 13"

1

0D6V_VREF_S0

2

1

2

1

RN1302

8

1

7

2

6

3

5

4

SRN36J-GP

RN1303

8

1

7

2

6

3

5

4

SRN36J-GP

RN1304

8

1

7

2

6

3

5

4

SRN36J-GP

RN1305

8

1

7

2

6

3

5

4

SRN36J-GP

RN1306

8

1

7

2

6

3

5

4

SRN36J-GP

RN1307

8

1

7

2

6

3

5

4

SRN36J-GP

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

Taipei Hsie n 221, Taiwan, R.O.C .

13 106

of

13 106

of

13 106

of

A00

D

C

B

A

5

4

3

2

1

D

C

D

C

(Blanking)

A00

B

A

B

Wistron Corporation

A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

KR CS MLK 13"

14 106Thursday, July 19, 2018

1

of

Main Func = PCH

SPKR[19,27] NRB_BIT[20]

CPU_SMB_ALER T#[18]

GPP_B22_GSP I1_MOSI[20]

CPU_SMB_ALER T#_P0[18]

SPI_SI_CPU[18,25,91]

RTC_DET#[20,25]

CPU_SMB_ALER T#_P1[18]

SPI_WP_CPU[18,25]

SPI_HOLD_C PU[18,25]

HDA_SDOUT_C PU[1 9]

GPP_H17_ST RAP[4]

GPP_H21[21]

CNV_RGI_DT[20]

INPUT3VSEL[17]

GPD_7[21]

GPP_H23[21]

CFG3[6]

D

CFG4[6]

5

SPKR

1

R1501 Do Not Stuff

DY

2

4

3D3V_S5_PC H

1

R1502 Do Not Stuff

DY

2

NRB_BIT

GPP_B18

1

R1503 Do Not Stuff

DY

2

3

3D3V_S5_PC H

20180301 Stuff R1551

1

R1551 4K7R2J-2-GP

2

CPU_SMB_ALER T#

GPP_C2

1

20180207

R1552 Do Not Stuff

DY

2

GPP_B22_GSP I1_MOSI

GPP_B22

1

R1553 Do Not Stuff

DY

2

20180207

1

D

3D3V_S5_PC H

1

R1504 4K7R2J-2-GP

2

CPU_SMB_ALER T#_P0

GPP_C5

1

R1505 Do Not Stuff

DY

2

C

B

3D3V_S5_PC H

1

R1508 100KR2F-L1 -GP

2

SPI_WP_CPU

SPI0_IO2 SPI0_IO3

1

R1509 Do Not Stuff

DY

2

1D8V_S5

1

R1515 20KR2J-L2 -GP

2

CNV_RGI_DT

1

R1516 Do Not Stuff

DY

2

20180207

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

CFG3

1

R1517 Do Not Stuff

DY

2

GPP_F6/CNV_RGI_DT

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

An external Display Port device is connected to the Embedded Display Port. 1 : DISABLED (Default)

No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

3D3V_S5_PC H

1

R1506 100KR2F-L1 -GP

2

SPI_SI_CPU

SPI0_MOSI

1

R1507 Do Not Stuff

DY

2

3D3V_S5_PC H

1

R1510 100KR2F-L1 -GP

2

SPI_HOLD_C PU

1

R1511 Do Not Stuff

DY

2

3D3V_VCCDSW

1

R1519 Do Not Stuff

DY

2

INPUT3VSEL

1

R1520 4K7R2J-2-GP

2

CFG4

1

R1518 1KR2J-1-GP

2

3D3V_S5_PC H

1D8V_VCCPRIM

DY

1

2

1

2

1

DY

2

R1512 Do Not Stuff

HDA_SDOUT_C PU

1

DY

2

3D3V_VCCDSW

R1554 20KR2J-L2 -GP

RTC_DET#

R1521 Do Not Stuff

20180207

GPP_H17_ST RAP

R1527 Do Not Stuff

CPU_SMB_ALER T#_P1

GPP_B23

1

R1555 Do Not Stuff

GPP_D12

20180207

DY

2

20170207

C

HDA_SDO/I2S0_TXD

GPP_H17

20180207

1

R1524 100KR2F-L1 -GP

2

GPD_7

1

R1525 Do Not Stuff

DY

2

20180207

3D3V_S5_PC H

DY

1

R1522 4K7R2J-2-GP

2

1

R1523 Do Not Stuff

2

3D3V_S5_PC H

DY

GPP_H21

20180207

B

1

R1526 Do Not Stuff

2

GPP_H23

1

R1528 Do Not Stuff

2

A

Wistron Corporation

21F, 88, Sec.1, Hs in Tai Wu Rd ., Hsichih,

Taipei Hsi en 221, Taiw an, R.O.C.

Title

CPU_(CS-2/EMMC)

Size Documen t Number Rev

A0

KR CS MLK 13"

Date: Sheet

5

4

3

2

1

A

A00

of

15 1 06Thursd ay, July 19, 2018

of

15 1 06Thursd ay, July 19, 2018

of

15 1 06Thursd ay, July 19, 2018

SSID= PCH

USB1_USB30_RX _N[66]

USB1_USB30_RX _P[66]

USB1_USB30_TX _N[66]

USB1_USB30_TX _P[66]

USB2_USB30_RX _N[35]

USB2_USB30_RX _P[35]

USB2_USB30_TX _N[35]

USB2_USB30_TX _P[35]

D

USB4_USB30_RX _N[71]

USB4_USB30_RX _P[71]

USB4_USB30_TX _N[71]

USB4_USB30_TX _P[71]

USB4_USB20_N[72]

USB4_USB20_P[72]

USB1_USB20_N[66]

USB1_USB20_P[66]

USB2_USB20_N[36]

USB2_USB20_P[36]

CCD_USB20_ N[55]

CCD_USB20_ P[55]

CARD1_USB 20_N[66]

CARD1_USB 20_P[66]

BT_USB20_N[66]

BT_USB20_P[66]

FP1_USB20_N[92]

FP1_USB20_P[92]

USB_OC0#[66]

C

B

USB_OC1#[36]

USB_OC3#[72]

SSD_DEVSLP[63]

M2_SSD_PEDET[63]

PCH_SATA_LED #[64]

WLAN_PC IE_RX_N[66]

WLAN_PC IE_RX_P[66]

WLAN_PC IE_TX_CON_N[66]

WLAN_PC IE_TX_CON_P[66]

SSD_PCIE_RX_N 3[63]

SSD_PCIE_RX_P3[63]

SSD_PCIE_TX_N3[63]

SSD_PCIE_TX_P3[63]

SSD_PCIE_RX_N 2[63]

SSD_PCIE_RX_P2[63]

SSD_PCIE_TX_N2[63]

SSD_PCIE_TX_P2[63]

SSD_PCIE_RX_N 1[63]

SSD_PCIE_RX_P1[63]

SSD_PCIE_TX_N1[63]

SSD_PCIE_TX_P1[63]

SSD_SATA_RX _N[63]

SSD_SATA_RX _P[63]

SSD_SATA_TX_N[63]

SSD_SATA_TX_P[63]

USB3.0

USB2.0

PCIE

5

OPTANE MEMORY

WLAN

SSD

4

#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.

WLAN_PC IE_TX_CON_N

WLAN_PC IE_TX_CON_P

2

1

C6107 SC D1U25V2KX-1- DL-GP

2

1

C6108 SC D1U25V2KX-1- DL-GP

2

1

R1604 100R2F-L1-G P-U

WLAN_PC IE_RX_N

WLAN_PC IE_RX_P

WLAN_PC IE_TX_N

WLAN_PC IE_TX_P

SSD_PCIE_RX_N 3

SSD_PCIE_RX_P3

SSD_PCIE_TX_N3

SSD_PCIE_TX_P3

SSD_PCIE_RX_N 2

SSD_PCIE_RX_P2

SSD_PCIE_TX_N2

SSD_PCIE_TX_P2

SSD_PCIE_RX_N 1

SSD_PCIE_RX_P1

SSD_PCIE_TX_N1

SSD_PCIE_TX_P1

SSD_SATA_RX _N

SSD_SATA_RX _P

SSD_SATA_TX_N

SSD_SATA_TX_P

PCIE_RCOMPN

PCIE_RCOMPP

3

(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.

8 OF 20CPU1H

USB1_USB30_RX _N

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10

USB2P_10

USB2_COMP

USB_ID

RSVD#AR3

CB5

USB1_USB30_RX _P

CB6

USB1_USB30_TX _N

CA4

USB1_USB30_TX _P

CA3

USB2_USB30_RX _N

BY8

USB2_USB30_RX _P

BY9

USB2_USB30_TX _N

CA2

USB2_USB30_TX _P

CA1

BY7

BY6

BY4

BY3

USB4_USB30_RX _N

BW6

USB4_USB30_RX _P

BW5

USB4_USB30_TX _N

BW2

USB4_USB30_TX _P

BW1

USB1_USB20_N

CE3

USB1_USB20_P

CE4

USB2_USB20_N

CE1

USB2_USB20_P

CE2

CG3

CG4

USB4_USB20_N

CD3

USB4_USB20_P

CD4

FP1_USB20_N

CG5

FP1_USB20_P

CG6

CCD_USB20_ N

CC1

CCD_USB20_ P

CC2

CARD1_USB 20_N

CG8

CARD1_USB 20_P

CG9

CB8

CB9

CH5

CH6

BT_USB20_N

CC3

BT_USB20_P

CC4

CC5

USBCOMP

USB2_ID

CE8

USB2_VBUSSEN SE

CC6

USB_OC0#

CK6

USB_OC1#

CK5

USB_OC2#

CK8

USB_OC3#

CK9

CP8

SIO_EXT_SCI#

CR8

SSD_DEVSLP

CM8

GPP_E0/SATAXPC IE0/SATAGP0

CN8

GPP_E1/SATAXPC IE1/SATAGP1

CM10

M2_SSD_PEDET

CP10

PCH_SATA_LED #

CN7

AR3

20180115 Remove by Jerry

USB2_ID

USB2_VBUSSEN SE

Follow SKL PDG design guide

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2_CFG0

CP28

GPP_H13/M2_SKT2_CFG1

CN28

GPP_H14/M2_SKT2_CFG2

CM28

GPP_H15/M2_SKT2_CFG3

WHISKEY-LAKE- GP

Layout Note:

1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) Note: Must maintain low DC resistance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent high speed I/O.

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the motherboard. Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

USB_VBUSSENSE

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0

GPP_E5/DEVSLP1

GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

USB 2.0 Table

Pair

Device

USB3.0 port1

1

N/A

2

USB3.0 Port2 (IOBD)

3

Type-c

4

CAMERA

5

WLAN

6

Touch Panel

7

8

Card Reader

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

IO board USB3.0

RO13_20170811 follow HSIO MAP

MB USB3.0

USB3.0 Type C

IO board USB3.0

MB USB3.0

USB3.0 Type C

Fingerprint Reader

CAMERA

Card Reader

WLAN (BT)

IO USB3

TYPEC

2016/12/28

2

1

R1601 Do Not Stuff

DY

2

1

R1602 Do Not Stuff

DY

2

(#543611) The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.

3D3V_S0

PCH_SATA_LED #

SIO_EXT_SCI#

(#543016) When used as DEVSLP, no external pull-up or pull-down termination required from SATA Host DEVSLP.

USB_OC3#

USB_OC2#

USB_OC1#

USB_OC0#

20180221 Add PH res for GPP_E0

GPP_E0/SATAXPC IE0/SATAGP0

GPP_E1/SATAXPC IE1/SATAGP1

USBCOMP

20180604 Add PH res for GPP_E1

R1603 113R2F-GP

1

R1606 10KR2J-3-GP

1

R1608 10KR2J-3-GP

RN1601

8

7

6

5

SRN10KJ-6-G P

RN1602

1

2

SRN100KJ-6-G P

1

2

3D3V_S5_PCH

1

2

3

4

3

2

1

D

3D3V_S0

C

B

A00

A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

A2

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C .

CPU_(PCIE/SATA/USB)

KR CS MLK 13"

1

16 106Thursday, July 19, 2018

of

16 106Thursday, July 19, 2018

of

16 106Thursday, July 19, 2018

of

SSID = PCH

SYS_PWROK[24]

RESET_OUT#[24,26]

VCCST_PWRGD[24,40]

PCH_RSMRST#[24]

D

C

3V_5V_PWRGD[25,40,45]

PM_SLP_S0#[40,91]

PM_SLP_S3#[40,51]

PM_SLP_S4#[40,53]

AUX_EN_WOW L[24,61]

SIO_PWRBTN#[24]

AC_IN#[43,44]

PLTRST#_CPU[26,63,66,91]

H_CPUPW RGD[3]

INPUT3VSEL[15]

3D3V_VCCDSW

1

R1721 10KR2J-3-GP

2

PCH_BATLOW#

1

R1722 Do Not Stuff

DY

2

RO13_20171027 PCH_BATLOW# Software set GPD0 avoid PCH

󰵖󲋮

RN1704.6 PU

󲕸󱘩󳀃

layout

5

󱮵󱽰

BATLOW# PU

󴲹󰵖󴾗󱌄

3D3V_VCCDSW

RN1701

1

2

GPD11 pull high by Intel PDG1.3 request

3D3V_S5

RTC_AUX_S5

SRN10KJ-5-GP

1

R1703 10KR2J-3-GP

1

R1730 330KR2J-L1-GP

#544669 (CRB): 330k.

3D3V_VCCPRIM

1

R1731 100KR2F-L1-GP

1D8V_VCCPRIM

1

R1738

DY

Do Not Stuff

RN1703

1

2

SRN10KJ-5-GP

1

R1717 10KR2J-3-GP

1

R1714

DY

󲙌󲹘󵙄

Do Not Stuff

AOZ Power switch, P/N: 074.01334.0093 Low Rds(on)= 5m Ohm Turn on rise time = 10us

#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.

AC_PRESENT

4

PCIE_WAKE#_CPU

3

2

GPD11/LANPHYPC

SM_INTRUDER#

2

EXT_PW R_GATE#

2

ME_SUS_PWR_ACK_R

2

PM_RSMRST#

4

PM_PCH_PWROK

3

SYS_PWROK

2

20180410 Stuff R1717

H_CPUPW RGD

2

4

3D3V_VCCPRIM

1

R1701 10KR2J-3-GP

XDP_DBRESET#

RESET_OUT#

PM_RSMRST#

3D3V_VCCDSW

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

R1706 Do Not Stuff

R1704 Do Not Stuff

RO13_20171001

1

ED1702

3

AZ5125-02S-R7G-GP

75.05125.07D

2

1

2

1

2

1

R1707 10KR2J-3-GP

2

1

2

ED1701

3

AZ5125-02S-R7G-GP

75.05125.07D

3

PCH_PLTRST#

PM_RSMRST#

H_CPUPW RGD

VCCST_PWRGD_R

SYS_PWROK

PM_PCH_PWROK

PCH_DPW ROK

ME_SUS_PWR_ACK_R

SUSACK#_R

PCIE_WAKE#_CPU

LAN_WAKE#

GPD11/LANPHYPC

1

2

DY

ED1703

3

Do Not Stuff

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPWRDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHISKEY-LAKE-GP

SYS_PWROK

PLTRST#_CPU

3V_5V_PWRGD

RESET_OUT#

XDP_DBRESET#

1

EC1706

DY

Do Not Stuff

2

11 OF 20CPU1K

GPP_B12/SLP_S0#

GPD4/SLP_S3#

GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SPL_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

INPUT3VSEL

BATLOW#: Pull-up required even if not implemented.

RO13_20171027 PCH_BATLOW# Software set GPD0 avoid

AC_PRESENT

ME_SUS_PWR_ACK_R

PLTRST#_CPU

DY

R1708 Do Not Stuff

1

R1715

Do Not Stuff

1

DY

2

PM_SLP_S0#

BJ37

PM_SLP_S3#

BU36

PM_SLP_S4#

BU27

BT29

BU29

BT31

AUX_EN_WOW L

BT30

BU37

SIO_PWRBTN#

BU28

AC_PRESENT

BU35

PCH_BATLOW#

BV36

SM_INTRUDER#

BR35

EXT_PW R_GATE#

CC37

CC36

VRALERT#

BT27

INPUT3VSEL

󱮵󱽰

BATLOW# PU

EC1707

Do Not Stuff

1

DY

1

DY

1

R1713 Do Not Stuff

C1701

Do Not Stuff

󲙌󲹘󵙄

2

TP1708 Do Not Stuff

1

SUSACK#_R

1

D

C

PCH_PLTRST#

A00

B

A

B

3D3V_AUX_S5

2

1

R1727 100KR2J-1-GP

1

R1726 10KR2J-3-GP

2

3V_5V_POK#

A

Q1701

1

S1

2

G1

D2

3

PJT138KA-GP

075.00138.0A7C

NON DS3 function

3D3V_AUX_S5

1

R1737 100KR2J-1-GP

5

D1

G2

S2

6

5

4

PM_RSMRST#_M

2

PM_RSMRST#

3V_5V_POK_C

R1702 1KR2J-1-GP

R1728 Do Not Stuff

RO13_20171011 common part

1

2

3

2N7002KDW-1-GP

75.27002.F7C

1

Q1702

Note:ZZ.27002.F7C01

6

5

4

2

D1701

A

RB520S30-GP

83.R2003.A8M

2

1

PCH_RSMRST#

3V_5V_PWRGD

1

C1710

DY

Do Not Stuff

2

Dummy C1710 by it's useless

AC_IN#

K

AC_PRESENT

PM_RSMRST#

4

Power Sequence

20180409 Modify RC for power sequencing

VCCST_PWRGD

VCCST_PWRGD_R

3

DY

1

2

EC1712 Do Not Stuff

RO13_20171001

2

DY

ED1704

3

Do Not Stuff

3D3V_S0

1

R1718 Do Not Stuff

DY

2

1

R1716 100KR2F-L1-GP

1

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST.

1

R1719 47KR2F-GP

2

Dis-wire with XDP_PM_RSMRST_PWRGD_XDP

VCCST_PWRGD_R

1

C1711 SCD022U16V2KX-3DLGP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(POWER MANAGEMENT)

Size Document Number Rev

A3

Date: Sheet

KR CS MLK 13"

1

17 106Thursday, July 19, 2018

of

17 106Thursday, July 19, 2018

of

17 106Thursday, July 19, 2018

of

SSID = PCH

WLAN_CLK _CPU_N[66]

WLAN_CLK _CPU_P[66]

WLAN_CLK REQ_CPU_N[66]

SSD_CLK_CPU _N[63]

SSD_CLK_CPU _P[63]

SSD_CLKREQ _CPU_N[63]

SPI_SO_CPU[25,91]

SPI_CLK_CPU[25,91]

SPI_SI_CPU[15,25,91]

SPI_CS_CPU_N0[25]

SPI_CS_CPU_N2[91]

D

SPI_HOLD_CPU[15,25]

SPI_WP_CPU[15,25]

ESPI_CPU_IO[3..0][24,68]

CPU_SMB_SCL_ P1[24,26]

CPU_SMB_SDA _P1[24,26]

ESPI_CS#[2 4,68]

ESPI_RESET#[24,68]

ESPI_CLK[2 4,68]

SUS_CLK[24]

TPM_SPI_IRQ#[91]

RTCRST_O N[2 4,25]

CPU_SMB_ALER T#[15]

CPU_SMB_ALER T#_P0[15]

CPU_SMB_ALER T#_P1[15]

PROJECT_ID0[21]

FFS_INT1[70]

C

5

ESPI_CPU_IO3

ESPI_CPU_IO1

ESPI_CPU_IO2

ESPI_CPU_IO0

20180222 Modify PH power

3D3V_S0

20180226 DY R1820

1

R1820 Do Not Stuff

DY

1D8V_VCCPR IM

1

R1821 10KR2J-3-G P

SERIRQ PH: PDG: 8.2k CRB: 10k

For eSPI

PCH strap pin:

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SIO_RCIN#

2

ESPI_ALERT#

2

CPU_SMB_ALERT#_P0

Sampled at rising edge of RSMRST#

eSPI or LPC

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

4

SPI_CLK_CPU

SPI_SO_CPU

SPI_SI_CPU

SPI_WP_CPU

SPI_HOLD_CPU

SPI_CS_CPU_N0

SPI_CS_CPU_N2

TPM_SPI_IRQ#

FFS_INT1

CPU_D4_TP

1

TP1804Do Not Stuff

PROJECT_ID0

CPU_D6_TP

1

TP1806Do Not Stuff

20180115 Remove C-Link

SIO_RCIN#

ESPI_ALERT#

RCIN#: Frequency to Avoid: 33 MHz

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

CG34

CG36

CG35

CH34

CF20

CG22

CF22

CG23

CH23

CG20

CH7

CH8

CH9

BV29

BV28

Strap

SPI0_IO2

SPI0_IO3

SPI0_CS0#

SPI0_CS1#

SPI0_CS2#

GPP_D1/SPI1_CLK/BK1/SBK1

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3

GPP_D0/SPI1_CS0#/BK0/SBK0

CL_CLK

CL_DATA

CL_RST#

GPP_A0/RCIN#/TIME_SYNC1

GPP_A6/SERIRQ

WHISKEY-LAKE- GP

PCH strap pin:

SPI_SI_CPU

BOOT HALT

SPI0_MOSI

This signal has a weak internal pull-up.

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

3

5 OF 20CPU1E

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

Strap

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

CPU_SMB_SCL

CK14

CPU_SMB_SDA

CH15

CPU_SMB_ALER T#

CJ15

CPU_SMB_SCL_ P0

CH14

CPU_SMB_SDA _P0

CF15

CPU_SMB_ALER T#_P0

CG15

CPU_SMB_SCL_ P1

CN15

CPU_SMB_SDA _P1

CM15

CPU_SMB_ALER T#_P1

CC34

20180221 Remove R1837 PH res for CPU_SMB_ALERT#_P1

ESPI_CPU_IO0_R

CA29

ESPI_CPU_IO1_R

BY29

ESPI_CPU_IO2_R

BY27

ESPI_CPU_IO3_R

BV27

ESPI_CS#

CA28

ESPI_RESET#

CA27

ESPI_CPU_CLK_R

BV32

BV30

BY30

CLKRUN#

BIOS:GPP_C2 internal pd

ESPI_CPU_CLK_R

2

CPU_SMB_SDA _P1

CPU_SMB_SCL_ P1

CPU_SMB_SDA

CPU_SMB_SCL

CPU_SMB_SDA _P0

CPU_SMB_SCL_ P0

CPU_SMB_ALER T#_P1

For eSPI

ESPI_CPU_IO0

1

ESPI_CPU_IO3

2

ESPI_CPU_IO2

3

ESPI_CPU_IO1

4

2

1

R1805 33R2F-3-G P

RO13_CFLU_20171206

DY

R1801 150KR2J-GP

20180412 Follow RO13

RN1806

8

7

6

5

SRN15J-GP

1

EC1801 Do Not Stuff

2

RN1811

1

2

SRN2K2J-1-G P

RN1807

8

7

6

5

SRN2K2J-4-G P

1

ESPI_CPU_IO0_R

ESPI_CPU_IO3_R

ESPI_CPU_IO2_R

ESPI_CPU_IO1_R

ESPI_CLK

3D3V_S5_PCH

4

3

1

2

3

4

2

CLKRUN#

1

2

1

R1818 Do Not Stuff

R1815

1

X1802

1

XTAL-32D768KH Z-98-GP

082.30003.0301

C1804 SC15P50V2JN-D L-GP

1

20180221 Modify PH power

3D3V_S0

2

DY

2

10MR2J-L-GP

2

XTL_32K_X1_CPU

XTL_32K_X2_CPU

1

C1803 SC15P50V2JN-D L-GP

2

D

C

B

A

3D3V_S0

RN1813 SRN10KJ-6-G P

1

2

3

4

RN1802

1

2

20180601 PH all PCIE CLK REQ

SRN10KJ-5-G P

WLAN_CLK REQ_CPU_N

8

CARD_CLKR EQ_CPU_N

7

CLK_PCIE_PEG_RE Q0_N

6

CLK_PCIE_PEG_RE Q5_N

5

CLK_PCIE_PEG_RE Q2_N

4

SSD_CLKREQ _CPU_N

3

5

WLAN

SSD

CLK_PCIE_PEG_RE Q0_N

WLAN_CLK _CPU_N

WLAN_CLK _CPU_P

WLAN_CLK REQ_CPU_N

CLK_PCIE_PEG_RE Q2_N

CARD_CLKR EQ_CPU_N

SSD_CLK_CPU _N

SSD_CLK_CPU _P

SSD_CLKREQ _CPU_N

CLK_PCIE_PEG_RE Q5_N

20180221 Modify X1801

XTL_24M_X1_CPU

20180710 Don't change to short-pad

XTL_24M_X2_CPU

AW2

CLKOUT_PCIE_N0

AY3

CLKOUT_PCIE_P0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N1

BC2

CLKOUT_PCIE_P1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N2

BC3

CLKOUT_PCIE_P2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N3

BH4

CLKOUT_PCIE_P3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N4

BA2

CLKOUT_PCIE_P4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N5

BE2

CLKOUT_PCIE_P5

CF31

GPP_B10/SRCCLKREQ5#

WHISKEY-LAKE- GP

2

1

R1839 0R2J-L-GP

2

1

R1840 0R2J-L-GP

4

1

2

R1841 1MR2J-1-GP

XTL_24M_X1_R

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

CLKIN_XTAL

XTL_24M_X2_R

10 OF 20CPU1J

AU1

AU2

BT32

CK3

XTAL_IN

CK2

XTAL_OUT

CJ1

CM3

BN31

RTCX1

BN32

RTCX2

BR37

SRTCRST#

BR34

RTCRST#

C1807 SC 15P50V2JN-D L-GP

3

4

2

1

C1808 SC 15P50V2JN-D L-GP

XDP_CLK_CPU _N

XDP_CLK_CPU _P

SUS_CLK

XTL_24M_X1_CPU

XTL_24M_X2_CPU

XCLK_BIASREF

XTL_32K_X1_CPU

XTL_32K_X2_CPU

SRTC_RST #

RTC_RST#

2

1

X1801 XTAL-24MHZ- 182-GP

082.30006.0531

2

1

TP1808 Do Not Stuff

TP1807 Do Not Stuff

1

R1803 60D4R2F-GP

RO13_CFLU_20171206

2

3

For RTC Gen 9 reset circuit need DY 20170814

RTCRST_O N

NON_RTC_RST

1

R1816

Do Not Stuff

EC1804

Do Not Stuff

1

DY

2

Q1802

G

D

NON_RTC_RST

S

Notice:ZZ.2N70 2.J3101

Do Not Stuff

(#514849)

Layout: Place at the open door area.

2

1

G1801

C1806

2

1

SC1U10V2KX-1DLGP

2

RTC_AUX_S5

Do Not Stuff

2

1

RN1801 SRN20KJ-1-G P

4

3

1

C1805 SC1U10V2KX-1D LGP

2

2017/03/17

SUS_CLK

FC1801

Do Not Stuff

EC1803

Do Not Stuff

1

DY

2

RO13_20171026 FC1801 close to EC1803

SRTC_RST #

RTC_RST#

1

2

ED1801

DY

Do Not Stuff

3

RO13_20171001 EMI request

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

Taipei Hsie n 221, Taiwan, R.O.C .

Title

CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Num ber Rev

A2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C .

KR CS MLK 13"

1

B

A

A00

18 106Thursday, July 19, 2018

A00

of

SSID = PCH

SPKR[15,27]

HDA_SDIN0_CPU[27]

HDA_SYNC_CODEC[27]

HDA_BITCLK_CODEC[27]

D

HDA_SDOUT_CODEC[27]

HDA_SDOUT_CPU[15]

KB_LED_BL_DET[65]

ME_FWP[98]

DMIC_SCL_PCH[55]

DMIC_SDA_PCH[55]

C

5

4

3

2

1

Strap pin:

Port B / Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected. 1 = Port B is detected.

*

0 = Port C is not detected. 1 = Port C is detected.

*

These two signals have weak internal pull-down.

3D3V_S5

1

R1910 10KR2J-3-GP

fTPM

2

TPM_ID

1

R1911 Do Not Stuff

TPM

2

RO13_20171027 delete ED1901

EC1901

Do Not Stuff

HDA_SDOUT_CODEC

1

EC1903

DY

Do Not Stuff

2

1

DY

HDA_BITCLK_CODEC

2

HDA_SYNC_CPU

HDA_BITCLK_CPU

BIOS:HDA_SDO Internal PD

Do Not Stuff

TP1903

HDA_SDOUT_CPU

HDA_SDIN0_CPU

HDA_RST_N_CPU

1

DMIC_SCL_PCH

DMIC_SDA_PCH

TPM_ID

SPKR

R1920~R1921 need to close for merge prepare

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

ME_FWP

R1920 Do Not Stuff

R1921 Do Not Stuff

R1909 1KR2J-1-GP

2

1

2

1

2

1

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHISKEY-LAKE-GP

HDA_BITCLK_CPU

HDA_SDOUT_CPU

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

7 OF 20CPU1G

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_G2/SD_DATA1

GPP_G3/SD_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_1P8_RCOMP

SD_3P3_RCOMP

HDA_SYNC_CODEC

CH36

CL35

CL36

CM35

CN35

CH35

CK36

CK34

BW36

BY31

CK33

CM34

1

R1908 Do Not Stuff

KB_LED_BL_DET

SD_RCOMP

2

RO13_CFLU_20171207

200R2F-L-GP

2

1

R1901

HDA_SYNC_CPU

D

C

A00

B

A

B

A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

A3

Date: Sheet

KR CS MLK 13"

1

19 106Thursday, July 19, 2018

of

19 106Thursday, July 19, 2018

of

19 106Thursday, July 19, 2018

of

SSID = PCH

CPU_I2C_SDA_P1[55]

CPU_I2C_SCL_P1[55]

CPU_I2C_SDA_P0[65]

CPU_I2C_SCL_P0[65]

CPU_I2C_SDA_ISH[55,70]

CPU_I2C_SCL_ISH[55,70]

UART_2_CRXD_DTXD[68]

D

UART_2_CTXD_DRXD[68]

GYRO_INT_C[55]

GYRO_DRDY[55]

GSEN2_INT1_C[70]

GSEN2_INT2_C[70]

FFS_INT2[70]

GSEN_INT1[55]

GSEN_INT2[55]

NRB_BIT[15]

RTC_DET#[15,25]

BOARD_ID2[21]

CNV_RGI_DT[15]

KB_DET#[65]

SIO_EXT_W AKE#[24]

GPP_B22_GSPI1_MOSI[15]

PIRQA#[91]

DBC_PANEL_EN[55]

C

B

IR_CAM_DET#[55]

NB_MODE#[24]

1D8V_S5

1

R2016 Do Not Stuff

DY

2

MEM_CONFIG0

1

R2015 Do Not Stuff

DY

2

1D8V_S5

1

R2011 Do Not Stuff

Micron

2

MEM_CONFIG3

1

R2012 10KR2J-3-GP

Samsung/Hynix

2

5

1D8V_S5

1

R2018 Do Not Stuff

8GB

2

MEM_CONFIG1

1

R2017 10KR2J-3-GP

4GB/16GB

2

1D8V_S5

1

R2013 10KR2J-3-GP

Hynix

2

MEM_CONFIG4

1

R2014 Do Not Stuff

Samsung/Micron

2

3D3V_S0

2

1

R2048 Do Not Stuff

DEBUG

2

1

R2049 Do Not Stuff

DEBUG

2

1

R2043 Do Not Stuff

DY

2

1

R2044 10KR2J-3-GP

R2045 10KR2J-3-GP

R2046 10KR2J-3-GP

R2053 Do Not Stuff

20180221 Modify PH power 20180226 DY res

3D3V_S5_PCH

R2041 10KR2J-3-GP

CNV_BRI_DT

XTAL FREQUENCY SELECTION 1 = 24MHZ 0 = 38.4/19.2MHZ PCH HAS INTERNAL 20K PD

3D3V_S0

1

DY

4

3

4

1D8V_S5

2

RN2007

SRN1KJ-7-GP

RN2008

DY

Do Not Stuff

1

R2029 10KR2J-3-GP

16GB

2

MEM_CONFIG2

1

R2022 Do Not Stuff

4GB/8GB

2

1

R2031 10KR2J-3-GP

2

MEM_CHA_EN

1

R2030 Do Not Stuff

DY

2

1

2

1

4

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

DBC_PANEL_EN

FFS_INT2

KB_DET#

IR_CAM_DET#

PIRQA#

SIO_EXT_W AKE#

Touch panel

CPU_I2C_SDA_ISH0

CPU_I2C_SCL_ISH0

CPU_I2C_SDA_ISH1

CPU_I2C_SCL_ISH1

1D8V_S0

1

R2052 Do Not Stuff

DY

2

1

R2051 Do Not Stuff

DY

2

1D8V_S5

1

R2033 10KR2J-3-GP

2

1

R2032 Do Not Stuff

DY

2

TPAD

GYRO_DRDY_ISH

MEM_CHB_EN

CC27

GPP_B15/GSPI0_CS0#

PIRQA#

VRAM_ID1

NRB_BIT

DBC_PANEL_EN

GPP_B22_GSPI1_MOSI

20180330 Follow RO13

CNV_RGI_DT

UART_2_CRXD_DTXD

UART_2_CTXD_DRXD

SIO_EXT_W AKE#

KB_DET#

CPU_I2C_SDA_P0

CPU_I2C_SCL_P0

CPU_I2C_SDA_P1

CPU_I2C_SCL_P1

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

MEM_CONFIG4

MEM_CHA_EN

KBLR:GPP_F4~F9: 1.8V only CFLU:GPP_H4~H9: ?V

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHISKEY-LAKE-GP

RAM ID

MEM_CONFIG [0]Vender CapacityMfr. PN

Samsung

NA

Micron

Hynix

Samsung

Micron

NA

NA 10

3

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

Strap

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

GPP_D11/ISH_SPI_MISO/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_D14/ISH_UART0_TXD

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

3D3V_S5

1

R2050 Do Not Stuff

2IN1

2

NB_MODE#

1

R2004 Do Not Stuff

DY

2

MEM_CONFIG[1:2] MEM_CONFIG[3:4]

01 00 K4AAG165WB-MCRC

10 00

10

01Hynix

2

6 OF 20CPU1F

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1

GPP_A20/ISH_GP2

GPP_A21/ISH_GP3

GPP_A22/ISH_GP4

GPP_A23/ISH_GP5

CN22

CR22

IR_CAM_DET#

CM22

RTC_DET#

CP22

CPU_I2C_SDA_ISH0

CK22

CPU_I2C_SCL_ISH0

CH20

CPU_I2C_SDA_ISH1

CH22

CPU_I2C_SCL_ISH1

CJ22

MEM_CHB_EN

CJ27

CJ29

CM24

VRAM_ID2

CN23

CM23

CR24

BOARD_ID1

CG12

FFS_INT2

CH12

CF12

CG14

ISH_KB_DISABLE

BW35

GSEN_INT1

BW34

GSEN_INT2

CA37

GSEN2_INT1_ISH

CA36

GSEN2_INT2_ISH

CA35

GYRO_INT_ISH

CA34

GYRO_DRDY_ISH

BW37

3D3V_S5

1

R2003 Do Not Stuff

2IN1

2

KB_DISABLE_CPU_R

MT40A1G16KNR-075E

H5ANAG6NAMR-UHC01 01

K4A8G165WB-BCRC

MT40A512M16LY-075E

H5AN8G6NAFR-UHC

1

RO13_20170721

S1

G1

D2

GSEN2_INT1_C

GSEN2_INT2_C

GYRO_INT_C

GYRO_DRDY

1

ISH_KB_DISABLE

2

NB_MODE#

3

CPU_I2C_SDA_ISH

CPU_I2C_SCL_ISH

2

1

R2021 Do Not Stuff

DY

2

1

R2020 Do Not Stuff

DY

KBLR:GPP_F10~F11: 1.8V only CFLU:GPP_H10~H11: ?V

remove TP2012 TP2014 TP2016 TP2017 and net. 20131031

20180416 BOM control

2

1

R2001 Do Not Stuff

FFS

2

1

R2002 Do Not Stuff

FFS

2

1

R2027 Do Not Stuff

DY

2

1

R2028 Do Not Stuff

FFS

Vth(max)=1.1V

Q2001

6

D1

5

G2

2IN1

4

S2

Do Not Stuff

Wistron PN

VK98W$BA

VK98W$ABNA

VK98W$CA

4YVD1$CA

4YVD1$BB

4YVD1$AA

D

C

16G01 10

B

8G

3D3V_S0

1

R2010 Do Not Stuff

DY

2

A

BOARD_ID1

1

R2009 10KR2J-3-GP

2

20180207 R2009 for WHLU R2008 for CLAM

5

3D3V_S0

1

2IN1

2

1

CLAM

2

R2005 Do Not Stuff

BOARD_ID2

R2008 10KR2J-3-GP

3D3V_S0

1

2

1

DY

2

R2035 10KR2J-3-GP

R2034 Do Not Stuff

20180207 R2035, R2038 for UMA

VRAM_ID1

3D3V_S0

1

2

1

DY

2

R2038 10KR2J-3-GP

VRAM_ID2

R2037 Do Not Stuff

4

Samsung

Micron

Hynix

VRAM_ID[2:1] dGPU VRAM size

NA

00

10

01

K4A4G165WE-BCRC

MT40A256M16GE-083E

H5AN4G6NBJR-UHC

11 UAM Board 10

N/A

Title

01

DIS Board with 4GB VRAM

00

DIS Board with 2GB VRAM

3

2

Title

Size Document Number Rev

A3

Date: Sheet

M9J68$BA

M9J68$AA

M9J68$CA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(LPSS/ISH)

KR CS MLK 13"

1

4G

A

A00

20 106Thursday, July 19, 2018

of

20 106Thursday, July 19, 2018

of

20 106Thursday, July 19, 2018

of

A00

5

4

3

2

1

SSID = PCH

TOUCH_DETECT[55]

BLUETOOTH_EN[66]

D

GPPC_H18_VCCIO_LPM[40]

C

WIFI_RF_EN[66]

BOARD_ID2[20]

PROJECT_ID0[18]

GPP_H21[15]

GPP_H23[15]

GPD_7[15]

SPK_ID[29]

3D3V_S0

1

R2107 Do Not Stuff

1

R2109 Do Not Stuff

1

R2110 Do Not Stuff

TOUCH_DETECT

2

DY

2

DY

2

DY

R2101 150R2F-1-GP

1

R2102 Do Not Stuff

WIFI_RF_EN

BLUETOOTH_EN

SPK_ID

20180222 DY

DY

2

1

CNV_WT_RCOMP

PROJECT_ID1

PROJECT_ID2

SPK_ID

BLUETOOTH_EN

TOUCH_DETECT_R

BOARD_ID2

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP#CP32

CR32

CNV_WT_RCOMP#CR32

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHISKEY-LAKE-GP

9 OF 20CPU1I

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC0

GPP_H21

GPP_H22

GPP_H23

GPP_F10

GPD7

GPP_F3

GPP_D4/IMGCLKOUT0/BK4/SBK4

GPP_H20/IMGCLKOUT1

GPP_F12/EMMC_DATA0

GPP_F13/EMMC_DATA1

GPP_F14/EMMC_DATA2

GPP_F15/EMMC_DATA3

GPP_F16/EMMC_DATA4

GPP_F17/EMMC_DATA5

GPP_F18/EMMC_DATA6

GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

GPPC_H18_BOOTMPC

CN27

CM27

GPP_H21

CF25

CN26

GPP_H23

CM26

CK17

GPD_7

BV35

PROJECT_ID3

CN20

WIFI_RF_EN

CG25

CH25

CR20

CM20

CN19

CM19

GPP_F: VCCPGPPF = 1.8V Only

CN18

CR18

CP18

CM18

CM16

CP16

CR16

CN16

EMMC_RCOMP

CK15

1

R2108 200R2F-L-GP

1

R2119 Do Not Stuff

2

GPPC_H18_VCCIO_LPM

D

C

2

RO13_20171025

PROJECT_ID[3:2] 11: InspironPROJECT_ID[1:0] 01: 7000 Series

1D8V_VCCPRIM

1

B

A

5

R2111 Do Not Stuff

DY

2

1

R2112 10KR2J-3-GP

2

PROJECT_ID1

4

1D8V_VCCPRIM

1

R2113 10KR2J-3-GP

2

PROJECT_ID0

1

R2114 Do Not Stuff

DY

2

3

1D8V_VCCPRIM

1

R2115 10KR2J-3-GP

2

PROJECT_ID3

1

R2116 Do Not Stuff

DY

2

1D8V_VCCPRIM

1

R2117 10KR2J-3-GP

2

PROJECT_ID2

1

R2118 Do Not Stuff

DY

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(POWER1)

Size Document Number Rev

A4

Date: Sheet

2

CPU_(POWER1)

KR CS MLK 13"

21 106Thursday, July 19, 2018

1

of

A00

B

A

SSID = PCH

D

RO13_CFLU_20171208 RVP_CRB: +VCCPRIM_CORE

RO13_CFLU_20171211 VCCDSW_1P05 (BT24): PCH internal VRM

C

3D3V_VCCDSW

B

3D3V_VCCPRIM

C2202

SC1U10V2KX-1DLGP

1

2

1D0V_VCCAMPHYPLL

C2208

Do Not Stuff

1

DY

2

A

2

5

1D0V_S5

1D0V_VCCPRIM_MPHY

1D0V_VCCAMPHYPLL

1

2

1D0V_VCCPRIM_MPHY

C2203

SC1U10V2KX-1DLGP

1

2

C2209

SC1U10V2KX-1DLGP

5

RO13_20171107

1D0V_S5

1D8V_VCCPRIM

RO13_CFLU_20171208

3D3V_VCCPRIM

2.57A

EC2201

SCD1U25V2KX-1-DL-GP

DY

1D0V_S5

C2205

1

2

C2223

1

2

SC1U10V2KX-1DLGP

1

2

1D0V_VCCDSW

RO13_CFLU_20171208

3D3V_VCCPRIM

C2224 SC1U10V2KX-1DLGP

C2204

SC1U10V2KX-1DLGP

Layout Note:

22uF: C2208 near BV2 1uF: C2209 near BV2

1

D

C

B

1

R2202

R2203

R2204

R2205

2

RSVD#AA24

RSVD#AA26

RSVD#AB25

RSVD#AC24

RSVD#AC25

RSVD#AC26

RSVD#AD24

RSVD#AD26

RSVD#V25

RSVD#T25

RSVD#A35

RSVD#D34

RSVD#N5

1D0V_VCCA_XTAL

2

1D0V_VCCPRIM_MPHY

2

3D3V_VCCPRTC

2

1D0V_VCCAMPHYPLL

2

1D0V_VCCDSW

C2213

1

2

15 OF 20CPU1O

AA24

AA26

AB25

AC24

AC25

AC26

AD24

AD26

V25

T25

A35

D34

N5

SC1U10V2KX-1DLGP

4

BP20

VCCPRIM_1P05

BW16

VCCPRIM_1P05

BW18

VCCPRIM_1P05

BW19

VCCPRIM_1P05

BY16

VCCPRIM_1P05

CA14

VCCPRIM_1P05

CC15

VCCPRIM_1P8

CD15

VCCPRIM_1P8

CD16

VCCPRIM_1P8

CP17

VCCPRIM_1P8

CB22

VCCPRIM_3P3

CB23

VCCPRIM_3P3

CC22

VCCPRIM_3P3

CC23

VCCPRIM_3P3

CD22

VCCPRIM_3P3

CD23

VCCPRIM_3P3

CP29

VCCPRIM_3P3

BU15

VCCPRIM_CORE

BU22

VCCPRIM_CORE

BV15

Do Not Stuff

VCCPRIM_CORE

BV16

VCCPRIM_CORE

BV18

VCCPRIM_CORE

BV19

VCCPRIM_CORE

BV20

VCCPRIM_CORE

BV22

VCCPRIM_CORE

BW20

VCCPRIM_CORE

BW22

VCCPRIM_CORE

CA12

VCCPRIM_CORE

CA16

VCCPRIM_CORE

CA18

VCCPRIM_CORE

CA19

VCCPRIM_CORE

CA20

VCCPRIM_CORE

CB12

VCCPRIM_CORE

CB14

VCCPRIM_CORE

CB15

VCCPRIM_CORE

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05

BV12

VCCPRIM_MPHY_1P05

BW12

VCCPRIM_MPHY_1P05

BW14

VCCPRIM_MPHY_1P05

BY12

VCCPRIM_MPHY_1P05

BY14

VCCPRIM_MPHY_1P05

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05

BT19

VCCPRIM_1P05

BU18

VCCPRIM_1P05

BU19

VCCPRIM_1P05

BT22

VCCPRIM_1P05

BP22

VCCPRIM_1P05

BV14

VCCPRIM_MPHY_1P05

WHISKEY-LAKE-GP

16 OF 20CPU1P

VCCPRIM_3P3

VCCRTC

VCCPRIM_1P05

DCPRTC

VCCPRIM_1P05

VCCAPLL_1P05

VCCA_BCLK_1P05

VCCAPLL_1P05

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24

VCCDSW_3P3

VCCA_19P2_1P05

VCCPRIM_1P8

VCCPRIM_3P3

GPP_B0/CORE_VID0

GPP_B1/CORE_VID1

CB16

BR23

BY20

BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24

CA24

BY23

CA23

CP25

BT23

BR12

CC18

CC19

CD18

CD19

CP23

BW23

BP23

CB36

CB35

V0.85A_VID0

V0.85A_VID1

3D3V_VCCPRIM

3D3V_VCCPRTC

1D0V_S5

VCCRTCEXT

1D0V_S5

1D0V_VCCA_XTAL

1D24V_VCCDPHY

1D24V_VCCDPHY_EC

3D3V_VCCDSW

1D0V_S5

RO13_CFLU_20171208

1D8V_VCCPRIM

3D3V_VCCPRIM

Do Not Stuff

1

TP2201

1

TP2202

Do Not Stuff

3

RO13_CFLU_20171211 VCCRTCEXT (BP24): PCH internal VRM

1

C2201

DY

Do Not Stuff

2

1D8V_VCCPRIM

1

DY

2

K12

K14

K15

K17

K18

K20

L25

M24

M26

P24

P26

R24

R25

R26

V24

W25

Y24

Y25

G2

G1

C34

G3

G4

A34

B35

AJ27

AH26

L5

RO13_CFLU_20171208

1D0V_S5

RO13_20171030

C2210

Do Not Stuff

C2211

SC1U10V2KX-1DLGP

1

2

WHL QS/CFL U/WHL ES1_CNL U22

RSVD#K12

RSVD#K14

RSVD#K15

RSVD#K17

RSVD#K18

RSVD#K20

RSVD#L25

RSVD#M24

RSVD#M26

RSVD#P24

RSVD#P26

RSVD#R24

RSVD#R25

RSVD#R26

RSVD#V24

RSVD#W25

RSVD#Y24

RSVD#Y25

RSVD#G2

RSVD#G1

RSVD#C34

RSVD#G3

RSVD#G4

RSVD#A34

RSVD#B35

RSVD#AJ27

RSVD#AH26

RSVD#L5

WHISKEY-LAKE-GP

Do Not Stuff

RTC_AUX_S5

Do Not Stuff

1D0V_S5

Do Not Stuff

RO13_20171107

SCD1U25V2KX-1-DL-GP

1

2

3D3V_VCCPRTC

1uF: C2202 near BT20 C2203 near BV23 C2204 near BW23 C2205 near CB22 C2206 near CC22 C2207 near CD22

C2222

SC1U10V2KX-1DLGP

C2221

1

2

SCD1U25V2KX-1-DL-GP

1

2

Layout Note:

0.1uF: C2221 near BR23 1uF: C2222 near BR23

4

C2206

1

2

Layout Note:

C2207

RO13_20171107

1D0V_S5

C2212

1

2

SC1U10V2KX-1DLGP

RO13_20171110 KR EC list

C2214

SC1U10V2KX-1DLGP

1

2

Layout Note:

1uF: C2116 near A10 22uF: C2115 near K19 C2119 near N20 C2122 near L19

1D24V_VCCDPHY_EC

1

C2218 SC4D7U6D3V3KX-DLGP

2

RO13_CFLU_20171208 follow CFLU CRB 0.8

3

1D0V_S5

1

2

1D0V_VCCA_XTAL

C2219

SC1U10V2KX-1DLGP

1

2

C2215

SC1U10V2KX-1DLGP

C2216

SC1U10V2KX-1DLGP

1

2

1D0V_VCCPRIM_MPHY

1

2

C2217

SC1U10V2KX-1DLGP

SC22U6D3V3MX-1-DL-GP

C2220

2

Layout Note:

1uF: C2101 near AB19 C2104 near K17 C2116 near A10 C2121 near AL1

Title

Size Document Number Rev

A3

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(RSVD)

KR CS MLK 13"

A

A00

22 106Thursday, July 19, 2018

of

22 106Thursday, July 19, 2018

of

22 106Thursday, July 19, 2018

1

of

A00

5

SSID = PCH

4

3

2

1

18 OF 20CPU1R

CR34

D

C

B

A

5

VSS

BT5

VSS

BY5

VSS

CP35

VSS

CM37

VSS

CK37

VSS

AW1

VSS

CM1

VSS

BD6

VSS

AY4

VSS

B34

VSS

E35

VSS

A4

VSS

AE24

VSS

AE26

VSS

AF25

VSS

AG24

VSS

AG26

VSS

AH24

VSS

AH25

VSS

B2

VSS

B36

VSS

C36

VSS

C37

VSS

CN1

VSS

CN2

VSS

CN37

VSS

CP2

VSS

D1

VSS

A32

VSS

F33

VSS

A3

VSS

BJ7

VSS

CJ36

VSS

A36

VSS

BK10

VSS

CJ4

VSS

AB27

VSS

BK2

VSS

CK1

VSS

AB3

VSS

BK28

VSS

AB30

VSS

BK3

VSS

CK4

VSS

AB33

VSS

BK33

VSS

CK7

VSS

AB36

VSS

BK4

VSS

CL2

VSS

AB4

VSS

BK7

VSS

CM13

VSS

AB7

VSS

BL25

VSS

CM17

VSS

AC10

VSS

BL28

VSS

CM21

VSS

AC27

VSS

BL29

VSS

CM25

VSS

AC30

VSS

BL30

VSS

CM29

VSS

BL31

VSS

CM31

VSS

AD33

VSS

BL32

VSS

CM33

VSS

AD35

VSS

WHISKEY-LAKE-GP

VSS

BL7

AE25

BM33

CM5

AE27

BM35

CM9

AE30

BM36

CN13

AE7

BM9

CN17

AF27

BN30

CN21

AF3

BN7

CN25

AF30

CN29

AF33

BP15

AF36

AF4

CN5

AF7

BP25

CN9

AG10

BP3

CP1

BP32

CP11

AH27

BP33

CP13

AH28

BP4

CP15

AH29

BP7

CP19

AH30

CP21

AH31

BR19

CP27

AH33

BR25

AH35

CP37

AJ25

BT15

AJ28

BT16

CP9

AJ7

CR2

AK3

CR36

AK33

D21

AK36

BT25

D25

AK4

BT28

AL28

BT33

D5

AL29

4

BT35

D6

AL32

BT36

D8

AL7

D9

AM10

BU11

E23

AM28

E27

AM33

BU23

E29

AM35

BU24

E31

BU25

E33

AN25

BU7

E9

AN28

BV11

F12

AN29

F15

AN30

F18

AN31

BV3

F2

AN7

BV31

F21

AN8

BV33

F24

BV4

F3

AP3

BW11

F4

AP33

BW15

G21

AP36

G27

AP4

G33

AR28

G35

G36

AT33

BW24

G9

AT35

H21

AT36

BW7

H27

AT4

BY11

AU10

BY15

H9

AU28

BY22

J12

AU29

J15

WHISKEY-LAKE-GP

VSS

19 OF 20CPU1S

VSS

BY25

J18

AU32

BY28

J21

AV25

BY33

J24

AV28

BY35

J33

AV3

BY36

J36

AV33

J6

AV36

C1

K21

AV4

C21

K22

AV6

C25

K24

AV8

C29

K25

AW28

C33

K27

AW29

C4

K28

AW3

C9

K29

AW30

CA11

K3

AW31

CA15

K30

AY33

CA22

K31

AY35

K32

B12

K4

B15

CA25

K9

B18

CB11

L27

B21

L33

B23

L35

B25

CB18

L36

B27

CB19

L6

B29

CB2

N25

B31

CB20

N27

CB25

N6

VSS

B37

VSS

CB3

VSS

P10

VSS

B5

VSS

CB33

VSS

P3

VSS

B7

VSS

CB4

VSS

P33

VSS

B9

VSS

CB7

VSS

P36

VSS

BA10

VSS

CC11

VSS

P4

VSS

BA28

VSS

P7

VSS

BA3

VSS

CC20

VSS

R27

VSS

BB3

VSS

CC25

VSS

R28

VSS

BB33

VSS

CC28

VSS

R29

VSS

BB36

VSS

CC31

VSS

R30

VSS

BB4

VSS

CC7

VSS

R31

VSS

BC25

VSS

CD11

VSS

T27

VSS

CD12

VSS

T30

VSS

BC29

VSS

CD14

VSS

T33

VSS

T35

VSS

BC32

VSS

CD24

VSS

T36

VSS

CD25

VSS

T7

VSS

BC8

VSS

CE33

VSS

U26

VSS

BD28

VSS

CE35

VSS

U7

VSS

BD33

VSS

CE36

VSS

V26

VSS

BD35

VSS

CE7

VSS

V27

VSS

BD36

VSS

CF11

VSS

V3

VSS

BE10

VSS

CF14

VSS

V30

VSS

BE28

VSS

CF19

VSS

V33

VSS

BE29

VSS

CF2

VSS

V36

VSS

BE3

VSS

WHISKEY-LAKE-GP

3

20 OF 20CPU1T

CF23

VSS

V4

BE30

CF28

W10

BE31

CF3

W27

CF4

W30

BF3

CG33

W7

BF33

CG7

BF36

Y26

BF4

CH31

Y27

BG25

Y30

BG28

CJ11

Y33

CJ14

Y35

BH28

CJ19

Y7

BH29

CJ23

BH32

CJ28

BH33

CJ33

BH35

CJ35

BP19

BR16

BY18

BY19

CC16

BU16

CC14

BR22

BU20

CD20

BT14

BP12

CB24

CC24

J5

U24

BD7

AR4

AU4

AW4

BA6

BC4

BE4

BE8

BA4

BD4

BG4

CJ2

CJ3

AM5

CM4

AC5

AG5

CR6

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(VSS)

Size Document Number Rev

Custom

Date: Sheet

2

CPU_(VSS)

KR CS MLK 13"

23 106Thursday, July 19, 2018

1

of

A00

D

C

B

A

SSID = KBC

KSI[0..7][65]

ESPI_CPU_IO[3..0][18,68]

KSO[0..16][65]

D

CPU_SMB_SDA_P1[18,26]

CPU_SMB_SCL_P1[18,26]

USB_PWR_SHR_EN#[36]

C

USB_POWERSHARE_VBUS_EN[36]

PBAT_CHG_SMBDAT[43,44]

PBAT_CHG_SMBCLK[43,44]

LCD_VCC_TEST_EN[55]

TOUCH_REPORT_SW[55]

MASK_SATA_LED#[64]

CHG_AMBER_LED#[64]

BATT_WHITE_LED#[64]

SYS_LED_MASK#_R[64]

LID_CL_SIO#[64,67]

LID_CL_SIO_TAB#[67]

HOST_DEBUG_TX[68]

TYPEC_SMBDA_Q[72]

TYPEC_SMBCLK_Q[72]

TYPEC_DCIN1_EN#[74]

B

1

D

C

B

3D3V_S5

3D3V_ECVBAT

3D3V_S5_KBC

3D3V_S5

1

MODEL_ID

2

1

2

EC_AGND

2

R2442 27KR2F-L-GP

MODEL_ID_DET (GPIO153)

KR 15" MLK UMA

R2441 100KR2F-L1-GP

KR 15" MLK DIS 100.0K 154K(64.15435.6DL)

RO13_20171031

1

R2495

DY

Do Not Stuff

RO13_20171011

Q2416

BAT2_LED#

1

2

3D3V_S5

CHG_AMBER_LED#

3

common part

2N7002KDW-1-GP

75.27002.F7C

1

R2498

DY

Do Not Stuff

RO13_20171031

3D3V_S0

1

R2489

100KR2J-1-GP

G

2

CAP_LED#

For USB TypeC 65982DC

1

R2467 Do Not Stuff

3D3V_S5_KBC

R2468 Do Not Stuff

D2402

A

DY

Do Not Stuff

1

R2440 Do Not Stuff

Q2417

3

2

DY

1

Do Not Stuff

1

LID_CL_SIO#

K

2

Note:ZZ.27002.F7C01

TYPEC_SMBDA_Q

TYPEC_SMBCLK_Q

TOUCH_REPORT_SW

20180502 DY D2402

BKLT_IN_EC

2

Note:ZZ.27002.F7C01

6

5

4

2

Q2414

S

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

2

4

5

6

2

L_BKLT_EN

1

R2455 100KR2J-1-GP

2

100.0KKR 13" MLK UMA

100.0K

BATT_WHITE_LED#

3D3V_S5

BAT1_LED#

D

3D3V_S5_KBC

CAP_LED#_R

3D3V_S5_KBC

1

4

PULL-HIGH RESISTORPULL-LOW RESISTOR

2

RN2413 SRN2K2J-1-GP

3

TYPEC_SMBDA

TYPEC_SMBCLK

27.0K(64.27025.6DL)

LID_CL_SIO#

TP_EN#

VOLTAGE

RN2405

1

2

3

4

SRN100KJ-5-GP

2.598V

2.001V64.9K(64.64925.6DL)

1.299V

3D3V_S5

8

7

6

5

Kyloren13_MLK_X00 Kyloren13_MLK_X01 Kyloren13_MLK_X02 Kyloren13_MLK_A00

U3_PD#_EC

AUX_EN_WOWL

PECI_CPU

3D3V_S5_KBC

CMP_VIN0_R

3D3V_S5_KBC

3D3V_S5

Reserve Reserve Reserve Reserve Reserve Reserve

1

R2424 20KR2F-L-GP

2

1

R2448 10KR2F-2-DL-GP

2

3

3D3V_S0

1

2

3D3V_AUX_S5

Vref = 1.117 temp around 85

R2430 10KR2J-3-GP

1

DY

2

1

2

100.0K

D2403

FAN_TACH1

A

K

RB520S30-GP

83.R2003.A8M

20180508 Follow KR15 MLK common part

R2463 Do Not Stuff

2017/03/09

R2454 100KR2J-1-GP

10.0K

17.8K

27.0K

37.4K

49.9K

64.9K

82.5K 107K 154K 200KK

20180528 Add PH 150K 20180604 DY 20180711 Stuff 10K

NC_U3_PD#_EC

RO13_20171101 GPIO002:open drain

SYS_LED_MASK#_R

LID_CL_SIO_TAB#

VCI_IN1#

PCIE_WAKE#

1D0V_S5

Just for Starload placement 2015/09/23 modify

R2402 Do Not Stuff

Layout Note:

Need very close to EC

20180330 Remove USB_PWR_SHR_EN# LS

USB_PWR_SHR_EN#

R2401 Do Not Stuff

AD_IA

R2423 Do Not Stuff

Layout Note:

Need very close to EC

I_ADP

1

2

EC_AGND

2016/12/28 Reserve by NON DS3 function 2 0150413

GPU_THM_SMBDAT

GPU_THM_SMBCLK

Power Switch Logic(PSL)

KBC_PWRBTN#

3D3V_S5_KBC

1

2

SRN4K7J-8-GP

20180211

VOLTAGEP ULL-HIGH RESISTORPULL-LOW RESISTORBOARD_ID VERSION A/D

3.0V

2.801V

2.598V

2.402V

2.201V

2.001V

1.808V

1.594V100 .0K

1.299V

1.100V

1

R2406 10KR2J-3-GP

1

R2456 Do Not Stuff

1

R2496 Do Not Stuff

R2497 100KR2J-1-GP

20180713 Add PH RES

R2407 100KR2J-1-GP

2

1

USB_PWR_SHR_EN_L#

2

1

2

1

DY

2

1

R2421 330R2J-3-GP

C2435 SC2200P50V2KX-2DLGP

20180202 Remove DY res

2

1

R2447 Do Not Stuff

2

1

R2459 Do Not Stuff

3D3V_ECVBAT

2

1

R2432 1KR2J-1-GP

RN2402

PBAT_CHG_SMBDAT

4

PBAT_CHG_SMBCLK

3

2

DY

2

2IN1

2

1

2

1

2

I_BATT

1

C2441

DY

Do Not Stuff

2

EC_AGND

AD_IA

1

R2451 100KR2J-1-GP

2

POWER_SW_IN#

1

C2427 SC2D2U10V3KX-1DLGP-U

2

MODEL_ID

1

C2407 SCD1U25V2KX-1-DL-GP

2

1V_VREF_CPU

C2406 SCD1U25V2KX-1-DL-GP

CPU_SMB_SDA_P1

CPU_SMB_SCL_P1

5

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

ESPI_CPU_IO0

ESPI_CPU_IO1

ESPI_CPU_IO2

ESPI_CPU_IO3

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

KSO16

PECI_CPU[3]

PROCHOT#_CPU[3,44,46]

TP_WAKE_KBC#[3,65]

L_BKLT_EN[4]

SYS_PWROK[17]

SIO_PWRBTN#[17]

PCH_RSMRST#[17]

RESET_OUT#[17,26]

AUX_EN_WOWL[17,61]

VCCST_PWRGD[17,40]

RTCRST_ON[18,25]

VCCDSW_ON[25]

ESPI_CLK[18,68]

ESPI_CS#[18,68]

ESPI_RESET#[18,68]

SUS_CLK[18]

SIO_EXT_WAKE#[20]

CMP_VIN0_R[26]

CMP_VOUT0[26]

FAN1_PWM[26]

FAN_TACH1[26]

NB_MUTE#[27]

BEEP[27]

ALWON[40]

PRIM_PWRGD[40,53]

AC_DIS[43]

PS_ID[43]

HW_ACAVIN_NB[43]

PBAT_PRES#[43,44]

HW_ACAV_IN[44]

AD_IA[44]

PANEL_BKEN[55]

LCD_TST[55]

SSD_SCP#[63]

CLK_TP_SIO[65]

DAT_TP_SIO[65]

TP_EN#[65]

CAP_LED#_R[65]

KB_LED_PWM[65]

PTP_DIS#[65]

BREATH_LED#[66]

USB_PWR_EN#[66]

KBC_PWRBTN#[66]

UPD1_ALERT[72]

FPR_SCAN#[92]

ME_FWP_EC[98]

NB_MODE#[20]

U3_PD#_EC[66]

3D3V_S5

SCD1U25V2KX-1-DL-GP

3D3V_S5_KBC

RN2409

1

2

3

4

SRN100KJ-5-GP

RN2410

1

2

3

4

SRN100KJ-5-GP

RN2411

1

2

3

4

SRN100KJ-5-GP

RN2412

1

2

3

4

SRN100KJ-5-GP

3D3V_S5

R2465 10KR2F-2-DL-GP

1

2

1

3D3V_S5_KBC

C2416

8

7

6

5

8

7

6

5

8

7

6

5

8

7

6

5

RO13_20171031 Vender review

1

R2414 10KR2J-3-GP

2

1

2

For eSPI

2

1

R2446

Do Not Stuff

C2421

1

2

3D3V_S5_KBC

KSO5

KSO4

KSO7

KSO6

KSO12

KSO14

KSO11

KSO10

KSO0

KSO16

KSO15

KSO13

KSO8

KSO3

KSO1

KSO2

FPR_SCAN#

3D3V_S5_KBC

1

R2480 Do Not Stuff

DEBUG

2

GPIO102 (CR_STRAP)

3D3V_S5_KBC

2

R2452 100KR2J-1-GP

1

KSO9

2

R2453 Do Not Stuff

DY

1

3D3V_S5_KBC

C2412

C2420

1

2

SCD1U25V2KX-1-DL-GP

Just for Starload placement 2015/09/23 modify

RN2403

1

2

3

4

SRN10KJ-6-GP

RN2404

1

2

3

4

SRN10KJ-6-GP

20180409 Follow CY18

SYS_LED_MASK#_R

3D3V_S5

SUS_CLK

R2461 Do Not Stuff

1

2

Microchip: Use CL=9p Xtal

ICSP_CLK

ICSP_DAT

HOST_DEBUG_TX

ICSP_CLR

C2411

C2410

1

2

SCD1U25V2KX-1-DL-GP

8

KSI0

7

KSI1

6

KSI4

5

KSI5

8

KSI6

7

KSI7

6

KSI2

5

KSI3

1.8V GPIO

1

R2410 Do Not Stuff

1

R2434 100KR2J-1-GP

RO13_20171108

2

1

DY

RO13_20170901

X2401

2

1

XTAL-32D768KHZ-98-GP

082.30003.0301

common part

C2425 SC18P50V2JN-1DLGP

3D3V_S5_KBC

DB3

7

1

2

3

4

5

6

8

Do Not Stuff

GPIO123 (BSS_STRAP)

Already pull low on CPU side

PCH_RSMRST#

1

TP2402 Do Not Stuff

2017/03/21

C2413

C2414

1

DY

2

Do Not Stuff

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

KSO16

CAP_LED#

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

CLK_TP_SIO

DAT_TP_SIO

SIO_PWRBTN#

VCCDSW_ON

ESPI_CPU_IO0

ESPI_CPU_IO1

ESPI_CPU_IO2

ESPI_CPU_IO3

ESPI_CS#

MASK_SATA_LED#

ESPI_CLK

TYPEC_DCIN1_EN#

SYS_LED_MASK#

2

DY

TP_EN#

ESPI_RESET#

LID_CL_SIO#

UPD1_ALERT

SYS_PWROK

PBAT_PRES#

PRIM_PWRGD

RTCRST_ON

PCH_RSMRST#

BKLT_IN_EC

AC_DIS

USB_POWERSHARE_VBUS_EN

FPR_SCAN#

TP_WAKE_KBC#

USB_PWR_EN#

VCCST_PWRGD

RESET_OUT#

MEC_XTAL2

MEC_XTAL1_R

1

C2424 SC18P50V2JN-1DLGP

2

󶁜

C = 10p

LPC

EC2402

1

DY

2

20180508 Follow KR15 MLK common part

eDP backlight Control from EC

eDP backlight Control from PCH

4

EC2403

RTC GEN 9 reset circuit

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

RO13_20170814

3D3V_AUX_S5

2

R2472 Do Not Stuff

DY

1

3D3V_ECVBAT

1

C2428 SCD1U25V2KX-1-DL-GP

2

U2401

2

GPIO02 7/KSO00 /PVT_IO 1

14

GPIO01 5/KSO01 /PVT_CS #

15

GPIO01 6/KSO02 /PVT_SC LK

16

GPIO01 7/KSO03 /PVT_IO 0

37

GPIO04 5/BCM_INT 1#/KSO04

38

GPIO04 6/BCM_DA T1/KSO05

39

GPIO04 7/BCM_CL K1/KSO06

50

GPIO02 5/KSO07 /PVT_IO 2

46

GPIO05 5/PWM2/K SO08/PVT _IO3

68

GPIO10 2/KSO09 /CR_STR AP

72

GPIO10 6/KSO10

74

GPIO11 0/KSO11

75

GPIO11 1/KSO12

76

GPIO11 2/PS2_C LK1A/KS O13

77

GPIO11 3/PS2_D AT1A/KS O14

86

GPIO12 5/KSO15

92

GPIO13 2/KSO16

93

GPIO14 0/KSO17

98

GPIO14 3/KSI0/D TR#

99

GPIO14 4/KSI1/D CD#

6

GPIO00 5/SMB00_ DATA/SMB0 0_DATA 18/KSI2

7

GPIO00 6/SMB00_ CLK/SMB00 _CLK18 /KSI3

104

GPIO14 7/KSI4/D SR#

105

GPIO15 0/KSI5/R I#

107

GPIO15 1/KSI6/R TS#

108

GPIO15 2/KSI7/C TS#

78

GPIO11 4/PS2_C LK0

79

GPIO11 5/PS2_D AT0

52

GPIO02 6/PS2_C LK1B

88

GPIO12 7/PS2_D AT1B

59

GPIO04 0/LAD0/E SPI_IO 0

60

GPIO04 1/LAD1/E SPI_IO 1

61

GPIO04 2/LAD2/E SPI_IO 2

62

GPIO04 3/LAD3/E SPI_IO 3

58

GPIO04 4/LFRAME #/ESPI_ CS#

56

GPIO06 4/LRESE T#

57

GPIO03 4/PCI_C LK/ESPI _CLK

63

GPIO06 7/CLKRUN#

55

GPIO06 3/SER_I RQ/ESPI _ALERT #

10

GPIO01 1/SMI#/EMI _INT#

49

GPIO06 0/KBRST

53

GPIO06 1/LPCPD #/ESPI_ RESET#

66

GPIO10 0/EC_SC I#

32

GPIO12 6/SHD_SC LK

28

GPIO13 3/SHD_IO 0

29

GPIO13 4/SHD_IO 1

30

GPIO13 5/SHD_IO 2

31

GPIO13 6/SHD_IO 3

27

GPIO12 3/SHD_CS #

67

GPIO10 1/SPI_C LK

69

GPIO10 3/SPI_I O0

71

GPIO10 5/SPI_I O1

42

GPIO05 2/SPI_I O2

33

GPIO06 2/SPI_I O3

3

GPIO00 1/SPI_C S#/32KHZ _OUT

13

RESET_ IN#/GPIO 014

48

GPIO05 7/VCC_P WRGD

73

GPIO10 7/RESET _OUT#

125

XTAL2

123

XTAL1

MEC1416-NU-D0-GP

071.01416.000G

PANEL_BKEN_EC

L_BKLT_EN

1

R2403

DY

Do Not Stuff

3D3V_RTC

2

R2473 Do Not Stuff

1

122

103

82

65

43

19

5

VTR

VBAT

GPIO00 7/SMB01_ DATA/SMB0 1_DATA 18

GPIO01 0/SMB01_ CLK/SMB01 _CLK18

GPIO01 2/SMB02_ DATA/SMB0 2_DATA 18

GPIO01 3/SMB02_ CLK/SMB02 _CLK18

GPIO13 0/SMB03_ DATA/SMB0 3_DATA 18

GPIO13 1/SMB03_ CLK/SMB03 _CLK18

GPIO14 1/SMB04_ DATA/SMB0 4_DATA 18

GPIO14 2/SMB04_ CLK/SMB04 _CLK18

GPIO03 0/BCM_INT 0#/PWM4

GPIO03 1/BCM_DA T0/PWM5

GPIO03 2/BCM_CL K0/PWM6

GPIO15 7/LED0/T ST_CLK _OUT

GPIO11 6/TFDP_ DATA/UAR T_RX

GPIO11 7/TFDP_ CLK/UART _TX

GPIO03 3/PECI_ DAT/SB_ TSI_DA T

GPIO14 5/ICSP_ CLOCK

SYSPWR _PRES/G PIO003

VCI_OV RD_IN/GP IO164

GPIO12 4/CMP_VO UT0

GPIO16 5/CMP_VR EF0

GPIO12 0/CMP_VO UT1

GPIO16 6/CMP_VR EF1/UART_ CLK

VSS

VSS_VBAT

AVSS

VSS

VR_CAP

84

64

51

17

18

100

124

112

EC_AGND

VR_CAP

1

R2445

2

1

Do Not Stuff

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

L_BKLT_EN_R

2

EC_AGND

D2401

1

2

BAT54C-12-GP

75.00054.A7D

2

3

For eSPI

1D8V_S5

R2462 Do Not Stuff

VTR_33 _18

GPIO05 0/TACH0

GPIO05 1/TACH1

GPIO05 3/PWM0

GPIO05 4/PWM1

GPIO05 6/PWM3

GPIO00 2/PWM7

GPIO15 6/LED1

GPIO10 4/LED2

GPIO03 5/SB-TSI _CLK

VREF_C PU

GPIO14 6/ICSP_ DATA

ICSP_MC LR

BGPO/GP IO004

VCI_OUT /GPIO03 6

VCI_IN1 #/GPIO1 62

VCI_IN0 #/GPIO1 63

GPIO16 0/DAC_0

GPIO16 1/DAC_1

DAC_VR EF

GPIO02 0/CMP_VI N0

GPIO02 1/CMP_VI N1

GPIO02 4/ADC7

GPIO02 3/ADC6/A 20M

GPIO02 2/ADC5

GPIO15 3/ADC4

GPIO15 4/ADC3

GPIO15 5/ADC2

GPIO12 2/ADC1

GPIO12 1/ADC0

ADC_VR EF

C2418 SC1U10V2KX-1DLGP

PANEL_BKEN

1

1D8V_S5_KBC

2

54

PBAT_CHG_SMBDAT

8

PBAT_CHG_SMBCLK

9

GPU_THM_SMBDAT

11

GPU_THM_SMBCLK

12

TYPEC_SMBDA

89

TYPEC_SMBCLK

91

NC_U3_PD#_EC

96

NC_SIO_SLP_S4#_EC

97

FAN1_TACH

40

LID_CL_SIO_TAB#

41

KB_LED_PWM

44

45

BEEP

FAN1_PWM

47

NB_MODE#

34

35

PS_ID

36

PCIE_WAKE#

4

BAT2_LED#

1

BAT1_LED#

106

BREATH_LED#

70

ME_FWP_EC

80

HOST_DEBUG_TX

81

PTP_DIS#

90

H_PECI

94

1V_VREF_CPU

95

ICSP_CLK

101

ICSP_DAT

102

ICSP_CLR

87

NB_MUTE#

119

SYSPWR_PRES

120

121

ALWON

VCI_IN1#

126

POWER_SW_IN#

127

HW_ACAV_IN

128

23

HW_ACAVIN_NB

24

22

CMP_VOUT0

85

CMP_VIN0_R

20

25

VCREF0

83

PROCHOT

SSD_SCP#

21

LCD_TST

26

USB_PWR_SHR_EN_L#

118

PANEL_BKEN_EC

117

SIO_EXT_WAKE#

116

MODEL_ID

109

I_ADP

110

BOARD_ID

111

LCD_VCC_TEST_EN

113

I_BATT

114

115

1

C2423 SCD1U25V2KX-1-DL-GP

2

3D3V_S5_KBC

1

C2422 SCD1U25V2KX-1-DL-GP

2

EC_AGND

PBAT_PRES#

USB_PWR_SHR_EN_L#

EC_AGND

3D3V_S5_KBC

1

R2443 37K4R2F-1-GP

PCB_REV

2

BOARD_ID

C2408

SCD1U25V2KX-1-DL-GP

1

R2444 100KR2F-L1-GP

2

EC_AGND

BATTER /CHARGER

CPU/ Thermal/TYPEC

RO13_20171026

2

1

R2404 0R2J-L-GP

2

1

R2405 Do Not Stuff

DY

20180227 Follow CY18 20180222 Remove net

RO13_CFLU_20171220

Need very close to EC, PDG: <0.5 inches.

2

1

R2437 43R2J-GP

1

C2405

DY

Do Not Stuff

2

3D3V_S5_KBC

2

1

C2429 SCD1U25V2KX-1-DL-GP

1

C2409 SCD01U50V2KX-1DLGP

2

1

R2494 Do Not Stuff

DY

MEC1416’s pin 118 (GPIO024). This pin is a strap option pin. It should be pulled up to enable Comparator 0 function for thermal shutdown function.

Just for Starload placement 2015/09/23 modify

2

1

R2415 10KR2J-3-GP

2

1

R2416 10KR2J-3-GP

2

1

R2418 Do Not Stuff

A

PROCHOT

1

R2417 Do Not Stuff

DY

2

5

Q2408

G

S

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

DY

PROCHOT#_CPU

D

RO13_20171001 EMI request

1

2

ED2403 Do Not Stuff

DY

3

Do Not Stuff

4

3

2

Title

KBC Nuvoton NPCE285PA0DX

Size Document Number Rev

A1

KR CS MLK 13"

Thursday, July 19, 2018

Date: Sheet

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

24 106

A

A00

of

5

SSID = SPI Flash

SPI_HOLD_CPU[15,18]

SPI_CLK_CPU[18,91]

SPI_SI_CPU[15,18,91]

D

SPI_CS_CPU_N0[18]

SPI_SO_CPU[18,91]

SPI_WP_CPU[15,18]

SPI_CS_CPU_N0

SPI_SO_CPU

SPI_WP_CPU

RO13_20171001 10 ohm to 0 ohm RO13_CFLU_20171206 0 ohm to 33 ohm

2

1

R2506 33R2F-3-GP

R2507 33R2F-3-GP

2

1

4

3D3V_S5_PCH

1

R2519 4K7R2J-2-GP

2

SPI_SO_ROM

SPI_WP_ROM

EC2502

1

DY

2

1

72.12873.001

72.25128.0E1

3

QUAD/DUAL fast read DUAL fast readSource

O

SFDP

O

3D3V_S5_PCH

C2501

1

DY

2

Do Not Stuff

C2502

Do Not Stuff

1

DY

2

OO O

D

20180419 Modify PN

BIOS1

1

CS#

2

3

Do Not Stuff

4

W25Q128JVSIQ-GP

072.25128.0B51

DO/IO1

WP#/IO2

GND

HOLD#/RESET#/IO3

VCC

CLK

DI/IO0

8

7

6

5

3D3V_S5_PCH

SPI_HOLD_ROM

SPI_CLK_ROM

SPI_SI_ROM

DY

EC2501

Do Not Stuff

1

2

RO13_20171001 10 ohm to 0 ohm RO13_CFLU_20171206 0 ohm to 33 ohm

2

1

R2503 15R2F-2-GP

R2508 33R2F-3-GP

R2509 33R2F-3-GP

EC2503

Do Not Stuff

1

DY

2

1

2

1

SPI_HOLD_CPU

SPI_CLK_CPU

SPI_SI_CPU

Main Func = RTC

C

B

A

RTCRST_ON[18,24]

3V_5V_PWRGD[17,40,45]

VCCDSW _ON[24]

RTC_DET#[15,20]

3V_5V_DSW_OK[52,53]

SSID RTC 09M

3D3V_AUX_S5

1

2

1

DY

2

+RTC_VCC

1

2

20180131 Don't change to short pad when MP

R2505 0R2J-L-GP

3D3V_RTC_SYS

R2517 Do Not Stuff

1

2

G

R2504 10MR2J-L-GP

S

D2501

BAT54C-12-GP

75.00054.A7D

Q2505

Notice:ZZ.2N702 .J3101

2N7002K-2-GP

84.2N702.J31

SSID RTC reset 09N

NON_RTC_RST

2

1

3D3V_RTC

3

D

1

C2503 SCD47U10V2KX-1-GP

2

RTC_DET#

R2512 Do Not Stuff

S

D

RTC_RST

20180424 Swap main and 2nd source

Q2507

G

PJA3415-GP

084.03415.0031

RTCRST_ON

1

R2518 100KR2J-1-GP

RTC_RST

2

D2502

A

K

DY

Do Not Stuff

R2567

2

1

RTC_RST

1MR2J-1-GP

RTC_3P3_EN_G

1

C2517 SCD022U16V2KX-3DLGP

RTC_RST

2

RTC_AUX_S5

2

RTC_RST

1

RTC_3P3_EN_D

D

G

R2511 4K7R2J-2-GP

Q2510 2N7002K-2-GP

84.2N702.J31RTC_RST

Notice:ZZ.2N702 .J3101

S

3D3V_S5

1

R2520 100KR2J-1-GP

RTC_RST

2

1

C2525

DY

Do Not Stuff

2

3V_5V_PWRGD

VCCDSW _ON

3D3V_S5

R2513

1

NON_RTC_RST

Do Not Stuff

D2503

1

RTC_RST

2

BAT54A-11-GP

U2502

4

EN

RTC_RST

5

IN

G517F1T12U-GP

074.51712.009F

RO13_20171102 common part

R2522

1

NON_RTC_RST

Do Not Stuff

2

3

OC#

2

GND

1

OUT

2

3D3V_S5

1

R2514 10KR2J-3-GP

RTC_RST

2

3V_5V_DSW_OK

3D3V_VCCDSW

1

R2516

Do Not Stuff

3D3V_S5_PCH

2

C

B

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Thursday, July 19, 2018

Date: Sheet

5

4

3

2

Date: Sheet

Flash/RTC

KR CS MLK 13"

1

25 106

of

25 106

of

25 106

of

A00

5

SSID = Thermal Sensor

CPU_SMB_SDA_P1[18,24]

CPU_SMB_SCL_P1[18,24]

PLTRST#_CPU[17,63,66,91]

RESET_OUT#[17,24]

PURE_HW _SHUTDOWN#[40]

FAN_TACH1

FAN1_PW M

FAN_TACH1[24]

FAN1_PW M[24]

CMP_VOUT0[24]

CMP_VIN0_R[24]

2017/05/08

5V_S0

1

R2612 Do Not Stuff

1

DY

2

PWM FAN1

2

R2613 Do Not Stuff

R2614 Do Not Stuff

EC2602

Do Not Stuff

EC2601

1

DY

2

5

5V_FAN_VCC

C2605

C2604

SC4D7U6D3V3KX-DLGP

1

2

1

2

1

Do Not Stuff

K

SCD1U25V2KX-1-DL-GP

DY

A

Do Not Stuff

FAN_TACH1_C

FAN_PW M1_C

5V_FAN_VCC

D

C

SSID FAN 07B

B

A

D2601

Do Not Stuff

Layout Note:

Signal Routing Guideline: Trace width = 15mil

1

C2603 Do Not Stuff

DY

2

5V_FAN_VCC

FAN_TACH1_C

FAN_PW M1_C

AFTP2604

1

AFTP2601

1

AFTP2602

1

AFTP2603

4

RO13_20171002 follow ME connector list

FAN1

1

2

3

4

1

ACES-CON4-29-GP

20.F1639.004

4

3D3V_S0

1

R2603 7K5R2F-1-GP

7718

1

R2604 7K5R2F-1-GP

7718

Q2603 MMBT3904-5-GP-U

84.T3904.K11

2.System Sensor, Put on palm rest

Layout Note:

C2607 close THM2601

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

5

6

2

1

C2614

DY

Do Not Stuff

2

CMP_VOUT0

D

C

3

3D3V_S0

C2601

Do Not Stuff

C2602

1

2

C

7718

E

ALERT#

T_CRIT#

C2606

1

DY

B

2

DY

2

NCT7718_DXP

Do Not Stuff

7718

NCT7718_DXN

SCD1U25V2KX-1-DL-GP

1

7718

2

T_CRIT#

1

DY

2

U2601

1

2

3

4

NCT7718W-GP

74.07718.0B9

R2601 Do Not Stuff

VDD

7718

D+

ALERT#

D-

T_CRIT#

PLTRST#_CPU

RESET_OUT#

THERM_SYS_SHDN#

SCL

SDA

GND

C2607

SC2200P50V2KX-2DLGP

1

2

8

7

6

5

1

R2616 Do Not Stuff

3D3V_S5

CPU_SMB_SDA_P1

CPU_SMB_SCL_P1

ALERT#

KBC T8

2

3D3V_S0

C2608

Do Not Stuff

1

DY

2

DY

R2607 10KR2J-3-GP

R2602 Do Not Stuff

1

Q2602

G

S

Notice:ZZ.2N702 .J3101

2N7002K-2-GP

84.2N702.J31

2

Q2601

Note:ZZ.27002.F7C01

6

1

5

2

7718

4

3

2N7002KDW-1-GP

75.27002.F7C

CPU_SMB_SCL_THM

CPU_SMB_SDA_THM

C2609

Do Not Stuff

1

DY

2

D

3D3V_S0

1

7718

4

DVT1 0210, for T8 function

C2610

Do Not Stuff

1

DY

2

CMP_VOUT0

2

RN2602 SRN2K2J-1-GP

3

CPU_SMB_SDA_THM

CPU_SMB_SCL_THM

PURE_HW _SHUTDOWN#

1

R2615 Do Not Stuff

RESET_OUT#

DY

Close to Thermal sensor

3D3V_S0

1

R2609 Do Not Stuff

DY

2

3

R2610

NTC-100K-8-GP

3D3V_S5_KBC

1

R2608 27KR2F-L-GP

DVT1 0210, for T8 function

2

1

2

C2612 SCD1U25V2KX-1-DL-GP

VD_IN1_C

2

Close to KBC VD_IN1 for system thermal sensor

CMP_VIN0_R

1

C2613

SC100P50V2JN-3DLGP

2

1

R2611 Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Number Rev

A3

KR CS MLK 13"

Thursday, July 19, 2018

Date: Sheet

26 106

1

of

A00

B

A

SSID = Audio

HDA_SYNC_CODEC[19]

HDA_BITCLK_CODEC[19]

HDA_SDOUT_CODEC[19]

HDA_SDIN0_CPU[19]

D

DMIC_SCL_CODEC[55]

DMIC_SDA_CODEC[55]

SPKR[15,19]

BEEP[24]

MIC2_VREFO_L[29]

MIC2_VREFO_R[29]

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R+[29]

AUD_SPK_R-[29]

AUD_RING[29]

AUD_SELEEVE[29]

LINE1_L[29]

LINE1_R[29]

AUD_HPJD_N[29]

NB_MUTE#[24]

AUD_HPOUT_L[29]

C

B

AUD_HPOUT_R[29]

SPK_SCL_CODEC[29]

SPK_SDA_CODEC[29]

1D8V_S0

3D3V_S0

Do Not Stuff

R2748 Do Not Stuff

3D3V_S0

Do Not Stuff

R2750 Do Not Stuff

1

C2731

SC10U6D3V2MX-2-GP

1

R2747

100KR2J-1-GP

1

2017/05/08

moat

1

Do Not Stuff

C2727

SC10U6D3V3MX-DL-GP

1

Layout Note:

2

Place close to Pin 40

2

AUD_AGND

R2705

D

5V_S0

2

C

B

AUD_AGND

SCD1U25V2KX-1-DL-GP

1

R2745 2K2R2J-2-GP

2

1D8V_CPVDD

C2730

C2740

SCD1U25V2KX-1-DL-GP

1

2

AUD_AGND

2

Layout Note:

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

2

1

C2737 SC2D2U10V3KX-1DLGP-U

2

1

C2734 SC10U6D3V2MX-2-GP

2

1

C2736 SC10U6D3V2MX-2-GP

2

1

C2735 SC10U6D3V2MX-2-GP

2

1

C2741 SC1U25V3KX-1-DLGP

2

1

C2739 SC1U25V3KX-1-DLGP

C2726

AUD_PC_BEEP_R

2

1

SC10U6D3V3MX-DL-GP

Layout Note:

Close pin 20

AUD_AGND

+5V_AVDD

C2721

SCD1U25V2KX-1-DL-GP

1

2

AUD_AGND

moat

1

EC2709 Do Not Stuff

DY

1

EC2710 Do Not Stuff

DY

1

EC2711 SCD01U50V2KX-1DLGP

1

EC2712 Do Not Stuff

DY

1

EC2713 SCD1U25V2KX-1-DL-GP

1

EC2714 SCD1U25V2KX-1-DL-GP

AUD_AGND

1

R2739

Do Not Stuff

AUD_AGND

20180604 Install EC2711, EC2713, EC2714

Layout Note:

R2739 should place nearby codec IC.

1

2

3

RN2702

1

2

SRN1KJ-7-GP

C2733

SC10U6D3V3MX-DL-GP

KBC_BEEP_R

4

3

HDA_SPKR_R

Layout Note:

Close pin46

PCBEEP

MIC2-L(PORT-F-L)/RING2

MIC2-R(PORT-F-R)/SLEEVE

LINE2-L(PORT-E-L)

LINE2-R(PORT-E-R)

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R+

SPK-OUT-R-

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

VREF

LDO1-CAP

LDO2-CAP

LDO3-CAP

MIC2-VREFO-L

MIC2-VREFO-R

MIC2-CAP

CPVEE

CBP

CBN

AVSS1

AVSS2

GND

RO13_20171013 common part

D2702

1

3

2

BAT54C-12-GP

75.00054.A7D

2017/05/08

1D8V_S0

1

R2724

Do Not Stuff

AUD_PC_BEEP_R

34

AUD_RING

30

AUD_SELEEVE

31

LINE1_L

36

LINE1_R

35

AUD_SPK_L+

42

AUD_SPK_L-

43

AUD_SPK_R+

45

AUD_SPK_R-

44

AUD_HPOUT_L

27

AUD_HPOUT_R

26

AUD_VREF

38

LDO1_CAP

39

LDO2_CAP

21

LDO3_CAP

19

MIC2_VREFO_L

28

MIC2_VREFO_R

29

MIC_CAP

32

25

CPVEE

23

CBP

24

CBN

37

22

49

AUD_PC_BEEP_C

2

1

2

AUD_AGND

5

3D3V_S0

2

1

RN2703 SRN2K2J-1-GP

4

3

1

EC2701 SC10P50V2JN-4DLGP

2

3D3V_1D8V_AVDD

DMIC_SDA_CODEC

DMIC_SCL_CODEC

FC2701

Do Not Stuff

1

DY

2

Close pin5 FC2701 close to C2738

3D3V_1D8V_AVDD

2

1

R2749

2

1

DY

2

1

R2751

2

1

DY

C2729

SCD1U25V2KX-1-DL-GP

1

2

3D3V_1D8V_AVDD_IO

C2744

SCD1U25V2KX-1-DL-GP

1

2

3D3V_AUX_S5

Close pin6 pin7

HDA_SDIN0_CPU

C2738

Do Not Stuff

3D3V_1D8V_AVDD

1

DY

2

RO13_20170828 0603->0402

C2743

SC10U6D3V2MX-2-GP

1

2

RO13_20171019 0402->0603

C2745

SC10U6D3V3MX-DL-GP

1

2

RTC_AUX_S5

AUD_HPJD_N

4

3D3V_1D8V_AVDD

1

C2722 SCD1U25V2KX-1-DL-GP

2

1

R2728 Do Not Stuff

DY

2

1

R2754 Do Not Stuff

2

1

R2730 33R2F-3-GP

R2746 Do Not Stuff

Layout Note:

R2741 200KR2F-L-GP

R2744 100KR2J-1-GP

R2738 Do Not Stuff

R2721 Do Not Stuff

R2743 10KR2J-3-GP

3D3V_1D8V_AVDD

5V_S0

1

DY

1

R2742

1

100KR2J-1-GP

2.5A

1

R2707

Do Not Stuff

1

R2712

Do Not Stuff

2

+5V_PVDD

3D3V_1D8V_AVDD_IO

+5V_AVDD

1D8V_CPVDD

+5V_PVDD

SPK_SDA_CODEC

SPK_SCL_CODEC

HDA_SYNC_CODEC

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

HDA_SDIN0_CODEC

DVSS

Place close to Pin 1

DY

AUD_SENSE_A

Audio_47

DMIC_SDA_CODEC_R

DMIC_SCL_CODEC_R

NB_MUTE#

AUD_SENSE_A

1

C2746 Do Not Stuff

2

C2732

SC10U6D3V3MX-DL-GP

1

2

Layout Note:

Close pin41

AUX_MODE

C2742

SCD1U25V2KX-1-DL-GP

1

2

U2701

3

DVDD

18

DVDD-IO

40

AVDD1

20

CPVDD/AVDD2

41

PVDD1

46

PVDD2

33

5VSTB/AUX_MODE

6

I2C-DATA

7

I2C-CLK

15

AUDIOLINK_SYNC

14

AUDIOLINK_BCLK

17

AUDIOLINK_SDATA-OUT

16

AUDIOLINK_SDATA-IN

13

DC-DET/EAPD

11

I2S-MCLK

10

I2S-BCLK

12

I2S-LRCK

8

I2S-IN

9

I2S-OUT

48

HP/LINE2-JD(JD1)

47

I2S-IN/I2S-OUT-JD(JD2)

4

GPIO0/DMIC-DATA12

5

GPIO1/DMIC-CLK

1

DMIC-CLK-IN/I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34

2

PDB

ALC3254-VA3-CG-GP

071.03254.M001

RO13_20171103 U2701 from 071.03254.0003 to 071.03254.M001.

BEEP

SPKR

C2714

SCD1U25V2KX-1-DL-GP

1

2

A00

A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3254

Size Document Number Rev

A3

Date: Sheet

Audio Codec ALC3254

KR CS MLK 13"

27 106Thursday, July 19, 2018

1

of

5

4

3

2

1

D

C

D

C

(Blanking)

A00

B

A

B

Wistron Corporation

A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

2

KR CS MLK 13"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

28 106Thursday, July 19, 2018

of

28 106Thursday, July 19, 2018

of

28 106Thursday, July 19, 2018

of

1

5

4

3

2

1

SSID = Audio

AUD_SPK_L+[27]

AUD_SPK_L-[27]

AUD_SPK_R+[27]

D

C

B

A

AUD_SPK_R-[27]

SPK_SCL_CODEC[27]

SPK_SDA_CODEC[27]

SPK_ID[21]

MIC2_VREFO_R[27]

MIC2_VREFO_L[27]

AUD_RING[27]

AUD_HPOUT_L[27]

LINE1_L[27]

AUD_HPOUT_R[27]

LINE1_R[27]

AUD_SELEEVE[27]

AUD_HPJD_N[27]

JACK_PLUG_DET

10 mils

20180221 Follow KR 13 to modify ESD 20180601 Movie TVS to close CONN.

2017/03/02

1

R2905 Do Not Stuff

2

AUD_AGND

CLOSS TO HPMIC1

1

2

ED2901

3

AZ5125-02S-R7G-GP

75.05125.07D

5

1

ED2902 AZ5125-02S-R7G-GP

75.05125.07D

Speaker

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

EC2906

1

AUD_SPK_L+_C

AUD_SPK_L-_C

AUD_SPK_R+_C

AUD_SPK_R-_C

SPK_SCL_CODEC

SPK_SDA_CODEC

SPK_DET#_CON

AUD_SPK_L-_C

AUD_SPK_L+_C

AUD_SPK_R-_C

AUD_SPK_R+_C

20180223 Modify to 10R

R2911 10R2F-L-GP

R2912 10R2F-L-GP

EC2905

SC680P50V2KX-2DLGP

1

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R+

AUD_SPK_R-

MIC2_VREFO_R

MIC2_VREFO_L

AUD_RING

AUD_HPOUT_L

LINE1_L

AUD_HPOUT_R

LINE1_R

AUD_SELEEVE

20160812 EMI

1

C2907

1

C2908

EC2901

1

2

LINE1-L_C

2

SC10U6D3V3MX-DL-GP

LINE1-L_R

2

SC10U6D3V3MX-DL-GP

EC2902

SC1KP50V2KX-1DLGP

1

2

SC1KP50V2KX-1DLGP

EC2903

SC1KP50V2KX-1DLGP

EC2904

1

2

RN2901

1

2

SRN2K2J-1-GP

1

R2907 Do Not Stuff

1

R2922 Do Not Stuff

1

R2909 Do Not Stuff

1

R2921 Do Not Stuff

SC1KP50V2KX-1DLGP

1

2

4

3

2

1

ER2901 Do Not Stuff

1

ER2902 Do Not Stuff

1

ER2903 Do Not Stuff

1

ER2904 Do Not Stuff

SPK_ID

1

R2915 Do Not Stuff

SPK_DET

1

3D3V_S0

R2914 Do Not Stuff

R2908

R2910

2

EC2908

SC680P50V2KX-2DLGP

1

Do Not Stuff

1

Do Not Stuff

2

RING2_R

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

SLEEVE_R

1

Default stuff

EC2907

SC680P50V2KX-2DLGP

Layout Note:

EC2908 EC2907 should place nearby codec IC.

20180212

AUD_HP1_JACK_R1_R

RING2_R

JACK_PLUG

JACK_PLUG_DET

SLEEVE_R

AUD_HP1_JACK_L1_R

1

2

3

ED2903 AZ5125-02S-R7G-GP

2

3

JACK_PLUG

10 mils Delay circuit (JACK_PLUG_DET: on IO Board)

1

Do Not Stuff

R2923

2

AUD_HPJD_N

10 mils

1

C2909

DY

Do Not Stuff

2

75.05125.07D

AUD_AGND

4

3

2

AUD_AGND

2

AUD_AGND

Title

Audio IO

Size Document Number Rev

A4

Date: Sheet

Audio IO

KR CS MLK 13"

Thursday, July 19, 2018

2

RO13_20171002 follow ME connector list

SPK1

9

1

2

3

4

5

6

7

8

10

ACES-CON8-13-GP-U2

20.F1295.008

1

20160812 EMI

2

RING2_R

AUD_HP1_JACK_L1_R

JACK_PLUG

JACK_PLUG_DET

AUD_HP1_JACK_R1_R

SLEEVE_R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

AFTP2901

AFTP2902

AFTP2903

AFTP2904

AUD_AGND

AUD_HP1_JACK_L1_R

AUD_HP1_JACK_R1_R

HPMIC1

3

1

5

6

2

4

MS

AUDIO-JK569-GP

022.10002.00U1

29 106

of

29 106

of

29 106

of

1

A00

D

C

B

A

5

4

3

2

1

D

C

D

C

(Blanking)

A00

B

A

B

Wistron Corporation

A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

(Reserved)

KR CS MLK 13"

Thursday, July 19, 2018

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

30 106

of

30 106

of

30 106

of

1

Dell Inspiron 7380 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual