DELL Inspiron 6400, Inspiron 1505 Schematics

1

www.kythuatvitinh.com

Digitally signed by dd DN: cn=dd, o=dd, ou=dd, email=dddd@yahoo.com, c=US Date: 2009.11.30 17:33:02 +07'00'

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3

4

5

6

7

8

KEYLARGO-Integrate

01

VER : 2A

A A

AC/BATT

RUN POWER SW

PG 44

B B

DDR-SODIMM1

PG 15,16

CONNECTOR

BATT CHARGER

400/533/667 MHZ DDR II

PG 45

PG 39

Yonah

PG 3,4

(478 Micro-FCPGA)

533/667 MHz FSB

Calistoga

PG 5,6,7,8,9,10

DDR-SODIMM2

PG 15,16

SATA - HDD

PG 24

Fixed Odd

PG 24

C C

AUDIO

Audio Jacks

PG 35

D D

MDC

PG 27PG 34

Tip Ring

PG 27

IDE

AC97/Azalia

SPI

Flash

PG 30 PG 28

LPC

SIO MEC5004 128KB Flash TMKBC

128 Pins VTQFP

DMI interfaceSATA

PG 28

1466 uFCBGA

ICH7-M

652 BGA

PG 11,12,13,14

SMB

PS/2

Touch padKeyboard

PG 32

USB2.0 (P4,P6) USB2.0 (P0,P2)

33MHz PCI

SIO ECE5011 Expander USB 2.0 Hub(4)

128 Pins VTQFP

PG 29

1

2

3

4

DC/DC +3V_SRC +5VSUS

PG 41,42,43 PG 40

VGA Daughter Connector

PG 18

TVOUT

CRT

PCI-Express Grapfic

BCM4401

PG 36

CPU VR

LVDS

TVOUT

CRT

2 Back side 2 Right Side

5 in 1 Card/1394

R5C832 PG 21,23

USB2.0 (P1,P5)

PCIEx2

USB2.0 (P7)

5

CLOCKS Thermal

PG 30 PG 30

RJ45/Magnetics

PG 37

1394 Conn.

PG 22

Bluetooth

PG 27

PG 17

Panel Connector

PG 19

S-Video

PG 20

CRT

PG 20

Mini-Card

WLAN

EXPRESS-CARD

PG 25,26

6

Monitor

PG 33

RESET CKT

PG 38

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

COMPUTER

Schematic Block Diagram1

FM1 2A

7

of

151Tuesday, September 06, 2005

8

1

www.kythuatvitinh.com

Pg# Description

1

Schematic Block Diagram 1

2

Blank Page

3

A A

B B

C C

D D

Front Page

4-5

Dothan

6-10

Alviso

11-13

ICH6

14-15

DDRII SO-DIMM(200P)

16

Clock Generator

17

CH7306/7

18-19

Blank Pages

20

LCD Conn. & SSP

21

CRT & TV Conn.

22

SATA & IDE Conn.

23

Screw Hole

24

TI PIC6515

25

Mini PCI Conn.

26

MDC Conn.

27-28

SIO (LPC47N354)

29

SERIAL PORT & USB

30

PARALLEL CONN.

31

Flash ROM

32

TOUCH PAD & BLUE TOOTH

33

Switch Board Conn. & LED

FAN & Thermal

34

Audio CODEC (STAC9751) & Phone Jack

35-36

37-38

LOM (BCM5751), Switch

39

FIR

40-41 Docking Conn. & Q-Switch

42

Power Good

43-44

Battery Selector & Charger

45

CPU Power

46

1.8V,0.9V,1.5V,1.05V

47

3VALW/5V/3V/Power ON

48

RUN Power Switch

49

VGA DC/DC

50

DCIN/Batt Conn.

2

INDEX

DNI LIST

3

4

5

6

7

8

Power & Ground

Label Description

DC_IN+

PBATT+

PWR_SRC

RTC_PWR3_3V

+12V +12V

VHCORE

V1_2RUN AGTL+ POWER (1.2V)

+3VRUN

+3VSUS

+5VALW

+5VRUN

+5VSUS

+5VHDD

+5VMOD

STRB#/5V

+5VFAN1, +5VFAN2

VDDA

1_8VSUS

1_8VRUN

+3VALW 8051 POWER (3V)

V1_5RUN

GND

GNDP

CGNDP

DGNDP DC/DC POWER GND

LANGND

ALL PAGES DIGITAL GROUND

Pg#

AC ADAPTER (20V)

MAIN BATTERY + (10~17V)

MAIN POWER (10~20V)

RTC & PCL POWER

CPU CORE POWER (1.25/1.15V)

SLP_S3# CTRLD POWER

SLP_S5# CTRLD POWER

8051 POWER (5V)

SLP_S3# CTRLD POWER

SLP_S5# CTRLD POWER

HDD POWER (5V)

MODULE POWER (5V)

EXTERNAL FDD POWER (5V)

FAN POWER (5V)

AUDIO ANALOG POWER (5V)

RESUME WELL IN ICH

SLP_S3# CTRLD POWER

AGP I/O POWER

CPU POWER GND

CHARGER GND

COMBO CONN GND

(3_3V)

Control Signal

DRUNPWROK

RUNPWROK

RUN_ON

SUS_ON

RUN_ON

SUS_ON

HDDC_EN#

MODC_EN#

FDD/LPT#

FAN_OFF/ON#

RUN_ON

02

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

1

2

3

4

5

6

Size Document Number Rev

Date: Sheet

COMPUTER

Index, DNI, Power & Ground

FM1 2A

7

of

251Tuesday, September 06, 2005

8

A

www.kythuatvitinh.com

U10A

H_A#[3..31]5

1 1

H_ADSTB#05

H_REQ#05 H_REQ#15 H_REQ#25 H_REQ#35 H_REQ#45

H_A#[3..31]5

H_ADSTB#15

H_A20M#11

H_FERR#11

2 2

H_IGNNE#11

H_STPCLK#11

H_INTR11 H_NMI11

H_SMI#11

H_A#[3..31]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18

H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

U10A

J4

A[3]#

L4

A[4]#

M3

A[5]#

K5

A[6]#

M1

ADDR GROUP 0

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L1

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

L2

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L5

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U2

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W3

A[27]#

W5

A[28]#

Y4

A[29]#

W2

A[30]#

Y1

A[31]#

V4

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

AA1

RSVD[01]#

AA4

RSVD[02]#

AB2

RSVD[03]#

AA3

RSVD[04]#

M4

RSVD[05]#

N5

RSVD[06]#

T2

RSVD[07]#

V3

RSVD[08]#

B2

RSVD[09]#

C3

RSVD[10]#

B25

RSVD[11]#

Yonah

CONTROL

XDP/ITP SIGNALS

THERMTRIP#

THERMH CLK

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

PROCHOT THERMDA THERMDC

BCLK[0] BCLK[1]

RSVD[12]#

RSVD[13]# RSVD[14]# RSVD[15]# RSVD[16]# RSVD[17]# RSVD[18]# RSVD[19]# RSVD[20]#

TDI

B

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

B1 F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

CPU_PROCHOT#

D21 A24 A25

C7

A22 A21

T22

D2 F6 D3 C1 AF1 D22 C23 C24

H_IERR#

ITP_BPM0# ITP_BPM1# ITP_BPM2# ITP_BPM3# ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET#

H_ADS# 5 H_BNR# 5 H_BPRI# 5

H_DEFER# 5 H_DRDY# 5 H_DBSY# 5

H_BR0# 5

H_INIT# 11

H_LOCK# 5

H_RESET# 5 H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5

H_HIT# 5 H_HITM# 5

H_THERMDA & H_THERMDC trace routing W:10/S:10

H_THERMDA 33 H_THERMDC 33

H_THERMTRIP# 33

CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17

H_THERMDA

H_THERMDC

12

C406

C406 2200P_NC

2200P_NC

Place voltage divider within

0.5" of GTLREF pin

H_D#[0..63]5

+1.05V_VCCP

R158

1K/F_0402

R160

2K/F_0402

Populate R114 for Yonah B0 and forward

C

U10B

H_D#[0..63]

H_DSTBN#05 H_DSTBP#05 H_DSTBP#2 5

H_DINV#05

H_D#[0..63]

H_DSTBN#15 H_DSTBP#15

H_DINV#15

R113 1K_NCR113 1K_NC

R114 51_0402R114 51_0402

CPU_BSEL06,17 CPU_BSEL16,17 CPU_BSEL26,17

CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

133 166

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13

H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

V_CPU_GTLREF

TEST1

TEST2

0 0 1 0 1 1

U10B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22 F23 G25 E25 E23 K24 G24

J24

J23 H26 F26 K22 H25 H23 G22

J26

N22 K25 P26 R23 L25 L22 L23

M23

P25 P22 P23 T24

R24

L26 T25

N24 M24 N25 M26

AD26

C26

D25

B22 B23

C21

Delete R320,R321 per

ref sch UMA_A08

D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF

TEST1

TEST2

BSEL[0] BSEL[1] BSEL[2]

Yonah

DATA GRP 0 DATA GRP 1

MISC

D

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]#

DATA GRP 2

D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

DATA GRP 3

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23

AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20

R26 U26 U1 V1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46H_D#14 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51H_A#19 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_D#[0..63]

H_DPRSTP# 11,40 H_DPSLP# 11 H_DPWR# 5

H_PWRGOOD 11

H_CPUSLP# 5,11 H_PSI# 40

E

H_D#[0..63] 5

H_DSTBN#2 5

H_DINV#2 5

H_D#[0..63] 5

H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5

R146

R371

27.4/F_0402

R146

54.9/F_0402

1 2

R384

54.9/F_0402

1 2

Comp0,2 connect with Zo = 27.4ohms, Comp1,3 connect with Zo = 55ohms, make those traces length within 0.5" Need 25mils space for other toggling signals.

03

R141

27.4/F_0402

1 2

Change R391,R405,R406 value per ref sch UMA_A08

3 3

Place R341 within 0.5" with ITP connector

CLK_CPU_ITP#17 CLK_CPU_ITP17

4 4

+1.05V_VCCP

12

R341

51_0402

ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST#

H_RESET# RESET#

ITP_TCK

R396 22.6/F_NCR396 22.6/F_NC

R385 22.6/F_NCR385 22.6/F_NC

A

R406

R406 51_0402

51_0402

1 2

+1.05V_VCCP

R405

39_0402

TDO

12

Plece R391 close to U10

R391

R391 150_0402

150_0402

JITP1

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLKN

9

BCLKP

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

ITP700_NC

VTT0 VTT1

VTAP

DBR# DBA#

BPM0# BPM1# BPM2# BPM3# BPM4# BPM5#

NC0 NC1

+1.05V_VCCP +3.3V_SUS

27 28 26

Place close to JITP1

25 24

ITP_BPM0#

23

ITP_BPM1#

21

ITP_BPM2#

19

ITP_BPM3#

17

ITP_BPM#4

15

ITP_BPM#5

13

4 6

B

1 2

C459

C459 .1U_NC

.1U_NC

12

R366

R366 150_0402

150_0402

ITP_DBRESET# 13,28

H_THERMTRIP#

H_IERR#

H_PWRGOOD

ITP_BPM#5

Signal Resistor Value Connect To ITP_TDI

ITP_TMS ITP_TRST# ITP_TCK TDO

Note: Populate R396, R385, C459 and R450 when ITP connector is populated.

R344 56_0402R344 56_0402

R351 56_0402R351 56_0402

R354 200_NCR354 200_NC

R450 54.9/F_NCR450 54.9/F_NC

150 ohm +/- 5% 39 ohm +/- 5% 680 ohm +/- 5% 27 ohm +/- 5%

Open

+1.05V_VCCP

1 2

C

+1.05V_VCCP +1.05V_VCCP

ITP_TCK

1 2

R404 27.4/F_0402R404 27.4/F_0402

ITP_TRST#

1 2

R403 680_0402R403 680_0402

GND GND N/A

Resistor Placement

Within 2.0" of the CPU Within 2.0" of the CPU Within 2.0" of the CPU Within 2.0" of the CPU Within 2.0" of the CPU

ITP disable guidelines

+1.05V_VCCP

R115

R115 75_0402

75_0402

1 2

D

Delete R129 & Q15. Change R115 from 56ohm to 75ohm per ref sch A08

CPU_PROCHOT# 29

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

COMPUTER

Yonah Processor (HOST)

FM1 2A

E

of

351Tuesday, September 06, 2005

A

www.kythuatvitinh.com

+VCC_CORE

12

C489

C489 22U/4V/0805

22U/4V/0805

1 1

12

C527

C527 22U/4V/0805

22U/4V/0805

12

C447

C447 22U/4V/0805

22U/4V/0805

C487

C487 22U/4V/0805

22U/4V/0805

1 2

2 2

12

C480

C480 22U/4V/0805

22U/4V/0805

12

C380

C380 22U/4V/0805

22U/4V/0805

3 3

12

C381

C381 22U/4V/0805

22U/4V/0805

12

C446

C446 22U/4V/0805

22U/4V/0805

12

C455

C455 22U/4V/0805

22U/4V/0805

C483

C483 22U/4V/0805

22U/4V/0805

1 2

12

C384

C384 22U/4V/0805

22U/4V/0805

12

C383

C383 22U/4V/0805

22U/4V/0805

Place 16caps on north side of CPU and 16 caps on sourth side of CPU

12

+

PC113

PC113 330U/2V/ESR6

330U/2V/ESR6

+VCC_CORE

C386

C386 22U/4V/0805

22U/4V/0805

1 2

+VCC_CORE

12

C439

C439 22U/4V/0805

22U/4V/0805

12

C379

C379 22U/4V/0805

22U/4V/0805

12

C454

C454 22U/4V/0805

22U/4V/0805

C482

C482 22U/4V/0805

22U/4V/0805

1 2

12

C382

C382 22U/4V/0805

22U/4V/0805

12

C433

C433 22U/4V/0805

22U/4V/0805

12

+

PC106

PC106 330U/2V/ESR6

330U/2V/ESR6

C385

C385 22U/4V/0805

22U/4V/0805

1 2

12

C435

C435 22U/4V/0805

22U/4V/0805

12

C463

C463 22U/4V/0805

22U/4V/0805

12

C448

C448 22U/4V/0805

22U/4V/0805

C481

C481 22U/4V/0805

22U/4V/0805

1 2

12

C526

C526 22U/4V/0805

22U/4V/0805

12

C438

C438 22U/4V/0805

22U/4V/0805

12

+

PC114

PC114 330U/2V/ESR6

330U/2V/ESR6

12

C440

C440 22U/4V/0805

22U/4V/0805

12

C456

C456 22U/4V/0805

22U/4V/0805

12

C490

C490 22U/4V/0805

22U/4V/0805

C488

C488 22U/4V/0805

22U/4V/0805

1 2

12

C525

C525 22U/4V/0805

22U/4V/0805

12

C434

C434 22U/4V/0805

22U/4V/0805

B

+VCC_CORE

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10

AB10 AB12 AB14 AB15 AB17 AB18

C

D

E

04

U10D

A4

U10C

A7

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Yonah

VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] VCC[77] VCC[78] VCC[79] VCC[80] VCC[81] VCC[82] VCC[83] VCC[84] VCC[85] VCC[86] VCC[87] VCC[88] VCC[89] VCC[90] VCC[91] VCC[92] VCC[93] VCC[94] VCC[95] VCC[96] VCC[97] VCC[98] VCC[99]

VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

A9 A10 A12 A13 A15 A17 A18 A20

B7

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E7

E9 E10 E12 E13 E15 E17 E18 E20

F7

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

+VCC_CORE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26

AD6 AF5 AE5 AF4 AE3 AF2 AE2

AF7

AE7

Route VCCSENSE and VSSSENSE traces at 27.4ohms with 10mil spacing and for other signals keep out spacing 25mil and length match within 25mil. Place PU and PD within 2 inch of CPU.

+1.05V_VCCP

+

C466

C466 330U/2.5V/ESR9

330U/2.5V/ESR9

VID0 40 VID1 40 VID2 40 VID3 40 VID4 40 VID5 40 VID6 40

VCCSENSE

VSSSENSE

12

+VCC_CORE

C105

C105 .01U/25V/0402

.01U/25V/0402

Place C105,C110 near PIN B26

R408

R408 100/F_0603

100/F_0603

Place R408,R401 close to U1o within 0.5"

R401

R401 100/F_0603

100/F_0603

12

C110

C110 10U/4V/0805

10U/4V/0805

VCCSENSE 40

VSSSENSE 40

+1.5V_RUN

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

A26

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

Yonah

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24

+VCC_CORE

12

+

PC115

PC115 330U_NC

4 4

330U_NC

12

+

PC104

PC104 330U/2V/ESR6

330U/2V/ESR6

Total caps = 2684 uF ESR =6m ohm/4 // 3m ohm/32

A

12

+

PC105

PC105 330U_NC

330U_NC

+1.05V_VCCP

12

C458

C458 .1U/10V/0402

.1U/10V/0402

12

C452

C452 .1U/10V/0402

.1U/10V/0402

12

C449

C449 .1U/10V/0402

.1U/10V/0402

12

C468

C468 .1U/10V/0402

.1U/10V/0402

12

Place these inside socket cavity (North side Secondary)

B

C

C460

C460 .1U/10V/0402

.1U/10V/0402

12

C444

C444 .1U/10V/0402

.1U/10V/0402

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

COMPUTER

Yonah Processor (POWER)

FM1 2A

E

of

451Tuesday, September 06, 2005

A

www.kythuatvitinh.com

B

C

D

E

05

1 1

H_XRCOMP

12

R73

24.9/F_0402

+1.05V_VCCP

12

R71

54.9/F_0402

H_XSCOMP

+1.05V_VCCP

12

2 2

100/F_0402

3 3

100/F_0402

R77

R77 221/F_0402

221/F_0402

12

R78

12

R343

24.9/F_0402

+1.05V_VCCP

12

R319

54.9/F_0402

+1.05V_VCCP

12

R338

R338 221/F_0402

221/F_0402

12

R322

H_SWNG0

C69

C69 .1U/10V/0402

.1U/10V/0402

1 2

H_YRCOMP

H_YSCOMP

H_SWNG1

C409

.1U/10V/0402

1 2

H_D#[0..63]3

CLK_MCH_BCLK17

CLK_MCH_BCLK#17

H_D#[0..63]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_SWNG0

H_YRCOMP H_YSCOMP H_SWNG1

W11

AA10

AB11 AC11

AD10

U11

AB7 AA9

AB8

AA4 AA7 AA2 AA6

AA1 AB4 AC9

AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5

AD4 AC8

AG2 AG1

K11

T10

T11

Y10

F1

J1

H1

J6

H3

K2 G1 G2

K9

K1

K7

J8

H4

J3

G4

T3 U7 U9

W9

T1

T8

T4 W7 U5

T9 W6

T5

W4 W3

Y3

Y7 W5

W2

Y8

E1

E2

E4

Y1 U1 W1

U8A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_XRCOMP H_XSCOMP H_XSWING

H_YRCOMP H_YSCOMP H_YSWING

H_CLKIN H_CLKIN#

Calistoga

HOST

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_VREF_0

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF_1

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_SLPCPU#

H_TRDY#

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13

J7 W8 U3 AB10

K4 T7 Y5 AC4

K3 T6 AA5 AC5

D3 D4 B3

D8 G8 B8 F8 A8

B4 E6 D6

E3 E7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_A#[3..31]

H_A#[3..31] 3

H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3

H_BNR# 3 H_BPRI# 3 H_BR0# 3 H_RESET# 3 H_DBSY# 3 H_DEFER# 3

H_DPWR# 3

H_DRDY# 3

H_DINV#0 3 H_DINV#1 3 H_DINV#2 3 H_DINV#3 3

H_DSTBN#0 3 H_DSTBN#1 3 H_DSTBN#2 3 H_DSTBN#3 3

H_DSTBP#0 3 H_DSTBP#1 3 H_DSTBP#2 3 H_DSTBP#3 3

H_HIT# 3 H_HITM# 3 H_LOCK# 3

H_REQ#0 3 H_REQ#1 3 H_REQ#2 3 H_REQ#3 3 H_REQ#4 3

H_RS#0 3 H_RS#1 3 H_RS#2 3

H_CPUSLP# 3,11 H_TRDY# 3

H_VREF

12

C391

C391 .1U/10V/0402

.1U/10V/0402

+1.05V_VCCP

R312

R312 100/F_0402

100/F_0402

1 2

12

R302

R302 200/F_0402

200/F_0402

H_XRCOPM, H_XSCOMP, H_YRCOMP, H_YSCOMP, H_SWNG0, H_SWNG1 used W:10/S:20 mil.

R & C of HXRCOPM, HXSCOMP, HYRCOMP, HYSCOMP,

4 4

A

H_SWNG0, H_SWNG1 trace length less 0.5" from U3

B

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

C

D

Date: Sheet

COMPUTER

Calistoga (Host)

FM1 2A

E

of

551Tuesday, September 06, 2005

A

www.kythuatvitinh.com

U8B

T32

RSVD_1

R32

RSVD_2

F3

RSVD_3

F7

RSVD_4

AG11

RSVD_5

AF11

AH33 AH34

BA41 BA40 BA39

AY41

AW41

AW1

H7

J19

K30

J29 A41 A35 A34 D28 D27

K16 K18

J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15

J25 K27

J26

G28 F25 H26

G6

H28 H27 K28

D1

C41

C1

BA3 BA2 BA1 B41

B2

AY1

A40

A4

A39

A3

RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN#

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC#

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

Calistoga

PLTRST#12,13,26,28

CFG7

12

CFG9

12

CFGRSVD

PM

MISC

NC

Host PLL VCC Select Low=Reserved High=Mobility

R255

2.2K_NC

R240

FSB Dynamic ODT

2.2K_NC

Low=Dynamic ODT Disable High=Dynamic ODT Enable

1 1

Note: CFG3:17 has internal pullup; CFG18:19 has internal pulldown

CFG[2:0] 001=FSB533 011=FSB667 Others = Reserved

CPU_BSEL03,17 CPU_BSEL13,17 CPU_BSEL23,17

T37

PAD

T40

PAD

12

R257

PAD

2.2K_NC

Low=DMIx2 High=DMIx4

PAD

PAD PAD

PAD

2 2

PM_BMBUSY#13

PM_EXTTS#015

THERMTRIP_MCH#33

ICH_PWRGD13,33,38

DPRSLPVR13,40

MCH_ICH_SYNC#12

T8

PADT8PAD

T9

PADT9PAD

T5

PADT5PAD

T20

PAD

T27

PAD

T23

PAD

T19

PAD

T22

PAD

T26

PAD

T35

PAD

T6

PADT6PAD

T28

PAD

T25

PAD

T21

PAD

T24

PAD

T7

PADT7PAD

T4

PADT4PAD

T2

PADT2PAD

3 3

4 4

T3

PADT3PAD

SDVO_CTRL & SDVO_DATA Low = No SDVO Device Present High = SDVO Device Present

+1.8V_SUS

12

R368

80.6/F_0402

12

R362

80.6/F_0402

CFG3 CFG4

CFG5 CFG6

T39

CFG7 CFG8

T36

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14

T38

CFG15

T42

CFG16 CFG17

T41

CFG18 CFG19 CFG20

PM_EXTTS#1

PLTRST_R#

R434 0_NCR434 0_NC

TP_NC0 TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11 TP_NC12 TP_NC13 TP_NC14 TP_NC15 TP_NC16 TP_NC17 TP_NC18

SMRCOMPN

SMRCOMPP

CPU_Strap Low=RSVD High=Mobile CPU

PCIE Graphics Lane Low = Reveise Lane High = Normal operation

SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3

SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3

SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_OCDCOMP_0 SM_OCDCOMP_1

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP#

SM_RCOMP

DDR MUXINGCLKDMI

SM_VREF_0 SM_VREF_1

G_CLKIN#

G_CLKIN

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

CLK_REQ#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

12

R151 100_0402R151 100_0402

PSB 4X CLK Enable Low=Calistoga High=Reserved

A

AY35 AR1 AW7 AW40

AW35 AT1 AY7 AY40

AU20 AT20 BA29 AY29

AW13 AW12 AY21 AW21

AL20 AF10

BA13 BA12 AY20 AU21

AV9 AT9

AK1 AK41

AF33 AG33 A27 A26 C40 D41 H32

AE35 AF39 AG35 AH39

AC35 AE39 AF35 AG39

AE37 AF41 AG37 AH41

AC37 AE41 AF37 AG41

PLTRST_R#

CFG10

CFG11

CFG16

B

M_CLK_DDR0 15 M_CLK_DDR1 15 M_CLK_DDR2 15 M_CLK_DDR3 15

M_CLK_DDR#0 15 M_CLK_DDR#1 15 M_CLK_DDR#2 15 M_CLK_DDR#3 15

DDR_CKE0_DIMMA 15,16 DDR_CKE1_DIMMA 15,16 DDR_CKE2_DIMMB 15,16 DDR_CKE3_DIMMB 15,16

DDR_CS0_DIMMA# 15,16 DDR_CS1_DIMMA# 15,16 DDR_CS2_DIMMB# 15,16

M_OCDCOMP0 M_OCDCOMP1

SMRCOMPN SMRCOMPP

MCH_DREFCLK#_D MCH_DREFCLK_D DREF_SSCLK#_D DREF_SSCLK_D

12

R256

2.2K_NC

12

R52

2.2K_NC

Depopulate R52 per Intel Update.

12

R239

2.2K_NC

B

DDR_CS3_DIMMB# 15,16

1 2

R356 40.2/F_0402_NCR356 40.2/F_0402_NC

1 2

R353 40.2/F_0402_NCR353 40.2/F_0402_NC

M_ODT0 15,16 M_ODT1 15,16 M_ODT2 15,16 M_ODT3 15,16

V_DDR_MCH_REF

CLK_MCH_3GPLL# 17 CLK_MCH_3GPLL 17

R310 0_0402R310 0_0402 R309 0_0402R309 0_0402 R58 0_0402R58 0_0402 R64 0_0402R64 0_0402

DMI_MRX_ITX_N0 12 DMI_MRX_ITX_N1 12 DMI_MRX_ITX_N2 12 DMI_MRX_ITX_N3 12

DMI_MRX_ITX_P0 12 DMI_MRX_ITX_P1 12 DMI_MRX_ITX_P2 12 DMI_MRX_ITX_P3 12

DMI_MTX_IRX_N0 12 DMI_MTX_IRX_N1 12 DMI_MTX_IRX_N2 12 DMI_MTX_IRX_N3 12

DMI_MTX_IRX_P0 12 DMI_MTX_IRX_P1 12 DMI_MTX_IRX_P2 12 DMI_MTX_IRX_P3 12

V_DDR_MCH_REF

12

Place C442,C176 close to U3.AK1 & U3.AK41

CFG[13:12] 00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operatio *

PCIe Backward Interpoerability mode Low=Only SDVO or PCIEx1 is operational (defaults) High=SDVO and PCIEx1 are operating simultaneously via PEG port

C442

C442 .1U/10V/0402

.1U/10V/0402

CFG12

CFG13

12

C176

C176 .1U/10V/0402

.1U/10V/0402

12

+3.3V_RUN+3.3V_RUN

R215

R216

R216 10K_0402

10K_0402

1 2

Populate R356,R353 for A1 Calistoga(MCH).

For Discrete: Populate R298,R63,R299,R57 De-populate R58,R84,R301,R310

MCH_DREFCLK_D

DREF_SSCLK_D

MCH_DREFCLK#_D

DREF_SSCLK#_D

MCH_DREFCLK# 17 MCH_DREFCLK 17 DREF_SSCLK# 17 DREF_SSCLK 17 CLK_3GPLLREQ# 17

+1.05V_VCCP

NTCRT_B18

NTCRT_G18

NTCRT_R18

VCC Select Low=1.05V

R241

High=1.5V

2.2K_NC

DMI Lane Reversal

R51

Low=Normal

2.2K_NC

High=Lane Reversed

Updated it per Intel

10K_0402

check list and ref sch.

1 2

LDOC_CLK LDOC_DATA

ref CL:1301 P.26

1 2

R298 0_NCR298 0_NC

1 2

R63 0_NCR63 0_NC

1 2

R299 0_NCR299 0_NC

1 2

R57 0_NCR57 0_NC

INT_HSYNC18

INT_VSYNC18

R290 0_NCR290 0_NC R300 0_NCR300 0_NC

CFG18

CFG19

CFG20

C

For Discrete: De-populate R286,R275,R215,R216

BIA_PWM_MCH_R

PANEL_BKEN19

LDOC_CLK19 LDOC_DATA19

ENVDD19

+1.5V_RUN

COMP/B18

Y/G18 C/R18

1 2

R48 150/F_0402R48 150/F_0402

1 2

R31 150/F_0402R31 150/F_0402

1 2

R49 150/F_0402R49 150/F_0402

R56 0_NCR56 0_NC R41 0_NCR41 0_NC R54 0_NCR54 0_NC R232 0_NCR232 0_NC

1 2

R55 150/F_0402R55 150/F_0402

1 2

R39 150/F_0402R39 150/F_0402

1 2

R53 150/F_0402R53 150/F_0402

R233 0_0402R233 0_0402

For Discrete: Populate R32,R35,R37,R38,R308,R56 R41,R54,R232,R290,R300,R313. De-populate: R48,R31,R49,R297,R55 R39,R53,R233,R307,R33

+3.3V_RUN

R229

R229 1K_NC

1K_NC

1 2

+3.3V_RUN

R225

R225 1K_NC

1K_NC

1 2

+3.3V_RUN

R226

R226 1K_NC

1K_NC

1 2

C

1 2

R286 0_0402R286 0_0402

1 2

R275 1.5K/F_0402R275 1.5K/F_0402

LCD_ACLK-19 LCD_ACLK+19 LCD_BCLK-19 LCD_BCLK+19

LCD_A0-19 LCD_A1-19 LCD_A2-19

LCD_A0+19 LCD_A1+19 LCD_A2+19

LCD_B0-19 LCD_B1-19 LCD_B2-19

+1.5V_RUN

LCD_B0+19 LCD_B1+19 LCD_B2+19

R32 0_NCR32 0_NC R38 0_NCR38 0_NC R35 0_NCR35 0_NC R37 0_NCR37 0_NC R308 0_NCR308 0_NC

1 2

G_CLK_DDC2 G_DAT_DDC2

1 2

R307 255/F_0402R307 255/F_0402

+1.05V_VCCP

R313 0_NCR313 0_NC

BIA_PWM_MCH_R

Added BIA_PWM converted I/F gate per GG list

LCTLA_CLK LCTLB_DAT

R297

4.99K/F

U8C

BIA_PWM_MCH

TVIREF

U8C

D32

L_BKLTCTL

J30

L_BKLTEN

H30

L_CLKCTLA

H29

L_CLKCTLB

G26

L_DDC_CLK

G25

L_DDC_DATA

L_IBG

B38

L_IBG

C35

L_VBG

F32

L_VDDEN

C33

L_VREFH

C32

L_VREFL

A33

LA_CLK#

A32

LA_CLK

E27

LB_CLK#

E26

LB_CLK

C37

LA_DATA#_0

B35

LA_DATA#_1

A37

LA_DATA#_2

B37

LA_DATA_0

B34

LA_DATA_1

A36

LA_DATA_2

G30

LB_DATA#_0

D30

LB_DATA#_1

F29

LB_DATA#_2

F30

LB_DATA_0

D29

LB_DATA_1

F28

LB_DATA_2

A16

TV_DACA_OUT

C18

TV_DACB_OUT

A19

TV_DACC_OUT

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

R33

R33 0_0402

0_0402

E23

CRT_BLUE

D23

CRT_BLUE#

C22

CRT_GREEN

B22

CRT_GREEN#

A21

CRT_RED

B21

CRT_RED#

C26

CRT_DDC_CLK

C25

CRT_DDC_DATA

G23

CRT_HSYNC

J22

CRT_IREF

H23

CRT_VSYNC

Calistoga

VGA_IREF Nets should be Routed 20 mils away from any Signals.Per Intel

+3.3V_RUN

5

U40

2

1

NC7SZ08P5X_NL

4

+3.3V_RUN

R223 10K_0402R223 10K_0402

R224 10K_0402R224 10K_0402

R228 10K_0402R228 10K_0402

R227 10K_0402R227 10K_0402

+1.05V_VCCP

R86 75_0402R86 75_0402

D

LVDS

TV

VGA

BIA_PWM 18,19,28

For Discrete: De-populate R223,R224,RP1,Q4,Q5,U40

1 2

D

+1.5VRUN_PCIE

R284

24.9/F_0402

VCC3G_PCIE_R

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8

EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15

EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8

EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15

LCTLA_CLK

LCTLB_DAT

PM_EXTTS#0

PM_EXTTS#1

THERMTRIP_MCH#

D40 D38

PCIE_MRX_GTX_N0

F34

PCIE_MRX_GTX_N1

G38

PCIE_MRX_GTX_N2

H34

PCIE_MRX_GTX_N3

J38

PCIE_MRX_GTX_N4

L34

PCIE_MRX_GTX_N5

M38

PCIE_MRX_GTX_N6

N34

PCIE_MRX_GTX_N7

P38

PCIE_MRX_GTX_N8

R34

PCIE_MRX_GTX_N9

T38

PCIE_MRX_GTX_N10

V34

PCIE_MRX_GTX_N11

W38

PCIE_MRX_GTX_N12

Y34

PCIE_MRX_GTX_N13

AA38

PCIE_MRX_GTX_N14

AB34

PCIE_MRX_GTX_N15

AC38

PCIE_MRX_GTX_P0

D34

PCIE_MRX_GTX_P1

F38

PCIE_MRX_GTX_P2

G34

PCIE_MRX_GTX_P3

H38

PCIE_MRX_GTX_P4

J34

PCIE_MRX_GTX_P5

L38

PCIE_MRX_GTX_P6

M34

PCIE_MRX_GTX_P7

N38

PCIE_MRX_GTX_P8

P34

PCIE_MRX_GTX_P9

R38

PCIE_MRX_GTX_P10

T34

PCIE_MRX_GTX_P11

V38

PCIE_MRX_GTX_P12

W34

PCIE_MRX_GTX_P13

Y38

PCIE_MRX_GTX_P14

AA34

PCIE_MRX_GTX_P15

AB38

PCIE_MTX_GRX_N0

F36

PCIE_MTX_GRX_N1

G40

PCIE_MTX_GRX_N2

H36

PCIE_MTX_GRX_N3

J40

PCIE_MTX_GRX_N4

L36

PCIE_MTX_GRX_N5

M40

PCIE_MTX_GRX_N6

N36

PCIE_MTX_GRX_N7

P40

PCIE_MTX_GRX_N8

R36

PCIE_MTX_GRX_N9

T40

PCIE_MTX_GRX_N10

V36

PCIE_MTX_GRX_N11

W40

PCIE_MTX_GRX_N12

Y36

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AB36

PCIE_MTX_GRX_N15

AC40

PCIE_MTX_GRX_P0

D36

PCIE_MTX_GRX_P1

F40

PCIE_MTX_GRX_P2

G36

PCIE_MTX_GRX_P3

H40

PCIE_MTX_GRX_P4

J36

PCIE_MTX_GRX_P5

L40

PCIE_MTX_GRX_P6

M36

PCIE_MTX_GRX_P7

N40

PCIE_MTX_GRX_P8

P36

PCIE_MTX_GRX_P9

R40

PCIE_MTX_GRX_P10

T36

PCIE_MTX_GRX_P11

V40

PCIE_MTX_GRX_P12

W36

PCIE_MTX_GRX_P13

Y40

PCIE_MTX_GRX_P14

AA36

PCIE_MTX_GRX_P15

AB40

G_DAT_DDC2

G_CLK_DDC2

Title

Calistoga (VGA,DMI)

Size Document Number Rev

FM1 2A

Date: Sheet

1 2

+3.3V_RUN

RP1

RP1 4P2R-2.2K

4P2R-2.2K

+3.3V_RUN

2

+3.3V_RUN

1

Q5

Q5 2N7002W-7-F

2N7002W-7-F

3

1

3

2

4

1

QUANTA

QUANTA COMPUTER

COMPUTER

E

2

E

Q4

Q4 2N7002W-7-F

2N7002W-7-F

3

06

PCIE_MRX_GTX_N[0..15] 18

PCIE_MRX_GTX_P[0..15] 18

PCIE_MTX_GRX_N[0..15] 18

PCIE_MTX_GRX_P[0..15] 18

INT_DAT_DDC2 18

INT_CLK_DDC2 18

of

651Tuesday, September 06, 2005

A

www.kythuatvitinh.com

B

C

D

E

07

1 1

DDR_A_D[0..63]15

2 2

3 3

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ35

AJ34 AM31 AM33

AJ36 AK35

AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26

AL27 AM26 AN24 AK28

AL28 AM24 AP26 AP23

AL22 AP21 AN20

AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12

AL14

AL12

AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2

AW2

AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

U8D

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

Calistoga

AU12

SA_BS_0

AV14

SA_BS_1

BA20

SA_BS_2

AY13

SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR SYSTEM MEMORY A

SA_WE#

AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4

AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5

AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12

AW14 AK23 AK24 AY14

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_BS0 15,16 DDR_A_BS1 15,16 DDR_A_BS2 15,16 DDR_A_CAS# 15,16 DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..13] 15,16

DDR_A_RAS# 15,16

T58 PADT58 PAD

DDR_A_WE# 15,16

DDR_B_D[0..63]15

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AK39

AJ37 AP39 AR41

AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40

AW38

AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31

AW31

AV29

AW29

AM19

AL19 AP14 AN14 AN17 AM16 AP15

AL15

AJ11 AH10

AN10 AK13 AH11 AK10

BA10

AW10

AW4 AY10

AW5

U8E

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41

AJ9

SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46

AJ8

SB_DQ47 SB_DQ48 SB_DQ49

BA4

SB_DQ50 SB_DQ51 SB_DQ52

AY9

SB_DQ53 SB_DQ54

AY5

SB_DQ55

AV4

SB_DQ56

AR5

SB_DQ57

AK4

SB_DQ58

AK3

SB_DQ59

AT4

SB_DQ60

AK5

SB_DQ61

AJ5

SB_DQ62

AJ3

SB_DQ63

Calistoga

SB_RCVENIN#

SB_RCVENOUT#

DDR SYSTEM MEMORY B

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_WE#

AT24 AV23 AY28

AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4

AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5

AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23

AU23 AK16 AK18 AR27

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_BS0 15,16 DDR_B_BS1 15,16 DDR_B_BS2 15,16 DDR_B_CAS# 15,16 DDR_B_DM[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_MA[0..13] 15,16

DDR_B_RAS# 15,16

T59 PADT59 PADT52 PADT52 PAD T53 PADT53 PAD

DDR_B_WE# 15,16

4 4

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

A

B

C

D

Size Document Number Rev

Date: Sheet

COMPUTER

Calistoga (DDR2)

FM1

E

751Tuesday, September 06, 2005

2A

of

751Tuesday, September 06, 2005

E

www.kythuatvitinh.com

U8G

+1.05V_VCCP

4 4

3 3

2 2

1 1

AA33

W33

N33

AA32

W32

N32 M32

AA31

W31

R31

N31 M31

AA30

W30

U30

R30

N30 M30

AA29

W29

U29 R29

M29

AB28 AA28

U28

R28

N28 M28

N27 M27

N26

N25 M25

N24

M24 AB23 AA23

N23

M23

AC22 AB22

W22

N22

M22

AC21 AA21

W21

N21

M21

AC20 AB20

W20

N20

M20

AB19 AA19

N19

M19

N18

M18

N17

M17

N16

M16

VCC_0 VCC_1

P33

VCC_2 VCC_3

L33

VCC_4

J33

VCC_5 VCC_6

Y32

VCC_7 VCC_8

V32

VCC_9

P32

VCC_10 VCC_11 VCC_12

L32

VCC_13

J32

VCC_14 VCC_15 VCC_16

V31

VCC_17

T31

VCC_18 VCC_19

P31

VCC_20 VCC_21 VCC_22 VCC_23

Y30

VCC_24 VCC_25

V30

VCC_26 VCC_27

T30

VCC_28 VCC_29

P30

VCC_30 VCC_31 VCC_32

L30

VCC_33 VCC_34

Y29

VCC_35 VCC_36

V29

VCC_37 VCC_38 VCC_39

P29

VCC_40 VCC_41

L29

VCC_42 VCC_43 VCC_44

Y28

VCC_45

V28

VCC_46 VCC_47

T28

VCC_48 VCC_49

P28

VCC_50 VCC_51 VCC_52

L28

VCC_53

P27

VCC_54 VCC_55 VCC_56

L27

VCC_57

P26

VCC_58 VCC_59

L26

VCC_60 VCC_61 VCC_62

L25

VCC_63

P24

VCC_64 VCC_65 VCC_66 VCC_67 VCC_68

Y23

VCC_69

P23

VCC_70 VCC_71 VCC_72

L23

VCC_73 VCC_74 VCC_75

Y22

VCC_76 VCC_77

P22

VCC_78 VCC_79 VCC_80

L22

VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86

L21

VCC_87 VCC_88 VCC_89

Y20

VCC_90 VCC_91

P20

VCC_92 VCC_93 VCC_94

L20

VCC_95 VCC_96 VCC_97

Y19

VCC_98 VCC_99 VCC_100

L19

VCC_101 VCC_102 VCC_103

L18

VCC_104

P17

VCC_105 VCC_106 VCC_107 VCC_108 VCC_109

L16

VCC_110

VCC

Calistoga

E

D

VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8

VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99

VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107

D

AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

VCCSM_LF4 VCCSM_LF5

12

C193

C193 .47U/10V/0603

.47U/10V/0603

Place C193 close to U3.AM41 Place C192 close to U3.AT41

C640

.1U/10V/0402

1 2

C641

.1U/10V/0402

1 2

12

C192

C192 .47U/10V/0603

.47U/10V/0603

1 2

Added per ref sch UMA_A08

12

C477

C477 .47U/10V/0603

.47U/10V/0603

Place C477 close to U3.BA23

+1.8V_SUS

12

Place In Cavity

VCCSM_LF2

VCCSM_LF1

12

C437

C437 10U/4V/0805

10U/4V/0805

Place C465 close to U3.AV1

Place C146 close to U3.AJ1

C195

C195 10U/4V/0805

10U/4V/0805

Place C473 close to U3.BA15

1 2

C465 .47U/10V/0603C465 .47U/10V/0603

1 2

C146 .47U/10V/0603C146 .47U/10V/0603

+1.05V_VCCP

C642

.1U/10V/0402

12

C473

C473 .47U/10V/0603

.47U/10V/0603

C

+

C378

C378 330U/2.5V/ESR9

330U/2.5V/ESR9

+

C377

C377 330U/2.5V/ESR9

330U/2.5V/ESR9

C643

.1U/10V/0402

1 2

C

12

C422

C422 10U/4V/0805

10U/4V/0805

12

C423

C423 10U/4V/0805

10U/4V/0805

Delete C198 per ref sch M07_UMA_A08.

12

C403

C403 1U/10V/0603

1U/10V/0603

12

C398

C398 .22U/25V/0603

.22U/25V/0603

12

C411

C411 .22U/25V/0603

.22U/25V/0603

12

C397

C397 .22U/25V/0603

.22U/25V/0603

AD27 AC27

AB27 AA27

W27

AD26 AC26

AB26 AA26

W26

AD25 AC25

AB25 AA25

W25

AD24 AC24

AB24 AA24

W24

AD23

AD22

AD21

AD20

AD19

AD18 AC18

AB18 AA18

W18

B

Y27

V27

U27

T27

R27

Y26

V26

U26

T26

R26

Y25

V25

U25

T25

R25

Y24

V24

U24

T24

R24

V23

U23

T23

R23

V22

U22

T22

R22

V21

U21

T21

R21

V20

U20

T20

R20

V19

U19

T19

Y18

V18

U18

T18

B

U8F

VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72

NCTF

Calistoga

A

08

AE27

VSS_NCTF0

AE26

VSS_NCTF1

AE25

VSS_NCTF2

AE24

VSS_NCTF3

AE23

VSS_NCTF4

AE22

VSS_NCTF5

AE21

VSS_NCTF6

AE20

VSS_NCTF7

AE19

VSS_NCTF8

AE18

VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8

VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57

Title

Size Document Number Rev

Date: Sheet

AC17 Y17 U17

AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

QUANTA

QUANTA COMPUTER

COMPUTER

Calistoga (VCC, NCTF)

FM1 2A

A

+1.5V_RUN

of

851Tuesday, September 06, 2005

E

www.kythuatvitinh.com

12

+2.5V_CRTDAC

12

C347

+1.5V_RUN_DPLLA

12

+

C340

C340 470U/4V/ESR15

470U/4V/ESR15

+1.5V_RUN_DPLLB

12

+

C337

C337 470U/4V/ESR15

470U/4V/ESR15

1 2

L31

L31 BLM18PG330SN1D

BLM18PG330SN1D

3A

12

C354

C354 .1U/10V/0402

.1U/10V/0402

+1.5V_RUN

+2.5V_RUN

4 4

+1.05V_VCCP

For Discrete: Populate R296 Depopulate L27,C347,C354

+1.5V_RUN +1.5V_RUN

L29

L29 10uH_60mA(LQM21FN100N00L)

10uH_60mA(LQM21FN100N00L)

.1U/10V/0402

L30

3 3

L30 10uH_60mA(LQM21FN100N00L)

10uH_60mA(LQM21FN100N00L)

.1U/10V/0402

R449

0.002/F_1206

1 2

L27

L27 BLM18PG330SN1D

BLM18PG330SN1D

3A

.022U/16V/0402

1 2

R296 0_NCR296 0_NC

12

C364

12

C373

For Discrete: Depopulate C340, C337

+1.5VRUN_PCIE

C70

220U/6.3V/ESR25

0506: ref CL1301 P35

Place C347,C354 close to U8.E21 U8.F21 less than 250mils.

U8.G21 should connect to C347 C354 after connect to GND

+1.5V_RUN

40mA Max.

Place C70 & C78 on same side as U8. No Vias.

12

+

C78

C78 10U/4V/0805

10U/4V/0805

12

R467

12

0.002/F_1206

C191

C191 .1U/10V/0402

.1U/10V/0402

L7

12

BLM11A121S

0.2A

C129

.1U/10V/0402

L32

12

BLM11A121S

0.2A

C426

.1U/10V/0402

12

C88

C88 10U/4V/0805

10U/4V/0805

1 2

L11 BLM18PG181SN1DL11 BLM18PG181SN1D

12

C364,C129,C373,C426 pleaced within 200mil.

Delete C657,C676,C677 per ref schematic

+3V_TVDAC

+3.3V_RUN

2 2

+1.5V_RUN

For Discrete: Populate R34 De-populate L26,C335,C40,C346,C350,C32,C46,C35

+1.5V_RUN

1 1

For Discrete: Populate R235, C41 De-populate R254,C344,C334,C45

1 2

L26

L26 BLM18PG181SN1D

BLM18PG181SN1D

1.5A

10U/10V/0805

1 2

R34 0_NCR34 0_NC

R254 0_0805R254 0_0805

L2

1 2

BLM18PG181SN1D

1.5A

C335

12

R235

R235 0_NC

0_NC

C41

C41 22U_NC

22U_NC

12

2.2U/6.3V/0603

1 2

12

C32

C344

.1U/10V/0402

C48

.1U/10V/0402

Populate C657,C676,C677 per ref schematic A01

12

C675

.1U/10V/0402

12

.1U/10V/0402

12

C40

C346

C350

C46

12

C334

C334 .022U/16V/0402

.022U/16V/0402

12

C45

C45 .022U/16V/0402

.022U/16V/0402

C675 .022U/16V/0402

.022U/16V/0402

12

C676

C676 .022U/16V/0402

.022U/16V/0402

12

C677

C677 .022U/16V/0402

.022U/16V/0402

12

C35

4.7U/10V/0805

Place C334,C344 close to U8.D21 less than 250mils.

Place C45,C48 close to U8.H19 less than 250mils.

E

12

C658

.1U/10V/0402

1.5A

+1.5V_RUN_HPLL

12

C123

C123 22U/10V/1206

22U/10V/1206

+1.5V_RUN_MPLL

12

C431

C431 22U/10V/1206

22U/10V/1206

1 2

R44 0_0603R44 0_0603

123

C43

C43 22nF_3P_NC

22nF_3P_NC

1 2

R253 0_0603R253 0_0603

123

C349

C349 22nF_3P_NC

22nF_3P_NC

1 2

R250 0_0603R250 0_0603

123

C348

C348 22nF_3P_NC

22nF_3P_NC

R47 0_0603R47 0_0603

123

C42

C42 22nF_3P_NC

22nF_3P_NC

D

W=30

12

C659

.1U/10V/0402

+3GPLL_R

R149

0.5/F_0805

10U/4V/0805

C425 Should be placed in cavity

45mA Max.

+1.5V_RUN

For Discrete: Populate R258 De-populate R272,C356,C362

+3.3V_RUN_TVDACA

+3.3V_RUN_TVDACB

C43,C349,C348,C42 placed with in its pins

+3.3V_RUN_TVDACC

+3VRUN_ATVBG

VSS_TVBG

+1.5V_RUN_TVDAC

+1.5V_RUN_QTVDAC

D

+2.5V_RUN

C38

.1U/10V/0402

12

C425

+2.5V_RUN

For Discrete: Populate: R29 Depopulate: R46, C31,C34

12

R272 0_0805R272 0_0805

For Discrete:

R45

R45 0_0805

0_0805

1 2

12

+1.5V_RUN_3GPLL

12

C419

C419 .1U/10V/0402

.1U/10V/0402

R258

R258 0_NC

0_NC

Populate R50 De-populate R45,C38,C29,C36

R50

0_NC

1 2

+2.5V_RUN

12

C374

C374 .1U/10V/0402

.1U/10V/0402

Place C374 to U3.G41 within 200mil

R46 0_0805R46 0_0805

1 2

12

.1U/10V/0402

12

C356

10U/4V/0805

+1.05V_VCCP

+1.5V_RUN +3.3V_RUN

C29

4.7U/10V/0805

Place C29, C36 close to U4.C30, U4.B30, U4.A30

VSSA_3GBG

12

C31

C34

.01U/25V/0402

12

C362

.1U/10V/0402

10U/10V/0805

2 1

D22 1SS355D22 1SS355

2 1

D23 1SS355D23 1SS355

C

12

+3.3V_RUN

12

C328

R435 10_0402R435 10_0402

R436 10_0402R436 10_0402

C

12

C36

.1U/10V/0402

R29

R29 0_NC

0_NC

1 2

12

C369

.1U/10V/0402

1 2

+1.5VRUN_PCIE

+2.5V_CRTDAC

+1.5V_RUN_DPLLA +1.5V_RUN_DPLLB +1.5V_RUN_HPLL

+1.5V_RUN_MPLL

+3VRUN_ATVBG VSS_TVBG

+3.3V_RUN_TVDACA

+3.3V_RUN_TVDACB

+3.3V_RUN_TVDACC

+1.5V_RUN

+1.5V_RUN_TVDAC

+1.5V_RUN_QTVDAC

+1.5V_RUN

12

C421

C421 .1U/10V/0402

.1U/10V/0402

+2.5V_RUN

AJ41

AB41

AC33

G41

G21

G20

AH1 AH2

AK31

AF31 AE31 AC31

AL30 AK30

AJ30 AH30 AG30

AF30 AE30 AD30 AC30 AG29

AF29 AE29 AD29 AC29 AG28

AF28 AE28 AH22

AJ21 AH21

AJ20 AH20 AH19

AH15

AH14 AG14

AF14 AE14

AF13 AE13

AF12 AE12 AD12

H22

C30 B30 A30

Y41 V41 R41 N41

L41

H41

F21 E21

B26 C39 AF1

A38 B39

AF2

H20

E19 F19 C20 D20 E20 F20

A28 B28 C28

D21

A23 B23 B25

H19

P19 P16

P15

Y14

U8H

VCCSYNC

VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2

VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL

VCCA_LVDS VSSA_LVDS

VCCA_MPLL

VCCA_TVBG VSSA_TVBG

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2

VCCD_TVDAC

VCC_HV0 VCC_HV1 VCC_HV2

VCCD_QTVDAC

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40

B

POWER

Calistoga

B

A

AC14

VTT_0

AB14

VTT_1

W14

VTT_2

V14

VTT_3

T14

VTT_4

R14

VTT_5

P14

VTT_6

N14

VTT_7

M14

VTT_8

L14

VTT_9

AD13

VTT_10

AC13

VTT_11

AB13

VTT_12

AA13

VTT_13

Y13

VTT_14

W13

VTT_15

V13

VTT_16

U13

VTT_17

T13

VTT_18

R13

VTT_19

N13

VTT_20

M13

VTT_21

L13

VTT_22

AB12

VTT_23

AA12

VTT_24

Y12

VTT_25

W12

VTT_26

V12

VTT_27

U12

VTT_28

T12

VTT_29

R12

VTT_30

P12

VTT_31

N12

VTT_32

M12

VTT_33

L12

VTT_34

R11

VTT_35

P11

VTT_36

N11

VTT_37

M11

VTT_38

R10

VTT_39

P10

VTT_40

N10

VTT_41

M10

VTT_42

P9

VTT_43

N9

VTT_44

M9

VTT_45

R8

VTT_46

P8

VTT_47

N8

VTT_48

M8

VTT_49

P7

VTT_50

N7

VTT_51

M7

VTT_52

R6

VTT_53

P6

VTT_54

M6

VTT_55

A6

VTT_56

R5

VTT_57

P5

VTT_58

N5

VTT_59

M5

VTT_60

P4

VTT_61

N4

VTT_62

M4

VTT_63

R3

VTT_64

P3

VTT_65

N3

VTT_66

M3

VTT_67

R2

VTT_68

P2

VTT_69

M2

VTT_70

D2

VTT_71

AB1

VTT_72

R1

VTT_73

P1

VTT_74

N1

VTT_75

M1

VTT_76

Title

Size Document Number Rev

Date: Sheet

+1.05V_VCCP

+

C101

C101 330U/2.5V/ESR9

330U/2.5V/ESR9

VTTLF_CAP3

Place C44 close to U8.A6.

VTTLF_CAP2 VTTLF_CAP1

Place C117 close to U8.AB1.

QUANTA

QUANTA COMPUTER

COMPUTER

Calistoga (Power)

FM1 2A

12

C390

2.2U/6.3V/0603

Place in Cavity.

+1.05V_VCCP

12

C400

C400 .22U/25V/0603

.22U/25V/0603

Place on the edge.

Place C400 close to U8.AB13

1 2

C44 .47U/10V/0603C44 .47U/10V/0603

12

C117

C117 .47U/10V/0603

.47U/10V/0603

A

12

Place C368 close to U8.D2.

09

12

C418

4.7U/10V/0805

C368

C368 .22U/25V/0603

.22U/25V/0603

951Tuesday, September 06, 2005

of

E

www.kythuatvitinh.com

D

C

B

A

U8I

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

4 4

3 3

2 2

1 1

AV40 AP40 AN40 AK40

AJ40 AH40 AG40 AF40 AE40

AY39

AW39

AV39 AR39 AN39

AJ39 AC39 AB39 AA39

AT38

AM38

AH38 AG38 AF38 AE38

AK37 AH37 AB37 AA37

AY36

AW36

AN36 AH36 AG36 AF36 AE36 AC36

BA35 AV35 AR35 AH35 AB35 AA35

AN34

W39

R39

N39 M39

H39 G39

D39

C38

W37

R37

N37 M37

H37 G37

D37

C36

W35

R35

N35 M35

H35 G35

D35

VSS_6

F41

VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16

B40

VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26

Y39

VSS_27 VSS_28

V39

VSS_29

T39

VSS_30 VSS_31

P39

VSS_32 VSS_33

VSS

VSS_34

L39

VSS_35

J39

VSS_36 VSS_37 VSS_38

F39

VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51

Y37

VSS_52 VSS_53

V37

VSS_54

T37

VSS_55 VSS_56

P37

VSS_57 VSS_58 VSS_59

L37

VSS_60

J37

VSS_61 VSS_62 VSS_63

F37

VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74

B36

VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y35

VSS_82 VSS_83

V35

VSS_84

T35

VSS_85 VSS_86

P35

VSS_87 VSS_88 VSS_89

L35

VSS_90

J35

VSS_91 VSS_92 VSS_93

F35

VSS_94 VSS_95 VSS_96

Calistoga

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23

AT23 AN23 AM23 AH23 AC23

W23

AA22

BA21 AV21 AR21 AN21

AL21 AB21

AW20

AR20

AM20

AA20

AN19 AC19

W19

AH18

AY17 AR17 AP17

AM17

AK17 AV16 AN16

AL16

AN15

AM15

AK15

M15

BA14

AT14 AK14 AD14 AA14

AV13 AR13 AN13

AM13

AL13 AG13

AY12 AC12

AD11 AA11

U8J

VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185

K23

VSS_186

J23

VSS_187

F23

VSS_188

C23

VSS_189 VSS_190

K22

VSS_191

G22

VSS_192

F22

VSS_193

E22

VSS_194

D22

VSS_195

A22

VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202

Y21

VSS_203

P21

VSS_204

K21

VSS_205

J21

VSS_206

H21

VSS_207

C21

VSS_208 VSS_209 VSS_210

VSS

VSS_211 VSS_212

K20

VSS_213

B20

VSS_214

A20

VSS_215 VSS_216 VSS_217 VSS_218

K19

VSS_219

G19

VSS_220

C19

VSS_221 VSS_222

P18

VSS_223

H18

VSS_224

D18

VSS_225

A18

VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234

J16

VSS_235

F16

VSS_236

C16

VSS_237 VSS_238 VSS_239 VSS_240

N15

VSS_241 VSS_242

L15

VSS_243

B15

VSS_244

A15

VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250

U14

VSS_251

K14

VSS_252

H14

VSS_253

E14

VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260

P13

VSS_261

F13

VSS_262

D13

VSS_263

B13

VSS_264 VSS_265 VSS_266

K12

VSS_267

H12

VSS_268

E12

VSS_269 VSS_270 VSS_271

Y11

VSS_272

Calistoga

VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

10

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

E

D

C

B

Size Document Number Rev

Date: Sheet

COMPUTER

Calistoga (VSS,NCTF)

FM1 2A

A

of

10 51Tuesday, September 06, 2005

A

www.kythuatvitinh.com

B

C

D

E

11

+1.05V_VCCP

W1

32.768KHZ

1 2

R468 0_0402R468 0_0402

T16 PADT16 PAD T13 PADT13 PAD T15 PADT15 PAD T10 PADT10 PAD

T11 PADT11 PAD

T17 PADT17 PAD

T47 PADT47 PAD T45 PADT45 PAD T44 PADT44 PAD

T43 PADT43 PAD T46 PADT46 PAD T50 PADT50 PAD

ICH_AZ_CODEC_SDIN034

ICH_AZ_MDC_SDIN127

12

CLK_PCIE_SATA#17

CLK_PCIE_SATA17

IDE_DIOR#24 IDE_DIOW#24

IDE_DDACK#24

IDE_IRQ24 IDE_DIORDY24 IDE_DDREQ24

R126

STUFF

UNSTUFF

ICH_RTCX1

R106

R106 10M_0402

10M_0402

1 2

ICH_RTCX2

ICH_RTCRST#

SM_INTRUDER# INTVEREN#

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST#

T12 PADT12 PAD

ACZ_SDOUT

SATA_ACT#32

SATA_TX0-_C SATA_TX0+_C

SATABIAS

12

R123 24.9/F_0402R123 24.9/F_0402

AF18

AH10 AG10

AF15 AH15 AF16 AH16 AG16 AE15

AB1 AB2

AA3

AF3 AE3 AG2 AH2

AF7 AE7 AG6 AH6

AF1 AE1

W4

W1

W3

U3

U5

U7

U1 R6

R5

U11A

RTXC1 RTCX2

RTCRST#

Y5

INTRUDER# INTVRMEN

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT EE_DIN

V3

LAN_CLK

LAN_RSTSYNC

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST#

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

T4

ACZ_SDOUT

SATALED#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA_CLKN SATA_CLKP

SATARBIASN SATARBIASP

DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

ICH7-M

LPCCPU

RTCLAN

AC-97/AZALIA

SATA

IDE

LAD0 LAD1 LAD2 LAD3

LDRQ0#

LDRQ1#/GPIO23

LFRAME#

A20GATE

A20M#

CPUSLP#

TP1/DPRSTP#

TP2/DPSLP#

FERR#

GPIO49/CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THERMTRIP#

DD10 DD11 DD12 DD13 DD14 DD15

DCS1# DCS3#

NMI

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9

DA0 DA1 DA2

AA6 AB5 AC4 Y6

AC3 AA5

AB3

AE22 AH28

AG27

AF24 AH25

AG26

AG24

AG22 AG21 AF22 AF25

AG23

AH24 AF23

AH22

AF26

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15

AH17 AE17 AF17

AE16 AD16

R_H_H_CPUSLP#

R_H_DPRSTP#

THERMTRIP#_ICH

IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8

IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15

LPC_LAD0 28 LPC_LAD1 28 LPC_LAD2 28 LPC_LAD3 28

LPC_LFRAME# 28

SIO_A20GATE 13,28 H_A20M# 3

R163 0_NCR163 0_NC

R394 0_0402R394 0_0402

H_FERR# 3

H_PWRGOOD 3

H_IGNNE# 3

H_INIT# 3 H_INTR 3

SIO_RCIN# 13,28

H_NMI 3

H_STPCLK# 3

IDE_DD[0..15]

IDE_DA0 24 IDE_DA1 24 IDE_DA2 24

IDE_DCS1# 24 IDE_DCS3# 24

No PoP R163 if the MCH is driving CPUSLP# to the CPU. Place the resisters from ICH and MCH close together to minimize stubs for either PoP option.

H_DPRSTP# is a LOW true copy of DPRSLPVR on page 13. Route this signal Serially From ICH7(source) to CPU to

1 2

R390 0_0402R390 0_0402

Delete R82,R83 per GG0504

IDE_DD[0..15] 24

H_CPUSLP# 3,5

H_DPRSTP# 3,40 H_DPSLP# 3

H_SMI# 3

1 2

R399 56_0402R399 56_0402

12

C205

.1U_NC

VR.(check voltage level)

+1.05V_VCCP

placed R399,C205 as close as possible to the U4.AF26

H_FERR#

1 2

R159 56_0402R159 56_0402

12

C94 15P/50V/0402C94 15P/50V/0402

1 1

+RTC_CELL

1 2

R81 332K/F_0402R81 332K/F_0402

INTVEREN#

Update pre GG0512 recommend

Pop R79 and No Pop R81 to Disable internal VR

2 2

3 3

+RTC_CELL

1 2

R85 20K_0402R85 20K_0402

12

R82

1M_0402

12

R79

R79 0_NC

0_NC

SM_INTRUDER#

JP3 was used to VR.(check voltage level) "short" the reset line to gnd. This is used in the factory and engineer debug environment

Place TX Caps close to the U4 relation pins

+3.3V_RUN

R448 8.2K_0402R448 8.2K_0402

C93 15P/50V/0402C93 15P/50V/0402

12

JP3JP3

+3.3V_RUN

SATA_RX0-24 SATA_RX0+24

SATA_TX0-24

SATA_TX0+24

IDE_IRQ

12

X1,X2 Docking IAC_SYNC Port X Line

Place R123 within 500mils to U4

14

23

12

C86

C86 1U/10V/0603

1U/10V/0603

R469 10K_NCR469 10K_NC

12

C420 3900P/25V/0402C420 3900P/25V/0402

12

C417 3900P/25V/0402C417 3900P/25V/0402

101X2,2X1

4X1

+3.3V_RUN

R305

R305 1K_NC

ICH_AZ_MDC_SYNC27

ICH_AZ_CODEC_SYNC34

ICH_AZ_CODEC_BITCLK34

4 4

ICH_AZ_MDC_BITCLK27

C80

C80 27P_NC

27P_NC

1 2

12

R306 33_0402R306 33_0402

12

R304 33_0402R304 33_0402

12

R100 33_0402R100 33_0402

12

R101 33_0402R101 33_0402

C81

C81 27P_NC

27P_NC

ACZ_SYNC

ACZ_BIT_CLK

A

1K_NC

1 2

All resistors of termination used of "T" type routing need tuned equal and close to the source.

ACZ_SDOUT

ACZ_RST#

B

12

R315 33_0402R315 33_0402

12

R316 33_0402R316 33_0402

12

R88 33_0402R88 33_0402

12

R89 33_0402R89 33_0402

ICH_AZ_MDC_SDOUT 27

ICH_AZ_CODEC_SDOUT 34

ICH_AZ_MDC_RST# 27

ICH_AZ_CODEC_RST# 34

C

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

COMPUTER

ICH7-M (CPU,IDE,SATA,LPC,AC97)

FM1 2A

E

of

11 51Tuesday, September 06, 2005

A

www.kythuatvitinh.com

PCIE_RX1-25 PCIE_RX1+25

PCIE_TX1-25

PCIE_TX1+25

Place TX Caps close to the U4 relation pins

1 1

PCIE_RX4-26

PCIE_RX4+26

PCIE_TX4-26

PCIE_TX4+26

Place TX Caps close to the U4 relation pins

+3.3V_SUS

1 2

R293 10K_0402R293 10K_0402

1 2

R314 10K_0402R314 10K_0402

1 2

R99 10K_0402R99 10K_0402

2 2

ICH_EC_SPI_DIN

ICH_EC_SPI_DO

SPI_CS#

Over Current inputs to the ICH are ONLY from External USB ports.

ICH_EC_SPI_CLK28

ICH_EC_SPI_DO28 ICH_EC_SPI_DIN28

USB_OC0_2#30

USB_OC4_6#30

SPI_CS#28,30

+3.3V_SUS

B

1 2

C510 .1U/10V/0402C510 .1U/10V/0402

1 2

C511 .1U/10V/0402C511 .1U/10V/0402

1 2

C508 .1U/10V/0402C508 .1U/10V/0402

1 2

C509 .1U/10V/0402C509 .1U/10V/0402

1 2

RP2

10P8R-10K

R303 47_0402R303 47_0402

1 2

R350 47_0402R350 47_0402

5 4 3 2 1

Place R303 close USIO1, R350 close U4.

OC1#

OC3#

OC5#

OC7#

6

OC5#

7 8

OC7#

9

10

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN4_C PCIE_TXP4_C

OC1#

OC3#

F26 F25 E28 E27

H26 H25 G28 G27

K26 K25 J28 J27

M26 M25

L28 L27

P26

P25 N28 N27

T25

T24 R28 R27

R2 P6 P1

P5 P2

D3 C4 D5 D4 E5 C3 A2 B3

+3.3V_SUS

U11D

PERn1 PERp1 PETn1 PETp1

PERn2 PERp2 PETn2 PETp2

PERn3 PERp3 PETn3 PETp3

PERn4 PERp4 PETn4 PETp4

PERn5 PERp5 PETn5 PETp5

PERn6 PERp6 PETn6 PETp6

SPI_CLK SPI_CS# SPI_ARB

SPI_MOSI SPI_MISO

OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31

ICH7-M

C

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA28

DMI2TXN

AA27

DMI2TXP

AD25

DMI3RXN

AD24

DMI3RXP

AC28

DMI3TXN

AC27

DMI3TXP

PCI-Express

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

DMI_CLKN

DMI_CLKP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

USBRBIAS#

USBRBIAS

AE28 AE27

C25 D25

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

D2

USBRBIAS

D1

Place R104 within 500mils of ICH-7. Trace impedance should be 60ohms +/- 15%.

DMI_COMP

R104 22.6/F_0402R104 22.6/F_0402

D

DMI_MTX_IRX_N0 6 DMI_MTX_IRX_P0 6

DMI_MRX_ITX_N0 6

DMI_MRX_ITX_P0 6

DMI_MTX_IRX_N1 6 DMI_MTX_IRX_P1 6

DMI_MRX_ITX_N1 6

DMI_MRX_ITX_P1 6

DMI_MTX_IRX_N2 6 DMI_MTX_IRX_P2 6

DMI_MRX_ITX_N2 6

DMI_MRX_ITX_P2 6 DMI_MTX_IRX_N3 6

DMI_MTX_IRX_P3 6

DMI_MRX_ITX_N3 6

DMI_MRX_ITX_P3 6

CLK_PCIE_ICH# 17

CLK_PCIE_ICH 17

Place R400 within 500mils to U4

12

R400 24.9/F_0402R400 24.9/F_0402

USBP0- 30 USBP0+ 30 USBP1- 26 USBP1+ 26 USBP2- 30 USBP2+ 30

USBP4- 30 USBP4+ 30 USBP5- 25 USBP5+ 25 USBP6- 30 USBP6+ 30 USBP7- 27 USBP7+ 27

For Express Card

For Mini-Card

For Bluetooth

12

+1.5V_RUN

E

12

PCI_AD[0..31]21,36

3 3

PCI_PIRQB: for LOM PCI_PIRQC: 1394/Media Card PCI_PIRQD: for 1394

4 4

PCI_PIRQB#36 PCI_PIRQC#21 PCI_PIRQD#21

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_PIRQA#

A

U11B

E18

AD0

C18

C14

D14

C13 G15 G13

C11 D11

AE5 AD5 AG4 AH4 AD9

A16 F18 E16 A18 E17 A17 A15

E14

B12

E12

A11 A10 F11 F10

E9 D9 B9 A8 A6 C7 B6 E6 D6

A3 B4 C5

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#B5GPIO5/PIRQH#

MISC

RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]

ICH7-M

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3#

GNT3# REQ4#/GPIO22 GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG#

RSVD[6] RSVD[7] RSVD[8] RSVD[9]

MCH_SYNC#

PAR

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

B15 C12 D12 C15

A7 E10 B18 A12 C9 E11 B10 F15 F14 F16

C26 A9 B19

G8 F7 F8 G7

AE9 AG8 AH8 F21 AH20

PCI_REQ0#

PCI_REQ1#

PCI_REQ4#

PCI_REQ5#

PCIRST#

B

PCI_C_BE0# 21,36 PCI_C_BE1# 21,36 PCI_C_BE2# 21,36 PCI_C_BE3# 21,36

PCI_IRDY# 21,36 PCI_PAR 21,36

PCI_DEVSEL# 21,36 PCI_PERR# 21,36 PCI_PLOCK# PCI_SERR# 21,36 PCI_STOP# 21,36 PCI_TRDY# 21,36 PCI_FRAME# 21,36

PCI_PLTRST#

ICH_GPIO2_PIRQE# ICH_GPIO3_PIRQF# ICH_GPIO4_PIRQG# ICH_GPIO5_PIRQH#

Update per GG0504

PCI_REQ2# 21 PCI_GNT2# 21 PCI_REQ3# 36 PCI_GNT3# 36

PCI_GNT4#

PCI_GNT5#

ICH_PME# 29

ICH_PME# only goes to the EC

MCH_ICH_SYNC# 6

REQ2 : 1394/Media Card REQ3 : LAN PCI

R121

R121 1K_0402

1K_0402

R143

R143 1K_NC

1K_NC

1 2

R125

10_NC

Place R125,C132 cloase to U4.A9.

1 2

Reserved for EMI fine tune.

C132

8.2P_NC

1 2

CLK_PCI_ICH 17

C

Resister pop options to boot from various sources

LPC

PCI

SPI

GNT5# R121

Not Stuff Not Stuff

11

10

Stuff Not Stuff

01

+3.3V_SUS

PCIRST#

PCI_PLTRST#

Add Buffers as needed for Loading and fanout concerns

5

2

1

U13

U13 TC7SZ32FU

TC7SZ32FU

+3.3V_SUS

2

1

U17

GNT4# R143

StuffNot Stuff

C172

C172 .047U/10V/0402

.047U/10V/0402

C501

C501 .047U/10V/0402

.047U/10V/0402

5

TC7SZ32FU

PCI Pullups

RP5

PCI_REQ3#

+3.3V_RUN

PCI_TRDY# PCI_STOP# PCI_FRAME#

+3.3V_RUN

12

4

PCI_RST# 21,36

12

4

PLTRST# 6,13,26,28

D

+3.3V_RUN

PCI_PIRQB#

PCI_PIRQA# PCI_PIRQC# PCI_PIRQD# PCI_REQ2#

ICH_GPIO2_PIRQE# ICH_GPIO3_PIRQF# ICH_GPIO4_PIRQG# ICH_GPIO5_PIRQH#

Title

ICH7-M (USB,DMI,PCIE,PCI)

Size Document Number Rev

FM1 2A

Date: Sheet

RP5

6 7 8 9

10

10P8R-8.2K

RP6

6 7 8 9

10

10P8R-8.2K

RP3

6 7 8 9

10

10P8R-8.2K

7 8 5 6 3 4 1 2

8P4R-8.2K

QUANTA

QUANTA COMPUTER

COMPUTER

+3.3V_RUN

5

PCI_IRDY#

4

PCI_PERR#

3

PCI_DEVSEL#

2 1

+3.3V_RUN

5

PCI_REQ5#

4 3

PCI_SERR#

2

PCI_PLOCK#

1

+3.3V_RUN

5 4

PCI_REQ1#

3

PCI_REQ4#

2

PCI_REQ0#

1

+3.3V_RUN

RP4

of

12 51Tuesday, September 06, 2005

E

12 51Tuesday, September 06, 2005

A

www.kythuatvitinh.com

B

C

D

E

+3.3V_RUN

13

12

Change R369 to 8.2K and PUto

1 1

U11C

ICH_SMBCLK17,25,26

SMBALERT#

LINKALERT#

1 2

R152 10K_0402R152 10K_0402

1 2

R161 10K_0402R161 10K_0402

+3.3V_SUS

Update per GG0504 recommend

2 2

3 3

ICH_SMBDATA17,25,26

SPKR34

ITP_DBRESET#3,28

PM_BMBUSY#6

H_STP_PCI#17

H_STP_CPU#17

LCD_TST19

IDE_RST_MOD24

CLKRUN#21,28,36

BT_RADIO_DIS#27

ICH_PCIE_WAKE#29

IRQ_SERIRQ21,28

SIO_THRM#28

IMVP_PWRGD38,40

SIO_EXT_WAKE#28

LAMP_STAT#19

SIO_EXT_SMI#28

LINKALERT# ICH_SMLINK0 ICH_SMLINK1

R470 0_0402R470 0_0402

+3.3V_SUS

ICH_RI#

SMBALERT#

1 2

R471 8.2K_0402R471 8.2K_0402

7 8 5 6 3 4 1 2

8P4R-10K

RP9

3 1

4P2R-2.2K

R164 8.2K_0402R164 8.2K_0402

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0/BM_BUSY#

B23

GPIO11/SMBALERT#

AC20

GPIO18/STPPCI#

AF21

GPIO20/STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32/CLKRUN#

AC19

GPIO33/AZ_DOCK_EN#

U2

GPIO34/AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7-M

ICH_BATLOW#

12

RP8

12

4 2

SIO_EXT_SMI# SIO_EXT_SCI# ICH_SMLINK0 ICH_SMLINK1

ICH_SMBCLK ICH_SMBDATA

ICH_RI#

GPIO

SMB

SYS

GPIO

SYS

GPIO

GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP

SATA

GPIO

SATA

GPIO

GPIO37/SATA3GP

Clocks

GPIO16/DPRSLPVR

TP0/BATLOW#

Power MGT

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39

AF19 AH18 AH19 AE19

AC1 B2

C20

B24 D23 F22

AA4

AC22

C21

C23

C19

Y4

E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20

ICH_BATLOW#

SUSPWROK

CLK_ICH_14M 17 CLK_ICH_48M 17

SIO_SLP_S3# 28

T55PAD T55PAD

SIO_SLP_S5# 28

ICH_PWRGD 6,33,38

DPRSLPVR 6,40

SIO_PWRBTN# 28

PLTRST# 6,12,26,28

SUSPWROK 33,38

SIO_EXT_SCI# 28

HDDC_EN# 24

SATA_CLKREQ# 17 PLTRST_DELAY# 18,25

R359 10K_0402R359 10K_0402

R411 100K_0402R411 100K_0402

R324 10K_0402R324 10K_0402

+3.3V_RUN per ref schematic.

R369

8.2K_0402

12

1 2

12

ICH_PCIE_WAKE#

CLK_ICH_48M

Place closely pin U45.B2

CLK_ICH_14M

Place closely pin U45.AC1

1 2

R374 680_0402R374 680_0402

12

R112

R112 10_NC

10_NC

12

C118

4.7P_NC

12

R103

R103 10_NC

10_NC

12

C91

4.7P_NC

+3.3V_SUS

RP46

7 8

+3.3V_RUN

No Stuff R433 since EC is push-pull

4 4

+3.3V_RUN

5 6 3 4 1 2

8P4R-10K

R433 8.2K_NCR433 8.2K_NC

R472 8.2K_0402R472 8.2K_0402

R367 10K_0402R367 10K_0402

Change R367 from 8.2K to 10K per ref schematic. Change power rail from +3.3V_SUS to +3.3V_RUN per reduce backdrive.

R145 10K_0402R145 10K_0402

R150 10K_0402R150 10K_0402

12

BT_RADIO_DIS# IRQ_SERIRQ

SIO_THRM#

CLKRUN#

LAMP_STAT#

SIO_A20GATE 11,28

SIO_RCIN# 11,28

A

B

CLKRUN#

12

R95

R95 10_NC

10_NC

Option to " Disable " clkrun. Pulling it down will keep the clks running

C

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

COMPUTER

ICH7-M( PM,GPIO,SMB )

FM1 2A

E

of

13 51Tuesday, September 06, 2005

A

www.kythuatvitinh.com

B

C

D

E

+5V_RUN

+3.3V_RUN

Change C457 from 1U to

1 1

2 2

3 3

4 4

.1U per ref schematic

+5V_SUS

+3.3V_SUS

+1.5V_RUN

+3.3V_RUN

+1.5V_RUN

+3.3V_SUS

1 2

R357 100_0402R357 100_0402

D18

2 1

CH751H-40HPT

1 2

R323 10_0402R323 10_0402

2 1

D17

D17 CH751H-40HPT

CH751H-40HPT

1 2

L33

L33 BLM41P600SPG

BLM41P600SPG

1 2

R409 0.5_0402R409 0.5_0402

R107 0.5_0402R107 0.5_0402

1 2

220U/6.3V/ESR25

0506: ref CL1301 P55

C503

C503 .1U/10V/0402

.1U/10V/0402

1 2

C415

C415 .1U/10V/0402

.1U/10V/0402

C522

+1.5V_PCIE

+

+1.5V_DMIPLLR

C109

C109 10U/4V/0805

10U/4V/0805

1 2

+1.5V_RUN

ICH_V5REF_RUN

12

C457

Delete C319,C320

.1U/10V/0402

per ref M07_A02

C408

C408 .1U/10V/0402

.1U/10V/0402

1 2

C493

C493 .1U/10V/0402

.1U/10V/0402

1 2

L37

L37 BLM11A121S

BLM11A121S

C512

C512 10U/4V/0805

10U/4V/0805

1 2

L6 BLM11A121SL6 BLM11A121S

1 2

12

+3.3V_RUN

C407

C407 .1U/10V/0402

.1U/10V/0402

C410

C410 .1U/10V/0402

.1U/10V/0402

Delete C231 per ref M07_A02

C498

C498 .1U/10V/0402

.1U/10V/0402

1 2

+1.5V_RUN

1 2

+1.5V_RUN

1 2

T14 PADT14 PAD T51 PADT51 PAD

+1.5V_DMIPLL

C507

C507 .01U/25V/0402

.01U/25V/0402

C450

C450 .1U/10V/0402

.1U/10V/0402

C499

C499 .1U/10V/0402

.1U/10V/0402

1 2

C401

C401 .1U/10V/0402

.1U/10V/0402

1 2

12

C90

C90 1U/10V/0603

1U/10V/0603

TP_VCCSUSLAN1 TP_VCCSUSLAN2

U11F

G10

V5REF[1]

AD17

V5REF[2]

F6

V5REF_Sus

AA22

Vcc1_5_B[1]

AA23

Vcc1_5_B[2]

AB22

Vcc1_5_B[3]

AB23

Vcc1_5_B[4]

AC23

Vcc1_5_B[5]

AC24

Vcc1_5_B[6]

AC25

Vcc1_5_B[7]

AC26

Vcc1_5_B[8]

AD26

Vcc1_5_B[9]

AD27

Vcc1_5_B[10]

AD28

Vcc1_5_B[11]

D26

Vcc1_5_B[12]

D27

Vcc1_5_B[13]

D28

Vcc1_5_B[14]

E24

Vcc1_5_B[15]

E25

Vcc1_5_B[16]

E26

Vcc1_5_B[17]

F23

Vcc1_5_B[18]

F24

Vcc1_5_B[19]

G22

Vcc1_5_B[20]

G23

Vcc1_5_B[21]

H22

Vcc1_5_B[22]

H23

Vcc1_5_B[23]

J22

Vcc1_5_B[24]

J23

Vcc1_5_B[25]

K22

Vcc1_5_B[26]

K23

Vcc1_5_B[27]

L22

Vcc1_5_B[28]

L23

Vcc1_5_B[29]

M22

Vcc1_5_B[30]

M23

Vcc1_5_B[31]

N22

Vcc1_5_B[32]

N23

Vcc1_5_B[33]

P22

Vcc1_5_B[34]

P23

Vcc1_5_B[35]

R22

Vcc1_5_B[36]

R23

Vcc1_5_B[37]

R24

Vcc1_5_B[38]

R25

Vcc1_5_B[39]

R26

Vcc1_5_B[40]

T22

Vcc1_5_B[41]

T23

Vcc1_5_B[42]

T26

Vcc1_5_B[43]

T27

Vcc1_5_B[44]

T28

Vcc1_5_B[45]

U22

Vcc1_5_B[46]

U23

Vcc1_5_B[47]

V22

Vcc1_5_B[48]

V23

Vcc1_5_B[49]

W22

Vcc1_5_B[50]

W23

Vcc1_5_B[51]

Y22

Vcc1_5_B[52]

Y23

Vcc1_5_B[53]

B27

Vcc3_3[1]

AG28

VccDMIPLL

AB7

Vcc1_5_A[1]

AC6

Vcc1_5_A[2]

AC7

Vcc1_5_A[3]

AD6

Vcc1_5_A[4]

AE6

Vcc1_5_A[5]

AF5

Vcc1_5_A[6]

AF6

Vcc1_5_A[7]

AG5

Vcc1_5_A[8]

AH5

Vcc1_5_A[9]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10

Vcc1_5_A[10]

AB9

Vcc1_5_A[11]

AC10

Vcc1_5_A[12]

AD10

Vcc1_5_A[13]

AE10

Vcc1_5_A[14]

AF10

Vcc1_5_A[15]

AF9

Vcc1_5_A[16]

AG9

Vcc1_5_A[17]

AH9

Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

AA2

VccSus1_05/VccLAN1_05[1]

Y7

VccSus1_05/VccLAN1_05[2]

ICH7-M

Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9]

CORE

Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]

VCC PAUX

VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]

Vcc3_3/VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1] V_CPU_IO[2]

VCCA3GP

V_CPU_IO[3]

Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7]

IDE

Vcc3_3[8]

Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]

Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16]

PCI

Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]

VccRTC

VccSus3_3[1]

VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]

VccSus3_3[7] VccSus3_3[8]

VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12]

USB

VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]

Vcc1_5_A[19]

Vcc1_5_A[20]

Vcc1_5_A[21]

ATXARX

Vcc1_5_A[22]

Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]

VccSus1_05[1]

VccSus1_05[2] VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

USB CORE

L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

V5 V1 W2 W7

U6

R7

AE23 AE26 AH26

AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19

A5 B13 B16 B7 C10 D15 F9 G11 G12 G16

W5

P7

A24 C24 D19 D22 G19

K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7

AB17 AC17

T7 F17 G17

AB8 AC8

K7

C28 G20

A1 H6 H7 J6 J7

C443

C443 .1U/10V/0402

.1U/10V/0402

1 2

+3.3V_SUS

+3_3V_IDE

1 2

C464

C464 .1U/10V/0402

.1U/10V/0402

1 2

TP_ICHVCCSUS1

TP_ICHVCCSUS2 TP_ICHVCCSUS3

C467

C467 .1U/10V/0402

.1U/10V/0402

+3_3V_PCI

1 2

C82

C82 .1U/10V/0402

.1U/10V/0402

1 2

C474

C474 .1U/10V/0402

.1U/10V/0402

1 2

C486

C486 .1U/10V/0402

.1U/10V/0402

1 2

+1.5V_RUN

+1.5V_RUN +1.5V_RUN

C125

C125 .1U/10V/0402

.1U/10V/0402

1 2

12

C472

C472 1U/10V/0603

1U/10V/0603

C412

C412 .1U/10V/0402

.1U/10V/0402

1 2

C429

C429 .1U/10V/0402

.1U/10V/0402

1 2

C451

C451 .1U/10V/0402

.1U/10V/0402

1 2

T49PAD T49PAD

T29PAD T29PAD T54PAD T54PAD

+1.5V_RUN

+

+3.3V_SUS

+3.3V_RUN

C121

C121 .1U/10V/0402

.1U/10V/0402

1 2

C428

C428 .1U/10V/0402

.1U/10V/0402

+3.3V_SUS

C427

C427 .1U/10V/0402

.1U/10V/0402

+3.3V_SUS

C441

C441 .1U/10V/0402

.1U/10V/0402

+1.05V_VCCP

C461

C461 330U/2.5V/ESR9

330U/2.5V/ESR9

C495

C495 .1U/10V/0402

.1U/10V/0402

1 2

+3.3V_RUN

+RTC_CELL

+1.5V_RUN

C430

.1U/10V/0402

1 2

C496

C496 .1U/10V/0402

.1U/10V/0402

1 2

12

C494

4.7U/10V/0805

+1.05V_VCCP

U11E

A4

VSS[1]

A23

VSS[2]

B1

VSS[3]

B8

VSS[4]

B11

VSS[5]

B14

VSS[6]

B17

VSS[7]

B20

VSS[8]

B26

VSS[9]

B28

VSS[10]

C2

VSS[11]

C6

VSS[12]

C27

VSS[13]

D10

VSS[14]

D13

VSS[15]

D18

VSS[16]

D21

VSS[17]

D24

VSS[18]

E1

VSS[19]

E2

VSS[20]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7-M

VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]

P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27

14

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

A

B

C

D

Size Document Number Rev

Date: Sheet

COMPUTER

ICH7-M (POWER&GND)

FM1 2A

E

of

14 51Tuesday, September 06, 2005