Dell Inspiron 14 3462 Schematics

Vinaﬁx.com

5

D D

4

3

2

1

Turis 14" 15" 2SP Schematic

Apollo Lake

C C

2016-09-07 REV : A00

DY : None Installed

B B

A A

5

UMA: UMA only installed

4

3

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Turis APL UMA

1

X02

1 106Wednesd ay, September 07, 20 16

X02

Vinaﬁx.com

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Project Code : 4PD0AG010001 PCB P/N : 16823-1 Revision : A00

D D

TURIS 14" 15" 2SP Apollo Lake Block Diagram

14"/15" LCD

Touch Panel

Camera

Digital MIC

C C

HDMI V1.4a

Left side

USB1(USB3.0)

B B

Left side

USB2(USB3.0)

4

Intel CPU

Apollo Lake

BGA1296

Package

eDP

USB2.0

DDI1

USB2.0

USB3.0

USB2.0

31*24*1.3

DDI (2) / EDP1.4

MDSI (3) / MCSI (4)

USB 3.0 (6) / 2.0 ports (8)

SATA (2) / PCIE (4)

HDA / I2S (2)

I2C (8) / ISH_I2C (2) / SPI

SD / EMMC

LPC I/F / SMBS (1) / UART (2)

3

DDR3L 1866MHz Channel A

PCIe

USB2.0

SATA (Gen3)

Re-driver

SN75LVCP601RTJR

Reserve

SATA (Gen1)

eMMC BUS

LPC BUS

SPI

Non Share Rom

128K

eMMC

Reserve

KBC

NUVOTON NPCE985PB1

NGFF WLAN

802.11a/b/g/n BT V4.0 combo

HDD

ODD

63

Int. KB

65

2

DDR3L 1600

SODIMM A

12

G Sensor

LNG2DMTR-GP

int

LPC debug port

67

Reserve

1

CHARGER BQ24727RGRR

INPUTS

19V_DCBATOUT

SYSTEM DC/DC

TPS51225RUKR

INPUTS

19V_DCBATOUT

CPU DC/DC PMIC RT9610BZQW

INPUTS

5V_S5

1D35V_CPU_VDDQ_S3

CPU DC/DC PMIC RT9610BZQW

INPUTS

5V_S5

SYSTEM LDO APL3523AQBI

INPUTS OUTPUTS

5V_S5 5V_S0

3D3V_S5

SYSTEM LDO TPS22965DSGR

INPUTS OUTPUTS

3D3V_AUX_S5

3D3V_S5

5V_S5

0D675V_CPU_VDDQ_S3

1D35V_CPU_VDDQ_S3

PCB LAYER

L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Bottom

OUTPUTS

BT+

OUTPUTS

1D05V_S0

1D8V_S5

1D24V_S5

OUTPUTS

1V_CPU_VNN

1V_CPU_VCGI

3D3V_S0

1D8V_S01D8V_S5

44

45

50

51

40

USB3.0

Non Share Rom

16MB

PS2

PrecisionTouch pad

65

2CH SPEAKER (2CH 2W/4ohm)

Audio Codec

ALC3246

SPI

I2C

HDA

MIC_IN/GND

Universal Jack

USB3(USB2.0)

A A

SD Card Slot

IO Board

5

HP_R/L

Realtek RTS5170

CardReader

USB2.0

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Block Diagram

Turis APL UMA

1

X02

2 106Monday, Septemb er 05, 2016

X02

Vinaﬁx.com

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4

3

2

1

SSID = CPU

D D

C C

Blanking

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis APL UMA

3 106Wednesday, July 27, 2016

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

D D

C C

Blanking

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis APL UMA

4 106Wednesday, July 27, 2016

1

X02

Vinaﬁx.com

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

5

CPU1A

M_A_DQ0

AY62

MEM_CH0_DQ 0/MEM_CH0 _DQA0

M_A_DQ1

AY61

MEM_CH0_DQ 1/MEM_CH0 _DQA1

M_A_DQ2

BE62

MEM_CH0_DQ 2/MEM_CH0 _DQA2

M_A_DQ3

BG62

MEM_CH0_DQ 3/MEM_CH0 _DQA3

M_A_DQ4

BD63

MEM_CH0_DQ 4/MEM_CH0 _DQA4

M_A_DQ5

AW62

MEM_CH0_DQ 5/MEM_CH0 _DQA5

M_A_DQ6

AW63

MEM_CH0_DQ 6/MEM_CH0 _DQA6

M_A_DQ7

BD62

MEM_CH0_DQ 7/MEM_CH0 _DQA7

M_A_DQ8

AV59

MEM_CH0_DQ 8/MEM_CH0 _DQA8

M_A_DQ9

AU63

MEM_CH0_DQ 9/MEM_CH0 _DQA9

M_A_DQ10

AU62

MEM_CH0_DQ 10/MEM_C H0_DQA1 0

M_A_DQ11

AV58

MEM_CH0_DQ 11/MEM_C H0_DQA1 1

M_A_DQ12

AV57

MEM_CH0_DQ 12/MEM_C H0_DQA1 2

M_A_DQ13

AT55

MEM_CH0_DQ 13/MEM_C H0_DQA1 3

M_A_DQ14

AT54

MEM_CH0_DQ 14/MEM_C H0_DQA1 4

M_A_DQ15

AY59

MEM_CH0_DQ 15/MEM_C H0_DQA1 5

M_A_DQ16

AY57

MEM_CH0_DQ 16/MEM_C H0_DQA1 6

M_A_DQ17

BB57

MEM_CH0_DQ 17/MEM_C H0_DQA1 7

M_A_DQ18

BD59

MEM_CH0_DQ 18/MEM_C H0_DQA1 8

M_A_DQ19

BF59

MEM_CH0_DQ 19/MEM_C H0_DQA1 9

M_A_DQ20

AV54

MEM_CH0_DQ 20/MEM_C H0_DQA2 0

M_A_DQ21

AY55

MEM_CH0_DQ 21/MEM_C H0_DQA2 1

M_A_DQ22

AV52

MEM_CH0_DQ 22/MEM_C H0_DQA2 2

M_A_DQ23

BD58

MEM_CH0_DQ 23/MEM_C H0_DQA2 3

M_A_DQ24

BE56

MEM_CH0_DQ 24/MEM_C H0_DQA2 4

M_A_DQ25

BD54

MEM_CH0_DQ 25/MEM_C H0_DQA2 5

M_A_DQ26

BF58

MEM_CH0_DQ 26/MEM_C H0_DQA2 6

M_A_DQ27

BE50

MEM_CH0_DQ 27/MEM_C H0_DQA2 7

M_A_DQ29

BB50

MEM_CH0_DQ 29/MEM_C H0_DQA2 9

M_A_DQ28

BD50

MEM_CH0_DQ 28/MEM_C H0_DQA2 8

M_A_DQ30

BA50

MEM_CH0_DQ 30/MEM_C H0_DQA3 0

M_A_DQ31

BB54

MEM_CH0_DQ 31/MEM_C H0_DQA3 1

APOLLO-LAKE-GP-U

CPU1C

BJ26

MEM_CH1_DQ 0/MEM_CH1 _DQA0

BG30

MEM_CH1_DQ 1/MEM_CH1 _DQA1

BH31

MEM_CH1_DQ 2/MEM_CH1 _DQA2

BG31

MEM_CH1_DQ 3/MEM_CH1 _DQA3

BH27

MEM_CH1_DQ 4/MEM_CH1 _DQA4

BG27

MEM_CH1_DQ 5/MEM_CH1 _DQA5

BG26

MEM_CH1_DQ 6/MEM_CH1 _DQA6

BJ30

MEM_CH1_DQ 7/MEM_CH1 _DQA7

BA30

MEM_CH1_DQ 8/MEM_CH1 _DQA8

BB30

MEM_CH1_DQ 9/MEM_CH1 _DQA9

BE30

MEM_CH1_DQ 10/MEM_C H1_DQA1 0

BD30

MEM_CH1_DQ 11/MEM_C H1_DQA1 1

BE25

MEM_CH1_DQ 12/MEM_C H1_DQA1 2

BB27

MEM_CH1_DQ 13/MEM_C H1_DQA1 3

BD25

MEM_CH1_DQ 14/MEM_C H1_DQA1 4

BD27

MEM_CH1_DQ 15/MEM_C H1_DQA1 5

BG24

MEM_CH1_DQ 16/MEM_C H1_DQA1 6

BJ20

MEM_CH1_DQ 17/MEM_C H1_DQA1 7

BH23

MEM_CH1_DQ 18/MEM_C H1_DQA1 8

BJ24

MEM_CH1_DQ 19/MEM_C H1_DQA1 9

BG20

MEM_CH1_DQ 20/MEM_C H1_DQA2 0

BG21

MEM_CH1_DQ 21/MEM_C H1_DQA2 1

BH19

MEM_CH1_DQ 22/MEM_C H1_DQA2 2

BG25

MEM_CH1_DQ 23/MEM_C H1_DQA2 3

AT27

MEM_CH1_DQ 24/MEM_C H1_DQA2 4

AW29

MEM_CH1_DQ 25/MEM_C H1_DQA2 5

AR27

MEM_CH1_DQ 26/MEM_C H1_DQA2 6

AT23

MEM_CH1_DQ 27/MEM_C H1_DQA2 7

AV27

MEM_CH1_DQ 28/MEM_C H1_DQA2 8

AR25

MEM_CH1_DQ 29/MEM_C H1_DQA2 9

AR23

MEM_CH1_DQ 30/MEM_C H1_DQA3 0

AW27

MEM_CH1_DQ 31/MEM_C H1_DQA3 1

APOLLO-LAKE-GP-U

5

SSID = CPU

DDR_DATA

M_A_DQ[63:0][12]

M_A_DQS_DN[7:0][12]

D D

M_A_DQS_DP[7:0][12]

M_A_A[15:0][12]

M_A_BS0[12]

M_A_BS1[12]

M_A_BS2[12]

M_A_ODT0[12]

M_A_ODT1[12]

M_A_CAS#[12]

M_A_WE#[12]

M_A_RAS#[12]

M_A_CS#1[12]

M_A_CS#0[12]

M_A_CLK1[12]

C C

M_A_CLK#1[12]

M_A_CLK0[12]

M_A_CLK#0[12]

M_A_CKE0[12]

M_A_CKE1[12]

DDR_DRAMRST#[12]

B B

A A

4

1 OF 23

APL_SOC

4

APL_SOC

MEM_CH0_DQ 32/MEM_C H0_DQB0

MEM_CH0_DQ 33/MEM_C H0_DQB1

MEM_CH0_DQ 34/MEM_C H0_DQB2

MEM_CH0_DQ 35/MEM_C H0_DQB3

MEM_CH0_DQ 36/MEM_C H0_DQB4

MEM_CH0_DQ 37/MEM_C H0_DQB5

MEM_CH0_DQ 38/MEM_C H0_DQB6

MEM_CH0_DQ 39/MEM_C H0_DQB7

MEM_CH0_DQ 40/MEM_C H0_DQB8

MEM_CH0_DQ 41/MEM_C H0_DQB9

MEM_CH0_DQ 42/MEM_C H0_DQB1 0

MEM_CH0_DQ 43/MEM_C H0_DQB1 1

MEM_CH0_DQ 44/MEM_C H0_DQB1 2

MEM_CH0_DQ 45/MEM_C H0_DQB1 3

MEM_CH0_DQ 46/MEM_C H0_DQB1 4

MEM_CH0_DQ 47/MEM_C H0_DQB1 5

MEM_CH0_DQ 48/MEM_C H0_DQB1 6

MEM_CH0_DQ 49/MEM_C H0_DQB1 7

MEM_CH0_DQ 50/MEM_C H0_DQB1 8

MEM_CH0_DQ 51/MEM_C H0_DQB1 9

MEM_CH0_DQ 52/MEM_C H0_DQB2 0

MEM_CH0_DQ 53/MEM_C H0_DQB2 1

MEM_CH0_DQ 54/MEM_C H0_DQB2 2

MEM_CH0_DQ 55/MEM_C H0_DQB2 3

MEM_CH0_DQ 56/MEM_C H0_DQB2 4

MEM_CH0_DQ 57/MEM_C H0_DQB2 5

MEM_CH0_DQ 58/MEM_C H0_DQB2 6

MEM_CH0_DQ 59/MEM_C H0_DQB2 7

MEM_CH0_DQ 60/MEM_C H0_DQB2 8

MEM_CH0_DQ 61/MEM_C H0_DQB2 9

MEM_CH0_DQ 62/MEM_C H0_DQB3 0

MEM_CH0_DQ 63/MEM_C H0_DQB3 1

1 OF 23

MEM_CH1_DQ 32/MEM_C H1_DQB0

MEM_CH1_DQ 33/MEM_C H1_DQB1

MEM_CH1_DQ 34/MEM_C H1_DQB2

MEM_CH1_DQ 35/MEM_C H1_DQB3

MEM_CH1_DQ 36/MEM_C H1_DQB4

MEM_CH1_DQ 37/MEM_C H1_DQB5

MEM_CH1_DQ 38/MEM_C H1_DQB6

MEM_CH1_DQ 39/MEM_C H1_DQB7

MEM_CH1_DQ 40/MEM_C H1_DQB8

MEM_CH1_DQ 41/MEM_C H1_DQB9

MEM_CH1_DQ 42/MEM_C H1_DQB1 0

MEM_CH1_DQ 43/MEM_C H1_DQB1 1

MEM_CH1_DQ 44/MEM_C H1_DQB1 2

MEM_CH1_DQ 45/MEM_C H1_DQB1 3

MEM_CH1_DQ 46/MEM_C H1_DQB1 4

MEM_CH1_DQ 47/MEM_C H1_DQB1 5

MEM_CH1_DQ 48/MEM_C H1_DQB1 6

MEM_CH1_DQ 49/MEM_C H1_DQB1 7

MEM_CH1_DQ 50/MEM_C H1_DQB1 8

MEM_CH1_DQ 51/MEM_C H1_DQB1 9

MEM_CH1_DQ 52/MEM_C H1_DQB2 0

MEM_CH1_DQ 53/MEM_C H1_DQB2 1

MEM_CH1_DQ 54/MEM_C H1_DQB2 2

MEM_CH1_DQ 55/MEM_C H1_DQB2 3

MEM_CH1_DQ 56/MEM_C H1_DQB2 4

MEM_CH1_DQ 57/MEM_C H1_DQB2 5

MEM_CH1_DQ 58/MEM_C H1_DQB2 6

MEM_CH1_DQ 59/MEM_C H1_DQB2 7

MEM_CH1_DQ 60/MEM_C H1_DQB2 8

MEM_CH1_DQ 61/MEM_C H1_DQB2 9

MEM_CH1_DQ 62/MEM_C H1_DQB3 0

MEM_CH1_DQ 63/MEM_C H1_DQB3 1

M_A_DQ32

AR39

M_A_DQ33

AV37

M_A_DQ34

AW37

M_A_DQ35

AR37

M_A_DQ36

AT37

M_A_DQ37

AT41

M_A_DQ38

AR41

M_A_DQ39

AW35

M_A_DQ40

BJ44

M_A_DQ41

BG39

M_A_DQ42

BG40

M_A_DQ43

BJ40

M_A_DQ44

BG43

M_A_DQ45

BG44

M_A_DQ46

BH45

M_A_DQ47

BH41

M_A_DQ48

BA34

M_A_DQ49

BE34

M_A_DQ50

BD34

M_A_DQ51

BD37

M_A_DQ52

BB37

M_A_DQ53

BE39

M_A_DQ54

BD39

M_A_DQ55

BB34

M_A_DQ56

BJ38

M_A_DQ57

BG34

M_A_DQ58

BG33

M_A_DQ59

BH33

M_A_DQ60

BG38

M_A_DQ61

BH37

M_A_DQ62

BG37

M_A_DQ63

BJ34

3 OF 23

BF6

BD10

BE14

BB10

BA14

BB14

BD14

BE8

AV12

BD6

BD5

BB7

AV10

AY9

AY7

BF5

AU2

AT10

AT9

AU1

AY5

AV5

AV6

AV7

AY2

BD2

BD1

BE2

AW1

AW2

AY3

BG2

3

CPU1B

M_A_DQS_DP0

BB63

MEM_CH0_DQ SP0/MEM_ CH0_DQS PA0

M_A_DQS_DN0

BC62

MEM_CH0_DQ SN0/MEM_C H0_DQSNA 0

M_A_DQS_DP1

AT59

MEM_CH0_DQ SP1/MEM_ CH0_DQS PA1

M_A_DQS_DN1

AT58

MEM_CH0_DQ SN1/MEM_C H0_DQSNA 1

M_A_DQS_DP2

BB59

MEM_CH0_DQ SP2/MEM_ CH0_DQS PA2

M_A_DQS_DN2

BB58

MEM_CH0_DQ SN2/MEM_C H0_DQSNA 2

M_A_DQS_DP3

BD52

MEM_CH0_DQ SP3/MEM_ CH0_DQS PA3

M_A_DQS_DN3

BB52

MEM_CH0_DQ SN3/MEM_C H0_DQSNA 3

M_A_DQS_DP4

AV39

MEM_CH0_DQ SP4/MEM_ CH0_DQS PB0

M_A_DQS_DN4

AW39

MEM_CH0_DQ SN4/MEM_C H0_DQSNB 0

M_A_DQS_DP5

BJ42

MEM_CH0_DQ SP5/MEM_ CH0_DQS PB1

M_A_DQS_DN5

BG42

MEM_CH0_DQ SN5/MEM_C H0_DQSNB 1

M_A_DQS_DP6

BB35

MEM_CH0_DQ SP6/MEM_ CH0_DQS PB2

M_A_DQS_DN6

BD35

MEM_CH0_DQ SN6/MEM_C H0_DQSNB 2

M_A_DQS_DP7

BG36

MEM_CH0_DQ SP7/MEM_ CH0_DQS PB3

M_A_DQS_DN7

BH35

MEM_CH0_DQ SN7/MEM_C H0_DQSNB 3

M_A_A0

BG50

MEM_CH0_MA0 /MEM_CH0_ CAB7

M_A_A1

BG51

MEM_CH0_MA1 /MEM_CH0_ CAB9

M_A_A2

BH51

MEM_CH0_MA2 /MEM_CH0_ CAB5

M_A_A3

BD41

MEM_CH0_MA3 /NCTF_2 2

M_A_A4

BE41

MEM_CH0_MA4 /NCTF_2 3

M_A_A5

BJ52

MEM_CH0_MA5 /MEM_CH0_ CAA2

M_A_A6

BG53

MEM_CH0_MA6 /MEM_CH0_ CAA0

M_A_A7

BG55

MEM_CH0_MA7 /MEM_CH0_ CAA3

M_A_A8

BH53

MEM_CH0_MA8 /MEM_CH0_ CAA1

M_A_A9

BG52

MEM_CH0_MA9 /MEM_CH0_ CAA4

M_A_A10

BH49

MEM_CH0_MA1 0/MEM_CH0 _CAB6

M_A_A11

BH55

MEM_CH0_MA1 1/MEM_CH0 _CAA6

M_A_A12

BG54

MEM_CH0_MA1 2/MEM_CH0 _CAA5

M_A_A13

BG46

MEM_CH0_MA1 3/MEM_CH0 _CAB0

M_A_A14

BG56

MEM_CH0_MA1 4/MEM_CH0 _CAA8

M_A_A15

BG57

MEM_CH0_MA1 5/MEM_CH0 _CAA9

APOLLO-LAKE-GP-U

CPU1D

BG28

MEM_CH1_DQ SP0/MEM_ CH1_DQS PA0

BH29

MEM_CH1_DQ SN0/MEM_C H1_DQSNA 0

BD29

MEM_CH1_DQ SP1/MEM_ CH1_DQS PA1

BB29

MEM_CH1_DQ SN1/MEM_C H1_DQSNA 1

BJ22

MEM_CH1_DQ SP2/MEM_ CH1_DQS PA2

BG22

MEM_CH1_DQ SN2/MEM_C H1_DQSNA 2

AV25

MEM_CH1_DQ SP3/MEM_ CH1_DQS PA3

AW25

MEM_CH1_DQ SN3/MEM_C H1_DQSNA 3

BB12

MEM_CH1_DQ SP4/MEM_ CH1_DQS PB0

BD12

MEM_CH1_DQ SN4/MEM_C H1_DQSNB 0

BB5

MEM_CH1_DQ SP5/MEM_ CH1_DQS PB1

BB6

MEM_CH1_DQ SN5/MEM_C H1_DQSNB 1

AT5

MEM_CH1_DQ SP6/MEM_ CH1_DQS PB2

AT6

MEM_CH1_DQ SN6/MEM_C H1_DQSNB 2

BC2

MEM_CH1_DQ SP7/MEM_ CH1_DQS PB3

BB1

MEM_CH1_DQ SN7/MEM_C H1_DQSNB 3

BG9

MEM_CH1_MA0 /MEM_CH1_ CAB7

BG10

MEM_CH1_MA1 /MEM_CH1_ CAB9

BH9

MEM_CH1_MA2 /MEM_CH1_ CAB5

BD16

MEM_CH1_MA3 /NCTF_1

BB16

MEM_CH1_MA4 /NCTF_2

BG11

MEM_CH1_MA5 /MEM_CH1_ CAA2

BJ12

MEM_CH1_MA6 /MEM_CH1_ CAA0

BG14

MEM_CH1_MA7 /MEM_CH1_ CAA3

BG12

MEM_CH1_MA8 /MEM_CH1_ CAA1

BH11

MEM_CH1_MA9 /MEM_CH1_ CAA4

BG7

MEM_CH1_MA1 0/MEM_CH1 _CAB6

BH13

MEM_CH1_MA1 1/MEM_CH1 _CAA6

BG13

MEM_CH1_MA1 2/MEM_CH1 _CAA5

BH3

MEM_CH1_MA1 3/MEM_CH1 _CAB0

BG15

MEM_CH1_MA1 4/MEM_CH1 _CAA8

BG16

MEM_CH1_MA1 5/MEM_CH1 _CAA9

APOLLO-LAKE-GP-U

3

2

2 OF 23

APL_SOC

2

MEM_CH0_VR EFCA

MEM_CH0_VR EFDQ

MEM_CH0_BA 0/MEM_CH0 _CAB2

MEM_CH0_BA 1/MEM_CH0 _CAB8

MEM_CH0_BA 2/MEM_CH0 _CAA7

MEM_CH0_OD T0/MEM_C H0_ODTA

MEM_CH0_OD T1/MEM_C H0_ODTB

MEM_CH0_CA S#/MEM_C H0_CAB1

MEM_CH0_W E#/MEM_C H0_CAB4

MEM_CH0_RA S#/MEM_C H0_CAB3

NCTF/MEM_CH0 _CS1A #

NCTF/MEM_CH0 _CS0B #

MEM_CH0_CS 1#/MEM_C H0_CS1B #

MEM_CH0_CS 0#/MEM_C H0_CS0A #

MEM_CH0_CL KP1/MEM_ CH0_CLK P_A

MEM_CH0_CL KN1/MEM_C H0_CLKN_ A

MEM_CH0_CL KP0/MEM_ CH0_CLK P_B

MEM_CH0_CL KN0/MEM_C H0_CLKN_ B

MEM_CH0_CK E0/MEM_C H0_CKE0 A

MEM_CH0_CK E1/MEM_C H0_CKE1 A

NCTF/MEM_CH0 _CKE0 B

NCTF/MEM_CH0 _CKE1 B

MEM_CH1_RE SET#/NC TF_31

MEM_CH0_RE SET#/NC TF_33

MEM_CH0_DQ SP8/NCT F_28

MEM_CH0_DQ SN8/NCTF _30

MEM_CH0_CB 7/NCTF_ 35

MEM_CH0_CB 6/NCTF_ 34

MEM_CH0_CB 5/NCTF_ 32

MEM_CH0_CB 4/NCTF_ 29

MEM_CH0_CB 3/NCTF_ 27

MEM_CH0_CB 2/NCTF_ 26

MEM_CH0_CB 1/NCTF_ 25

MEM_CH0_CB 0/NCTF_ 24

MEM_CH1_VR EFDQ

MEM_CH1_VR EFCA

MEM_CH1_BA 0/MEM_CH1 _CAB2

MEM_CH1_BA 1/MEM_CH1 _CAB8

MEM_CH1_BA 2/MEM_CH1 _CAA7

MEM_CH1_RA S#/MEM_C H1_CAB3

MEM_CH1_CA S#/MEM_C H1_CAB1

MEM_CH1_W E#/MEM_C H1_CAB4

MEM_CH1_OD T0/MEM_C H1_ODTA

MEM_CH1_OD T1/MEM_C H1_ODTB

MEM_CH1_CL KP1/MEM_ CH1_CLK P_A

MEM_CH1_CL KN1/MEM_C H1_CLKN_ A

MEM_CH1_CL KP0/MEM_ CH1_CLK P_B

MEM_CH1_CL KN0/MEM_C H1_CLKN_ B

MEM_CH1_CK E0/MEM_C H1_CKE0 A

MEM_CH1_CK E1/MEM_C H1_CKE1 A

NCTF/MEM_CH1 _CKE0 B

NCTF/MEM_CH1 _CKE1 B

MEM_CH1_CS 0#/MEM_C H1_CS0A #

MEM_CH1_CS 1#/MEM_C H1_CS1B #

NCTF/MEM_CH1 _CS0B #

NCTF/MEM_CH1 _CS1A #

MEM_CH1_DQ SN8/NCTF _9

MEM_CH1_DQ SP8/NCT F_5

MEM_CH1_CB 0/NCTF_ 3

MEM_CH1_CB 1/NCTF_ 4

MEM_CH1_CB 6/NCTF_ 11

MEM_CH1_CB 3/NCTF_ 7

MEM_CH1_CB 4/NCTF_ 8

MEM_CH1_CB 5/NCTF_ 10

MEM_CH1_CB 7/NCTF_ 12

MEM_CH1_CB 2/NCTF_ 6

M_A_VREFDQ_CPU

AT34

M_A_BS0

BJ48

M_A_BS1

BG49

M_A_BS2

BH57

M_A_ODT0

AW43

M_A_ODT1

AW41

M_A_CAS#

BH47

M_A_WE#

BG48

M_A_RAS#

BG47

AT43

BB41

M_A_CS#1

BA41

M_A_CS#0

AR43

M_A_CLK1

BB48

M_A_CLK#1

BD48

M_A_CLK0

BD45

M_A_CLK#0

BE45

M_A_CKE0

BH61

M_A_CKE1

BH60

BH58

BJ58

AR30

DDR_DRAMRST#

AR34

BD47

BB47

BA45

BD43

AV47

AV48

AW45

BB43

AW47

AW48

4 OF 23

AT30

AR29

BH6

BG8

BH15

BJ6

BH4

BH7

AW16

AV16

BB21

BD21

BD19

BE19

BG18

BG17

BH17

BJ16

BD17

AW17

AV17

BB17

BE23

BD23

AR21

AT21

BA23

AW21

BA19

AW19

BB23

AW23

M_A_VREFCA_CPU

AR35

TP509TP509

1

TP510TP510

1

Title

Size Document Number Rev

A1

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(DDR)

Turis APL UMA

5 106Wednesday, July 27, 2016

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

22 OF 23

CPU1V

3D3V_USB

D D

R602

R603

1 2

R604

R605

R606

C C

1D05V_S0

R607

R608

R609

R610

B B

3D3V_USB3D3V_S5

R601 0R0402-PAD-2- GPR601 0R0402-PAD-2- GP

12

1D24V_USB21D24V_S5

0R0603-PAD-2- GP-U

12

1D24V_AUD_ISH_P LL

0R0805-PAD-2- GP-U

1D24V_MPHY

0R0603-PAD-2- GP-U

12

1D24V_GLML

0R0603-PAD-2- GP-U

12

1D24V_DSI_CSI

0R0603-PAD-2- GP-U

12

1D05V_IO_3PHASEIO

0R0603-PAD-2- GP-U

12

1D05V_FHV1

0R0603-PAD-2- GP-U

12

1D05V_FHV0

0R0603-PAD-2- GP-U

12

1D05V_FUSE

0R0603-PAD-2- GP-U

12

1D24V_USB2

1V_CPU_VNN

3D3V_USB

1D24V_AUD_ISH_P LL

1D24V_MPHY

1D24V_GLML

1D24V_DSI_CSI

1D24V_AUD_ISH_P LL

1D05V_IO_3PHASEIO

1D05V_FUSE

1D05V_FHV1

1D05V_FHV0

1D05V_IO_3PHASEIO

AJ25

VCC_3P3V_A_6

AK25

VCC_3P3V_A_5

AG20

VDD2_1P24_USB2

AJ37

VNN_SVID

AJ39

VNN_SVID

AJ41

VNN_SVID

AJ42

VNN_SVID

AJ46

VNN_SVID

AK37

VNN_SVID

AK39

VNN_SVID

AK41

VNN_SVID

AK42

VNN_SVID

AK44

VNN_SVID

AK46

VNN_SVID

AM44

VNN_SVID

AJ44

RSVD_11

AA42

VCC_3P3V_A_4

Y44

VCC_3P3V_A_1

V46

VCC_3P3V_A_2

V44

VCC_3P3V_A_3

AC41

VCC_3P3V_A_7

AJ20

VDD2_1P24_AUD_ISH_PLL

AJ22

VDD2_1P24_AUD_ISH_PLL

AE18

VDD2_1P24_MPHY

AE20

VDD2_1P24_MPHY

AE22

VDD2_1P24_MPHY

AG22

VDD2_1P24_MPHY

BJ61

RSVD_7

AK20

VDD2_1P24_GLM

AC20

RSVD_10

AC22

RSVD_9

AA18

VDD2_1P24_DSI_CSI

AA20

VDD2_1P24_DSI_CSI

AK22

VDD2_1P24_AUD_ISH_PLL

AA22

VCCRAM_1P05_IO

AC23

VCCRAM_1P05_IO

V18

VCCRAM_1P05_IO

Y18

VCCRAM_1P05_IO

Y20

VCCRAM_1P05_IO

P16

VCC_1P05V

T15

VCC_1P05V

T13

VCC_1P05V

AA23

VCCRAM_1P05_IO

APOLLO-LAKE-G P-U

VNN Max 4.4A

3D3V_S5 Max 0.15A

APL_SOC

22 OF 23

NCTF_18

NCTF_19

NCTF_17

NCTF_21

VDD2_1P24_GLM

VCC_VCGI_43

VCC_VCGI_41

VCC_VCGI_40

VCC_VCGI_39

VCC_VCGI_38

VCC_VCGI_37

VCC_VCGI_36

VCC_VCGI_34

VCC_VCGI_62

VCC_VCGI_60

VCC_VCGI_58

VCC_VCGI_56

VCC_VCGI_54

VCC_VCGI_52

VCC_VCGI_50

VCC_VCGI_48

VCC_VCGI_46

VCC_VCGI_44

VCC_VCGI_42

VCC_VCGI_63

VCC_VCGI_61

VCC_VCGI_59

VCC_VCGI_57

VCC_VCGI_55

VCC_VCGI_53

VCC_VCGI_51

VCC_VCGI_49

VCC_VCGI_47

VCC_VCGI_45

VCC_VCGI_35

VCC_VCGI_64

NCTF_20

VCCRTC_3P3V

VCCIOA

RSVD_8

RSVD_12

D4

T51

L14

E3

AM37

AM20

AM28

AA28

AA30

AA32

AC28

AC30

AC32

AE28

AE30

AE32

AG28

AG30

AG32

AJ28

AJ30

AJ32

AK28

AK30

AK32

AM30

E29

E37

U28

U30

U32

V28

V30

V32

Y28

Y30

Y32

E50

R19

AA44

AM23

AM25

AM41

AM42

BJ62

V49

1D24V_GLML

C601

1 2

SC1U10V2KX-1G P

1V_CPU_VCGI

3D3V_VCCRT C

1V_CPU_VNN

VCCIOA Max 1.5A Tie to VNN for LPDDR3/DDR3L Tie to VDDQ for for LPDDR4.

Note: AM28 IS INTERNAL SHORTED ON BXT-P PACKAGE TO VDD2

1V_CPU_VCGI

RTC_AUX_S5

R611 0R0402-PAD-2- GPR611 0R0402-PAD-2- GP

12

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Thursday, Augus t 25, 2016

Thursday, Augus t 25, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU (CFG)

Turis APL UMA

1

6 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

23 OF 23

CPU1W

AM32

AA25

AC25

AE25

AN32

BG63

AG48

AN18

AN20

AN22

AN23

AN41

AN42

AN44

AN46

AR17

AR47

AT13

AT17

AT47

AT51

AV14

AV50

E6

U22

U23

V22

V23

V25

Y23

U20

U25

Y25

D1

V48

R43

R41

F23

E23

BJ3

APOLLO-LAKE-G P-U

NCTF_16

VCCRAM_1P05

RSVD_4

RSVD_6

RSVD_2

RSVD_1

RSVD_3

VCC_VCGI_SENSE_N

VCC_VCGI_SENSE_P

VNN_SENSE

VDDQ_15

VDDQ_14

VDDQ_13

VDDQ_12

VDDQ_11

VDDQ_10

VDDQ_9

VDDQ

VDDQ_8

Max 2.8A

VDDQ_6

VDDQ_7

VDDQ_5

VDDQ_4

VDDQ_3

VDDQ_2

VDDQ_1

VDDQ_16

NCTF_14

NCTF_15

RSVD_5

R701

1 2

0R0805-PAD-2- GP-U

D D

VSS_VCCGI[50]

FB_VCCGI[50]

FB_VNN[50]

VSS_VCCGI

FB_VCCGI

FB_VNN

C C

1D35V_CPU_VD DQ_S3

B B

1D05V_S0 Max 2.7A

APL_SOC

1D8V_S5 Max 0.4A

23 OF 23

VCC_1P8V_A_1

VCC_1P8V_A_2

VCC_1P8V_A_3

VCC_1P8V_A_4

VCC_1P8V_A_5

VCC_1P8V_A_6

VCC_1P8V_A_7

VCC_1P8V_A_8

NCTF_13

VCC_VCGI_32

VCC_VCGI_31

VCC_VCGI_33

VCC_VCGI_30

VCC_VCGI_27

VCC_VCGI_24

VCC_VCGI_21

VCC_VCGI_18

VCC_VCGI_15

VCC_VCGI_12

VCC_VCGI_9

VCC_VCGI_7

VCC_VCGI_6

VCC_VCGI_3

VCC_VCGI_1

VCC_VCGI_28

VCC_VCGI_25

VCC_VCGI_22

VCC_VCGI_19

VCC_VCGI_16

VCC_VCGI_13

VCC_VCGI_10

VCC_VCGI_8

VCC_VCGI_5

VCC_VCGI_4

VCC_VCGI_2

VCC_VCGI_29

VCC_VCGI_26

VCC_VCGI_23

VCC_VCGI_20

VCC_VCGI_17

VCC_VCGI_14

VCC_VCGI_11

AE42

AE44

AA46

AC42

AC44

AC46

AE46

AG25

R17

F29

E35

AK34

E45

AC37

AE36

AE37

AG36

E43

E48

R45

R47

U36

U37

U39

U41

U42

U44

U46

U47

U48

V36

V37

V39

V41

Y36

Y37

Y39

Y41

AC36

AA36

AA37

AA39

1D8V_PCH1D05V_PCH

0R0603-PAD-2- GP-U

1V_CPU_VCGI

1D8V_S51D05V_S0

R702

12

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Thursday, Augus t 25, 2016

Thursday, Augus t 25, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Turis APL UMA

1

7 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

HDMI

HDMI_DATA_CPU_P2[57]

HDMI_DATA_CPU_N2[57]

HDMI_DATA_CPU_P1[57]

HDMI_DATA_CPU_N1[57]

D D

HDMI_DATA_CPU_P0[57]

HDMI_DATA_CPU_N0[57]

HDMI_DATA_CPU_P3[57]

HDMI_DATA_CPU_N3[57]

HDMI_CLK_CPU[57]

HDMI_DATA_CPU[57]

HDMI_DET_CPU#[57]

EDP

eDP_AUX_CPU_P[55]

eDP_AUX_CPU_N[55]

eDP_TX_CPU_P0[55]

eDP_TX_CPU_N0[55]

eDP_TX_CPU_P1[55]

eDP_TX_CPU_N1[55]

eDP_VDDEN_CPU[24,55]

eDP_BLCTRL_CPU[55]

eDP_BLEN_CPU[24]

C C

B B

Space/Width = 20/25 mils

EDP

CRB p39

HDMI_DET_CPU#

HDMI_CLK_CPU

HDMI_DATA_CPU

SRN2K2J-1-GP

R802

1 2

402R2F-GP

RN802

1D8V_S01D8V_S5

4

DY

1

2 3

eDP_AUX_CPU_P

eDP_AUX_CPU_N

EDP_RCOMP_N

EDP_RCOMP_P

eDP_TX_CPU_N0

eDP_TX_CPU_P1

eDP_TX_CPU_N1

CPU1F

AP12

MDSI_A_ DP_0

AP10

MDSI_A_ DN_0

AR2

MDSI_A_ DP_1

AR1

MDSI_A_ DN_1

AP15

MDSI_A_ DP_2

AP13

MDSI_A_ DN_2

AP6

MDSI_A_ DP_3

AP5

MDSI_A_ DN_3

AP2

MDSI_A_ CLKP

AP3

MDSI_A_ CLKN

B51

MIPI_I2 C_SDA

C51

MIPI_I2 C_SCL

A50

GPIO_1 99/HV_DD I1_HPD

C50

GPIO_2 00/HV_DD I0_HPD

M45

MDSI_A_ TE

M43

MDSI_C_ TE

APOLLO-LAKE-GP-U

4

RN801

RN801 SRN2K2J-1-GP

SRN2K2J-1-GP

DY

1

2 3

CPU1E

B49

C49

A54

C54

AH10

AH9

AG5

AG6

AG7

AG9

AG12

AG10

AC6

AC5

AC7

AC9

CPU1E

DDI0_D DC_SCL

DDI0_D DC_SDA

DDI1_D DC_SCL

DDI1_D DC_SDA

EDP_AUX P

EDP_AUX N

EDP_RC OMP_N

EDP_RC OMP_P

EDP_TX P_0

EDP_TX N_0

EDP_TX P_1

EDP_TX N_1

EDP_TX P_2

EDP_TX N_2

EDP_TX P_3

EDP_TX N_3

APOLLO-LAKE-GP-U

1.8V

1.05V

APL_SOC

1.24V

1.8V

1.05V

DDI0_R COMP_P

DDI0_R COMP_N

!!Notice:

!!Notice: AB2/AB3

AB2/AB3

1.24V

1.8V

DDI0_T XP_0

DDI0_T XN_0

DDI0_T XP_1

DDI0_T XN_1

DDI0_T XP_2

DDI0_T XN_2

DDI0_T XP_3

DDI0_T XN_3

DDI0_A UXP

DDI0_A UXN

DDI1_A UXP

DDI1_A UXN

DDI1_T XP_0

DDI1_T XN_0

DDI1_T XP_1

DDI1_T XN_1

DDI1_T XP_2

DDI1_T XN_2

DDI1_T XP_3

DDI1_T XN_3

MDSI_C_ DP_0

MDSI_C_ DN_0

MDSI_C_ DP_1

MDSI_C_ DN_1

MDSI_C_ DP_2

MDSI_C_ DN_2

MDSI_C_ DP_3

MDSI_C_ DN_3

MDSI_C_ CLKP

MDSI_C_ CLKN

PNL0_BK LTEN

PNL0_BK LTCTL

PNL1_BK LTEN

PNL1_BK LTCTL

5 OF 23

PNL0_VD DEN

PNL1_VD DEN

AK3

AK2

AM3

AM2

AH3

AH2

AL2

AL1

AG1

AG2

AM16

AM15

AK16

AK15

AF2

AF3

AD3

AD2

AC1

AC2

AB3

AB2

6 OF 23

HDMI_DATA_CPU_P2

HDMI_DATA_CPU_N2

HDMI_DATA_CPU_P1

HDMI_DATA_CPU_N1

HDMI_DATA_CPU_P0

HDMI_DATA_CPU_N0

HDMI_DATA_CPU_P3

HDMI_DATA_CPU_N3

DDI0_RCOMP_P

DDI0_RCOMP_NeDP_TX_CPU_P0

AK7

AK6

AM5

AM6

AM12

AM10

AK13

AM13

AM9

AM7

eDP_VDDEN_CPU

C47

eDP_BLEN_CPU

B47

eDP_BLCTRL_CPU

C46

C52

B53

C53

R801

12

402R2F-GP

CRB p132, P190 EDS p43

CRB p39

HDMI

DP to VGA

eDP_BLEN_CPU

eDP_BLCTRL_CPU

eDP_BLEN_CPU

eDP_VDDEN_CPU

R804 100KR2J-1-GP

12

DY

R805 100KR2J-1-GP

12

DY

R803 1MR2J-1-GP

12

DY

R808 100KR2J-1-GP

12

DY

1D8V_S0

Intel suggest DY and follow Intel CRB

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Wednesday, July 27, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP/GPIO)

Turis APL UMA

8 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

7 OF 23

CPU1G

D D

C C

P17

M17

P21

R21

L17

J17

F17

E17

M19

L19

H19

F19

CPU1G

MCSI_DP_0

MCSI_DN_0

MCSI_DP_1

MCSI_DN_1

MCSI_DP_2

MCSI_DN_2

MCSI_DP_3

MCSI_DN_3

MCSI_CLKP_0

MCSI_CLKN_0

MCSI_CLKP_2

MCSI_CLKN_2

APL_SOC

7 OF 23

MCSI_RX_DATA0_P

MCSI_RX_DATA0_N

MCSI_RX_CLK0_P

MCSI_RX_CLK0_N

MCSI_RX_DATA1_P

MCSI_RX_DATA1_N

MCSI_RX_DATA2_P

MCSI_RX_DATA2_N

MCSI_RX_CLK1_P

MCSI_RX_CLK1_N

MCSI_RX_DATA3_P

MCSI_RX_DATA3_N

M23

P23

L23

J23

J21

H21

M25

L25

F25

E25

H25

J25

L37

GP_CAMERASB0

P34

GP_CAMERASB1

J34

GP_CAMERASB2

H30

GP_CAMERASB3

M37

GP_CAMERASB4

F30

B B

A A

5

GP_CAMERASB5

APOLLO-L AKE-GP-U

4

3

GP_CAMERASB6

GP_CAMERASB7

GP_CAMERASB8

GP_CAMERASB9

GP_CAMERASB10

GP_CAMERASB11

R35

L34

M34

M35

R34

E30

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose application without get Wistron permission

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

2

Date: Sheet of

CPU (VSS)

Turis APL UMA

Wednesd ay, July 27, 2016

Turis APL UMA

Taipei Hsien 221, Taiwan, R.O.C.

9 106

1

X02

Vinaﬁx.com

SSID = CPU

5

4

3

2

1

1V_CPU_ VCGI

D D

C C

VNN

1V_CPU_ VNN

B B

IccMax = 21 A

PC1010

PC1012

PC1013

12

SC22U6D3V3MX-1-GP

PC1025

SC22U6D3V3MX-1-GP

PC1049

12

PC1013

12

SC22U6D3V3MX-1-GP

PC1026

12

SC22U6D3V3MX-1-GP

PC1051

12

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

PC1024

12

SC22U6D3V3MX-1-GP

CRB: 1U 0402 x 3, 22U 0603 x 4

22U 0603 x 4 , DY x2

0.1U 0402 x 1

+VCCSA(ICCMAX.= 6A)

PC1048

PC1050

12

PC1050

12

SC22U6D3V3MX-1-GP

VCCGI

CRB: 1U 0402 x 12, 22U 0603 x 8, 47U 0805 x 10

0.1U 0402 x 1 22U 0603 x 24 , DY x 4

PC1014

SC22U6D3V3MX-1-GP

PC1028

SC22U6D3V3MX-1-GP

12

PC1015

SC22U6D3V3MX-1-GP

PC1030

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

PC1031

SC22U6D3V3MX-1-GP

12

PC1017

SC22U6D3V3MX-1-GP

PC1032

SC22U6D3V3MX-1-GP

PC1016

PC1015

follow power team

PC1023

12

PC1009

SC22U6D3V3MX-1-GP

PC1011

12

DY

PC1023

12

SCD1U25V2KX-GP

SC22U6D3V3MX-1-GP

SCD1U25V2KX-GP

12

PC1018

SC22U6D3V3MX-1-GP

PC1033

SC22U6D3V3MX-1-GP

12

PC1019

SC22U6D3V3MX-1-GP

PC1034

SC22U6D3V3MX-1-GP

follow power team

PC1021

PC1020

12

PC1035

SC22U6D3V3MX-1-GP

1D24V_M PHY

12

SC22U6D3V3MX-1-GP

PC1036

SC22U6D3V3MX-1-GP

12

PC1046

PC1022

12

SC22U6D3V3MX-1-GP

PC1037

12

SC22U6D3V3MX-1-GP

22U 0603 x 1 1D8V_PCH But Layout No Space So change to Cap list 1U 0402

SC22U6D3V3MX-1-GP

CRB p56

PC1044

PC1038

12

1D8V_PC H 1D24V_D SI_CSI

12

PC1039

12

SCD1U25V2KX-GP

DY

22U 0603 x 1

PC1101

SC1U10V2KX-1GP

PC1044

12

SC22U6D3V3MX-1-GP

DY

22U 0603 x 1

12

PC1102

1D05V_IO_ 3PHASEIO

22U 0603 x 1

PC1008

SC22U6D3V3MX-1-GP

12

1D05V_P CH

22U 0603 x 2

PC1041

PC1040

12

1D24V_A UD_ISH_PLL

SC22U6D3V3MX-1-GP

3D3V_US B

SC22U6D3V3MX-1-GP

12

22U 0603 x 1

PC1042

12

SC22U6D3V3MX-1-GP

1D24V_G LML

22U 0603 x 1

PC1043

12

SC22U6D3V3MX-1-GP

22U 0603 x 1

12

PC1103

SC22U6D3V3MX-1-GP

(VNN)

1V_CPU_ VNN

for 1V_VCCIOA

22U 0603 x 2

A A

PC1006

12

PC1007

SC22U6D3V3MX-1-GP

12

5

4

1D35V_C PU_VDDQ_S3

PC1047

PC1045

SC22U6D3V3MX-1-GP

12

DY

0.1U 0402 x 1 22U 0603 x 8 , DY x 2

X00_0504

PC1001

PC1002

SC10U6D3V3MX-GP

PC1052

12

DY

3

PC1002

SC22U6D3V3MX-1-GP

12

SC10U6D3V3MX-GP

DY

SC22U6D3V3MX-1-GP

12

PC1003

SC10U6D3V3MX-GP

DY

PC1027

12

follow CRB

SC22U6D3V3MX-1-GP

12

PC1004

SC10U6D3V3MX-GP

DY

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

CPU (Power CAP1)

Turis APL UMA

Wednesd ay, July 27, 2016

Turis APL UMA

Taipei Hsien 221, Taiwan, R.O.C.

10 106

1

X02

Vinaﬁx.com

SSID = CPU

5

4

3

2

1

D D

1D8V_PC H

CRB p57

1U 0402 x 5

C1104

SC1U10V2KX-1GP

C1104

SC1U10V2KX-1GP

C1103

SC1U10V2KX-1GP

C1103

SC1U10V2KX-1GP

C1102

SC1U10V2KX-1GP

C1102

SC1U10V2KX-1GP

C1101

SC1U10V2KX-1GP

C1101

SC1U10V2KX-1GP

12

1D24V_D SI_CSI

1U 0402 x 2

C C

B B

1V_CPU_ VCGI

C1107

SC1U10V2KX-1GP

C1107

SC1U10V2KX-1GP

C1106

12

change from INTEL 559091 MOW Page 4

SC1U10V2KX-1GP

3D3V_US B

1U 0402 x 4

C1109

12

SC1U10V2KX-1GP

12

C1108

SC1U10V2KX-1GP

C1108

SC1U10V2KX-1GP

C1111

12

3D3V_VC CRTC

C1113

12

1D24V_U SB2

1U 0402 x1

C1112

SC1U10V2KX-1GP

C1112

C1110

SC1U10V2KX-1GP

C1110

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

(VNN) for 1V_VCCIOA

1V_CPU_ VNN

C1016

12

1D24V_M PHY

1U 0402 x 2

C1017

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

1D05V_IO_ 3PHASEIO

1U 0402 x 4

C1001

12

1D05V_P CH

1U 0402 x 4

C1005

12

1D24V_A UD_ISH_PLL

1U 0402 x 2

C1009

C1010

12

SC1U10V2KX-1GP

C1002

C1003

C1004

SC1U10V2KX-1GP

C1007

12

SC1U10V2KX-1GP

1D24V_G LML

12

C1008

SC1U10V2KX-1GP

12

C1006

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

1U 0402 x 3

C1013

C1012

C1011

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

C1014

C1015

C1018

12

SC1U10V2KX-1GP

12

C1019

C1020

SC1U10V2KX-1GP

A A

5

12

C1021

12

C1022

SC1U10V2KX-1GP

12

C1023

C1025

SC1U10V2KX-1GP

4

12

C1024

12

C1026

SC1U10V2KX-1GP

12

C1027

12

C1028

12

C1030

SC1U10V2KX-1GP

3

C1029

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose application without get Wistron permission

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

2

Date: Sheet of

CPU (Power CAP2)

Turis APL UMA

Wednesd ay, July 27, 2016

Turis APL UMA

Taipei Hsien 221, Taiwan, R.O.C.

11 106

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = MEMORY

DDR_DATA

D D

C C

B B

M_A_DQS_DN[7:0][5]

M_A_DQS_DP[7:0][5]

M_A_DQ[63:0][5]

M_A_A[15:0][5]

DDR CMD/ADD

M_A_RAS#[5]

M_A_WE#[5]

M_A_CAS#[5]

M_A_BS2[5] M_A_BS0[5] M_A_BS1[5]

DDR CTRL

M_A_CS#0[5] M_A_CS#1[5]

M_A_CKE0[5] M_A_CKE1[5]

M_A_ODT0[5] M_A_ODT1[5]

DDR CLOCK

M_A_CLK0[5]

M_A_CLK#0[5]

M_A_CLK1[5]

M_A_CLK#1[5]

DDR OTHERS

DDR_DRAMRST#[5]

PCH_SMB_DATA[17,65,70]

PCH_SMB_CLK[17,65,70]

M_A_ODT0 M_A_ODT1

VREF_CA VREF_DQ

DDR_DRAMRST#_R

0D675V_VREF_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_BS2

M_A_BS0 M_A_BS1

M_A_DQ20 M_A_DQ21 M_A_DQ17 M_A_DQ18 M_A_DQ22 M_A_DQ16 M_A_DQ19 M_A_DQ23 M_A_DQ10 M_A_DQ13 M_A_DQ8 M_A_DQ11 M_A_DQ9 M_A_DQ14 M_A_DQ12 M_A_DQ15 M_A_DQ5 M_A_DQ0 M_A_DQ4 M_A_DQ2 M_A_DQ6 M_A_DQ1 M_A_DQ7 M_A_DQ3 M_A_DQ24 M_A_DQ25 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ26 M_A_DQ28 M_A_DQ27 M_A_DQ32 M_A_DQ38 M_A_DQ35 M_A_DQ33 M_A_DQ37 M_A_DQ36 M_A_DQ34 M_A_DQ39 M_A_DQ40 M_A_DQ46 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ41 M_A_DQ47 M_A_DQ53 M_A_DQ54 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ55 M_A_DQ48 M_A_DQ56 M_A_DQ61 M_A_DQ58 M_A_DQ63 M_A_DQ60 M_A_DQ62 M_A_DQ59 M_A_DQ57

M_A_DQS_DN2 M_A_DQS_DN1 M_A_DQS_DN0 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP2 M_A_DQS_DP1 M_A_DQS_DP0 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_C A

1

VREF_D Q

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

DDR3-204P-262-GP-U

62.10024.S21

Need Handchange Main :62.10024.M31 Second :62.10017.X41

EVENT#

VDDSPD

NC#/TEST

NP1

NP2

M_A_RAS#

110

RAS#

M_A_WE#

113

WE#

M_A_CAS#

115

CAS#

M_A_CS#0

114

CS0#

M_A_CS#1

121

CS1#

M_A_CKE0

73

CKE0

M_A_CKE1

74

CKE1

M_A_CLK0

101

CK0

M_A_CLK#0

103

CK0#

M_A_CLK1

102

CK1

M_A_CLK#1

104

CK1#

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

PCH_SMB_DATA

200

SDA

PCH_SMB_CLK

202

SCL

TS#_DIMM0_1

198

199

197

SA0

201

SA1

77

NC#1

122

NC#2

125

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

DIMM1_SA0 DIMM1_SA1

1D35V_DIMM_VDDQ_S3

1

X00_0504

1D35V_DIMM_VDDQ_S3

A00_0908

12

C1216

TP1201 T PAD14-OP-GPTP1201 TPAD14-OP-GP

12

C1224

SCD1U16V2KX-3GP

Layout Note: Place these Caps near SO-DIMMA.

SODIMM A DECOUPLING

12

C1202

C1201

SC10U6D3V3MX-GP

SC1KP50V2KX-1GP

SC10U6D3V3MX-GP

DY

12

C1213

C1214

C1206

SC1KP50V2KX-1GP

SC100P50V2JN-3GP

3D3V_S0

SC100P50V2JN-3GP

12

C1223

SCD1U16V2KX-3GP

12

C1205

C1218

C1203

SC10U6D3V3MX-GP

12

C1215

SC1U10V2KX-1GP

SC10U6D3V3MX-GP

0D675V_VREF_S0

A00_0908

12

C1211

SC1KP50V2KX-1GP

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

DIMM1_SA0

R1213

R1213 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

Layout Note: Place these capsclose to VTT1 and VTT2.

12

C1209

C1207

SC1U10V2KX-1GP

DY

12

C1217

SC100P50V2JN-3GP

DIMM1_SA1

12

C1210

C1208

SC1U10V2KX-1GP

For EMI Reserved

DDR_DRAMRST#

ED1202

DDR_DRAMRST#

R1201

R1201 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

12

C1212

C1220

SC10U6D3V3MX-GP

DY

For Intel Recommend Close to DIMM

The design of Vref refer to PDG rev.1.0.

VREF_DQ

For Intel Recommend Close to DIMM

DDR_DRAMRST#_R

12

AZ5725-01FDR7G-GP

DY

12

ED1201

AZ5725-01FDR7G-GP

DY

VREF_CA

RN1201

SRN1KJ-7-GP

1D35V_DIMM_VDDQ_S3

1234

DDR_DRAMRST#_R

1D35V_DIMM_VDDQ_S3

12

R1208

R1208 3K65R2F-1-GP

3K65R2F-1-GP

12

R1212

R1212 3K65R2F-1-GP

3K65R2F-1-GP

1D35V_DIMM_VDDQ_S3

12

R1207

R1207 3K65R2F-1-GP

3K65R2F-1-GP

12

R1211

R1211 3K65R2F-1-GP

3K65R2F-1-GP

A00_0908

X01_0531

A A

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose application without get Wistron permission

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, September 08, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3L-Memory Down

Turis APL UMA

12 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = MEMORY

D D

C C

Blanking

B B

Wistron Corporation

A A

Title

Size Document Number Rev

Size Document Number Rev A4

A4

Wednesday, July 27, 2016

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Turis APL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

X02

13 106

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

D D

C C

Blanking

B B

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose

A A

Title

Size Document Number Rev

Size Document Number Rev A4

A4

Date: Sheet of

5

4

3

Date: Sheet of

application without get Wistron permission

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Turis APL UMA

Wednesday, July 27, 2016

2

Turis APL UMA

14 106

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = STRAP

GPIO

Schematic

D D

High

Low

GPIO

Schematic

GPIO_36

1D8V_S5

12

R1501

DY

4K7R2F-GP

GPIO36_VCCIO_LEVEL [21]

12

R1502

DY

10KR2F-2-GP

VCCIO used for B-step

default (A-step)

default (A-step)default (A-step)

Weak internal pull-down Weak internal pull-down

GPIO_88

1D8V_S5

12

R1523

DY

10KR2F-2-GP

12

R1511

4K7R2F-GP

High

PMU 3.3V mode select

PMU 3.3V mode selectPMU 3.3V mode select

Low

Weak internal pull-up

C C

GPIO

GPIO_123

1D8V_S5

12

R1525

Schematic

DY

12

R1525

10KR2J-3-GP

R1526

4K7R2F-GP

GP_SSP2_TXD [19,99]

GPIO_39

1D8V_S5

12

R1503

4K7R2F-GP

DY

GPIO39_TXE_BPS [18]

12

R1504

DY

4K7R2F-GP

enable CSE ROM bypass

default (disable bypass)

default (disable bypass)default (disable bypass)

GPIO_92 GPIO_111

1D8V_S5

12

R1512

DY

10KR2F-2-GP

GPIO92_SMB_NRB [19]

12

R1513

DY

4K7R2F-GP

SMBS No-reboot enable

default (SMBus No Re-Boot

default (SMBus No Re-Boot default (SMBus No Re-Boot

Disable)

Disable)Disable)

Weak internal pull-down

GPIO_43 GPIO_44

1D8V_S5

12

R1521

A00_0905

DY

4K7R2F-GP

GPIO43_EMMC_BOOT [18]

12

R1505

4K7R2F-GP

A00_0905

RSVD

Weak internal pull-up

1D8V_S5

12

R1514

DY

10KR2F-2-GP

GPIO111_BBS [19]

12

R1515

4K7R2F-GP

Do not boot from SPI

Do not boot from SPIDo not boot from SPI

Weak internal pull-up

boot from SPI

1D8V_S5

12

R1506

4K7R2F-GP

GPIO44_SPI_BOOT [18]

12

R1507

DY

4K7R2F-GP

default

defaultdefault

( allow SPI as a boot source)

( allow SPI as a boot source)( allow SPI as a boot source)

Weak internal pull-up

disable

GPIO_110

1D8V_S5

12

R1524

4K7R2F-GP

DY

GPIO110_LPC_LEVEL [19]GPIO88_PMU_LEVEL [19]

12

R1516

4K7R2F-GP

LPC 1.8V mode selectPMU 1.8V mode select

LPC 3.3V mode select

LPC 3.3V mode selectLPC 3.3V mode select

Weak internal pull-up

GPIO_47

1D8V_S5

12

R1509

DY

4K7R2F-GP

GPIO47_DNXFW [18]

12

R1508

DY

10KR2F-2-GP

force DNX FW Load

default

defaultdefault

( don't force DNX FW Load)

( don't force DNX FW Load)( don't force DNX FW Load)

Weak internal pull-down

GPIO_118

1D8V_S5

12

R1518

4K7R2F-GP

GPIO118_FLASH_OVR [19]

12

R1517

DY

4K7R2F-GP

Flash Descriptor Override

No Override (Normal Operation)

No Override (Normal Operation)No Override (Normal Operation)

Weak internal pull-down

GPIO_78

1D8V_S5

12

R1522

DY

10KR2F-2-GP

GPIO78_SMB_LEVEL [19]

12

R1510

4K7R2F-GP

SMBus 1.8V mode select

SMBus 3.3V mode select

SMBus 3.3V mode selectSMBus 3.3V mode select

Weak internal pull-up

GPIO_120

1D8V_S5

12

R1520

DY

4K7R2F-GP

GPIO120_BIOS_SWAP [19]

12

R1519

DY

10KR2F-2-GP

Two SWAP override enable

default

defaultdefault

( Disable top swap override )

( Disable top swap override )( Disable top swap override )

Weak internal pull-down

RSVD (Internal 20K PU)

High

RSVD

Low

B B

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Monday, September 05, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(STRAP)

Turis APL UMA

15 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

9 OF 23

1.24V

9 OF 23

T2

PCIE_P 2_TXP

T3

PCIE_P 2_TXN

M5

PCIE_P 2_RXP

M6

PCIE_P 2_RXN

R1

PCIE_P 1_TXP

R2

PCIE_P 1_TXN

T10

PCIE_P 1_RXP

T12

PCIE_P 1_RXN

V3

PCIE_P 0_TXP

V2

PCIE_P 0_TXN

P7

PCIE_P 0_RXP

P6

PCIE_P 0_RXN

PCIE_W AKE3#

PCIE_W AKE2#

1.8V

PCIE_W AKE1#

PCIE_W AKE0#

10 OF 23

B7

B5

A7

B8

C10

A10

C11

B11

AJ62

AH61

AH62

AK62

AH13

AH12

AG16

AG15

N62

P61

P62

R62

WLAN_CLK_CPU

WLAN_CLK_CPU#

LAN_CLKREQ_CPU#

WLAN_CLKREQ_CPU#

PCIE_CLKREQ1_CPU#

GFX_CLKREQ_CPU#

PCIE_WAKE3_CPU

PCIE_WAKE2_CPU

PCIE_WAKE1_CPU

PCIE_WAKE0_CPU

CRB 122 page

X01_0518

WLAN

X01_0518

VIL=0.35*1.8=0.63 V

WLAN_CLKREQ_CPU# WLAN_CLKREQ_D

X01_0518

RN1607

PCIE_WAKE3_CPU PCIE_WAKE2_CPU

PCIE_WAKE1_CPU

PCIE_WAKE0_CPU

RN1607

1 2 3

SRN10KJ-5-GP

RN1608

1 2 3

SRN10KJ-5-GP

X01_0518

PCIE_CLKREQ1_CPU# GFX_CLKREQ_CPU#

WLAN and LAN side are OD pin, so no need LS

WLAN_CLKREQ_CPU# LAN_CLKREQ_CPU#

1 2 3

RN1606

SRN10KJ-5-GP

1 2 3

RN1603

SRN10KJ-5-GP

X01_0616

3D3V_S5

12

R1605

R1605 10KR2J-3-GP

10KR2J-3-GP

DY

LBAS16LT1G-GP

123

DY

D1601

83.00016.P11

R1607

4

1D8V_S5

4

1D8V_S5

4

12

0R0402-PAD-2-GP

1D8V_S5

Q1601

D

DY

2N7002K-2-GP

84.2N702.J31

2ND = 084.27002.0A31

3rd = 84.07002.I31

3D3V_S0

12

3D3V_S0

R1606

R1606 10KR2J-3-GP

10KR2J-3-GP

DY

G

S

PEG_CLKREQ_WLAN# [61]

CPU1I

L2

PCIE_P 5_USB3_ P2_TX P

L1

PCIE_P 5_USB3_ P2_TX N

K7

PCIE_P 5_USB3_ P2_RX P

M7

D D

WLAN

WLAN_PCIE_TX_P[61]

WLAN_PCIE_TX_N[61]

WLAN_PCIE_RX_P[61]

WLAN_PCIE_RX_N[61]

WLAN_CLK_CPU[61]

C C

B B

WLAN_CLK_CPU#[61]

PEG_CLKREQ_WLAN#[61]

USB3.0

USB1_USB30_TX_P[35]

USB1_USB30_TX_N[35]

USB1_USB30_RX_P[35]

USB1_USB30_RX_N[35]

USB2_USB30_TX_P[35]

USB2_USB30_TX_N[35]

USB2_USB30_RX_P[35]

USB2_USB30_RX_N[35]

ODD

ODD_SATA_TX_P[60]

ODD_SATA_TX_N[60]

ODD_SATA_RX_P[60]

ODD_SATA_RX_N[60]

HDD

HDD_SATA_TX_P[60]

HDD_SATA_TX_N[60]

HDD_SATA_RX_P[60]

HDD_SATA_RX_N[60]

X01_0518

WLAN

USB3.0 port2

USB3.0 port1

ODD

HDD

C1601

SCD1U16V2KX-3GP

12

C1602

12

R1601

PCIE_OBSP_CPU

1 2

402R2F-GP

PCIE_OBSN_CPU

Impedance / Space = 85R / 20 mils

CPU1J

USB2_USB30_TX_P

USB2_USB30_TX_N

USB2_USB30_RX_P

USB2_USB30_RX_N

USB1_USB30_TX_P

USB1_USB30_TX_N

USB1_USB30_RX_P

USB1_USB30_RX_N

ODD_SATA_TX_P

ODD_SATA_TX_N

ODD_SATA_RX_P

ODD_SATA_RX_N

HDD_SATA_TX_P

HDD_SATA_TX_N

HDD_SATA_RX_P

HDD_SATA_RX_N

CPU1J

K3

K2

F2

G2

J1

J2

K9

K10

W1

W2

T5

T6

Y3

Y2

T9

T7

APOLLO-LAKE-GP-U

WLAN_CPU_TX_PWLAN_PCIE_TX_P

WLAN_CPU_TX_NWLAN_PCIE_TX_N

WLAN_PCIE_RX_P

WLAN_PCIE_RX_N

USB3_P1 _TXP

USB3_P1 _TXN

USB3_P1 _RXP

USB3_P1 _RXN

USB3_P0 _TXP

USB3_P0 _TXN

USB3_P0 _RXP

USB3_P0 _RXN

SATA_P 1_USB3_ P5_TX P

SATA_P 1_USB3_ P5_TX N

SATA_P 1_USB3_ P5_RX P

SATA_P 1_USB3_ P5_RX N

SATA_P 0_TXP

SATA_P 0_TXN

SATA_P 0_RXP

SATA_P 0_RXN

PCIE_P 5_USB3_ P2_RX N

N2

PCIE_P 4_USB3_ P3_TX P

M2

PCIE_P 4_USB3_ P3_TX N

H5

PCIE_P 4_USB3_ P3_RX P

H6

PCIE_P 4_USB3_ P3_RX N

P3

PCIE_P 3_USB3_ P4_TX P

P2

PCIE_P 3_USB3_ P4_TX N

P12

PCIE_P 3_USB3_ P4_RX P

P10

PCIE_P 3_USB3_ P4_RX N

F6

PCIE2_ USB3_SA TA3_R COMP_P

F5

PCIE2_ USB3_SA TA3_R COMP_N

APOLLO-LAKE-GP-U

APL_SOC

1.24V

APL_SOC

PCIE_C LKOUT3P

PCIE_C LKOUT3N

PCIE_C LKOUT2P

PCIE_C LKOUT2N

PCIE_C LKOUT1P

PCIE_C LKOUT1N

PCIE_C LKOUT0P

PCIE_C LKOUT0N

PCIE_C LKREQ3 #

PCIE_C LKREQ2 #

PCIE_C LKREQ1 #

PCIE_C LKREQ0 #

USB_SSI C_0_TX _P

USB_SSI C_0_TX _N

USB_SSI C_0_RX _P

USB_SSI C_0_RX _N

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, August 25, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (USB/LPC/GPIO)

Turis APL UMA

16 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

CPU and VR side both PU 170R, and damping 20R close VR

Only VR side PU 85R, and dampi ng 95R close VR

Only CPU side PU 68R,and dampi ng 220R close CPU

CPU1L

C18

SVID0_DATA

C17

SVID0_CLK

B17

SVID0_ALERT#

T61

SMB_DATA

T62

SMB_CLK

R63

SMB_ALERT#

AC16

USB2_VBUS_SNS

USB2_OTG_ID and USB2_VBUS_SNS pin, Set the soft strap for disabling USB OTG.

AC15

USB2_OTG_ID

C55

USB2_OC1#

B55

USB2_OC0#

APOLLO-LAKE-G P-U

1.05V

3.3V

1.8V

APL_SOC

RN1701

1 2 3

SRN10KJ-5-G P

R1703

DY

100KR2J-1-GP

R1701

1 2

PDG1.2

4

12

1KR2J-1-GP

USB_OC#0 USB_OC#1

USB2_OTG_ID

SMB_ALERT#_CP U

SMB_DATA

SMB_CLK

SMB_ALERT#_CP U

R1702

USB2_VBUS_SN S

1 2

0R0402-PAD-2- GP

USB2_OTG_ID

USB_OC#1

USB_OC#0

CRB p91

3D3V_S53D3V_S0

D D

PCH_SMB_DAT A[12,65,70]

PCH_SMB_CLK[12,65,70]

USB_OC#1[36]

USB_OC#0[36]

CARD1_USB 20_P [66]

CARD1_USB 20_N [66]

BT_USB20_P [61]

BT_USB20_N [61]

TS_USB20_P [55]

C C

TS_USB20_N [55]

CCD_USB20_ P [55]

CCD_USB20_ N [55]

USB3_USB20_P [35]

USB3_USB20_N [35]

USB2_USB20_P [35]

USB2_USB20_N [35]

Card reader

BT

Touch Panel

Camera

USB Port3 (USB3.0 Port 2)

USB Port1 (USB3.0 Port 1)

1D8V_S5

3D3V_S5

3.3V

12 OF 23

USB2_DP7

USB2_DN7

USB2_DP6

USB2_DN6

USB2_DP5

USB2_DN5

USB2_DP4

USB2_DN4

USB2_DP3

USB2_DN3

USB2_DP2

USB2_DN2

USB2_DP1

USB2_DN1

USB2_DP0

USB2_DN0

V5

V6

AC12

AC10

AB6

AB7

Y9

Y10

V9

V7

Y13

V13

V16

V15

V12

V10

CARD1_USB 20_P

CARD1_USB 20_N

BT_USB20_P

BT_USB20_N

TS_USB20_P

TS_USB20_N

CCD_USB20_ P

CCD_USB20_ N

USB3_USB20_P

USB3_USB20_N

USB2_USB20_P

USB2_USB20_N

USB1_USB20_P

USB1_USB20_N

Card reader

BT

Touch Panel

Camera

USB Port2 (USB3.0 Port 3)

USB Port1 (USB3.0 Port 2)

USB Port0 (USB2.0 Port 1) (OTG)

USB1_USB20_P [66]

USB1_USB20_N [66]

B B

A A

USB Port0 (USB2.0 Port 1) (OTG)

5

1

23

RN1704

RN1704 SRN2K2J-1-G P

SRN2K2J-1-G P

4

PCH_SMB_DAT A

Note:ZZ.27002.F7C01

1

6

PCH_SMB_CLK SMB_CLK

4

2345

Q1701

2N7002KDW -1-GP

75.27002.F7C

1

23

RN1703

RN1703 SRN1KJ-7-G P

SRN1KJ-7-G P

4

SMB_DATA SMB_CLKPCH_SMB_CLK

PCH_SMB_DAT ASMB_DATA

3D3V_S03D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Thursday, Augus t 25, 2016

Thursday, Augus t 25, 2016 Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Turis APL UMA

1

17 106

X02

Vinaﬁx.com

SSID = PCH

5

4

3

2

1

SUSCLK[24]

SIO_SLP_S4#[40]

SIO_SLP_S3#[40]

PM_SLP_S0#[24,50]

PM_RSTBTN#[99]

D D

PM_PWRBTN#[24,99]

PLT_RST#[24,55,61,63,99]

AC_PRESENT[24]

PMIC_THERMTRIP#[24,50]

PMIC_I2C_SDA[50]

PMIC_I2C_SCL[50]

KB_DET#[20,65]

XDP

XDP_TRST#[99]

XDP_TMS[99]

XDP_TDO[99]

XDP_TDI[99]

XDP_TCK[99]

XDP_PREQ#[99]

XDP_PRDY#[99]

C C

B B

SUS_PWRDN_ACK[24]

RTCRST_ON[24]

H_PROCHOT#[24,44]

GPIO47_DNXFW[15]

EC_SMI#[21,24]

GPIO43_EMMC_BOOT[15]

LPSS_UART1_TXD[99]

XDP_UART_RXD_CPU[99]

GPIO44_SPI_BOOT[15]

GPIO39_TXE_BPS[15]

RSMRST#_KBC[24]

PMIC_RSMRST#[24,50]

PM_RSMRST#[40,99]

eDP_HPD_CPU_D[55]

3V_5V_PWRGD[45,50]

3D3V_S5

PM_RSTBTN#

R18361KR2J-1-GP R18361KR2J-1-GP

1 2

PM_BATLOW#

R182320KR2J-L2-GP R182320KR2J-L2-GP

1 2

SUSCLK

PM_SUS_STAT#

R181110KR2J-3-GP R181110KR2J-3-GP

12

1 2 3

RN1803

RN1803 SRN10KJ-5-GP

SRN10KJ-5-GP

R18351KR2J-1-GPDYR18351KR2J-1-GP

1 2

RN1802

1 2 3

SRN100J-3-GP

XDP

1 2

XDP

SRN20KJ-1-GP

SRN20KJ-1-GP RN1804

RN1804

12

C1802

SC1U10V2KX-1GP

1 2

10MR2J-L-GP

4 1

82.30001.G01

2nd = 82.30001.G11

CL=12.5P 20PPM

R1814

12

DY

R1824

DY

12

R1807

DY

XDP

12

R1810

X1801

12

PM_PWRBTN#_CPU

KB_DET#

4

AC_PRESENT

PM_WAKE#

R180810KR2J-3-GP R180810KR2J-3-GP

R181310KR2J-3-GPDYR181310KR2J-3-GP

12

4

CRB p96

R18191KR2J-1-GP R18191KR2J-1-GP

R18151KR2J-1-GP R18151KR2J-1-GP

CRB p77

R181251R2J-2-GP

R180651R2J-2-GP

R1833100R2J-2-GP

R182851R2J-2-GP

R182751R2J-2-GP

R1826100KR2J-1-GP R1826100KR2J-1-GP

21

G1801

GAP-OPEN

XTL_32K_X1_CPU

XTL_32K_X2_CPU

XTAL-32D768KHZ-68-GP

23

12

SUS_PWRDN_ACK

AC_PRESENT

XDP_PRDY# XDP_PREQ#

PMIC_THERMTRIP#

PROCHOT#_CPU_R

XDP_TMS

XDP_TDI

XDP_TDO

Note:

XDP_TRST#

However it is recommended to not populate the 50 ohm pu lldown on TRST_N if the MIPI60 connector is not populated

XDP_TCK

or if BSSB/DCI is implemente d.

PM_RSMRST#

RTC_RST#

RTC_TEST#

Layout Note:

place on bottom side

ESR=50K for PDG request

C1804

12

SC4P50V2CN-GP

X02_0801X02_0801

Q1801

G

S

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q1802

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

RTC_RST#

D

12

R1818

DY

0R2J-2-GP

RTC_TEST#

D

EC1801

EC1801 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

3D3V_S5

if use XDP,connect to connector.

R1832

1 2

DY

+VRTC

RTC_AUX_S5

12

DY

1 2

PM_PWRBTN#

PLT_RST#

EDS p35

R1817

R1817 100KR2J-1-GP

100KR2J-1-GP

INTRUDER

R1816

R1816 10KR2J-3-GP

10KR2J-3-GP

1KR2J-1-GP

SUSCLK

0R0402-PAD-2-GP

PLTRST#_CPU

to TPM

CRB p50

X01_0601

PDG PH

H_PROCHOT#

CRB p50

R1803

DY

R1804

R1829

PM_BATLOW#

AC_PRESENT

PMIC_THERMTRIP#

CRB p63

C1805

SCD1U16V2KX-3GP

12

0R2J-2-GP

PM_PWRBTN#_CPU

12

PM_SUS_STAT#

PMIC_I2C_SDA

PMIC_I2C_SCL

0R0402-PAD-2-GP

10KR2J-3-GP

100KR2J-1-GP

1D8V_S5

+VRTC

RTC_AUX_S5

1

23

4

12

C1801

SC1U10V2KX-1GP

C1803

SC4P50V2CN-GP

12

RTCRST_ON

100KR2J-1-GP

RTCRST_ON

PM_WAKE#

PM_SUSCLK

SIO_SLP_S4#

SIO_SLP_S3#

PM_SLP_S0#

PM_RSTBTN#

PLTRST#_CPU

TP1803

PM_RSMRST#

R1809

1 2

TPAD14-OP-GP

SUS_PWRDN_ACK

12

CPU1N

AG55

PMU_WAK E#

AE62

PMU_SUSCLK

AK54

PMU_SLP_ S4#

AC62

PMU_SLP_ S3#

AD61

PMU_SLP_ S0#

AD62

PMU_RSTB TN#

AK55

PMU_PWR BTN#

AG57

PMU_PLTR ST#

AH51

PMU_BATL OW#

AK49

PMU_AC_P RESENT

J47

PMIC_THE RMTRIP#

J45

PMIC_ST DBY

M47

GPIO_2 13/PMIC_ SDWN#

F48

PMIC_RE SET#

H48

PMIC_PW RGOOD

R30

NCTF_83

AG58

SUS_STA T#

F47

PMIC_I2 C_SDA

H45

PMIC_I2 C_SCL

L47

GPIO_2 14/PMIC_ BCUDIS W2

P47

GPIO_2 15/PMIC_ BCUDIS CRIT

APOLLO-LAKE-GP-U

XDP_TRST#

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_PREQ#

XDP_PRDY#

JTAG_PMODE

1

RTC_RST#

RTC_TEST#

PROCHOT#_CPU_R

BVCCRTC_EXTPAD

XTL_32K_X2_CPU

XTL_32K_X1_CPU

INTRUDER

A18

C19

C24

C23

A22

C22

B23

C20

C21

B19

AC63

AC55

AH49

AC57

E47

AG51

AC58

AC59

AC54

3.3V

1.8V

3.3V

1.8V

CPU1P

RSVD_2 1

RSVD_2 2

JTAG_T RST#

JTAG_T MS

JTAG_T DO

JTAG_T DI

JTAG_T CK

JTAG_P REQ#

JTAG_P RDY#

JTAG_P MODE

SUSPWR DNACK

RTC_RS T#

RTC_TE ST#

RSM_RST #

PROCHOT #

VCC_RT C_EXTP AD

RTC_X2

RTC_X1

INTRUDER

APOLLO-LAKE-GP-U

APL_SOC

1.8V

APL_SOC

1.8V

3.3V

1.8V

3.3V

Note:

LPSS_UART0 and LPSS_UART3 are not POR for UART functionality.

‧‧‧‧

These signals can be used as GPIOs.

LPSS_UART1 should be dedicated for discrete GNSS

‧‧‧‧

LPSS_UART2 should be dedicated for Host OS Debug

‧‧‧‧

14 OF 23

LPSS_UA RT2_TX D

LPSS_UA RT2_RX D

1.8V

LPSS_UA RT2_RT S#

LPSS_UA RT2_CT S#

LPSS_UA RT1_TX D

LPSS_UA RT1_RX D

LPSS_UA RT1_RT S#

1.8V

LPSS_UA RT1_CT S#

LPSS_UA RT0_TX D

LPSS_UA RT0_RX D

LPSS_UA RT0_RT S#

1.8V

LPSS_UA RT0_CT S#

PMC_SPI _TXD

PMC_SPI _RXD

PMC_SPI _FS2/FS T_SPI _CS2

PMC_SPI _FS1/HV_ DDI2_ HPD

PMC_SPI _FS0

PMC_SPI _CLK

14 OF 23

16 OF 23

RSVD_1 3

RSVD_1 4

NCTF_71

RSVD_1 5

RSVD_1 6

NCTF_76

NCTF_69

NCTF_79

NCTF_73

NCTF_81

NCTF_82

NCTF_78

NCTF_75

NCTF_72

NCTF_70

NCTF_80

NCTF_77

NCTF_74

RSVD_1 7

RSVD_1 8

RSVD_1 9

RSVD_2 0

H41

J41

L41

M41

B43

C43

A42

C42

B45

C45

A46

C44

H50

J50

M48

P48

L48

E52

H43

AG52

A60

J43

AG54

A61

BJ2

BG1

B15

C15

D8

E8

F8

C9

E10

H10

A14

C14

C1

F1

B4

A4

UART2_RXD

UART2_RTS#

NMI_SMI_DBG#_CPU

GPIO43_EMMC_BOOT

XDP_UART_RXD_CPU

GPIO44_SPI_BOOT

GPIO39_TXE_BPS

GPIO40_CPU

eDP_HPD_CPU_D

UART

1 2

R1802 0R2J-2-GP

GPIO47_DNXFW

TP1802 T PAD14-OP-GPTP1802 TPAD14-OP-GP

1

1 2

DY

R1805 0R2J-2-GP

1 2

XDP

R1801 0R2J-2-GP

TP1804 T PAD14-OP-GPTP1804 TPAD14-OP-GP

1

GPIO43_EMMC_BOOT

UART2_TXD

EC_SMI#

LPSS_UART1_TXD

EDS p43

R1834

EC_SMI#

1 2

10KR2J-3-GP

UART DEBUG PORT

1D8V_S5

RSMRST#_KBC

PMIC_RSMRST#

U1801

1

A

2

DY

B

GND3Y

73.01G08.EHG

2ND = 73.7SZ08.EAH

3RD = 73.01G08.L04

R1830 0R0402-PAD-2-GPR1830 0R0402-PAD-2-GP

1 2

5V_S5

1

UART2_TXD

2

UART2_RXD

3 4

ACES-CON4-37-GP

20.F1897.004

5

VCC

U74LVC1G08G-AL5-R-GP-U

4

56

DB3

UART

3D3V_S5

PM_RSMRST#

For EMI Reserved

PLT_RST#

A A

5

XDP_TRST#

PM_RSMRST#

RSMRST#_KBC

3V_5V_PWRGD

PMIC_RSMRST#

RTC_RST#

ED1806

AZ5725-01FDR7G-GPDYED1806

AZ5725-01FDR7G-GP

ED1805

AZ5725-01FDR7G-GPDYED1805

ED1808

AZ5725-01FDR7G-GPDYED1808

AZ5725-01FDR7G-GP

ED1809

AZ5725-01FDR7G-GPDYED1809

AZ5725-01FDR7G-GP

12

DY

AZ5725-01FDR7G-GP

ED1807

AZ5725-01FDR7G-GPDYED1807

ED1803

AZ5725-01FDR7G-GPDYED1803

AZ5725-01FDR7G-GP

ED1804

AZ5725-01FDR7G-GPDYED1804

AZ5725-01FDR7G-GP

12

DY

4

AZ5725-01FDR7G-GP

12

DY

3

2

Title

CPU (PMU/UART/JTAG/RTC/MSC)

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, August 25, 2016

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis APL UMA

18 106

X02

Vinaﬁx.com

SSID = PCH

5

4

3

2

1

GPIO92_SMB_NRB[15]

GPIO88_PMU_LEVEL[15]

GPIO78_SMB_LEVEL[15]

DMIC_CLK_C#[55]

X01_0518

SPI_CLK_ROM_CPU[25]

GPIO120_BIOS_SWAP[15]

GPIO118_FLASH_OVR[15]

GPIO111_BBS[15]

GPIO110_LPC_LEVEL[15]

DMIC_DATA_C#[55]

SPI

SPI_SI_ROM_CPU[25]

SPI_SO_ROM[25]

SPI_WP_ROM[25]

SPI_HOLD_ROM[25]

SPI_CS_CPU_N0[25]

GP_SSP2_TXD[15,99]

ME_FWP_EC_CPU[24]

GP_SSP0_FS1[99]

DBG_I2C_SDA_LB[99]

DBG_I2C_SCL_LB[99]

SERIRQ[24]

Touch Pad

TP_I2C_CLK[65]

TP_I2C_DATA[65]

D D

C C

X01_0518

LPC_AD_CPU_P[3..0][24,99]

LPC_FRAME#_CPU[24,99]

CLKRUN#[24]

LPC_CLK_KBC[24]

LPC_CLK_DBG[99]

B B

LPC_AD_CPU_P0 LPC_AD_CPU_P1 LPC_AD_CPU_P2 LPC_AD_CPU_P3

RN1905

7 8

RN

0R8P4R-PAD-1-GP

LPC_LAD0_R LPC_LAD1_R

3456

LPC_LAD2_R

2

LPC_LAD3_R

1

LPC

X01_0518

ME_FWP_EC_CPU

TP1901TPAD14-OP-GP TP1901TPAD14-OP-GP

GPIO118_FLASH_OVR

AVS_DMIC_DATA

1

AVS_DMIC_CLK

GPIO92_SMB_NRB

GPIO88_PMU_LEVEL

GPIO78_SMB_LEVEL

SPI_SI_ROM_CPU

SPI_SO_ROM

SPI_WP_ROM

SPI_HOLD_ROM

SPI_CS_CPU_N0

SPI_CLK_ROM_CPU

GP_SSP2_TXD

GPIO120_BIOS_SWAP

R1909

0R0402-PAD-2-GP

GPIO110_LPC_LEVEL

GP_SSP0_FS1

GPIO82_CPU

12

GPIO111_BBS

CPU1K

M52

AVS_DMI C_DATA _2

M54

AVS_DMI C_DATA _1

P52

AVS_DMI C_CLK_ B1

M55

AVS_DMI C_CLK_ AB2

P54

AVS_DMI C_CLK_ A1

M61

AVS_I2 S3_WS _SYNC

L63

AVS_I2 S3_SDO

L62

AVS_I2 S3_SDI

M62

AVS_I2 S3_BCL K

M57

AVS_I2 S2_WS _SYNC

M58

AVS_I2 S2_SDO

K59

AVS_I2 S2_SDI

K58

AVS_I2 S2_MCLK /AVS_HD A_RST#

H59

AVS_I2 S2_BCL K

J62

AVS_I2 S1_WS _SYNC

K62

AVS_I2 S1_SDO

K61

AVS_I2 S1_SDI

G62

AVS_I2 S1_MCLK

H63

AVS_I2 S1_BCL K

APOLLO-LAKE-GP-U

CPU1M

A58

FST_SP I_MOSI_ IO0

B58

FST_SP I_MISO_ IO1

B60

FST_SP I_IO2

B61

FST_SP I_IO3

C57

FST_SP I_CS1#

B57

FST_SP I_CS0#

C56

FST_SP I_CLK

E62

SIO_SP I_2_TX D

C62

SIO_SP I_2_RX D

D59

SIO_SP I_2_FS 2

E56

SIO_SP I_2_FS 1

D61

SIO_SP I_2_FS 0

F62

SIO_SP I_2_CL K

H58

SIO_SP I_1_TX D

H57

SIO_SP I_1_RX D

F61

SIO_SP I_1_FS 1

K55

SIO_SP I_1_FS 0

F58

SIO_SP I_1_CL K

J52

SIO_SP I_0_TX D

H54

SIO_SP I_0_RX D

H52

SIO_SP I_0_FS 1

F52

SIO_SP I_0_FS 0

F54

SIO_SP I_0_CL K

APOLLO-LAKE-GP-U

APL_SOC

3.3V /

1.8V

APL_SOC

1.8V

OSC_CL K_OUT_4

1.8V

OSC_CL K_OUT_3

OSC_CL K_OUT_2

OSC_CL K_OUT_1

OSC_CL K_OUT_0

I2C

ISH

11 OF 23

INT_SERIRQ SERIRQ

AB62

LPC_SE RIRQ

LPC_FRAME#_CPU

V61

LPC_FR AME#

PM_CLKRUN#_EC

V62

LPC_CL KRUN#

LPC_CLK_CPU_P1

AA62

LPC_CL KOUT1

LPC_CLK_CPU_P0

AB61

LPC_CL KOUT0

LPC_LAD3_R

W63

LPC_AD 3

LPC_LAD2_R

W62

LPC_AD 2

LPC_LAD1_R

Y62

LPC_AD 1

LPC_LAD0_R

Y61

LPC_AD 0

XTL_19D2M_X1_CPU

P29

OSCOUT

XTL_19D2M_X2_CPU

R27

OSCIN

AF62

AE60

AG63

AF61

AG62

13 OF 23

I2C7_SDA_CPU

LPSS_I 2C4_SD A

LPSS_I 2C4_SC L

LPSS_I 2C3_SD A

LPSS_I 2C3_SC L

LPSS_I 2C2_SD A

LPSS_I 2C2_SC L

LPSS_I 2C1_SD A

LPSS_I 2C1_SC L

LPSS_I 2C0_SD A

LPSS_I 2C0_SC L

AP62

I2C7_SCL_CPU

AP61

AL63

AK61

AP49

AP51

AP52

AP54

I2C3_SDA_CPU

AM62

I2C3_SCL_CPU

AL62

For Touch Pad

AP59

AP58

AN62

AM61

AR62

AR63

LPSS_I 2C7_SD A/ISH_I 2C2_SD A

LPSS_I 2C7_SC L/ISH_I 2C2_SC L

LPSS_I 2C6_SD A/ISH_I 2C1_SD A

LPSS_I 2C6_SC L/ISH_I 2C1_SC L

LPSS_I 2C5_SD A/ISH_I 2C0_SD A

LPSS_I 2C5_SC L/ISH_I 2C0_SC L

1.8V

33R2J-2-GP

CRB p45

R1919

0R0402-PAD-2-GP

R190833R2J-2-GP R190833R2J-2-GP

LPC_CLK_KBC

12

R1905

LPC_CLK_DBG

12

LPC

CRB p45

I2C7_SDA_CPU DBG_I2C_SDA_LB

1D8V_S5 1D8V_S5

DBG_I2C_SCL_LB I2C7_SCL_CPU

R1911

0R2J-2-GP

R1912

0R2J-2-GP

12

CLKRUN#

R1924

12

For EMI Reserved

12

EC1901

EC1901 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

Q1903

S1

D1

S1

D1

1

6

G2

2 5

G1

XDP

D2

S2

43

PJT138KA-GP

075.00138.0A7C

DBG_I2C_SDA_LB

12

DY

DBG_I2C_SCL_LB

12

DY

CLKRUN#

R1921 10KR2J-3-GPR1921 10KR2J-3-GP

1D8V_S5

1

23

XDP

RN1909

4

SRN1KJ-7-GP

1 2

R1922 1KR2J-1-GPR1922 1KR2J-1-GP

1 2

SERIRQ SERIRQ

LPC_CLK_DBGLPC_CLK_KBC

12

EC1902

EC1902 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

I2C7_SDA_CPU I2C7_SCL_CPU

To XDP

3D3V_S5

RN1908

DBG_I2C_SDA_LB DBG_I2C_SCL_LB

RN1908

1 2 3

DY

SRN1KJ-7-GP

4

3D3V_S0 3D3V_S5

R1923

1KR2J-1-GP

1 2

DY

XTL_19D2M_X1_CPU

200KR2F-L-GP

XTL_19D2M_X2_CPU

R1907

1 2

X1901

2 3

XTAL-19D2MHZ-21-GP

2nd = 82.30071.131

CL=7PF 10PPM

41

082.30001.0061

For Touch Pad

Note:ZZ.27002.F7C01

TP_I2C_CLK TP_I2C_CLK_D

1

6

2

5

TP_I2C_DATA_D

3 4

Q1902

Q1902 2N7002KDW-1-GP

2N7002KDW-1-GP

75.27002.F7C

Vth(max)=2.5V

TP_I2C_DATA

TP_VDDTP_VDD

C1901

1 2

SC3D9P50V2CN-1GP

C1902

1 2

SC3D9P50V2CN-1GP

Q1901

I2C3_SCL_CPU TP_I2C_CLK_D

S1

D1

S1

D1

1

6

G2

2 5

G1

1D8V_S5 1D8V_S5

D2

TP_I2C_DATA_D I2C3_SDA_CPU

I2C3_SDA_CPU I2C3_SCL_CPU

TP_I2C_CLK TP_I2C_DATA

TP_I2C_CLK_D TP_I2C_DATA_D

S2

43

PJT138KA-GP

075.00138.0A7C

1 2 3

RN1904

RN1904 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

RN1906

RN1906 SRN2K2J-1-GP

SRN2K2J-1-GP

1 2 3

RN1907

RN1907 SRN10KJ-5-GP

SRN10KJ-5-GP

1D8V_S5

4

TP_VDD

4

3D3V_S5

4

ISST

Q1904

AVS_DMIC_DATA

1D8V_S5 1D8V_S5

DMIC_CLK_D

Note:ZZ.27002.F7C01

DMIC_CLK_C# DMIC_CLK_D

DMIC_DATA_D

A A

5

Note:ZZ.27002.F7C01

1

2

DY

3 4

Q1905

Q1905 2N7002KDW-1-GP

2N7002KDW-1-GP

75.27002.F7C

Vth(max)=2.5V

6

5

DMIC_DATA_C#

AVS_DMIC_DATA

3D3V_S03D3V_S0

4

AVS_DMIC_CLK

DMIC_CLK_C# DMIC_DATA_C#

DMIC_CLK_D DMIC_DATA_D

S1

1

2 5

G1

DY

D2

PJT138KA-GP

075.00138.0A7C

1 2 3

D1

6

G2

S2

43

1 2 3

DY

RN1910

RN1910 SRN10KJ-5-GP

SRN10KJ-5-GP

DY

RN1912

RN1912 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

DY

RN1911

RN1911 SRN10KJ-5-GP

SRN10KJ-5-GP

DMIC_DATA_D

AVS_DMIC_CLK

1D8V_S5

4

3D3V_S0

4

3D3V_S5

4

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, September 01, 2016

Date: Sheet of

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (SATA/PCIE/IHDA)

Turis APL UMA

19 106

X02

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

18 OF 23

CPU1R

PMU_RCOMP

USB_RCOMP

GPIO_RCOMP

MCSI_RCOMP_2

EMMC_RCOMP

MDSI_RCOMP

SM_RCOMP_1

SM_RCOMP_0

1D8V_S0

CPU1R

E21

PCIE_R EF_CLK _RCOMP

AG59

PMU_RCOMP

AB15

USB_SSI C_RCOMP

Y15

USB2_RC OMP

H27

MCSI_DP HY1.1_RCO MP

E34

GPIO_R COMP

F27

MCSI_DP HY1.2_RCO MP

V59

EMMC_RCO MP

AP7

MDSI_RC OMP

D2

NCTF_41

AV30

MEM_CH1_RC OMP

AV34

MEM_CH0_RC OMP

APOLLO-LAKE-GP-U

R2018

1 2

10KR2J-3-GP

R2001

PCIE_REF_CLK_RCOMP

CRB p52

D D

C C

B B

PWR

SYS_PWROK[24,26]

PMIC_PWRGD[24,26,50]

DBC_EN[55]

KB_DET#[18,65]

CAMERA_DET#[55]

EMMC

EMMC_DATA_7[63]

EMMC_DATA_6[63]

EMMC_DATA_5[63]

EMMC_DATA_4[63]

EMMC_DATA_3[63]

EMMC_DATA_2[63]

EMMC_DATA_1[63]

EMMC_DATA_0[63]

EMMC_RCLK[63]

EMMC_CMD[63]

EMMC_CLK[63]

PANEL_SIZE_ID[55]

VRAM_ID1

Vegas

PROJECT_ID1

BOARD_ID2

10KR2J-3-GP

VRAM_2G

VRAM_4G

1D8V_S0

BIOS strap pin:

PROJECT Strap pin

12

R2019

R2020

Turis

OPS

UMA

1D8V_S0

12

R2029

R2029 10KR2J-3-GP

10KR2J-3-GP

12

R2028

R2028 10KR2J-3-GP

10KR2J-3-GP

12

R2024

R2024 10KR2J-3-GP

10KR2J-3-GP

12

10KR2J-3-GP

R2025

Turis

Vegas

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

BIOS strap pin:

BIOS VRAM Size Strap pin

4G

2G

EMMC_RCOMP Signal Routing General Layout Requirement Trace length :500<L<1000 Trace width : 20 mils Isolation to other signal: 8mils

GPP_A18GPP_A19

PROJECT_ID1

0

1

GPP_C11

BOARD_ID2

0

1

GPP_B17

VRAM_ID1

0

1

X01_0616

1 2

60D4R2F-GP

R2002

1 2

200R2F-L-GP

R2003

1 2

DY

137R2F-GP

R2004

1 2

113R2F-GP

R2005

1 2

DY

150R2F-1-GP

R2006

1 2

200R2F-L-GP

R2007

1 2

DY

150R2F-1-GP

R2008

1 2

200R2F-L-GP

R2009

1 2

150R2F-1-GP

DY

R2010

1 2

105R2F-GP

R2011

1 2

105R2F-GP

KB_DET#

USB_SSIC_RCOMP

MCSI_RCOMP_1

Level Shift

3D3V_S5 3D3V_S03D3V_S0

DBC_EN_C

10KR2J-3-GP

R2122

12

Q2104

D

2N7002K-2-GP

84.2N702.J31

2ND = 084.27002.0A31

3rd = 84.07002.I31

12

R2123

2K2R2J-2-GP

G

DBC_EN

S

APL_SOC

Space/Width = 20/20 mils

Space/Width = 8/15 mils

Space/Width = 20/20 mils

Space/Width = 15/15 mils

X02_0718

CAMERA_DET#

DBC_EN_C

CAMERA_DET#

PROJECT_ID1

BOARD_ID2

VRAM_ID1

PANEL_SIZE_ID

18 OF 23

NCTF_51

NCTF_50

NCTF_46

NCTF_44

NCTF_43

NCTF_40

NCTF_48

NCTF_39

NCTF_47

SOC_PW ROK

NCTF_52

JTAGX

NCTF_36

NCTF_42

NCTF_38

NCTF_45

NCTF_49

NCTF_37

NCTF_53

CPU1H

T55

SDIO_D 3

T54

SDIO_D 2

P57

SDIO_D 1

T52

SDIO_D 0

T57

SDIO_C MD

P58

SDIO_C LK

P51

SDIO_P WR_DW N#

AB58

SDCARD _CLK/GP IO_17 2

AB54

SDCARD _CD#/GP IO_17 7

AB55

SDCARD _LVL_W P/GPI O_186

AC52

SDCARD _CMD/GPI O_178

AB51

SDCARD _D3/GPI O_176

AC51

SDCARD _D2/GPI O_175

AC48

SDCARD _D1/GPI O_174

AC49

SDCARD _D0/GPI O_173

APOLLO-LAKE-GP-U

AM58

AM59

AB49

R25

C13

B13

AB13

all S0 power rail ok (PCH_PWROK)

AC13

" delay 1D05V_S0 between 5~100ms") (input pin)

P27

SOC_PWROK_CPU

AG49

12

R2023

J29

B21

100KR2J-1-GP

A3

P25

C2

M39

If the SOC_PWROK signal is connected to the EC then in the G3 state the EC is turned off and there is no termination for the SOC_PWROK signal. Floating SOC_PWROK

P39

signal in G3 State can cause high leakage in the RTC 3.3V rail. To address this, please make sure there is a weak pull down (~100 kohm) path to GND for SOC_PWROK in

R39

G3 State to ensure low leakage on RTC. From M0W44

R37

R2013

0R0402-PAD-2-GP

1 2

DY

R2014 0R2J-2-GP

APL_SOC

12

SYS_PWROK

PMIC_PWRGD

1.8V

3.3V /

1.8V

CRB p52

EDS p35

8 OF 23

EMMC_DATA_7

V57

EMMC_D7

EMMC_DATA_6

V55

EMMC_D6

EMMC_DATA_5

Y49

EMMC_D5

EMMC_DATA_4

V52

EMMC_D4

EMMC_DATA_3

V51

EMMC_D3

EMMC_DATA_2

EMMC_D2

EMMC_D1

EMMC_D0

EMMC_RCL K

EMMC_CMD

EMMC_CLK

T59

EMMC_DATA_1

T58

EMMC_DATA_0

V58

EMMC_RCLK

V54

EMMC_CMD

Y51

EMMC_CLK

Y58

1.8V

1.8V3.3V /

CRB P64

For EMI Reserved RC

R2017

12

DY

0R2J-2-GP

R2016

12

DY

0R2J-2-GP

EMMC_RCLK

12

R2012

eMMC

100KR2J-1-GP

EMMC_CLK_RC

12

EC2001

EC2001 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

EMMC_RCLK_RC

12

EC2002

EC2002 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Friday, August 26, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Turis APL UMA

20 106

X02

Vinaﬁx.com

SSID = CPU

5

4

3

2

1

CFG[7:0][99]

KB_LED_BL_DET_R [65]

TP_IN#_CPU [65]

HDD_FALL_INT [70]

D D

FFS_INT2 [70]

EC_SMI# [18,24]

SOC_RUNTIME_SCI# [24]

DBG_PTI_CLK0 [99]

HDA

HDA_SPKR[27]

HDA_CODEC_SDOUT[27]

HDA_SDIN0_CPU[27]

HDA_CODEC_SYNC[27]

HDA_CODEC_BITCLK[27]

HDA_CODEC_SDIN0 [27]

X02_0728

SOC_RUNTIME_SCI# PMIC_IRQ

1 2 3

PMIC_IRQ

RN2101

RN2101 SRN10KJ-5-GP

SRN10KJ-5-GP

1D8V_S5

4

ISH INT: Active low, OD

HDA_CODEC_SDOUT

HDA_CODEC_SYNC

HDA_CODEC_BITCLK

33R2J-2-GP

EDS p42

R2104

1 2

R2105

1 2

R2107

1 2

HDA_SPKR

HDA_SDOUT_CPU

HDA_SDIN0_CPU

HDA_SYNC_CPU

HDA_BITCLK_CPU

For EMI Reserved

PMIC_IRQ[50]

EMMC_RESET# [63]

GPIO36_VCCIO_LEVEL [15]

SATA_LED#_CPU[64]

HDD_DEVSLP [60]

SATA_ODD_PRSNT#[60]

C C

HDA_CODEC_BITCLK

12

EC2102

EC2102 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

#560733 HDA Sighting: Passive Workaround DY R2121 and R2101 after QS sample.

HDA_SYNC_CPU HDA_CODEC_SDIN0

R2121

1 2

DY

12

249R2F-GP

R2101

R2101 1KR2F-3-GP

1KR2F-3-GP

DY

HDD_FALL_INT

SATA_LED#_CPU

X01_0519

CPU1O

AK57

ISH_GPI O_9/SPK R

AM52

ISH_GPI O_8/MEMHOT #

AM55

ISH_GPI O_7/AVS _I2S5 _SDO/LP SS_UAR T2_CTS #

AM57

ISH_GPI O_6/AVS _I2S5 _SDI/LP SS_UAR T2_RTS #

AM49

ISH_GPI O_5/AVS _I2S5 _WS_S YNC/LPSS _UART2_ TXD

AM51

ISH_GPI O_4/AVS _I2S5 _BCLK/L PSS_UA RT2_RX D

AM54

ISH_GPI O_3/AVS _I2S6 _SDO/AV S_HDA_ SDO

AK51

ISH_GPI O_2/AVS _I2S6 _SDI/AV S_HDA_ SDI

AK58

ISH_GPI O_1/AVS _I2S6 _WS_S YNC/AVS_ HDA_WS _SYNC

AM48

ISH_GPI O_0/AVS _I2S6 _BCLK/A VS_HDA _BCLK

F34

GPIO_3 3/ISH_GP IO_15 /SUS_CLK 3

F35

GPIO_3 2/ISH_GP IO_14 /SUS_CLK 2

H34

GPIO_3 1/ISH_GP IO_13 /SUS_CLK 1

C37

GPIO_3 0/ISH_GP IO_12

H35

GPIO_2 9/ISH_GP IO_11

B37

GPIO_2 8/ISH_GP IO_10

C29

GPIO_2 7

C31

GPIO_2 6/SATA_ LED#

C27

GPIO_2 5/SATA_ DEVSL P1

APOLLO-LAKE-GP-U

APL_SOC

1.8V

15 OF 23

GPIO_1 8

GPIO_2 4/SATA_ DEVSL P0

GPIO_2 3/SATA_ GP1

GPIO_2 2/SATA_ GP0

GPIO_2 1

GPIO_2 0

GPIO_1 9

GPIO_9

GPIO_1 7

GPIO_1 6

GPIO_1 5

GPIO_1 4

GPIO_1 3

GPIO_1 2

GPIO_1 1

GPIO_1 0

GPIO_0

GPIO_8

GPIO_7

GPIO_6

GPIO_5

GPIO_4

GPIO_3

GPIO_2

GPIO_1

J39

C25

B25

A26

C26

B27

C33

A30

C35

C36

F39

C38

C30

E39

C34

L39

A38

B29

H39

B31

A34

B35

B39

C39

B33

TP_IN#_CPU

SATA_DEVSLP_HDD_CPU

SATA_ODD_PRSNT#_CPU

FFS_INT2

TOUCH_INT_CPU

TOUCH_RST_CPU

KB_LED_BL_DET_R

EC_SMI#_SOC

SOC_RUNTIME_SCI#

XDP_PTI_CLK0

CFG7

CFG6

CFG5

CFG4

CFG3

CFG2

CFG1

CFG0

1

R2128

1 2

0R0402-PAD-2-GP

R2117

1 2

XDP

0R2J-2-GP

CRB p49

Serial ATA Port [0] General Purpose Inputs (SATA_GP0): When configured as SATA_GP0, this is an input pin that issued as an interlock switch status indicator for SATA Port 0. Drive the pin to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.

TP2101TPAD14-OP-GPTP2101TPAD14-OP-GP

TP2102TPAD14-OP-GPTP2102TPAD14-OP-GP

TP_IN#_CPU

SATA_LED#_CPU

EC_SMI#

DBG_PTI_CLK0

X01_0523

SATA_ODD_PRSNT#_CPU SATA_ODD_PRSNT#_D

1 2

100KR2J-1-GP

R2114

10KR2J-3-GP

R2106

10KR2J-3-GP

R2115

1D8V_S5

1D8V_S0

12

DY

1D8V_S51D8V_S5

12

R2120

R2120 10KR2J-3-GP

10KR2J-3-GP

ODD

X01_0616

R2129 0R0402-PAD-2-GPR2129 0R0402-PAD-2-GP

G

S

G

S

DEVSLP

DY

12

DEVSLP

X01_0523

D

Q2101

Q2101 PJA138KA-GP

PJA138KA-GP

084.00138.0A31

ODD PRSNT

X01_0616

D

Q2102

Q2102 PJA138KA-GP

PJA138KA-GP

084.00138.0A31

3D3V_S01D8V_S01D8V_S0

12

R2116

R2116 4K7R2J-2-GP

4K7R2J-2-GP

DY

HDD_DEVSLPSATA_DEVSLP_HDD_CPU

3D3V_S5

12

R2124

R2124 10KR2J-3-GP

10KR2J-3-GP

DY

2ND = 84.2N702.031

SATA_ODD_PRSNT#SATA_ODD_PRSNT#_CPU

DY

D

2N7002K-2-GP

84.2N702.J31

Q2103

3D3V_S0 3D3V_S0

G

S

12

DY

R2126

R2126 10KR2J-3-GP

10KR2J-3-GP

SATA_ODD_PRSNT#

CRB_REV1.2 Page 71

1D8V_S5 1D8V_S0

R2119

R2118

1 2

DY

0R2J-2-GP

20KR2J-L2-GP

R2119

DY

1

1 2

TP2104 TPAD14-OP-GPTP2104 TPAD14-OP-GP

TP2105 TPAD14-OP-GPTP2105 TPAD14-OP-GP

17 OF 23

CPU1Q

M16

NCTF_59

L16

F16

E16

J16

H16

H12

F12

M12

M10

F14

H14

NCTF_60

NCTF_63

NCTF_54

NCTF_66

NCTF_58

NCTF_68

NCTF_56

NCTF_65

NCTF_62

NCTF_57

NCTF_55

APOLLO-LAKE-GP-U

B B

APL_SOC

17 OF 23

EMMC_RST_N EMMC_RESET#

L30

GPIO_2 19

M30

GPIO_2 18

M29

GPIO_2 17

P30

GPIO_2 16

AP57

NCTF_67

1.8V

NCTF_64

NCTF_61

E41

PWM3

GPIO36_VCCIO_LEVEL

F41

PWM2

GPIO35_CPU

C41

PWM1

GPIO34_CPU

B41

PWM0

C63

E63

EDS1.0 Page 52 QS Sample can Support R2119, R2118 stuff and DY Q6301, R2125

R2125

R2125 20KR2J-L2-GP

20KR2J-L2-GP

eMMC

1 2

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, August 25, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

1

CPU (POWER1)

Turis APL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

21 106

X02

Vinaﬁx.com

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose application without get Wistron permission

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

Wednesday, July 27, 2016

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Turis APL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

X02

22 106

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

D D

19 OF 23

CPU1S

AM36

VSS_394

AG42

VSS_190

AG44

VSS_193

AG46

VSS_196

AH15

VSS_199

AH16

VSS_202

AH48

VSS_205

AH5

VSS_208

AH52

VSS_211

AH54

VSS_214

AH55

VSS_217

AH57

VSS_220

AH58

VSS_223

AH59

VSS_226

AH6

VSS_229

AH7

VSS_232

AJ1

VSS_235

AJ18

VSS_388

AJ2

VSS_238

AJ23

VSS_241

AJ27

VSS_244

AJ34

VSS_247

AJ36

VSS_250

AJ63

VSS_253

AK10

VSS_256

AK12

AM18 AM22 AM27 AM34 AM39 AM46

AK18 AK23 AK27 AK48

AK52 AK59

AN10 AN11 AN13 AN14 AN16 AN17

AN25 AN27 AN28 AN30 AN34 AN36 AN37 AN39 AN47 AN48

AN50 AN51 AN53

AC18

AK5

AK9

AN1

AN2

AN5

B63

A5

VSS_259 VSS_262 VSS_265 VSS_268 VSS_273 VSS_276 VSS_279 VSS_282 VSS_285 VSS_288 VSS_291 VSS_294 VSS_297 VSS_300 VSS_303 VSS_306 VSS_309 VSS_312 VSS_315 VSS_318 VSS_321 VSS_324 VSS_327 VSS_330 VSS_333 VSS_336 VSS_339 VSS_342 VSS_345 VSS_348 VSS_351 VSS_354 VSS_357 VSS_360 VSS_363 VSS_366 VSS_369 VSS_392 VSS_393 VSS_391

APOLLO-LAKE-G P-U

C C

B B

APL_SOC

19 OF 23

VSS_1 VSS_4

VSS_7 VSS_10 VSS_13 VSS_16 VSS_19 VSS_22 VSS_25 VSS_28 VSS_31

VSS_380

VSS_34

VSS_382

VSS_37 VSS_40 VSS_43

VSS_384

VSS_46 VSS_49 VSS_52 VSS_55 VSS_58 VSS_61 VSS_64 VSS_67 VSS_70 VSS_73 VSS_76 VSS_79 VSS_82 VSS_85 VSS_88 VSS_91

VSS_386

VSS_94 VSS_97

VSS_100 VSS_103 VSS_106 VSS_109 VSS_112 VSS_115 VSS_118 VSS_121 VSS_124 VSS_127 VSS_130 VSS_133 VSS_136 VSS_139 VSS_142 VSS_145 VSS_148 VSS_151 VSS_154 VSS_157 VSS_160 VSS_163 VSS_166 VSS_169 VSS_172 VSS_175 VSS_178 VSS_181 VSS_184 VSS_187

A12 A16 A20 A24 A28 A32 A36 A40 A44 A48 A52 A56 A62 A9 AA1 AA2 AA27 AA34 AA41 AA63 AB10 AB12 AB16 AB48 AB5 AB52 AB57 AB59 AB9 AC27 AC34 AC39 AE1 AE10 AE11 AE13 AE14 AE16 AE17 AE2 AE23 AE27 AE34 AE39 AE4 AE41 AE47 AE48 AE5 AE50 AE51 AE53 AE54 AE56 AE57 AE59 AE63 AE7 AE8 AG13 AG18 AG23 AG27 AG34 AG37 AG39 AG41

AW14 AW30 AW34 AW50

AR19 AR32 AR45 AT12 AT16 AT19

AT25 AT29

AT35 AT39 AT45 AT48 AT52 AT57 AT61 AT62

AU32 AV19

AV21 AV23 AV29

AV32 AV35 AV41 AV43 AV45 AV55 AV61 AV62

AY10 AY32 AY54 AY58

BA12 BA16 BA17

BA21 BA25 BA27 BA29 BA32 BA35 BA37 BA39 BA43 BA47 BA48 BA52 BA62 BA63 AK36

AT2

AT3

AT7

AV2

AV3

AV9

AY6

B2 B3

B62

B9

BA1

BA2

CPU1T

VSS_2 VSS_5 VSS_8 VSS_11 VSS_14 VSS_17 VSS_20 VSS_23 VSS_26 VSS_29 VSS_32 VSS_381 VSS_35 VSS_383 VSS_38 VSS_41 VSS_44 VSS_385 VSS_47 VSS_50 VSS_53 VSS_56 VSS_59 VSS_62 VSS_65 VSS_68 VSS_71 VSS_74 VSS_77 VSS_80 VSS_83 VSS_86 VSS_89 VSS_92 VSS_387 VSS_95 VSS_98 VSS_101 VSS_104 VSS_107 VSS_110 VSS_113 VSS_116 VSS_119 VSS_122 VSS_125 VSS_128 VSS_131 VSS_134 VSS_137 VSS_140 VSS_143 VSS_146 VSS_149 VSS_152 VSS_155 VSS_158 VSS_161 VSS_164 VSS_167 VSS_170 VSS_173 VSS_176 VSS_179 VSS_182 VSS_185 VSS_188 VSS_390

APOLLO-LAKE-G P-U

APL_SOC

20 OF 23

VSS_191 VSS_194 VSS_197 VSS_200 VSS_203 VSS_206 VSS_209 VSS_212 VSS_215 VSS_218 VSS_221 VSS_224 VSS_227 VSS_230 VSS_233 VSS_236 VSS_389 VSS_239 VSS_242 VSS_245 VSS_248 VSS_251 VSS_254 VSS_257 VSS_260 VSS_263 VSS_266 VSS_269 VSS_271 VSS_274 VSS_277 VSS_280 VSS_283 VSS_286 VSS_289 VSS_292 VSS_295 VSS_298 VSS_301 VSS_304 VSS_307 VSS_310 VSS_313 VSS_316 VSS_319 VSS_322 VSS_325 VSS_328 VSS_331 VSS_334 VSS_337 VSS_340 VSS_343 VSS_346 VSS_349 VSS_352 VSS_355 VSS_358 VSS_361 VSS_364 VSS_367

BB19 BB25 BB3 BB39 BB45 BB61 BC32 BD3 BD32 BD56 BD61 BD8 BE1 BE10 BE12 BE16 BE17 BE21 BE27 BE29 BE35 BE37 BE43 BE47 BE48 BE52 BE54 BE63 BF3 BF32 BF61 BG19 BG23 BG29 BG32 BG35 BG41 BG45 BH1 BH2 BH21 BH25 BH39 BH43 BH62 BH63 BJ10 BJ14 BJ18 BJ28 BJ32 BJ36 BJ4 BJ46 BJ50 BJ54 BJ56 BJ60 BJ8 C12 C16

CPU1U

D6

VSS_21

E12

VSS_24

E14

VSS_27

E19

VSS_30

E27

VSS_33

E4

VSS_36

E54

VSS_39

F10

VSS_42

F21

VSS_45

F3

VSS_48

F32

VSS_51

F37

VSS_54

F43

VSS_57

F45

VSS_60

F50

VSS_63

F56

VSS_66

F59

VSS_69

F63

VSS_72

G1

VSS_75

G32

VSS_78

H17

VSS_81

H23

VSS_84

H29

VSS_87

H3

VSS_90

H37

VSS_93

H47

VSS_96

H61

VSS_99

H7

VSS_102

J12

VSS_105

J14

VSS_108

J19

VSS_111

J27

VSS_114

J30

VSS_117

J32

VSS_120

J35

VSS_123

J37

VSS_126

J48

VSS_129

J63

VSS_132

K32

VSS_135

K5

VSS_138

K54

VSS_141

K57

VSS_144

K6

VSS_147

L21

VSS_150

L27

VSS_153

L29

VSS_156

L35

VSS_159

L43

VSS_162

L45

VSS_165

L50

VSS_168

M14

VSS_171

M21

VSS_174

M27

VSS_177

M3

VSS_180

M32

VSS_183

M50

VSS_186

M59

VSS_189

M9

VSS_192

N1

VSS_195

N32

VSS_198

N63

VSS_201

P13

VSS_204

P19

VSS_207

P35

VSS_210

P37

VSS_213

R29

VSS_395

APOLLO-LAKE-G P-U

APL_SOC

21 OF 23

VSS_222 VSS_225 VSS_228 VSS_231 VSS_234 VSS_237 VSS_240 VSS_243 VSS_246 VSS_249 VSS_252 VSS_255 VSS_258 VSS_261 VSS_264 VSS_267 VSS_270 VSS_272 VSS_275 VSS_278 VSS_281 VSS_284 VSS_287 VSS_290 VSS_293 VSS_296 VSS_299 VSS_302 VSS_305 VSS_308 VSS_311 VSS_314 VSS_317 VSS_320 VSS_323 VSS_326 VSS_329 VSS_332 VSS_335 VSS_338 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_341 VSS_344 VSS_347 VSS_350 VSS_353 VSS_356 VSS_359 VSS_362 VSS_365 VSS_368 VSS_370

VSS_3 VSS_6

VSS_9 VSS_12 VSS_15 VSS_18

VSS_216 VSS_219

P45 P5 P55 P59 P9 R23 R32 T49 U1 U10 U11 U13 U14 U16 U17 U18 U2 U27 U34 U5 U50 U51 U53 U54 U56 U57 U59 U62 U63 U7 U8 V20 V27 V34 V42 Y12 Y16 Y22 Y27 Y34 AP9 AP55 AN63 AN7 AN8 AN54 AN56 AN57 AN59 Y42 Y46 Y48 Y5 Y52 Y54 Y55 Y57 Y59 Y6 Y7 C28 C32 C40 C48 D32 D58 P41 P43

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, July 27, 2016

Wednesd ay, July 27, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

(Reserved)

Turis APL UMA

1

23 106

X02

Vinaﬁx.com

SSID = KBC

SATA_LED[64]

BATT_WHITE_LED#[64]

CHG_AMBER_LED #[64]

BKLGT_PWM[65]

BEEP[27]

SATA_LED[64]

PMIC_RSMRST#[18,50]

D D

C C

B B

eDP_BLEN_ CPU[8]

PMIC_PWRGD[20,26,50]

DAT_TP_SIO[65]

CLK_TP_SIO[65]

LCD_TST[55]

PTP_DIS#[65 ]

AD_IA[44]

PSID[43]

USB_PWR_EN #[36]

VD_IN1[26 ]

AD_IA_HW[44]

EC_BRIGHTNE SS[55]

LID_CLOSE#[64]

SMBCLK1[43,44]

SMBDA1[43,44]

SMB_CLK_CPU[26 ]

SMB_DATA_CPU[26]

RTCRST_ON[18]

LCD_TST_EN[55]

TP_INT#_EC[65]

AC_DIS[43]

PANEL_BKEN_ EC[55]

PM_PWRBTN#[18 ,99]

SYS_PWROK[20 ,26]

BLUETOOTH_EN _KBC[61]

WIFI_RF_EN[61]

ME_FWP_EC_CP U[19]

E51_TxD[61] AD_IA_HW2[44]

SUS_PWRDN _ACK[1 8]

PM_SLP_S3#[4 0,50]

PM_SLP_S0#[1 8,50]

VD_IN1[26 ]

VD_OUT1#[26]

CLKRUN#[1 9]

EC_MUTE#[27]

3V_EN[40]

LPC_CLK_ KBC[19 ]

PMIC_EN_KBC[50]

5

LPC_FRAME#_C PU [19,9 9]

SPI_CS_ROM_N 0_R [25] SPI_CLK_ROM [25]

SPI_SI_ROM [25] EC_SPI_MISO [25]

RTC_DET# [25]

PM_SLP_S4# [4 0,50] eDP_VDDEN_ CPU [8,55 ]

RSMRST#_KBC [18]

S5_ENABLE [4 0]

SOC_RUNTIME_ SCI# [2 1]

SERIRQ [19]

AC_PRESENT [18]

EC_SMI# [18,21]

TOUCH_PANEL _EN [55 ]

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

LPC_AD_CPU _P0 LPC_AD_CPU _P1 LPC_AD_CPU _P2 LPC_AD_CPU _P3

TP_EN# [65]

PLT_RST# [18,55,61 ,63,99]

CAP_LED# [6 5] PBAT_PRES# [4 3,44]

SUSCLK [18]

TOUCH_PANEL _EN [55]

KSI[0..7] [65 ]

KSO[0..16] [65]

LPC_AD_CPU _P[3..0] [19,99]

3D3V_AUX_KBC

R2462 1 0KR2J -3-GP

3D3V_S5

R2439 1 00KR2 J-1-GPR2 439 100KR2J-1-GP

R2473 1 0KR2J -3-GPR2473 10KR2J-3-GP

3D3V_S0

R2445 8 K2R2J -3-GPR2445 8K2R2J-3-GP

R2472 1 0KR2J -3-GPR2472 10KR2J-3-GP

3D3V_S5

R2471 1 0KR2J -3-GP

R2426 10KR2J-3-GP

3D3V_S0

R2427 1 0KR2J -3-GP

R2468 1 KR2J-1 -GP

C2428 SCD1U 16V2KX-3GP

C2438 SCD1U16V2KX-3GPC2438 SCD1U16V2KX-3GP

EC_AGND

UMA and DIS and NOVA KB modle ID

RN2402

RN2402 SRN10KJ-5- GP

SRN10KJ-5- GP

1

4

2 3

1 2

DY

RN2404

RN2404 SRN10KJ-5- GP

SRN10KJ-5- GP

1

4

2 3

RN2401

2 3 1

4

SRN2K2J-1- GP

1 2

DY

1 2

DY

Touch Panel PH internally.

1 2

DY

12

T8_KBC

1 2

DY

1 2

PROJECT_ID2

C2418

SCD1U16V2KX-3GP

ECRST# PBAT_PRES#

AC_IN_KBC#

RTC_DET# TP_EN#

SMB_CLK_CPU SMB_DATA_CPU

RSMRST_IN_PMIC

LID_CLOSE#

H_A20GATE

BLUETOOTH_EN _KBC

USB_PWR_EN #

SYS_PWROK

TOUCH_PANEL _EN

VD1_EN#

AD_IA

3D3V_AUX_KBC

12

R2441

UMA

10KR2J-3-GP

12

R2443

12

100KR2F-L1-GP

DY

DIS

PROJECT_ID2

UMA

4

R2497 0 R040 2-PAD-2-G PR2 497 0R0402-PAD-2-G P

1 2

12

C2439

SCD1U16V2K X-3GP

EC_AVCC

12

C2436

EC_AGND

EC_VCC1V81D8V_S5

EC_AVCC EC_VCC1V8

PMIC_RSMRST#

eDP_BLEN_ CPU

12

C2416

SC2D2U10V3KX-1GP

SCD1U16V2KX-3GP

R2415

R2498 0R04 02-PAD-2 -GPR2498 0R 0402-P AD-2-GP

R2422 0R04 02-PAD-2 -GPR2422 0R 0402-P AD-2-GP

R2411 0 R2J-2 -GP

R2411 0 R2J-2 -GP R2414 0R0402-PAD-2-GPR2414 0R0402-PAD -2-GP

R2444

1 2

1 2 1 2

TP2410 TPAD14 -OP-GPTP2410 TP AD14-OP-GP

TP2412 TPAD14 -OP-GPTP2412 TP AD14-OP-GP

3D3V_S0

12

R2430

R2430 10KR2F-2-GP

10KR2F-2-GP

DY

EC_VTT

C2447

SCD1U16V2KX-3GPDYC2447

SCD1U16V2KX-3GP

12

R2509

DY

0R0402-PAD -2-GP

1 2

3D3V_S01 D8V_S0

12

R2511

R2511 0R2J-2-GP

0R2J-2-GP

DY

KBC_VCC1D8 V

C2432

SCD1U16V2K X-3GP

12

R2512

0R0402-PAD -2-GP

Serves as the power supply for the SERIRQ LPC signal. This power supply is active during S0 power state only. (Page 43 , 985 KBC)

12

C2433

DY

SC2D2U10 V3KX-1GP

Start up

KBC_PWRBTN #[64,99]

High Active

Q2402

H_PROCHOT_ EC

G

R2442

R2442 100KR2J-1 -GP

100KR2J-1 -GP

A00_0829

PCB_VER_AD

C2417

SCD1U16V2KX-3GP

12

DY

S

2N7002K-2 -GP

84.2N702.J31

2ND = 84.2N702.031

3D3V_AUX_KBC

12

R2437

R2437 47KR2J-2-GP

47KR2J-2-GP

-1

12

R2438

100KR2F-L1-GP

D

H_PROCHOT# [18,44 ]

12

DY

H

KBC_VCC

12

C2429

SCD1U16V2KX-3GP

0R0402-PAD -2-GP

TP2408

TPAD14-OP-GP

DY

X01_0518

12

0R0402-PAD -2-GP

PSL_OUT#

EE Note: If want to use XDP, R2489 need to rework to 3K ohm

AC_IN#[44]

R2435

1 2

0R0603-PAD -2-GP-U

12

C2440

SCD1U16V2KX-3GP

1

R2499

R2500

12

C2430

EC_VTT

AD_IA PCB_VER_AD PSID SATA_LED USB_PWR_EN # RSMRST_IN_PMIC VD_IN1 PROJECT_ID2

FAN1_DAC_1 AD_IA_HW EC_BRIGHTNE SS LID_CLOSE#

SMBCLK1 SMBDA1 SMB_CLK_CPU SMB_DATA_CPU SIO_EXT_SMI# RTCRST_ON H_PROCHOT_ EC LCD_TST_EN TP_INT#_EC LCD_TST_KB CL CD_TS T

CLK_TP_SIO DAT_TP_SIO PMIC_PWROK_KBCPMIC_PWRGD AC_DIS SUS_PWR_ACK _RSUS _PWRD N_ACK PANEL_BKEN_ EC_KBCPANEL_BKEN_ EC

FAN_TACH1 PM_PWRBTN# 3V_EN PM_SLP_S3#

BEEP BATT_WHITE_LED# BKLGT_PWM AC_IN_KBC# L_BKLT_EN_ EC CHG_AMBER_LED # PM_SLP_S0# VD1_EN#

VD_IN1

VD_OUT1# PMIC_EN_KBC

SYS_PWROK BLUETOOTH_EN _KBC WIFI_RF_EN ME_FWP_EC_CP U

DGPU_PWROK H_A20GATE E51_TxD AD_IA_HW2

CLKRUN# EC_MUTE#

1 2

3

3D3V_AUX_KBC

R2408

2D2R3-1-U -GP

1 2

12

C2431

C2441

C2414

C2414 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC2D2U10V3KX-1GP

KBC24

R2493

1 2

1KR2J-1-GP

3D3V_AUX_S5

1 2

0R0402-PAD -2-GP

KBC24

19

VCC

46

VCC

76

VCC

115

VCC

88

VCC1D8

102

AVCC

4

VDD1D8

12

VTT

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/EXT_PURST#/AD6

94

GPIO7/AD7/VD_IN2

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

70

GPIO17/SCL1/N2TCK

69

GPIO22/SDA1/N2TMS

67

GPIO73/SCL2/N2TCK

68

GPIO74/SDA2/N2TMS

119

GPIO23/SCL3/N2TCK

120

GPIO31/SDA3/N2TMS

24

GPIO47/SCL4/N2TCK

28

GPIO53/SDA4/N2TMS

26

GPIO51/TA3/N2TCK

123

GPIO67/N2TMS

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27/PSDAT2

25

GPIO50/PSCLK3/TDO

27

GPIO52/PSDAT3/RDY#

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DIO

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM/1_WIRE

81

GPIO66/G_PWM

66

GPO33/H_PWM/VD1_EN#

104

GPIO80/VD_IN1

110

GPIO82/IOX_LDSH/VD_OUT1

112

GPIO84/IOX_SCLK/VD_OUT2

84

GPIO77/SPI_MISO

83

GPIO76/SPI_MOSI

82

GPIO75/SPI_SCK

79

GPIO2/SPI_CS#

124

GPIO10/LPCPD#

121

GPIO85/GA20

111

GPIO83/SOUT_CR

9

GPIO65/SMI#

8

GPIO11/CLKRUN#

30

GPIO55/CLKOUT/IOX_DIN_DIO

NPCE985PB 1DX-GP-U

071.00985.000G

KBC_ON#_GATE_ L

R2489

330KR2J-L 1-GP

PSL_IN2#

PSL_IN1#

!!Notice:

VCC1D8

KBSOUT0/GPOB0/SOUT_CR/JENK#

3D3V_AUX_S5

R2491

330KR2J-L 1-GP

1 2

KBSIN1/GPIOA1/N2TMS

KBSOUT4/GPOB4/JEN0#

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GPIO63/TRIST#

KBSOUT14/GPIO62/XORTR# KBSOUT15/GPIO61/XOR_OUT

1.8V Only

PSL_IN2#/GPI6/EXT_PURST#

GPIO87/CIRRXM/SIN_CR

R2492

1 2

20KR2J-L2 -GP

KBSIN0/GPIOA0/N2TCK

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS KBSOUT3/GPIOB3/TDI

KBSOUT5/GPIOB5/TDO

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

GPIO60/KBSOUT16 GPIO57/KBSOUT17

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4

LCLK/GPIOF5 LFRAME#/GPIOF6 LRESET#/GPIOF7

GPIO30/F_WP# GPIO41/F_WP#

GPIO81/F_WP#

GPIO0/EXTCLK

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

SERIRQ/GPIOF0

GPIO36/TB3

GPIO44/TDI

GPIO43/TMS

GPIO42/TCK

GPIO46/CIRRXM/TRST#

GPIO34/CIRRXL

KBC_ON#_GATE

F_CS0# F_SCK

F_SDO

F_SDI

VSBY VBKUP VCORF

PECI

GPIO24

GND

AGND

Q2404

DMP2130L-7 -GP

84.02130.031

2ND = 84.03413.A31

3V_EN

54 55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

1.8V

90

1.8V

92 109 80

1.8V

87

1.8V

86

1.8V

91 77

73 93 74

29 85 122

75 114 44 13

3.3V

125 6 15

21

1.8V

20 17 23

113 14

5 18 45 78 89 116

103

C2442

C2442 SCD1U16V2K X-3GP

SCD1U16V2K X-3GP

1 2

G

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 TP_EN#

LPC_AD_CPU _P0 LPC_AD_CPU _P1 LPC_AD_CPU _P2 LPC_AD_CPU _P3 LPC_CLK_ KBC LPC_FRAME#_C PU PLT_RST#

EC_SPI_CS0 #

CAP_LED# PBAT_PRES#

EC_SPI_MISO PMIC_THERMTRIP#_ KBC SUSCLK

20150818

PSL_IN1# PSL_IN2# PSL_OUT#

TP_DISABLE#_R ECRST# H_RCIN#

KBC_VBKUP KBC_VCORF KBC_PECI INT_SERIRQ_KB C RTC_DET# RSMRST#_KBC

PM_SLP_S4#

SIO_EXT_SCI# TOUCH_PANEL _EN

AC_PRESENT_K BC S5_ENABLE

3D3V_AUX_S5

S

G

D

75.27002.F7C

2N7002KD W-1-GP

2N7002KD W-1-GP Q2403

Q2403

6

R2416 3 3R2J- 2-GPR24 16 33R2J-2-GP

1 2

R2418 3 3R2J- 2-GPR24 18 33R2J-2-GP

1 2

R2401 3 3R2J- 2-GPR24 01 33R2J-2-GP

1 2

R2412 0 R2J-2 -GP

PTP

C2443 SC1U10V2KX-1GPC2443 SC1U10V2KX-1GP

1 2

1

TP2407 TPAD1 4-OP-GPTP2407 TPAD14-OP-GP

R2506

1 2

R2507

0R0402-PAD -2-GP

1 2

EC_AGND

3D3V_AUX_KBC

S5_ENABLE

KBC_ON#_GATE

2345

1

0R2J-2-GP

S5_ENABLE

1 2

R2494

12

3V_EN

H_RCIN#

DY

PTP_DIS#

0R0402-PAD -2-GP

SRN10KJ-5- GP

PMIC_PWRGD

SYS_PWROK

PURE_HW_S HUTDOW N#

R2400

R2400 10KR2J-3-GP

10KR2J-3-GP

SPI_CS_ROM_N 0_R SPI_CLK_ROMEC_SPI_CLK

SPI_SI_ROMEC_SPI_MOSI

3D3V_AUX_S5

eDP_VDDEN_ CPULVDS_VDD_EN_ KBC

3D3V_AUX_KBC

RN2406

2 3 1

4

EC2401 AZ572 5-01FD R7G-GP

EC2402 AZ572 5-01FD R7G-GP

EC2403 AZ572 5-01FD R7G-GP

DY

3D3V_S0

12

RTC_AUX_S5

1 2

DY

PMIC_THERMTRIP# [1 8,50]

0R0402-PAD -2-GP

1 2

DY

2

R2501

1 2

0R0402-PAD -2-GP

Set as 1.8V pull-high at p.16

GPIO23 is 1.8V??

SIO_EXT_SMI#

R2503

1 2

0R0402-PAD -2-GP

Set as 1.8V

R2425

R2440

R2440 100KR2J-1 -GP

100KR2J-1 -GP

1 2

KBC RESET

3D3V_AUX_S5

12

PURE_HW_S HUTDOW N#[26,40]

R2405

10KR2J-3-GP

SOC_RUNTIME_ SCI#SIO_EXT_SCI#

EC_SMI#

10KR2J-3-GP

(1D8V_S5)

pull-high at p.16 (1D8V_S5)

D2401

D2401 RB751V-40H -GP

RB751V-40H -GP

K A

DY

83.R2004.G8F

1D8V_S5

12

R2421

DY

12

R2419

1KR2J-1-GP

DY

R2404

R2404 0R2J-2-GP

0R2J-2-GP

1 2

DY

TOUCH_PANEL _ENLID_CLOSE#

INT_SERIRQ_OE SERIRQ

B

SCD1U16V2K X-3GP

E

Q2401

LMBT3906LT1G -1-GP

C

84.T3906.E11

3D3V_S5

C2445

Set as 3.3V

12

DY

6 5 4

R2508 0 R040 2-PAD-2-G PR2 508 0R0402-PAD-2-G P

ECRST#

12

C2444

SC1U10V2KX-1GP

DY

R2505

20150116 2040Change symbol part number, because origin symbol is DELL OBS part

IRQ_SERIRQ:33MHz

U2404

VCCB OE

DY

B

G2129TL1U -GP

73.02129.02J

VCCB> VCCA

1 2

VCCA

GND

1

AC_PRESENTAC_PRESE NT_KBC

0R0402-PAD -2-GP

pull-high at p.18 (3D3V_S5)

1D8V_S5

C2446

SCD1U16V2KX-3GPDYC2446

SCD1U16V2KX-3GP

12

DY

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

DY

1 2

INT_SERIRQ_KB C

3

A

12

C2401

SC22P50V2JN-4GP

DY

DIS L

A A

Wistron Corporation

21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih ,

21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih , Taipei Hsi en 221 , Taiwan , R.O.C.

Taipei Hsi en 221 , Taiwan , R.O.C.

Title

EC - MEC5085

Size Docu men t Num ber Rev

A0

Turis APL UMA

Date: Sheet of

5

4

3

2

Date: Sheet of

1

24 106Monday, August 29 , 2016

X02

Vinaﬁx.com

5

SSID = Flash.ROM

4

3

2

1

A00_0824

Remove SKT251

SPI_CS_CPU_N0[19]

SPI_SO_ROM[19]

SPI_WP_ROM[19]

D D

SPI_HOLD_ROM[19]

SPI_CLK_ROM_CPU[19]

SPI_SI_ROM_CPU[19]

12

R2532

R2532 4K7R2J-2-GP

EC2502

4K7R2J-2-GP

SPI_CS_ROM_N0_R 1 SPI_SO_ROM_R1 SPI_WP_ROM_R

12

DY

SPI_CLK_ROM[24]

SPI_SI_ROM[24]

EC_SPI_MISO[24]

SPI_CS_ROM_N0_R[24]

1D8V_S5

SPI_CS_CPU_N0

R2531 0R0402-PAD-2- GPR2531 0R0402-PAD-2-G P

SPI_SO_ROM SPI_HOLD_ROM SPI_WP_ROM

R25333K3R 2J-3-GP R25333K3R 2J-3-GP

12

SPI_HOLD_ROM

R25343K3R 2J-3-GP R25343K3R 2J-3-GP

12

1 2

R2510 0R0402-PAD-2- GPR2510 0R0402-PAD-2-G P

1 2

R2514 0R0402-PAD-2- GPR2514 0R0402-PAD-2-G P

1 2

SC4D7P50V2BN- GP

SPI_WP_ROM

SC4D7P50V2BN- GP

X01_0531

SPI251

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25Q128FW SIQ-GP

072.25128.0I01

HOLD#/RESET#/IO3

DI/IO0

VCC

CLK

SPI_VCC_1D8V

8

SPI_HOLD_ROM_R

7

SPI_CLK_ROM_R1

6

SPI_SI_ROM_R1

5

12

DY

EC2501

SC4D7P50V2BN-GP

X01_0518

C C

X01_0602

Remove Share Rom

EC_SPI_MISO

SPI Flash ROM(16M) P/N: 072.25128.0I01 2nd P/N: 072.25128.0S01

SPI_VCC_1D8V

12

SC10U6D3V2MX- 3-GP

1D8V_S51D8V_S5

R2529

R2529 0R0402-PAD-2- GP

0R0402-PAD-2- GP

1 2

R2517 0R0402-PAD-2- GPR2517 0R0402-PAD-2-G P

1 2

R2502 33R2J-2-GPR2502 33R2J-2-GP

1 2

R2513

1 2

12

EC2503

DY

SC10P50V2JN-4G P

12

R2522

R2522 4K7R2J-2-GP

4K7R2J-2-GP

R2528

1 2

0R0402-PAD-2- GP

EC2506

SC4D7P50V2BN- GP

C2501

0R0402-PAD-2- GP

1D8V_S5 1D8V_S5

12

R2535

R2535 4K7R2J-2-GP

4K7R2J-2-GP

SPI_CS_ROM_N0_R SPI1_SO_ROM_R SPI1_WP_ROM_R

12

DY

12

DY

SPI_CLK_ROM_CPU SPI_SI_ROM_CPU

SPI FLASH ROM(128k byte) for KBC

C2502

C2502 SCD1U16V2KX- 3GP

SCD1U16V2KX- 3GP

SPI252

1

CS#

2

SO/SIO1

3

WP#/SIO2

4

GND

MX25U1001EMI-14G-GP

072.25101.0001

X01_0602

HOLD#/SIO3

SI/SIO0

SCLK

SPI1_VCC_1D8V

R2523

1 2

EC2505

EC2505 SC10P50V2JN-4G P

SC10P50V2JN-4G P

R2523 4K7R2J-2-GP

4K7R2J-2-GP

R2530

0R0402-PAD-2- GP

SPI1_VCC_1D8V

8

VCC

SPI1_HOLD_ROM_R

7

SPI_CLK_ROM

6

SPI_SI_ROM

5

1 2

12

DY

EC2504

SC4D7P50V2BN-GP

C2504

SCD1U16V2KX-3GPDYC2504

SCD1U16V2KX-3GP

C2503

SC10U6D3V2MX-3-GPDYC2503

SC10U6D3V2MX-3-GP

12

DY

SSID = RTC

B B

RTC_DET# [24]

RTC_AUX_S5

A A

5

4

R2515

R2515 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2501

3

BAS40C-2-GP

75.00040.07D

10MR2J-L-GP

2

1

R2516

RTC_DET#_ G

12

3D3V_AUX_S5

12

DY

R2518

R2518 0R2J-2-GP

0R2J-2-GP

R2527

1 2

1KR2J-1-GP

Width=20mils

Q2502

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

3

+RTC_PW R

1

AFTP2501AFTP2501

D

AFTP2502AFTP2502

RTC_DET#

RTC1

1 2

NP1

1

NP2

BAT-40-42010-00211 RHF-GP-U2

20.F2316.002

PWR GND NP1 NP2

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Flash/RTC

Turis APL UMA

1

X02

25 106Thursday, Augu st 25, 2016

X02

Vinaﬁx.com

5

4

3

2

1

SSID = Thermal

3D3V_S0

D D

EE Note:

1. T8: PURE_HW_SHUTDOWN# throu gh Q2603.

2. THM_SENSOR: Thermal sensor NCT7718W solution.

3D3V_S0

Thermal sensor NCT 7718W

12

C2602

C2601

SYS_PWROK[20, 24]

PMIC_PWRG D[2 0,24,50]

PURE_HW _SHUTDOW N#[24,40]

SMB_CLK_CPU[24]

SMB_DATA_CPU[24]

KBC T8

VD_OUT1#[24]

C C

VD_IN1[24 ]

C

DY

Q2604

E

LMBT3904LT1G-GP

84.T3904.H11

1.Q2604 (Remote for KB Skin ,TOP SIDE Reserved)

2.U2601 (OTP Sensor ,Bottom SIDE)

3.R2610 (Thermistorr for KB Skin ,TOP SIDE)

4.Q2601(Bot remote for skin)

5.THM262(Bot remote GPU)

ALERT#

T_CRIT#

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C

B

T8

Q2601

E

LMBT3904LT1G-GP

84.T3904.H11

R5

R2605 18K7R2F-GP

T8

R7

R2606 2KR2F-3-GP

T8

P2800_DXP

C2603

SC470P50V2KX-3GPDYC2603

SC470P50V2KX-3GP

12

DY

12

P2800_DXN

3D3V_S0

12

C2604

SC2200P50V2KX-2GP

T8

C2601

T8

12

R2601

R2601 0R2J-2-GP

0R2J-2-GP

T8

SYS_PWROK

PMIC_PWRG D

SCD1U16V2KX-3GP

T_CRIT#

T8

SC10U6D3V3MX-GP

1.H/W T8 Shutdown

U2601

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W -GP

74.07718.0B9

THERM_SYS_SHD N#

12

DY

12

DY

R2609 0R2J-2-GP

T8

R26070R2J-2-GP

ALERT#

SDA

ALERT#

6 5

NCT_CLK

8

SCL

NCT_DATA

7

Thermal sensor NCT 7718W

S

SYS_PWROK_G

G

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

X02_0727

Q2602

DY

X02_0727

D

NCT_CLK

NCT_DATA

RN2601

SRN2K2J-1-G P

12

DY

1

23

T8

4

C2605

SCD1U16V2KX- 3GP

3D3V_S0

Q2603

1

2

T8

3 4

2N7002KDW -1-GP

75.27002.F7C

PURE_HW _SHUTDOW N#

Note:ZZ.27002.F7C01

SMB_CLK_CPU

6

5

pull-high at p.24 (3D3V_S5)

SMB_DATA_CPU

R2603

R2603 0R0402-PAD-2- GP

0R0402-PAD-2- GP

VD_OUT1#

VD_IN1

2

KBC T8

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, August 30 , 2016

Tuesday, August 30 , 2016 Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

THERMAL & FAN

Turis APL UMA

1

26 106

X02

R2611

1 2

0R0402-PAD-2- GP

12

3D3V_AUX_KBC

THERM_SYS_SHD N#

Close to Thermal sensor

3D3V_AUX_KBC3D3V_AUX_S5

R2612

24K9R2F-L-GP

R2610

R2610 NTC-100K-8- GP

NTC-100K-8- GP

69.60035.041

12

T8_KBC

12

T8_KBC

R2608

24K9R2F-L-GP

12

DY

B B

A A

5

4

DY

3

DY

R2613 2KR2J-1-GP

1 2

DY

R2602 0R2J-2-GP

1 2

12

C2606

T8_KBC

SCD1U16V2KX- 3GP

VD_IN1_C

EE Note: R2608 need to fine tune base on thermal test.

Close to KBC VD_IN1 for system thermal sensor

12

C2607

T8_KBC

SC100P50V2JN-3 GP

Vinaﬁx.com

SSID = AUDIO

5

4

3

2

1

LINE1_VREFO_R[29]

LINE1_VREFO_L[29]

AUD_HP1_JACK_L[29]

AUD_HP1_JACK_R[29]

MIC2_VREFO[29]

D D

C C

LINE1_L[29]

LINE1_R[29]

AUD_SENSE[29]

SLEEVE[29]

RING2[29]

HDA_SPKR[21]

BEEP[24]

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

EC_MUTE#[24]

DMIC_DATA[55]

DMIC_CLK[55]

HDA_CODEC_SDOUT[21]

HDA_CODEC_BITCLK[21]

HDA_SDIN0_CPU[21]

HDA_CODEC_SDIN0[21]

HDA_CODEC_SYNC[21]

DC_DET[29]

3D3V_S0

R2708

1 2

0R0805-PAD-2-GP-U

25mA

1D8V_S0

R2705

1 2

0R0402-PAD-2-GP

1D8V_S0

R2724

AVDD2: +1.8VD@3246 +1.5VD@3234 (Iris BSW use 1D8 V_S0)

+3V_AVDD

C2714

12

SCD1U16V2KX-3GP

moat

1 2

0R0402-PAD-2-GP

CPVDD

12

C2701

SC4D7U6D3V3KX-GP

Close pin36

Azalia I/F EMI

HDA_CODEC_BITCLK

EC2708

12

SC22P50V2JN-4GP

DY

HDA-Link Power: APL is 1.8V

1D8V_S0

+3V_1D5V_AVDD

Speaker trace width >40mil @ 2W4ohm speaker power

12

C2721

C2715

Close pin40

AUD_AGND

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

DMIC_DATA

EC2709

EC2709 SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

1 2

R2729

1 2

0R0402-PAD-2-GP

+3V_AVDD

+3.3V_1.8V_DVDD-IO

Close pin9

C2723

SC10U6D3V3MX-GP

1 2

AUD_AGND

Layout Note:

R2706

1 2

DY

0R2J-2-GP

SC22P50V2JN-4GP

Close pin3

C2722

#560733

DMIC_DATA

DMIC_CLK

DY

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

R2722

1 2

0R0402-PAD-2-GP

X02_0718

1 2

Audio Codec Chip ALC3246

LINE1_VREFO_R

LINE1_VREFO_L

AUD_HP1_JACK_L

AUD_HP1_JACK_R

C2704

1 2

SC1U10V2KX-1GP

12

CPVDD

C2703

C2703 SC1U10V2KX-1GP

+3V_1D5V_AVDD

+5V_PVDD

TP2701

1

TPAD14-OP-GP

LDO2_CAP

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

PD#EC_MUTE#

COMBO-GPI

SC4D7U6D3V3KX-GP

DC_DET HDA_CODEC_SDOUT

HDA_CODEC_BITCLK

HDA_SDIN0_CPU

22R2J-2-GP

HDA_CODEC_SDIN0

HDA_CODEC_SYNC

SC1U10V2KX-1GP

CBP

C2716

R270922R2J-2-GP R270922R2J-2-GP

1 2

R272322R2J-2-GP R272322R2J-2-GP

1 2

37

38

39

40

41

42

43

44

45

46

47

48

49

+3V_AVDD

R2721

1 2

CPVEE

CBN

32

33

34

35

36

HDA27

CBN

CPVEE

CPVDD

CBP

AVSS2

LDO2-CA P

AVDD2

PVDD1

SPK-OUT-L +

SPK-OUT-L -

SPK-OUT-R -

SPK-OUT-R +

PVDD2

PDB

SPDIF-O UT/GPIO2 /DMIC-DAT A34/DMI C-CLK-IN

GND

ALC3246-CG-GP-U

12

DMIC_DATA_R

DMIC_CLK_R

HPOUT-L_PORT-I-L

HPOUT-R_PORT-I-R

071.03246.0003

(71.03234.003)

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3DC_DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10I2C-DATA11I2C-CLK

DVSS

12

C2717

12

0R2J-2-GP

DY

R2707

SCD1U16V2KX-3GP

HDA_CODEC_SDIN0

C2705

12

SC2D2U10V3KX-1GP

AUD_VREF

28

29

30

31

VREF

MIC2-VREFO

LINE1-VREFO-L

LINE1-VREFO-R

MIC2-R_P ORT-F-R/S LEEVE

MIC2-L_P ORT-F-L/R ING2

SPDIFO /FRONT-JD _JD3/G PIO3

HDA-Link Power

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

+3.3V_1.8V_DVDD-IO

12

MIC2_VREFO

12

C2702

SC4D7U6D3V3KX-GP

LDO1_CAP

25

26

27

AVSS1

AVDD1

LDO1-CAP LINE2-L_ PORT-E-L

LINE2-R_ PORT-E-R

LINE1-L_ PORT-C-L

LINE1-R_ PORT-C-R

VD33ST B

MIC2-CAP

PCBEEP

MIC2/LINE 2-JD_JD 2

HP/LINE1-J D_JD1

12

RESETB@3234

PCBEEP@3234

R2713

R2713 100KR2J-1-GP

100KR2J-1-GP

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

LINE1_L

LINE1_R

V3D3_STB

MIC_CAP

SLEEVE

RING2

AUD_PC_BEEP_3246

JDREF

AUD_SENSE_A

R2720

C2710

0R0603-PAD-2-GP-U

12

C2711

Layout Note:

Place close to Pin 26

SCD1U16V2KX-3GP

AUD_AGND

SC4D7U6D3V3KX-GP

moat

R2710 0R0402-PAD-2-GPR2710 0R0402-PAD-2-GP

1 2

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

1 2

R2714 20KR2F-L-GP

1 2

DY

AUD_SENSE

1 2

R2715

200KR2F-L-GP

Layout Note:

Place close to Pin 13

moat

HDA_SPKR

R2718 0R0402-PAD-2-GPR2718 0R0402-PAD-2-GP

BEEP

R2730 1KR2J-1-GPR2730 1KR2J-1-GP

moat

1 2

1 2 1 2

AUD_AGND

R2719

1 2

0R0402-PAD-2-GP

AUD_AGND

X01_0526

moat

EC2706 SC1KP50V2KX-1GPEC2706 SC1KP50V2KX-1GP

1 2

EC2705 SC1KP50V2KX-1GPEC2705 SC1KP50V2KX-1GP

1 2

EC2704 SC1KP50V2KX-1GPEC2704 SC1KP50V2KX-1GP

1 2

EC2703 SC1KP50V2KX-1GPEC2703 SC1KP50V2KX-1GP

1 2

EC2702 SC1KP50V2KX-1GPEC2702 SC1KP50V2KX-1GP

5V_S0+5V_AVDD

3D3V_S5

Layout Note:

AUD_PC_BEEP_R

HDA_SPKR_R

KBC_BEEP_R

1 2

AUD_AGND

1 2

R2727 0R0603-PAD-2-GP-UR2727 0R0603-PAD-2-GP-U

1 2

R2725 0R0603-PAD-2-GP-UR2725 0R0603-PAD-2-GP-U

1 2

R2728 0R0603-PAD-2-GP-UR2728 0R0603-PAD-2-GP-U

Layout Note:

AUD_AGND

Tied at point only under Codec or near the Codec

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

moat

D2701

2

AUD_PC_BEEP_C

3

1

BAT54C-7-F-3-GP

75.00054.E7D

2nd = 83.R2003.W81

3rd = 75.00054.A7D

4th = 83.R2003.V81

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

C2720

AUD_PC_BEEP_R

1 2

SCD1U16V2KX-3GP

12

R2717

2K2R2J-2-GP

R2711

100KR2J-1-GP

+3V_AVDD

12

X02_0718

5V_S0+5V_PVDD

5V_S0_SIP

2.5A

NON_HWDP

R2712 0R5J-5-GP

12

R2716 0R5J-5-GP

12

NON_HWDP

HWDP

Q2701

G

DMN3404L-7-1-GP

084.03404.0A31

DS

HWDP

19V_DCBATOUT

12

R2726

R2726 100KR2J-1-GP

100KR2J-1-GP

SD_AMP# [29]

Title

Audio Codec ALC3234

Size Document Number Rev

A1

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Turis APL UMA

X02

27 106Thursday, August 25, 2016

B B

5V_S0

12

R2733

R2733 100KR2J-1-GP

100KR2J-1-GP

DY

DC_DET

A A

5

4

3

Layout Note:

Close pin41

Layout Note:

Close pin46

+5V_PVDD

L2701 ACMS160808A121RDC05-GP

1 2

C2707

SC10U6D3V3MX-GP

C2707

SC10U6D3V3MX-GP

C2706

SCD1U16V2KX-3GP

C2706

SCD1U16V2KX-3GP

12

C2709

SC10U6D3V3MX-GP

C2709

SC10U6D3V3MX-GP

C2708

SCD1U16V2KX-3GP

C2708

SCD1U16V2KX-3GP

12

2

HWDP

C2728

SCD1U16V2KX-3GP

C2728

SCD1U16V2KX-3GP

C2729

SC10U6D3V3MX-GP

C2729

SC10U6D3V3MX-GP

12

HWDP

Vinaﬁx.com

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Turis APL UMA

28 106Wednesday, July 27, 2016

1

X02

Vinaﬁx.com

5

4

3

2

1

SSID = AUDIO

AUD_SPK_R+[27] AUD_SPK_R-[27] AUD_SPK_L+[27] AUD_SPK_L-[27]

RING2_R[66]

AUD_PORTA_L_R_B[66]

JACK_PLUG[66]

AUD_PORTA_R_R_B[66]

SLEEVE_R[66]

MIC2_VREFO[27]

D D

RING2[27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_VREFO_L[27]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

SLEEVE[27]

AUD_SENSE[27]

DC_DET[27]

SD_AMP#[27]

X02_0718

AUD_SPK_R+

AUD_SPK_R-

R2915 8K2R2J-L-2-GP

1 2

HWDP

R2916 8K2R2J-L-2-GP

1 2

HWDP

B

R2927

1 2

DY

SD_AMP

C

E

MMBT3906-4-GP

MMBT3906-4-GP Q2907

Q2907

1KR2J-1-GP

5V_S0

HWDP

12

R2928

10KR2F-2-GP

HWDP

R2929

1 2

1KR2J-1-GP

DC_DET

HWDP

B

SD_AMP#

C

Q2908

Q2908 LMBT3904LT1G-GP

LMBT3904LT1G-GP

84.T3904.H11

E

2nd = 84.T3904.K11

3rd = 84.T3904.C11

84.T3904.H11

AUD_SPK_R+_R

C2907

SC1KP50V2KX-1GP

C2907

SC1KP50V2KX-1GP

C2906

12

HWDP

AUD_SPK_R-_R

SC10U6D3V3MX-GP

C2905

SC1KP50V2KX-1GP

C2905

SC1KP50V2KX-1GP

12

R2930

R2930 22KR2J-GP

22KR2J-GP

HWDP

AUD_SPK_L+

R2922 8K2R2J-L-2-GP

1 2

HWDP

AUD_SPK_L- AUD_SPK_L-_R

R2923 8K2R2J-L-2-GP

1 2

HWDP

LMBT3904LT1G-GP

HWDP

C2908

12

Q2902

HWDP

SC10U6D3V3MX-GP

C2910

SC1KP50V2KX-1GP

84.T3904.H11

2nd = 84.T3904.K11

C

B

3rd = 84.T3904.C11

E

AUD_SPK_L+_R

HWDP

LMBT3904LT1G-GP

C2909

SC1KP50V2KX-1GP

C2909

SC1KP50V2KX-1GP

12

HWDP

Q2903

B

HWDP

C

84.T3904.H11

2nd = 84.T3904.K11

E

3rd = 84.T3904.C11

12

R2921

R2921 22KR2J-GP

22KR2J-GP

PRO_SP

LMBT3904LT1G-GP

Q2905

B

84.T3904.H11

2nd = 84.T3904.K11

C

3rd = 84.T3904.C11

E

2nd = 84.T3904.K11

HWDP

3rd = 84.T3904.C11

LMBT3904LT1G-GP

84.T3904.H11

R2926

1 2

HWDP

10KR2F-2-GP

12

R2924

10KR2F-2-GP

HWDP

Q2904

C

B

E

HWDP

12

DY

INT_SPK_1

C

DY

E

R2925

10KR2F-2-GP

Q2906

Q2906 LMBT3904LT1G-GP

LMBT3904LT1G-GP

B

84.T3904.H11

2nd = 84.T3904.K11

3rd = 84.T3904.C11

84.T3906.A11

2nd = 84.03906.F11

3rd = 84.T3906.E11

INT_SPK_R

SD_AMP_R

C C

AUD_SPK_R+

AUD_SPK_RAUD_SPK_L+

X01_0526

12

R2904 0R0603-PAD-2-GP-UR2904 0R0603-PAD-2-GP-U

12

R2903 0R0603-PAD-2-GP-UR2903 0R0603-PAD-2-GP-U

12

R2902 0R0603-PAD-2-GP-UR2902 0R0603-PAD-2-GP-U

12

R2901 0R0603-PAD-2-GP-UR2901 0R0603-PAD-2-GP-U

Bead 120ohm

EC2902

SC1KP50V2KX-1GP

EC2902

SC1KP50V2KX-1GP

EC2903

SC1KP50V2KX-1GP

EC2903

SC1KP50V2KX-1GP

EC2904

SC1KP50V2KX-1GP

EC2904

EC2901

SC1KP50V2KX-1GP

EC2901

SC1KP50V2KX-1GP

12

SC1KP50V2KX-1GP

12

AUD_SPK_R+_C

AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_CAUD_SPK_L-

Speaker

SPK1

5

1

2 3 4

6

ACES-CON4-29-GP

20.F1639.004

2nd = 20.F1804.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C AUD_SPK_R+_C

CONN Pin

Net name

SPK_R+

Pin1

SPK_R-

Pin2

SPK_L+

Pin3

Pin4

SPK_L_

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

Combo Jack

AUD_AGND AUD_SENSE

RN2901

1

B B

A A

5

X02_0718

C2903

SC10U6D3V3MX-GP

LINE1_R LINE1-L_R

C2904

SC10U6D3V3MX-GP

LINE1-L_CLINE1_L

R2920 1KR2J-1-GPR2920 1KR2J-1-GP

1 2

R2919 1KR2J-1-GPR2919 1KR2J-1-GP

1 2

4

MIC2_VREFO

RING2

SLEEVE

AUD_HP1_JACK_L LINE1_VREFO_L

AUD_HP1_JACK_R LINE1_VREFO_R

4

2 3

SRN2K2J-1-GP

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

R2918

10KR2J-3-GPDYR2918

10KR2J-3-GP

12

DY

3

EC2908

SC100P50V2JN-3GP

EC2908

SC100P50V2JN-3GP

EC2907

SC100P50V2JN-3GP

EC2907

SC100P50V2JN-3GP

R2917

10KR2J-3-GPDYR2917

10KR2J-3-GP

12

DY

Delay circuit

(JACK_PLUG_DET: on IO Board)

EC2906

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

12

EC2905

SC100P50V2JN-3GP

EC2905

SC100P50V2JN-3GP

12

AUD_AGNDAUD_AGND

R2906 0R0603-PAD-2-GP-UR2906 0R0603-PAD-2-GP-U

1 2

R2907 0R0603-PAD-2-GP-UR2907 0R0603-PAD-2-GP-U

1 2

R2909 0R0603-PAD-2-GP-UR2909 0R0603-PAD-2-GP-U

1 2

R2911 0R0603-PAD-2-GP-UR2911 0R0603-PAD-2-GP-U

1 2

R2914 0R0603-PAD-2-GP-UR2914 0R0603-PAD-2-GP-U

1 2

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B SLEEVE_R

DY

AUD_AGND

12

C2901

C2901 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

AFTP2908AFTP2908

1

AFTP2909AFTP2909

1

10 mils10 mils

AUD_SENSEJACK_PLUG

Title

Size Document Number Rev

A1

Date: Sheet of

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Speaker/HPMIC JACK

Turis APL UMA

X02

29 106Thursday, August 25, 2016

Vinaﬁx.com

5

4

3

2

1

Main Func = LAN

D D

C C

Blanking

B B

Wistron Corporation

A A

Title

LAN RTL8106

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

LAN RTL8106

A4

2

Turis APL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

X02

30 106Wednesday, July 27, 2016

1

Dell Inspiron 14 3462 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual