Dell 3150 Schematic

Vinaﬁx.com

5

D D

4

3

2

1

Starload Schematics

Skylake-U

C C

2016-02-18 REV : A00

B B

DY : None Installed

A A

UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Thursday, February 18, 20 16

Date: Sheet of

Cover Page

Starload SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

1 106

1

A00

Vinaﬁx.com

5

Project code: 4PD07S010001 PCB P/N: 15264

Star lord SKL-U Block Diagram

Revision: A00

D D

GPU

VRAM(GDDR5) *4

2GB/4GB

GDDR5

GPU BOARD

HDMI

70

5

57

55

34

35

7mm HDD

I2C

LPC debug port

MEC1404-NU-GP

Int. KB

KB transfer board

USB PowerShare

TI TPS2544RTER

SMSC

HDMI V1.4

13.3"/15.6"/17.3" (HD/FHD/UHD)

Touch panel

C C

USB3.0 Port2

Power share

USB3.0 Port3

ROR only

INT2

B B

Sensor BD on Panel side

Thermal

NUVOTON NCT7718W

Free fall Gsensor

ST LNG2DMTR

G + E-compass

ST LSM303DTR

Gyro

ST L3GD20TR

SMBUS

26

Fan Control

A A

PWM

FAN

NVDIA N16S-GTR 25W

HDMI Level Shifter

USB2.0

USB3.0

USB2.0

USB3.0

USB2.0

Sensor Hub

ST STM32L151CBU6TR

68

69

LPC BUS

KBC

24

PS2

Touch PAD

Image sensor

57

4

PCIE x 4

PCIE Lane1~Lane4

HDMI

eDP

USB2.0 LANE7

USB3.0 LANE1

USB2.0 LANE1

USB3.0 LANE3

USB2.0 LANE2

SATA

USB2.0 LANE9

USB2.0

I2C

SPI

4

Flash ROM

I2C

Intel CPU

Skylake U

28W (UMA only)

SKL PCH-LP

10 USB 2.0/1.1 ports

6 USB 3.0 ports

High Definition Audio

3 SATA ports

6 PCIE ports

LPC I/F

ACPI 5.0

16MB Quad Read

2526

Channel A

Channel B

DP

USB3.0

USB3.0 LANE4

USB2.0

USB2.0 LANE4

USB2.0 LANE8

PCIE LANE5

USB2.0 LANE6

USB2.0

USB2.0 x 1

USB2.0 LANE5

HDA

3

MUX and Redriver

SATA

USB2.0 x 1

USB2.0 LANE3

3

PARADE PS8740B

PCIe

USB2.0

38

CC

38

M.2 SSD

CardReader SD 3.0

Realtak RTS5176E

USB2.0 Port4

Camera (HD/IR)

D-MIC

HDA CODEC

Realtek ALC3253

DP/USB 3.0

USB2.0

63

NGFF WLAN

55

2CH SPEAKER (2CH 2W/4ohm)

27

MIC_IN/GND

HP_R/L

2

DDR4

SODIMM A

DDR4

SODIMM B

USB3.0 type c Port1

BBY only

SD Card Slot

IO Board

2

12

13

38

Universal Jack

1

CHARGER

ISL95521HRZ-T

INPUTS

AD+

BT+

SYSTEM DC/DC

SY8288CRAC-GP

INPUTS

DCBATOUT

CPU Core Power

NCP81208MNTXG-G P NCP81382MNTXG-1 -GP NCP81382MNTXG-1 -GP NCP81253MNTBG-G P

INPUTS

DCBATOUT

DCBATOUT +VCCGT

OUTPUTS

DCBATOUT

OUTPUTS

PWR_5V 5V_S5 5V_AUX_S5

OUTPUTS

VCC_CORE

+VCCSA_VRDCBATOUT

46~50

DDR4

SY8288RAC-GP APL5338XAI-TRG- GP

INPUTS OUTPUTS

DCBATOUT

CPU DCDC-V1D00A

AOZ1268QI-02-GP

INPUTS OUTPUTS

DCBATOUT

LDO-V1D5V

S-1339D15-M5001 -GP

3D3V_S5

LDO-V1D8V

APL5930KAI-TRG- GP

INPUTS OUTPUTS

3D3V_S5

G5016KD1U

INPUTS

5V_S5

M5938ARD1U-GP-U

INPUTS

1D0V_S5

TPS22965DSGR-GP -U

INPUTS

1D0V_S5

SYSTEM DC/DC

TPS51225RUKR-GP

INPUTS

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Starload SKL-U

1

1D2V_S3

0D675V_S0

1D0V_S5

OUTPUTSINPUTS

1D5V_S0

1D8V_S5

5V/3V S0

VCCSTG

OUTPUTS

+VCCSTG

VCCST

OUTPUTS

+V1.00U_CPU

OUTPUTS

3D3V_AUX_S5 3D3V_S5 PWR_3D3V

2 106Thursday, February 18, 2016

OUTPUTS

5V_S0

3D3V_S03D3V_S5

44

45

33

51

52

54

40

45

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

A3

(Reserved)

Starload SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

3 106Thursday, February 18, 20 16

1

A00

Vinaﬁx.com

5

Main Func = CPU

+VCCSTG

D D

[PECI] and [PRO CHOT#] Impedance contr ol: 50 ohm

H_PECI[24]

H_PROCH OT#[2 4,44,46]

TOUCH_P ANEL_INTR#[24 ,55]

3D3V_S5 _PCH

R404

1 2

DY

100KR2J -1-GP

3D3V_S0

R405

1 2

DS3

C C

INT_TP#[24,65]

DS3

100KR2J -1-GP

R410

1 2

NON DS3

0R2J-2-GP

D401

DS3

RB751V-4 0H-GP

K A

83.R2004.G8F

Rb

+VCCSTG = 1.0 V +VCCSTG = 1.0 V

12

R401

R401 1KR2J-1-G P

1KR2J-1-G P

TPAD14-O P-GP

R403499R2F-2 -GP R403499R2F-2 -GP

1 2

Ra

TPAD14-O P-GP

TP405

TPAD14-O P-GP

TPAD14-O P-GP TPAD14-O P-GP

TPAD14-O P-GP

TP405 TP406

TP406 TP407

TP407 TP408

TP408

TP403

TOUCHPA D_INTR#

TP404

Add resistor by NON DS3 function

TP401

TP402

1

R41249D9R2F -GP R41249D9R2F -GP R41349D9R2F -GP R41349D9R2F -GP R41449D9R2F -GP R41449D9R2F -GP R41549D9R2F -GP R41549D9R2F -GP

4

H_CATER R#

1

H_PROCH OT#_R PCH_THE RMTRIP# SKTOCC#

1

XDP_BPM 0

1

XDP_BPM 1

1

XDP_BPM 2

1

XDP_BPM 3

1

GPP_E3/C PU_GP0

GPP_B4/C PU_GP3

CPU_POP IRCOMP

12

PCH_POP IRCOMP

12

EDRAM_O PIO_RCOMP

12

EOPIO_RCO MP

12

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

CPU MISC

3

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

PCH_THE RMTRIP#

4 OF 20

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

JTAGX

+VCCST_ CPU

12

EC401

AZ5725-01FDR7G-GP

XDP_TCL K XDP_TDI XDP_TDO _CPU XDP_TMS XDP_TRS T#

PCH_JTA G_TCK PCH_JTA G_TDI PCH_JTA G_TDO PCH_JTA G_TMS XDP_TRS T# XDP_TCK _JTAGX

#544669 CRB Rev 0.52

R419

R419 1KR2J-1-G P

1KR2J-1-G P

EMI DVT1 0210

2

XDP_TMS XDP_TDI

XDP_TDO _CPU

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

XDP_TRS T# XDP_TCL K

PCH_JTA G_TCK

1 2

DY

R42151R2J-2-G P

DY

R42151R2J-2-G P R42251R2J-2-G P

R42251R2J-2-G P

R42351R2J-2-G P

R40851R2J-2-G P R 4085 1R2J-2-GP

R40951R2J-2-G P R 4095 1R2J-2-GP

R41651R2J-2-G P R 4165 1R2J-2-GP

R4171KR2J-1-GP

1 2

PH in P.99

1 2

R402 51R2J-2-G P

1 2

R406 51R2J-2-G PR406 51R2J-2-G P

1 2

R407 51R2J-2-G P

1 2

1

+VCCSTG

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 i nches Mt <0.3 mils Main route(M1+M 2+M3+M4+M5+M6+ MCPU): 1-12 inc hes

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(JTAG/CPU SIDE BAND)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Starload SKL-U

1

4 106Thursday, February 25, 20 16

A00

Vinaﬁx.com

Main Func = CPU

5

4

3

2

1

DDR4 ball type: Interleaved Type

D D

CPU1B

M_A_DQ0

M_A_DQ0[12] M_A_DQ1[12] M_A_DQ2[12]

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

B B

M_A_DQ3[12] M_A_DQ4[12] M_A_DQ5[12] M_A_DQ6[12] M_A_DQ7[12] M_A_DQ8[12]

M_A_DQ9[12] M_A_DQ10[12] M_A_DQ11[12] M_A_DQ12[12] M_A_DQ13[12] M_A_DQ14[12] M_A_DQ15[12] M_B_DQ0[13] M_B_DQ1[13] M_B_DQ2[13] M_B_DQ3[13] M_B_DQ4[13] M_B_DQ5[13] M_B_DQ6[13] M_B_DQ7[13] M_B_DQ8[13] M_B_DQ9[13] M_B_DQ10[13] M_B_DQ11[13] M_B_DQ12[13] M_B_DQ13[13] M_B_DQ14[13] M_B_DQ15[13] M_A_DQ16[12] M_A_DQ17[12] M_A_DQ18[12] M_A_DQ19[12] M_A_DQ20[12] M_A_DQ21[12] M_A_DQ22[12] M_A_DQ23[12] M_A_DQ24[12] M_A_DQ25[12] M_A_DQ26[12] M_A_DQ27[12] M_A_DQ28[12] M_A_DQ29[12] M_A_DQ30[12] M_A_DQ31[12] M_B_DQ16[13] M_B_DQ17[13] M_B_DQ18[13] M_B_DQ19[13] M_B_DQ20[13] M_B_DQ21[13] M_B_DQ22[13] M_B_DQ23[13] M_B_DQ24[13] M_B_DQ25[13] M_B_DQ26[13] M_B_DQ27[13] M_B_DQ28[13] M_B_DQ29[13] M_B_DQ30[13] M_B_DQ31[13]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[8]

AF64

DDR1_DQ[1]/DDR0_DQ[9]

AK65

DDR1_DQ[2]/DDR0_DQ[10]

AK64

DDR1_DQ[3]/DDR0_DQ[11]

AF66

DDR1_DQ[4]/DDR0_DQ[12]

AF67

DDR1_DQ[5]/DDR0_DQ[13]

AK67

DDR1_DQ[6]/DDR0_DQ[14]

AK66

DDR1_DQ[7]/DDR0_DQ[15]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-U-GP

SKYLAKE_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

DDR0_DQ[16]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

DDR0_DQ[17]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

DDR0_DQ[18]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_DQ[19]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_DQ[20]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[21]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

DDR0_DQ[22]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_DQ[23]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

071.SKYLA.000U

DDR1_DQSN[0]/DDR0_DQ[2] DDR1_DQSP[0]/DDR0_DQ[2] DDR1_DQSN[1]/DDR0_DQ[3] DDR1_DQSP[1]/DDR0_DQ[3]

PDG: DDR/ODT

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 AH66 AH65 AG69 AG70 BA64 AY64 AY60 BA60 AR66 AR65 AR61 AR60

AW50 AT52

AY67 AY68 BA67

AW67

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_A2

M_A_A10 M_A_A1 M_A_A0 M_A_A3 M_A_A4

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1 M_A_DQS_DP1 M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN1 M_B_DQS_DP1 M_A_DQS_DN2 M_A_DQS_DP2 M_A_DQS_DN3 M_A_DQS_DP3 M_B_DQS_DN2 M_B_DQS_DP2 M_B_DQS_DN3 M_B_DQS_DP3

SM_PGCNTL

M_A_CLK#0 [12] M_A_CLK0 [12] M_A_CLK#1 [12] M_A_CLK1 [12]

M_A_CKE0 [12] M_A_CKE1 [12]

M_A_CS#0 [12] M_A_CS#1 [12] M_A_DIMA_ODT0 [12] M_A_DIMA_ODT1 [12]

M_A_A5 [12] M_A_A9 [12] M_A_A6 [12] M_A_A8 [12]

M_A_A7 [12] M_A_BG0 [12] M_A_A12 [12] M_A_A11 [12] M_A_ACT_N [12] M_A_BG1 [12]

M_A_A13 [12] M_A_A15 [12] M_A_A14 [12] M_A_A16 [12] M_A_BA0 [12]

M_A_A2 [12] M_A_BA1 [12] M_A_A10 [12]

M_A_A1 [12]

M_A_A0 [12]

M_A_A3 [12]

M_A_A4 [12]

M_A_DQS0

M_A_DQS1

M_B_DQS0

M_B_DQS1 M_A_DQS2

M_A_DQS3

M_B_DQS2

M_B_DQS3

M_A_ALERT_N [12] M_A_PARITY [12]

V_SM_VREF_CN TA [12]

V_SM_VREF_CN TB [13]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

SM_PGCNTL

M_A_DQ32[12] M_A_DQ33[12] M_A_DQ34[12] M_A_DQ35[12] M_A_DQ36[12] M_A_DQ37[12] M_A_DQ38[12] M_A_DQ39[12] M_A_DQ40[12] M_A_DQ41[12] M_A_DQ42[12] M_A_DQ43[12] M_A_DQ44[12] M_A_DQ45[12] M_A_DQ46[12] M_A_DQ47[12] M_B_DQ32[13] M_B_DQ33[13] M_B_DQ34[13] M_B_DQ35[13] M_B_DQ36[13] M_B_DQ37[13] M_B_DQ38[13] M_B_DQ39[13] M_B_DQ40[13] M_B_DQ41[13] M_B_DQ42[13] M_B_DQ43[13] M_B_DQ44[13] M_B_DQ45[13] M_B_DQ46[13] M_B_DQ47[13] M_A_DQ48[12] M_A_DQ49[12] M_A_DQ50[12] M_A_DQ51[12] M_A_DQ52[12] M_A_DQ53[12] M_A_DQ54[12] M_A_DQ55[12] M_A_DQ56[12] M_A_DQ57[12] M_A_DQ58[12] M_A_DQ59[12] M_A_DQ60[12] M_A_DQ61[12] M_A_DQ62[12] M_A_DQ63[12] M_B_DQ48[13] M_B_DQ49[13] M_B_DQ50[13] M_B_DQ51[13] M_B_DQ52[13] M_B_DQ53[13] M_B_DQ54[13] M_B_DQ55[13] M_B_DQ56[13] M_B_DQ57[13] M_B_DQ58[13] M_B_DQ59[13] M_B_DQ60[13] M_B_DQ61[13] M_B_DQ62[13] M_B_DQ63[13]

M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

1D2V_S3 3D3V_S0

G

Q501

Q501 DMN5L06K-7-G P

DMN5L06K-7-G P

DS

CPU1C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U-GP

071.SKYLA.000U

12

R506

R506 220KR2F-GP

220KR2F-GP

SKYLAKE_ULT

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR CH - B

SM_PGCNTL_R [51]

3 OF 20

AN45

DDR1_CKN[0]

AN46

DDR1_CKN[1]

AP45

DDR1_CKP[0]

AP46

DDR1_CKP[1]

AN56

DDR1_CKE[0]

AP55

DDR1_CKE[1]

AN55

DDR1_CKE[2]

AP53

DDR1_CKE[3]

BB42

DDR1_CS#[0]

AY42

DDR1_CS#[1]

BA42

DDR1_ODT[0]

AW42

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

Design Guideline: SM_RCOMP keep routing length less than 500 mils.

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_ACT_N

M_B_A13 M_B_A15 M_B_A14 M_B_A16

M_B_A2

M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

SM_DRAMRST # SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

#543016

M_B_CLK#0 [13] M_B_CLK#1 [13] M_B_CLK0 [13] M_B_CLK1 [13]

M_B_CKE0 [13] M_B_CKE1 [13]

M_B_CS#0 [13] M_B_CS#1 [13] M_B_DIMB_ODT0 [13] M_B_DIMB_ODT1 [13]

M_B_A5 [13] M_B_A9 [13] M_B_A6 [13] M_B_A8 [13] M_B_A7 [13]

M_B_BG0 [13]

M_B_A12 [13]

M_B_A11 [13] M_B_ACT_N [13] M_B_BG1 [13]

M_B_A13 [13]

M_B_A15 [13]

M_B_A14 [13]

M_B_A16 [13] M_B_BA0 [13]

M_B_A2 [13]

M_B_BA1 [13]

M_B_A10 [13]

M_B_A1 [13] M_B_A0 [13] M_B_A3 [13] M_B_A4 [13]

M_A_DQS4

M_A_DQS5

M_B_DQS4

M_B_DQS5

M_A_DQS6

M_A_DQS7

M_B_DQS6

M_B_DQS7

M_B_ALERT_N [13] M_B_PARITY [13]

R501 121R2F-GPR501 121R2F-GP

1 2

R502 80D6R2F-L-G PR502 80D6R2F-L-G P

1 2

R503 100R2F-L1-GP- UR503 100R2F-L1 -GP-U

1 2

Layout Note:

1D2V_S3

12

close to CPU

R505

R505 470R2F-GP

470R2F-GP

1 2

R504

1 2

0R0402-PAD

D502

AZ5725-01FDR 7G-GP

83.05725.0A0

DDR4_DR AMRST# [12,13]

2015/11/18 Modify

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2

A A

5

4

M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

3

M_A_DQS_DN[7: 0] [12]

M_A_DQS_DP[7:0] [12]

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

2

M_B_DQS_DN[7: 0] [13]

M_B_DQS_DP[7:0] [13]

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(DDR)

Starload SKL-U

1

5 106Thursday, Feb ruary 25, 2016

X02

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

CPU1S

RESERVED SIGNALS-1

D D

C C

TP601TPAD14-OP- GP TP601TPAD1 4-OP-GP TP602TPAD14-OP- GP TP602TPAD1 4-OP-GP

TP612TPAD14-O P-GP TP612TPAD 14-OP-GP TP613TPAD14-O P-GP TP613TPAD 14-OP-GP

PCH strap pin:

CFG3

CFG4

B B

12

DY

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604

R604 1KR2J-1-GP

1KR2J-1-GP

CFG[3]

(#543016)

12

DISPLAY PORT PRESENCE STRAP

R605

R605 1KR2J-1-GP

1KR2J-1-GP

CFG[4]

CFG0

TP618TPAD14-OP- GP TP618TPAD1 4-OP-GP

1

CFG1

TP619TPAD14-OP- GP TP619TPAD1 4-OP-GP

1

CFG2

TP620TPAD14-OP- GP TP620TPAD1 4-OP-GP

1

CFG3

TP621TPAD14-OP- GP TP621TPAD1 4-OP-GP

1

CFG4

TP622TPAD14-OP- GP TP622TPAD1 4-OP-GP

1

CFG5

TP623TPAD14-OP- GP TP623TPAD1 4-OP-GP

1

CFG6

TP624TPAD14-OP- GP TP624TPAD1 4-OP-GP

1

CFG7

TP625TPAD14-OP- GP TP625TPAD1 4-OP-GP

1

CFG8

TP626TPAD14-OP- GP TP626TPAD1 4-OP-GP

1

CFG9

TP627TPAD14-OP- GP TP627TPAD1 4-OP-GP

1

CFG10

TP628TPAD14-OP- GP TP628TPAD1 4-OP-GP

1

CFG11

TP629TPAD14-OP- GP TP629TPAD1 4-OP-GP

1

CFG12

TP630TPAD14-OP- GP TP630TPAD1 4-OP-GP

1

CFG13

TP631TPAD14-OP- GP TP631TPAD1 4-OP-GP

1

CFG14

TP632TPAD14-OP- GP TP632TPAD1 4-OP-GP

1

CFG15

TP633TPAD14-OP- GP TP633TPAD1 4-OP-GP

1

CFG16

TP634TPAD14-OP- GP TP634TPAD1 4-OP-GP

1

CFG17

TP635TPAD14-OP- GP TP635TPAD1 4-OP-GP

1

CFG18

TP636TPAD14-OP- GP TP636TPAD1 4-OP-GP

1

CFG19

TP637TPAD14-OP- GP TP637TPAD1 4-OP-GP

1

CFG_RCOM P

R60149D9R2F-GP R60149D9R2F-GP

12

ITP_PMODE

TP638TPAD14-OP- GP TP638TPAD1 4-OP-GP

1

RSVD_TP_BA70

1

RSVD_TP_BA68

1

RSVD_F65

1

RSVD_G65

1

0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

0 : ENABLED An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

AL25 AL27

C71 B70

F60

A52

BA70 BA68

J71 J68

F65 G65

F61 E61

RESERVED SIGNALS-1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

RSVD_TP_AW71 RSVD_TP_AW70

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_AW71 RSVD_AW70

MSM#

PROC_SELECT#

RSVD_TP_BB68

BB68

RSVD_TP_BB69

BB69

RSVD_TP_AK13

AK13

RSVD_TP_AK12

AK12

BB2 BA3

TP5_AU5

AU5

TP5

TP6_AT5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

TP4_BB5

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

TP1_AY4

AY4

TP1

TP2_BB3

BB3

TP2

VSS_AY71

AY71

ZVM#

AR56

RSVD_TP_AW 71

AW71

RSVD_TP_AW 70

AW70

MSM#

AP56 C64

PROC_SELEC T#

1 1

1

1 1

R602 0R0402-PADR602 0R0402-PAD

1 2

1 1

1

1 2

R603

100KR2J-1-GP

TP603 TPAD14-OP-G PTP603 TPAD14- OP-GP TP604 TPAD14-OP-G PTP604 TPAD14- OP-GP

TP605 TPAD14-OP-G PTP605 TPAD14- OP-GP TP606 TPAD14-OP-G PTP606 TPAD14- OP-GP

TP607 TPAD14-OP-G PTP607 TPAD14- OP-GP TP608 TPAD14-OP-G PTP608 TPAD14- OP-GP

TP609 TPAD14-OP-G PTP609 TPAD14- OP-GP

TP610 TPAD14-OP-G PTP610 TPAD14- OP-GP TP611 TPAD14-OP-G PTP611 TPAD14- OP-GP

TP614 TPAD14-OP-G PTP614 TPAD14- OP-GP TP615 TPAD14-OP-G PTP615 TPAD14- OP-GP

TP617 TPAD14-OP-G PTP617 TPAD14- OP-GP

DY

ZVM# [40]

#54469 CRB.

+VCCST_CP U

2016/01/11 modify

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(RESERVED)

Starload SKL-U

1

6 106Thursday, Feb ruary 25, 2016

A00

Vinaﬁx.com

R702

1 2

23e

0R2J-2-GP

R704

1 2

23e

0R2J-2-GP

5

CPU1L

VCC_CORE VCC_CORE

+VCCCOREG0

TP701TPAD14-OP-GP TP701TPAD14-OP-GP

1

+VCCCOREG1

TP707TPAD14-OP-GP TP707TPAD14-OP-GP

1

+V_EDRAM_VR

3A

VCC_EDRAM_FUSEPRG

VCCSENSE_EDRAM_VR VSSSENSE_EDRAM_VR

+V_EOPIO_VR

3A

VCCSENSE_EOPIO_VR VSSSENSE_EOPIO_VR

+V_EDRAM_VR

12

R724

R724 100R2F-L1-GP-U

100R2F-L1-GP-U

23e

VCCSENSE_EDRAM_VR VSSSENSE_EDRAM_VR

12

R725

R725 100R2F-L1-GP-U

100R2F-L1-GP-U

23e

+V_EOPIO_VR

12

R729

R729 100R2F-L1-GP-U

100R2F-L1-GP-U

23e

VCCSENSE_EOPIO_VR VSSSENSE_EOPIO_VR

12

R731

R731 100R2F-L1-GP-U

100R2F-L1-GP-U

23e

A30

VCC_A3 0

A34

VCC_A3 4

A39

VCC_A3 9

A44

VCC_A4 4

AK33

VCC_AK 33

AK35

VCC_AK 35

AK37

VCC_AK 37

AK38

VCC_AK 38

AK40

VCC_AK 40

AL33

VCC_AL 33

AL37

VCC_AL 37

AL40

VCC_AL 40

AM32

VCC_AM3 2

AM33

VCC_AM3 3

AM35

VCC_AM3 5

AM37

VCC_AM3 7

AM38

VCC_AM3 8

G30

VCC_G3 0

K32

VCCG0

AK32

VCCG1

AB62

VCCOPC _AB62

P62

VCCOPC _P62

V62

VCCOPC _V62

H63

VCC_OP C_1P8_ H63

G61

VCC_OP C_1P8_ G61

AC63

VCCOPC _SENSE

AE63

VSSOPC _SENSE

AE62

VCCEOP IO

AG62

VCCEOP IO

AL63

VCCEOP IO_SENS E

AJ62

VSSEOP IO_SENS E

SKYLAKE-U-GP

071.SKYLA.000U

RSVD_K32

RSVD_AK32

CPU POWER 1 OF 4

SKYLAKE_ULT

12 OF 20

VCC_G3 2 VCC_G3 3 VCC_G3 5 VCC_G3 7 VCC_G3 8 VCC_G4 0 VCC_G4 2 VCC_J3 0 VCC_J3 3 VCC_J3 7 VCC_J4 0 VCC_K3 3 VCC_K3 5 VCC_K3 7 VCC_K3 8 VCC_K4 0 VCC_K4 2 VCC_K4 3

VCC_SE NSE VSS_SE NSE

VIDALE RT#

VIDSCK

VIDSOUT

VCCSTG _G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

+VCCFUSEPRG

VCC_SENSE [46] VSS_SENSE [46]

Main Func = CPU

D D

140mA

+V1.8S_EDRAM

+V_EDRAM_VR

12

C701SC10U6D3V3MX-GP

C702SC10U6D3V3MX-GP

23e

+V_EOPIO_VR

12

C704SC10U6D3V3MX-GP

C703SC10U6D3V3MX-GP

23e

C C

R703

1 2

0R0603-PAD

+VCCSTG

4

CPU1M

+VCCGT

VCCGT_SENSE[46] VSSGT_SENSE[46]

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_ SENSE

J69

VSSGT_ SENSE

SKYLAKE-U-GP

071.SKYLA.000U

CPU POWER 2 OF 4

SKYLAKE_ULT

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX _AK42 VCCGTX _AK43 VCCGTX _AK45 VCCGTX _AK46 VCCGTX _AK48 VCCGTX _AK50 VCCGTX _AK52 VCCGTX _AK53 VCCGTX _AK55 VCCGTX _AK56 VCCGTX _AK58 VCCGTX _AK60 VCCGTX _AK70 VCCGTX _AL43 VCCGTX _AL46 VCCGTX _AL50 VCCGTX _AL53 VCCGTX _AL56 VCCGTX _AL60 VCCGTX _AM48 VCCGTX _AM50 VCCGTX _AM52 VCCGTX _AM53 VCCGTX _AM56 VCCGTX _AM58 VCCGTX _AU58 VCCGTX _AU63 VCCGTX _BB57 VCCGTX _BB66

VCCGTX _SENSE VSSGTX _SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCCGT

3

2016/02/16 modify

#544669 CRB.

R705

1 2

0R0805-PAD

2

1D2V_S3

12

C719

C719 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+VDDQ_CPU_CLK

C715SC10U6D3V3MX-GP C715SC10U6D3V3MX-GP

12

+VCCST_CPU

C716SC1U10V2KX-1GP C716SC1U10V2KX-1GP

12

+VCCSTG

C717SC1U10V2KX-1GPDYC717SC1U10V2KX-1GP

12

DY

1D2V_S3

C718SCD1U16V2KX-3GP C718SCD1U16V2KX-3GP

12

+VCCSFR

VCC_CORE

+VCCGT

12

R719

R719 100R2F-L1-GP-U

100R2F-L1-GP-U

R720

R720 100R2F-L1-GP-U

100R2F-L1-GP-U

R721

R721 100R2F-L1-GP-U

100R2F-L1-GP-U

R722

R722 100R2F-L1-GP-U

100R2F-L1-GP-U

12

+VDDQ_CPU_CLK1D2V_S3

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

0.04 A

A18

A22

AL23

K20 K21

0.12 A

12

C721

C720

SCD1U16V2KX-3GP

VCC_SENSE [46]

VSS_SENSE [46]

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCGT_SENSE [46]

VSSGT_SENSE [46]

CPU1N

CPU POWER 3 OF 4

VDDQ_A U23 VDDQ_A U28 VDDQ_A U35 VDDQ_A U42 VDDQ_B B23 VDDQ_B B32 VDDQ_B B41 VDDQ_B B47 VDDQ_B B51

VDDQC

VCCST

VCCSTG _A22

VCCPLL _OC

VCCPLL _K20 VCCPLL _K21

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

VCCIO_ SENSE VSSIO_ SENSE

VSSSA_ SENSE

VCCSA_ SENSE

14 OF 20

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

VCCSA_SENSE VSSSA_SENSE

+VCCIO

+VCCIO(ICCMAX.=2.73A

+VCCSA

12

R735

R735 100R2F-L1-GP-U

100R2F-L1-GP-U

R734

R734 100R2F-L1-GP-U

100R2F-L1-GP-U

VSSSA_SENSE [46] VCCSA_SENSE [46]

1

Layout Note:

SVID DATA

+VCCST_CPU

CLOSE TO CPU

B B

12

H_CPU_SVIDDAT

SVID CLOCK

H_CPU_SVIDCLK

H_CPU_SVIDALRT#

220R2J-L2-GP

A A

5

220R2J-L2-GP

The total Length of Data and Clock (from CPU to each VR) m ust be equal (±0.1 inch). Route the Alert signal betwee n the Clock and the Data sign als.

#544669

R726

R726 100R2F-L1-GP-U

100R2F-L1-GP-U

R709

1 2

0R0402-PAD

+VCCST_CPU

12

DY

R732

1 2

0R0402-PAD

+VCCST_CPU

#544669

12

CLOSE TO CPU

R727

R727 56R2J-4-GP

56R2J-4-GP

R728

12

4

R723

R723 54D9R2F-L1-GP

54D9R2F-L1-GP

VR_SVID_ALERT# [46]

#544669 CLOSE TO VR

VR_SVID_DATA [46]

VR_SVID_CLK [46]

SVID_543016:

3

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Thursday, February 25, 2016

Date: Sheet of

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VCC_CORE)

Starload SKL-U

7 106

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

D D

CPU1A

SKYLAKE_ULT

HDMI_DATA 2#[57]

HDMI_DATA 2[57]

HDMI_DATA 1#[57]

HDMI_DATA 1[57]

HDMI

Dummy, Vendor suggest 20141117

3D3V_S0

SRN2K2J -1-GP

C C

3D3V_S0

SRN2K2J -1-GP

1

DY

2 3

RN801

RN803

2 3 1

SRN2K2J -1-GP

CPU_DP1 _CTRL_DATA

4

CPU_DP1 _CTRL_CLK

CPU_DP2 _CTRL_DATA CPU_DP2 _CTRL_CLK

4

DP and DP to VGA

HDMI

+VCCIO

Check

R801

1 2

24D9R2F -L-GP

HDMI_DATA 0#[57]

HDMI_DATA 0[57]

HDMI_CLK#[57]

HDMI_CLK[57]

PCH_DPC _N0[38]

PCH_DPC _P0[38]

PCH_DPC _N1[38]

PCH_DPC _P1[38]

PCH_DPC _N2[38]

PCH_DPC _P2[38]

PCH_DPC _N3[38]

PCH_DPC _P3[38]

CPU_DP1 _CTRL_CLK[57]

CPU_DP1 _CTRL_DATA[57]

CPU_DP2 _CTRL_CLK CPU_DP2 _CTRL_DATA

EDP_COM P

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U-GP

071.SKYLA.000U

(#543016) The S kylake U/Y pro cessor supports only two DDI ports - Port 1 and Port 2.

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

1 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_DISP_ UTIL

CPU_DP2 _HPD

EDP_TX0 _DN [55] EDP_TX0 _DP [55] EDP_TX1 _DN [55] EDP_TX1 _DP [55] EDP_TX2 _DN [55] EDP_TX2 _DP [55] EDP_TX3 _DN [55] EDP_TX3 _DP [55]

EDP_AUX _DN [55] EDP_AUX _DP [55 ]

1

TP801 TP AD14-OP-GPTP801 TP AD14-OP-GP

CPU_DP1 _HPD [57]

SIO_EXT_S MI# [24]

EDP_HPD [55]

DPB_AUX N [38] DPB_AUX P [38]

L_BKLT_ EN [24] L_BKLT_ CTRL [55] EDP_VDD _EN [55 ]

(#543016) eDP_RCOMP Guideline

Signal Tr ace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

B B

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port D isable Port

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A A

Design Guidelin e: Skylake process or signal eDP_ RCOMP should be connected to the VCCIO rail via a single 24 .9 ±1% Ω resis tor.

5

Isolation Spacing

PU to 3.3 V wit h 2.2-k ±5% resistor

Resistor Value

Length

Max = 100 mils

NC

4

3D3V_S0

SIO_EXT_S MI#

3

R802 10K R2J-3-GPR802 10KR2 J-3-GP

1 2

2

CPU_DP2 _HPD

R804 0R2 J-2-GP

1 2

TypeC

R803

R803 100KR2J -1-GP

100KR2J -1-GP

TypeC

1 2

Title

CPU_(DISPLAY)

Size Document N umber Rev

A3

Date: Sheet of

CPU_(DISPLAY)

Starload SKL-U

CPU_DP_ HPD_R [37,38]

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

8 106Thursday, February 25, 20 16

1

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

A3

(Reserved)

Taipei Hsien 221, Taiwan, R.O.C.

Starload SKL-U

1

9 106Thursday, February 18, 20 16

A00

Vinaﬁx.com

Main Func = CPU

5

4

3

2

1

D D

CORE

U-line 23e 28W IccMax current-10ms max = 34 A

22U 0603 x 35(5 DY)

VCC_CORE

PC1003

PC1005

PC1002

12

PC1011

12

PC1022

C C

12

PC1005

PC1004

12

SC22U6D3V3MX-1-GP

PC1014

PC1013

PC1012

12

SC22U6D3V3MX-1-GP

PC1023

PC1025

PC1024

12

SC22U6D3V3MX-1-GP

SLICED GT

U-line 23e 28W IccMax current-10ms max[A] = 67 A

22U 0603 x35 (5 DY)

+VCCGT

PC1038

PC1039

PC1037

12

SC22U6D3V3MX-1-GP

PC1044

PC1046

PC1045

12

SC22U6D3V3MX-1-GP

20140814 DAVID

EMI reserve , 20141118

PC1009

PC1010

PC1006

PC1007

12

SC22U6D3V3MX-1-GP

PC1015

PC1016

12

SC22U6D3V3MX-1-GP

PC1026

PC1027

12

SC22U6D3V3MX-1-GP

PC1041

PC1040

12

SC22U6D3V3MX-1-GP

PC1048

PC1047

12

SC22U6D3V3MX-1-GP

PC1010

EC1002

PC1008

12

SC22U6D3V3MX-1-GP

PC1018

PC1017

12

SC22U6D3V3MX-1-GP

PC1028

PC1029

12

SC22U6D3V3MX-1-GP

PC1043

PC1042

12

SC22U6D3V3MX-1-GP

PC1049

PC1050

12

SC22U6D3V3MX-1-GP

EC1002

12

SC22U6D3V3MX-1-GP

DY

PC1020

PC1019

PC1021

12

SC22U6D3V3MX-1-GP

PC1030

PC1031

12

PC1032

SC22U6D3V3MX-1-GP

12

DY

Remove PC1033 and PC1035 (power team request)

EC1005

EC1006

12

SC22U6D3V3MX-1-GP

SC1U10V2KX-1GP

DY

PC1053

PC1052

PC1051

12

SC22U6D3V3MX-1-GP

12

DY

Do Not Stuff

SC22U6D3V3MX-1-GP

Do Not Stuff

PC1054

12

SC22U6D3V3MX-1-GP

(#543016 PDG)

EC1003

EC1004

12

DY

Do Not Stuff

PC1034

PC1036

12

SC22U6D3V3MX-1-GP

DY

PC1055

PC1057

PC1056

12

SC22U6D3V3MX-1-GP

B B

PC1060

PC1059

PC1058

12

SC22U6D3V3MX-1-GP

PC1063

PC1062

PC1061

12

SC22U6D3V3MX-1-GP

PC1065

PC1064

12

SC22U6D3V3MX-1-GP

PC1001

PC1068

PC1069

PC1066

PC1067

12

SC22U6D3V3MX-1-GP

DY

PC1069

PC1070

12

SC22U6D3V3MX-1-GP

DY

PC1070

12

SC22U6D3V3MX-1-GP

DY

VCCSA

22U 0603 x13 (5 DY)

+VCCSA

PC1075

PC1076

PC1078

PC1071

PC1072

PC1074

PC1073

12

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

PC1078

PC1077

12

SC22U6D3V3MX-1-GP

2015/10/16 modify (Power team request)

A A

5

4

EC1001

EC1007

12

DY

Do Not Stuff

Title

Size Document Number Rev

A1

Date: Sheet of

3

2

Date: Sheet of

CPU_(Power CAP1)

Starload SKL-U

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 106Thursday, February 18, 2016

A00

Vinaﬁx.com

5

Main Func = CPU

4

3

2

1

PCH DERIVED RAILS

1D0V_S5

D D

+VCCPRIM_ CORE

R1101

1 2

0R1206-P AD

+V1.00A_ SIP

R1102

1 2

0R0603-P AD

3D3V_S5 _PCH +V3.3A_S IP

R1103

C C

1 2

0R0603-P AD

+V1.8A +V1.8A_S IP

R1104

12

0R0603-P AD

+VCCIO

DY

12

C1112

SC22U6D3V3MX-1-GPDYC1112

SC22U6D3V3MX-1-GP

C1113

SC22U6D3V3MX-1-GPDYC1113

SC22U6D3V3MX-1-GP

C1122

SC22U6D3V3MX-1-GPDYC1122

SC22U6D3V3MX-1-GP

+VCCPRIM_ CORE

C1114

SC1U10V2KX-1GP

C1114

SC1U10V2KX-1GP

12

DY

UNSLICED GT

+VCCGT

12

C1102

DY

Do Not Stuff

Dummy : 20150123 Dummy : 20150123

C1115

SC22U6D3V3MX-1-GPDYC1115

SC22U6D3V3MX-1-GP

C1103

12

C1104

DY

Do Not Stuff

12

C1105

SC1U10V2KX-1GP

Do Not Stuff

DY

12

C1106

Do Not Stuff

12

C1107

1U 0402 x 6

SC1U10V2KX-1GP

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

+VCCMPH YGTAON_1 P0_LS_SIP +VCCMPH YGTAON_1 P0_LS_SIP+VCCMPH YGTAON_1 P0_LS_SIP+VCCMPH YGTAON_1 P0_LS_SIP

C1117

SC1U10V2KX-1GP

C1117

SC1U10V2KX-1GP

C1116

SC1U10V2KX-1GP

C1116

SC1U10V2KX-1GP

12

VCCIO

+VCCIO

12

C1108

DY

Do Not Stuff

C1118

SC22U6D3V3MX-1-GPDYC1118

SC22U6D3V3MX-1-GP

12

DY

+VCCIO(ICCMAX.= 2.73A)

12

C1109

12

SC1U10V2KX-1GP

C1119

12

C1111

C1110

SC1U10V2KX-1GP

Layout Note:

1uF:

C1121

SC1U10V2KX-1GP

C1121

C1120

SC10U6D3V3MX-GPDYC1120

SC10U6D3V3MX-GP

12

SC1U10V2KX-1GP

12

DY

C1174 near N15 C1180 near K15 C1173 near AF20 C1172 near N18 C1175 near AB19 22uF : C1182 C1184 near N15 10uF: C1176 near N15

+VCCIO(ICCMAX.= 2.73A)

12

PC1102SC22U6D3V3MX-1-GP PC1102SC22U6D3V3MX-1-GP

B B

VCC_COR E

12

PC1104Do Not StuffDYPC1104Do Not Stuff

PC1103SC22U6D3V3MX-1-GP PC1103SC22U6D3V3MX-1-GP

DY

12

PC1106

PC1105

SC22U6D3V3MX-1-GP

Size:0805 change to 0603 20141117

1U 0402 x 5

+V3.3A_S IP

C1123

SC10U6D3V3MX-GPDYC1123

SC10U6D3V3MX-GP

12

1D2V_S3

12

PC1107SC10U6D3V3MX-GP PC1107SC10U6D3V3MX-GP

12

PC1114Do Not StuffDYPC1114Do Not Stuff

DY

12

PC1109SC10U6D3V3MX-GP PC1109SC10U6D3V3MX-GP

PC1115

12

PC1111

PC1110

SCD1U25V2KX-GP

EC1102

SC2D2U10V2KX-GP

12

PC1108SC10U6D3V3MX-GP PC1108SC10U6D3V3MX-GP

12

PC1101Do Not StuffDYPC1101Do Not Stuff

DY

12

PC1112

PC1113

SCD1U25V2KX-GP

Change to 0.1uF at 20150427 for Power team

EC1103

SC2D2U10V2KX-GP

12

DY

12

DY

A A

12

C1124

12

C1125

SC1U10V2KX-1GP

12

C1126

12

C1101

C1127

SC1U10V2KX-1GP

SC22U6D3V3MX-1-GP

RF request 2016/01/12 modify

U-line 23e 28W IccMax current- 10ms max = 34 A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(Power CAP2)

Size Document N umber Rev

A3

Date: Sheet of

CPU_(Power CAP2)

Starload SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

11 10 6Thursday, February 18, 20 16

1

A00

Vinaﬁx.com

5

M_A_A0[5] M_A_A1[5] M_A_A2[5] M_A_A3[5] M_A_A4[5] M_A_A5[5] M_A_A6[5] M_A_A7[5] M_A_A8[5] M_A_A9[5] M_A_A10[5] M_A_A11[5] M_A_A12[5] M_A_A13[5] M_A_A14[5] M_A_A15[5]

D D

C C

1D2V_S3

DDR4_DR AMRST#

12

ED1217

ED1217 AZ5725-01FDR 7G-GP

AZ5725-01FDR 7G-GP

1 2

R1215 240R 2F-1-GP

M_A_A16[5]

M_A_BA0[5]

M_A_BA1[5]

M_A_BG0[5]

M_A_BG1[5]

M_A_CLK0[5]

M_A_CLK#0[5]

M_A_CLK1[5]

M_A_CLK#1[5]

M_A_CKE0[5] M_A_CKE1[5]

M_A_CS#0[5] M_A_CS#1[5]

M_A_DIMA_ODT0[5] M_A_DIMA_ODT1[5]

DDR4_DR AMRST#[5,13] M_A_ACT_N[5] M_A_ALERT_N[5]

DY

M_A_PARITY[5]

12

C1229

SCD1U16V2KX-3GP

PCH_SMBDAT A[13,18]

PCH_SMBCLK[13,18]

M_VREF_CA_D IMMA

SA0_CHA_DIM0 SA1_CHA_DIM0 SA2_CHA_DIM0

TS#_DIMM0_1

DM1A

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-24-GP

062.10011.00U1

1 OF 4

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

Layout note: closed to Dimm

1D2V_S3

RN1201

1

4

2 3

SRN1KJ-7-G P

B B

M_VREF_CA_D IMMA

R1206

1 2

2R2F-GP

12

C1222

SCD022U16V2KX -3GP

+V_VREF_PATH 1

12

R1209

24D9R2F-L-G P

V_SM_VREF_CN TA [5]

4

M_A_DQ0 [5] M_A_DQ1 [5] M_A_DQ2 [5] M_A_DQ3 [5] M_A_DQ4 [5] M_A_DQ5 [5] M_A_DQ6 [5] M_A_DQ7 [5] M_A_DQ8 [5] M_A_DQ9 [5] M_A_DQ10 [5] M_A_DQ11 [5] M_A_DQ12 [5] M_A_DQ13 [5] M_A_DQ14 [5] M_A_DQ15 [5] M_A_DQ16 [5] M_A_DQ17 [5] M_A_DQ18 [5] M_A_DQ19 [5] M_A_DQ20 [5] M_A_DQ21 [5] M_A_DQ22 [5] M_A_DQ23 [5] M_A_DQ24 [5] M_A_DQ25 [5] M_A_DQ26 [5] M_A_DQ27 [5] M_A_DQ28 [5] M_A_DQ29 [5] M_A_DQ30 [5] M_A_DQ31 [5] M_A_DQ32 [5] M_A_DQ33 [5] M_A_DQ34 [5] M_A_DQ35 [5] M_A_DQ36 [5] M_A_DQ37 [5] M_A_DQ38 [5] M_A_DQ39 [5] M_A_DQ40 [5] M_A_DQ41 [5] M_A_DQ42 [5] M_A_DQ43 [5] M_A_DQ44 [5] M_A_DQ45 [5] M_A_DQ46 [5] M_A_DQ47 [5] M_A_DQ48 [5] M_A_DQ49 [5] M_A_DQ50 [5] M_A_DQ51 [5] M_A_DQ52 [5] M_A_DQ53 [5] M_A_DQ54 [5] M_A_DQ55 [5] M_A_DQ56 [5] M_A_DQ57 [5] M_A_DQ58 [5] M_A_DQ59 [5] M_A_DQ60 [5] M_A_DQ61 [5] M_A_DQ62 [5] M_A_DQ63 [5]

DDR4 SWAP 0212

3D3V_S0

R1204 10KR2F-L1 -GP

R1205

0R0402-PAD

3D3V_S0

0R0402-PAD

3D3V_S0

0R0402-PAD

1D2V_S3

跟跟跟跟sw確確確確確確確確

12

DY

12

R1208 10KR2F-L1 -GP

12

DY

R1210

12

R1211 10KR2F-L1 -GP

12

DY

R1212

12

DM1B

DM8#/DBI#/NC

DDR4-260P-24-GP

SA0_CHA_DIM0

SA1_CHA_DIM0

SA2_CHA_DIM0

2 OF 4

DQS0_C DQS0_T DQS1_C DQS1_T DQS2_C DQS2_T DQS3_C DQS3_T DQS4_C DQS4_T DQS5_C DQS5_T DQS6_C DQS6_T DQS7_C DQS7_T DQS8_C DQS8_T

DM0#/DBI0#

DM1#/DBI# DM2#/DBI2# DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

11 13 32 34 53 55 74 76 177 179 198 200 219 221 240 242 95 97

12 33 54 75 178 199 220 241 96

DM1C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-24-GP

1D2V_S3

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1 M_A_DQS_DP1 M_A_DQS_DN2 M_A_DQS_DP2 M_A_DQS_DN3 M_A_DQS_DP3 M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7

3 OF 4

VDDSPD

VPP VPP

VTT

261 262

NP1 NP2

12

C1208

SC10U6D3V3MX-GP

DY

12

C1214

SC1U10V2KX-1GP

12

C1202

12

C1215

3

4 OF 4

DM1D

4 OF 4

DM1D

VSS1VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

1D2V_S3

3D3V_S0

255

257 259

258

261 262

NP1 NP2

0D6V_S0

2D5V_S3

12

C1228

R1216

SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP

DY

SC2D2U10V3KX-L-GP

DY

39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR4-260P-24-GP

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

2

1

UN 0225

0D6V_S0

12

C1225

C1226

SC1U10V2KX-1GP

12

C1209

C1203

SC10U6D3V3MX-GP

12

C1204

12

C1206

C1210

C1205

SC10U6D3V3MX-GP

DY

12

C1223

SC4D7U6D3V2MX-1-GP

0D6V_S00D6V_S0

12

C1230

SC4D7U6D3V2MX-1-GP

DY

12

C1224

C1227

SC4D7U6D3V2MX-1-GP

DY

SC4D7U6D3V2MX-1-GP

for placement modifu 2015/10/1 9

2D5V_S3

12

C1218

C1216

C1217

SC1U10V2KX-1GP

12

C1219

12

C1220

SC1U10V2KX-1GP

C1221

EC1202

SC2D2U10V2KX-GP

SC1U10V2KX-1GP

12

DY

12

C1211

DY

12

C1231

C1232

SC4D7U6D3V2MX-1-GP

DY

C1212

12

C1207

C1213

SC1U10V2KX-1GP

SC1U10V2KX-L1-GP

DY

SC4D7U6D3V2MX-1-GP

RF request 2016/01/12 modify

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

M_A_DQS_DN[7: 0] [5]

M_A_DQS_DP[7:0] [5]

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1

Size Document Number Rev

Size Document Number Rev A2

A2

Thursday, Feb ruary 25, 2016

Thursday, Feb ruary 25, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Starload SKL-U

1

12 106

A00

Vinaﬁx.com

5

DM2A

SA0_CHB_DIM0 SA1_CHB_DIM0 SA2_CHB_DIM0

TS#_DIMM1_1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-23-GP

062.10011.00T1

M_B_A0[5] M_B_A1[5] M_B_A2[5] M_B_A3[5] M_B_A4[5] M_B_A5[5] M_B_A6[5] M_B_A7[5] M_B_A8[5] M_B_A9[5] M_B_A10[5] M_B_A11[5] M_B_A12[5] M_B_A13[5] M_B_A14[5]

D D

PCH_SMBDAT A[12,18]

1D2V_S3

C C

1 2

DDR4_DR AMRST#

12

ED1302

ED1302 AZ5725-01FDR 7G-GP

AZ5725-01FDR 7G-GP

R1312

M_B_A15[5] M_B_A16[5]

M_B_BA0[5]

M_B_BA1[5]

M_B_BG0[5 ]

M_B_BG1[5]

M_B_CLK0[5]

M_B_CLK#0[5]

M_B_CLK1[5]

M_B_CLK#1[5]

M_B_CKE0[5] M_B_CKE1[5]

M_B_CS#0[5] M_B_CS#1[5]

M_B_DIMB_ODT0[5] M_B_DIMB_ODT1[5]

PCH_SMBCLK[12,18]

DDR4_DR AMRST#[5,12] M_B_ACT_N[5] M_B_ALERT_N[5]

240R2F-1-GP

DY

M_B_PARITY[5]

M_VREF_CA_D IMMB

12

C1301

SCD1U16V2KX-3GP

Layout note: closed to Dimm

1D2V_S3

RN1301

1 2 3

SRN1KJ-7-G P

4

M_VREF_CA_D IMMB

B B

R1305

1 2

2R2F-GP

12

C1323

C1323 SCD022U16V2KX -3GP

SCD022U16V2KX -3GP

+V_VREF_PATH 2

12

R1309

24D9R2F-L-G P

1 OF 4

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

V_SM_VREF_CN TB [5]

8 7 20 21 4 3 16 17 28 29 41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

3D3V_S0

4

M_B_DQ8 [5]

M_B_DQ9 [5] M_B_DQ10 [5] M_B_DQ11 [5] M_B_DQ12 [5] M_B_DQ13 [5] M_B_DQ14 [5] M_B_DQ15 [5]

M_B_DQ0 [5]

M_B_DQ1 [5]

M_B_DQ2 [5]

M_B_DQ3 [5]

M_B_DQ4 [5]

M_B_DQ5 [5]

M_B_DQ6 [5]

M_B_DQ7 [5] M_B_DQ16 [5] M_B_DQ17 [5] M_B_DQ18 [5] M_B_DQ19 [5] M_B_DQ20 [5] M_B_DQ21 [5] M_B_DQ22 [5] M_B_DQ23 [5] M_B_DQ24 [5] M_B_DQ25 [5] M_B_DQ26 [5] M_B_DQ27 [5] M_B_DQ28 [5] M_B_DQ29 [5] M_B_DQ30 [5] M_B_DQ31 [5] M_B_DQ32 [5] M_B_DQ33 [5] M_B_DQ34 [5] M_B_DQ35 [5] M_B_DQ36 [5] M_B_DQ37 [5] M_B_DQ38 [5] M_B_DQ39 [5] M_B_DQ40 [5] M_B_DQ41 [5] M_B_DQ42 [5] M_B_DQ43 [5] M_B_DQ44 [5] M_B_DQ45 [5] M_B_DQ46 [5] M_B_DQ47 [5] M_B_DQ48 [5] M_B_DQ49 [5] M_B_DQ50 [5] M_B_DQ51 [5] M_B_DQ52 [5] M_B_DQ53 [5] M_B_DQ54 [5] M_B_DQ55 [5] M_B_DQ56 [5] M_B_DQ57 [5] M_B_DQ58 [5] M_B_DQ59 [5] M_B_DQ60 [5] M_B_DQ61 [5] M_B_DQ62 [5] M_B_DQ63 [5]

DDR4 SWAP 0212

跟跟跟跟sw確確確確確確確確

DY

R1302 10KR2F-L1-GP

12

R1303

12

0R0402-PAD

R1306 10KR2F-2- GPR1306 10K R2F-2-GP

12

R1307 0R2J-L-GP

12

DY

R1310 10KR2F-L1-GP

12

R1311

12

0R0402-PAD

By layou modify 20150916

1D2V_S3

SA0_CHB_DIM0

SA1_CHB_DIM0

SA2_CHB_DIM0

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

DM2B

DM8#/DBI#/NC

DDR4-260P-23-GP

12

C1303

SC10U6D3V3MX-GP

12

C1315

SC1U10V2KX-1GP

DM2C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-23-GP

2 OF 4

DQS0_C DQS0_T DQS1_C DQS1_T DQS2_C DQS2_T DQS3_C DQS3_T DQS4_C DQS4_T DQS5_C DQS5_T DQS6_C DQS6_T DQS7_C DQS7_T DQS8_C DQS8_T

DM0#/DBI0#

DM1#/DBI# DM2#/DBI2# DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

12

C1304

SC10U6D3V3MX-GP

DY

12

C1316

SC1U10V2KX-1GP

3 OF 4

255

VDDSPD

257

VPP

259

VPP

258

VTT

261

262

NP1

NP2

By layou modify 20150916

M_B_DQS_DN1

11

M_B_DQS_DP1

13

M_B_DQS_DN0

32

M_B_DQS_DP0

34

M_B_DQS_DN2

53

M_B_DQS_DP2

55

M_B_DQS_DN3

74

M_B_DQS_DP3

76

M_B_DQS_DN4

177

M_B_DQS_DP4

179

M_B_DQS_DN5

198

M_B_DQS_DP5

200

M_B_DQS_DN6

219

M_B_DQS_DP6

221

M_B_DQS_DN7

240

M_B_DQS_DP7

242 95 97

12 33 54 75 178 199 220 241 96

12

C1307

C1305

C1306

SC10U6D3V3MX-GP

DY

12

C1318

C1319

C1317

SC1U10V2KX-1GP

3D3V_S5

EC1302

SC2D2U10V2KX-GP

12

DY

3

12

C1308

12

C1320

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

2D5V_S3

0D6V_S0

M_B_DQS_DN1 [5] M_B_DQS_DP1 [5] M_B_DQS_DN0 [5] M_B_DQS_DP0 [5] M_B_DQS_DN2 [5] M_B_DQS_DP2 [5] M_B_DQS_DN3 [5] M_B_DQS_DP3 [5] M_B_DQS_DN4 [5] M_B_DQS_DP4 [5] M_B_DQS_DN5 [5] M_B_DQS_DP5 [5] M_B_DQS_DN6 [5] M_B_DQS_DP6 [5] M_B_DQS_DN7 [5] M_B_DQS_DP7 [5]

12

C1309

DY

C1321

12

C1328

C1329

SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP

DY

1D2V_S3

12

C1324

SC10U6D3V3MX-GP

12

C1310

SC10U6D3V3MX-GP

EC1303

12

C1322

SC2D2U10V2KX-GP

SC1U10V2KX-1GP

12

DY

RF request 2016/01/12 modify

3D3V_S0

12

DY

UN 0225

12

C1325

2

4 OF 4

DM2D

4 OF 4

DM2D

VSS1VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

DDR4-260P-23-GP

12

C1326

C1327

SC10U6D3V3MX-GP

C1327

SC1U10V2KX-1GP

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

2D5V_S30D6V_S0 0D6V_S 0 0D6V_S0

12

C1311

SC4D7U6D3V2MX-1-GP

DY

C1330

SC4D7U6D3V2MX-1-GP

DY

C1331

SC4D7U6D3V2MX-1-GP

M_B_DQS_DN[7: 0] [5]

M_B_DQS_DP[7:0] [5]

DY

12

C1312

12

C1313

C1314

SC1U10V2KX-1GP

SC1U10V2KX-L1-GP

DY

SC4D7U6D3V2MX-1-GP

1

RF request 2016/01/12 modify

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1

Size Document Number Rev

Size Document Number Rev A2

A2

Thursday, Feb ruary 25, 2016

Thursday, Feb ruary 25, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Starload SKL-U

1

13 106

A00

Vinaﬁx.com

5

D D

4

3

2

1

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Starload SKL-U

14 106Thursday, February 18, 2016

1

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

3D3V_S0

R1503

CPU1I

SKYLAKE_ULT

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37 D37 C32 D32 C29

DC resistance < 0.5ohm.

D29 B26 A26

CSI2_COMP

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

WIFI_RF_ EN [66]

GPP_F: VCCPGPPF = 1.8V Only

EMMC_RC OMP

1 2

R1501 100R2F-L 1-GP-UR1501 100R 2F-L1-GP-U

1 2

R1502

200R2F-L -GP

WIFI_RF_ EN

R1503

12

DY

10KR2J-3 -GP

Change to Dummy 20150402

[#545659 Rev0.7 ]

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(CS-2/EMMC)

Starload SKL-U

15 10 6Thursday, February 25, 20 16

1

A00

Vinaﬁx.com

Main Func = PCH

#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.

GPU

D D

WLAN

HDD1

SSD

Layout Note:

3D3V_S0

R1607 10KR2J-3-GPR1607 10KR2J-3-GP

1 2

C C

5

CPU_RXN_C_dGPU_TXN0[66] CPU_RXP_C_dGPU_TXP0[66] dGPU_RXN_C_CPU_TXN0[66] dGPU_RXP_C_CPU_TXP0[66]

CPU_RXN_C_dGPU_TXN1[66] CPU_RXP_C_dGPU_TXP1[66] dGPU_RXN_C_CPU_TXN1[66] dGPU_RXP_C_CPU_TXP1[66]

CPU_RXN_C_dGPU_TXN2[66] CPU_RXP_C_dGPU_TXP2[66] dGPU_RXN_C_CPU_TXN2[66] dGPU_RXP_C_CPU_TXP2[66]

CPU_RXN_C_dGPU_TXN3[66] CPU_RXP_C_dGPU_TXP3[66] dGPU_RXN_C_CPU_TXN3[66] dGPU_RXP_C_CPU_TXP3[66]

PCIE_RX_CPU_N5[66] PCIE_RX_CPU_P5[66] PCIE_TX_WLAN_N5[66] PCIE_TX_WLAN_P5[66]

SATA_RX_CPU_N0[60] SATA_RX_CPU_P0[60] SATA_TX_CPU_N0[60] SATA_TX_CPU_P0[60]

SATA_RX_CPU_N1[63] SATA_RX_CPU_P1[63] SATA_TX_CPU_N1[63] SATA_TX_CPU_P1[63]

1. Trace Width: 4 mils min (b reakout) 12-15 mils (trace) Note: Must maintain low DC re sistance routing (<0.1 ohm).

2. Isolation Spacing: At leas t 12 mils to any adjacent high speed I/O.

R1604

TP1605TPAD14-OP-GP TP1605TPAD14-OP-GP TP1606TPAD14-OP-GP TP1606TPAD14-OP-GP

PIRQA#

1 2

100R2F-L1-GP-U

1 1

SCD22U10V2KX-1GP

1 2 1 2

XDP_PRDY# XDP_PREQ#

OPS

OPS OPS

OPS

SCD22U10V2KX-1GP

OPS

OPS OPS

OPS

SCD22U10V2KX-1GP

OPS

OPS OPS

OPS

SCD22U10V2KX-1GP

OPS

OPS OPS

OPS

SCD22U10V2KX-1GP

SCD1U16V2KX-3GP

PEG_TX_CPU_N0 PEG_TX_CPU_P0

PEG_TX_CPU_N1 PEG_TX_CPU_P1

PEG_TX_CPU_N2 PEG_TX_CPU_P2

PEG_TX_CPU_N3 PEG_TX_CPU_P3

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

PCIE_RCOMPN PCIE_RCOMPP

PIRQA#

USB 2.0 Table

Pair

Device

0

USB3.0 port1

1

USB3.0 Port2 (Debug Port/IOBD)

USB3.0 Port3 (IOBD)

2

3

Sensor HUB

4

CAMERA

WLAN

5

6

Touch Panel

7

Card Reader

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1601

C1601 C1602

C1602

CPU1H

PCIE/USB3/SATA

H13

PCIE1_ RXN/USB3_ 5_RXN

G13

PCIE1_ RXP/USB3 _5_RX P

B17

PCIE1_ TXN/USB3_ 5_TXN

A17

PCIE1_ TXP/USB3 _5_TX P

G11

PCIE2_ RXN/USB3_ 6_RXN

F11

PCIE2_ RXP/USB3 _6_RX P

D16

PCIE2_ TXN/USB3_ 6_TXN

C16

PCIE2_ TXP/USB3 _6_TX P

H16

PCIE3_ RXN

G16

PCIE3_ RXP

D17

PCIE3_ TXN

C17

PCIE3_ TXP

G15

PCIE4_ RXN

F15

PCIE4_ RXP

B19

PCIE4_ TXN

A19

PCIE4_ TXP

F16

PCIE5_ RXN

E16

PCIE5_ RXP

C19

PCIE5_ TXN

D19

PCIE5_ TXP

G18

PCIE6_ RXN

F18

PCIE6_ RXP

D20

PCIE6_ TXN

C20

PCIE6_ TXP

F20

PCIE7_ RXN/SATA 0_RXN

E20

PCIE7_ RXP/SAT A0_RX P

B21

PCIE7_ TXN/SATA 0_TXN

A21

PCIE7_ TXP/SAT A0_TX P

G21

PCIE8_ RXN/SATA 1A_RX N

F21

PCIE8_ RXP/SAT A1A_R XP

D21

PCIE8_ TXN/SATA 1A_TX N

C21

PCIE8_ TXP/SAT A1A_T XP

E22

PCIE9_ RXN

E23

PCIE9_ RXP

B23

PCIE9_ TXN

A23

PCIE9_ TXP

F25

PCIE10 _RXN

E25

PCIE10 _RXP

D23

PCIE10 _TXN

C23

PCIE10 _TXP

F5

PCIE_R COMPN

E5

PCIE_R COMPP

D56

PROC_P RDY#

D61

PROC_P REQ#

BB11

GPP_A7 /PIRQA#

E28

PCIE11 _RXN/SAT A1B_R XN

E27

PCIE11 _RXP/SA TA1B_ RXP

D24

PCIE11 _TXN/SAT A1B_T XN

C24

PCIE11 _TXP/SA TA1B_ TXP

E30

PCIE12 _RXN/SAT A2_RX N

F30

PCIE12 _RXP/SA TA2_R XP

A25

PCIE12 _TXN/SAT A2_TX N

B25

PCIE12 _TXP/SA TA2_T XP

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

4

SSIC / USB3

USB3_2_ RXN/SSIC _1_RX N USB3_2_ RXP/SSI C_1_R XP USB3_2_ TXN/SSIC _1_TX N USB3_2_ TXP/SSI C_1_T XP

USB3_3_ RXN/SSIC _2_RX N USB3_3_ RXP/SSI C_2_R XP USB3_3_ TXN/SSIC _2_TX N USB3_3_ TXP/SSI C_2_T XP

USB2

USB2_VB USSENSE

GPP_E9 /USB2_OC 0# GPP_E1 0/USB2_O C1# GPP_E1 1/USB2_O C2# GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0 GPP_E5 /DEVSLP 1 GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/S ATAGP0 GPP_E1 /SATAXP CIE1/S ATAGP1 GPP_E2 /SATAXP CIE2/S ATAGP2

GPP_E8 /SATALE D#

8 OF 20

H8

USB3_1_ RXN

G8

USB3_1_ RXP

C13

USB3_1_ TXN

D13

USB3_1_ TXP

J6 H6 B13 A13

J10 H10 B15

Cutomer remove IO board USB3.0

A15

E10

USB3_4_ RXN

F10

USB3_4_ RXP

C15

USB3_4_ TXN

D15

USB3_4_ TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

AH7

USB2N_10

DC resistance < 0.5ohm.

AH8

USB2P_1 0

USBCOMP

AB6

USB2_CO MP

USB2_ID

AG3

USB2_ID

USB2_VBUSSENSE

AG4

A9 C9

USB_OC2#

D9

USB_OC3#

B9

J1

SIO_EXT_SCI#

J2 J3

GPP_E0/SATAXPCIE0/SATAGP0

H2

GPP_E1/SATAXPCIE1/SATAGP1

H3

GPP_E2/SATAXPCIE2/SATAGP2

G4

SATA_ACT# USB_OC2#

H1

USB_CPU_PN0 [34] USB_CPU_PP0 [34]

USB_CPU_PN1 [36] USB_CPU_PP1 [36]

USB_CPU_PN2 [66] USB_CPU_PP2 [66]

USB_CPU_PN3 [38] USB_CPU_PP3 [38]

USB_CPU_PN4 [55] USB_CPU_PP4 [55]

USB_CPU_PN5 [66] USB_CPU_PP5 [66]

USB_CPU_PN6 [55] USB_CPU_PP6 [55]

USB_CPU_PN7 [66] USB_CPU_PP7 [66]

USB_CPU_PN8 [69] USB_CPU_PP8 [69]

R1603 113R2F-GPR1603 113R2F-GP

1 2

USB_OC0# [34,35] USB_OC1# [66]

HDD_DEVSLP [60]

SIO_EXT_SCI# [24]

MSATA_DEVSLP [63]

1 1 1

USB30_RX_CPU_N1 [36] USB30_RX_CPU_P1 [36] USB30_TX_CPU_N1 [36] USB30_TX_CPU_P1 [36]

USB30_RX_CPU_N2 [36] USB30_RX_CPU_P2 [36] USB30_TX_CPU_N2 [36] USB30_TX_CPU_P2 [36]

USB30_RX_CPU_N4 [38] USB30_RX_CPU_P4 [38] USB30_TX_CPU_N4 [38] USB30_TX_CPU_P4 [38]

USB3.0 port1

USB3.0 port2

USB3.0 port3

Type C

CAMERA

WLAN

Touch Panel

Card Reader

Sensor HUB

(#543016) When used as DEVSLP , no external pull-up or pull -down termination required from SAT A Host DEVSLP.

TP1602 TPAD14-OP-GPTP1602 TPAD14-OP-GP TP1603 TPAD14-OP-GPTP1603 TPAD14-OP-GP TP1604 TPAD14-OP-GPTP1604 TPAD14-OP-GP

SATA_ACT# [64]

USB2_ID USB2_VBUSSENSE

Follow SKL PDG design guide

(#543016) Unused SATAGP[2:0]/ GPP_E[2:0] pins must be termi nated to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the motherboard. Do not use both pull-up and p ull-down. Either pull-up or p ull-down is acceptable.

(#545659) The xHCI controller supports USB Debug port on a ll USB3.0 capable ports.

RN1602

1

4

2 3

SRN0J-6-GP

SIO_EXT_SCI#

USB_OC3# USB_OC0# USB_OC1#

3

12

R1608 10KR2J-3-GPR1608 10KR2J-3-GP

RN1601

8 7

SRN10KJ-6-GP

3D3V_S0

1 2 3456

3D3V_S5_PCH

2

TBD

3D3V_S0

R1606

SATA_ACT#

12

10KR2J-3-GP

(#543611) The SATALED# signal is open-c ollector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.

10KR2J-3-GP

1

#545659 (SKL_PCH_U_Y_EDS Rev0 .7)

B B

A A

Title

Size Document Number Rev

A1

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

Starload SKL-U

16 106Thursday, February 25, 2016

A00

Vinaﬁx.com

Main Func = PCH

5

4

3

2

1

Remove Power rail +V3.3A_SIP a nd R1712(DY), 20141118

3D3V_S5

D D

RTC_AUX_S5

C C

B B

A A

R1709,R1723,R1703,R1724 merge to RN1704

RN1704

1 2 3 4 5

SRN10KJ-6-G P

R1730

330KR2J-L1-GP

1 2

+V3.3A_SIP

R1731

1 2

20KR2J-L2-GP

RN1703

1 2 3

SRN10KJ-5-G P

R1717 10KR2J-3-GP

DY

AOZ Power switch, P/N: 074.013 34.0093 Low Rds(on)= 5m Ohm Turn on rise time = 10us

AC_PRESENT

8

PCH_WA KE#

7

PCH_BATLOW #

6

GPD11/LANPHYPC

GPD11 pull high by Intel PDG1.3 request

#544669 (CRB): 330k.

SM_INTRUDER #

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

EXT_PWR _GATE#

PM_RSMRST#

4

PM_PCH_PW ROK

SYS_PWROK

12

RF request 2016/01/12 modify

NON DS3

R1708

ME_SUS_PW R_ACK_R

SUSACK# SUSACK#_R

TP1711TPAD 14-OP-GP T P1711TPAD14- OP-GP

1

ME_SUS_PW R_ACK

TP1712TPAD 14-OP-GP T P1712TPAD14- OP-GP

1

3D3V_AUX_S5

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

1 2

0R2J-2-GP

2 3 1

R1727

100KR2J-1-GP

1 2

NON DS3

6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

5

R1708

RN1702

DS3

SRN0J-6-GP

Q1701

2345

1

2N7002KDW -GP

4

#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.

H_CPUPW RGD

12

DY

R1714

10KR2J-3-GP

+VCCMPHYGTAON_1P0

SKL: 1.0V

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A )

1D0V_S5

EC1710

SC2D2U10V2KX-GP

12

DY

DS3 BOM Option

SUSACK#_R

ME_SUS_PW R_ACK_R

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

PM_RSMRST#

1 2

R1728

3V_5V_POK_C3V_5V_P OK#

1 2

NON DS3

0R2J-2-GP

DS3

R1729

1 2

0R2J-2-GP

+VCCPDSW _3P33D3V_S5

R1711

1 2

0R0603-PAD

Layout note: 3 PAD SHARING

1

TP1709

TPAD14-OP-G P

SYS_PWROK[24]

12

EC1701

AZ5725-01FDR7G-GP

EMI DVT1 0210

EC_WAKE#[24]

R1724

1 2

0R0805-PAD

R1735

1 2

0R0805-PAD

Follow Iris SKL 2015/11/30 modify

SIO_SLP_SUS#

DY

C1710

SCD47U10V2KX-GP

RESET_OUT #[24,26]

ME_SUS_PW R_ACK_R[20]

+VCCPDSW _3P3

R1732

1 2

0R0402-PAD

+VCCMPHYGTA ON_1P0_LS_SIP

R1718 0R2J-2-GP

12

EC1711

AZ5725-01FDR7G-GP

12

GPD2/LAN_W AKE#

C1704

12

SC10U6D3V3MX- GP

1 2

DY

Change location to net PCH_DPW ROK

3V_5V_POK [40,45,52,54 ]

Dummy C1710 by it's useless

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

SIO_SLP_S3#[24,27,40,51,54]

Change dummy property from DS3 to DY

EC1711 modify to 100k and 0.01 uF at DVT1 20150203

4

+V3.3A_SIP

12

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

TP1705

TPAD14-OP-G P

1 2

1

2

EC1713

SC2D2U10V2KX-GP

DY

SCD1U16V2KX- 3GP

U1703

NC#1

VCC

DY

A

GND3Y

74LVC1G07GW -GP

ALL_SYS_PWRG D[24 ,40]

1 2

0R2J-2-GP

3D3V_S5

12

TPAD14-OP-G P

C1703

5

4

R1733

DY

EMI DVT1 0210

R1706 0R0402-PADR1706 0R0402-PAD

1 2

R1704 0R2J-2-GP

1 2

NON DS3

R1707 10KR2J-3-GPR1707 10KR2J-3-GP

For sequence fine tune 2016/01 /04

RF request 2016/01/12 modify

3V_5V_POK [40,45,52,54]PCH_DPW ROK[24]

PCH_RSMRS T# [24]

EC1712

12

DY

SCD1U16V2KX-3GP

EC1706

12

DY

PCH_PLTRST # XDP_DBRESE T# PM_RSMRST#

H_CPUPW RGD

1

H_VCCST_PW RGD

SYS_PWROK PM_PCH_PW ROK PCH_DPW ROKPM_RSMRST#

ME_SUS_PW R_ACK_R SUSACK#_R

PCH_WA KE# GPD2/LAN_W AKE# GPD11/LANPHYPC

3D3V_S5

12

DY

SC1KP50V2KX-1GP

CPU1K

SYSTEM POWER MANAGEMENT

SKYLAKE_ULT

071.SKYLA.000U

3D3V_S5

C1702

12

DY

5

4

12

R1719

R1719 47KR2F-GP

47KR2F-GP

XDP_DBRESE T#

SYS_PWROK

PLT_RST#

RESET_OUT #

3V_5V_POK

EMI DVT1 0210

SKYLAKE_ULT

GPP_B11/EXT_PWR_GATE#

+VCCSTG

12

R1722

R1722 100KR2J-1-GP

100KR2J-1-GP

DY

Dis-wire with XDP_PM_RSMRST_PW RGD_XDP

H_VCCST_PW RGD

12

C1711

DY

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/USB2_WAKEOUT#

SKYLAKE-U-GP

SCD1U16V2KX-3GP

U1701

1

NC#1

VCC

2

A

DY

GND3Y

74LVC1G07GW -GP

73.01G07.0HG

1 2

R1716

12

100KR2F-L1-GP

EC1709

EC1702

AZ5725-01FDR7G-GP

100KR2F-L1-GP

AZ5725-01FDR7G-GP

12

EC1703

AZ5725-01FDR7G-GP

12

EC1705

EC1704

AZ5725-01FDR7G-GP

GPD1/ACPRESENT

GPP_B2/VRALERT#

SCD01U50V2KX-1GP

EMI DVT1 0210

11 OF 20

GPD4/SLP_S3# GPD5/SLP_S4#

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

GPP_A11/PME#

INTRUDER#

12

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

SIO_SLP_S5#

SLP_LAN# AUX_EN_W OWL SIO_SLP_A#

AC_PRESENT PCH_BATLOW #

PME# SM_INTRUDER #

EXT_PWR _GATE# GPP_B2/VRALER T#

1

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD0/BATLOW#

EC1708

R1722 & EC1708 modify to 100k and 0.01uF at DVT1

AZ5725-01FDR7G-GP

3D3V_AUX_S5

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

R1737

PM_RSMRST#_M

1 2

NON DS3

100KR2J-1-GP

1

SIO_SLP_S0# [24,60] SIO_SLP_S3# [24,27,40,51,54]

SIO_SLP_S4# [24,40,54]

TP1703 TPAD14- OP-GPTP1703 TPAD14- OP-GP

SIO_SLP_SUS# [52,54]

TP1704 TPAD14-O P-GPTP1704 TPAD14-OP -GP

TP1710 TPAD14- OP-GPTP1710 TPAD14- OP-GP

TP1706 TPAD14- OP-GPTP1706 TPAD14- OP-GP

SIO_PWRBTN # [24]

TP1707 TPAD14-O P-GPTP1707 TPAD14-OP -GP

TP1708 TPAD14-O P-GPTP1708 TPAD14-OP -GP

PLT_RST#[24,66,68]

R1715

100KR2J-1-GP

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

Q1702

Q1702 2N7002KDW -GP

2N7002KDW -GP

2345

NON DS3

1

6

BATLOW#: Pull-up required even if not implemented.

AC_PRESENT

EC1707

12

DY

SCD1U16V2KX-3GP

R1713

PCH_PLTRST #

1 2

0R0402-PAD

12

C1701

C1701 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

D1701

RB751V-40H-G P

KA

ACOK_IN_M [43,44]

83.R2004.G8F

PM_RSMRST#_R PM_RSMRST#

1 2

NON DS3

R1720

R1720 0R2J-2-GP

0R2J-2-GP

AC_PRESENT

Reserve by NON DS3 function 20 150413

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

CPU_(POWER MANAGEMENT)

Size Document Number Rev

A2

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Starload SKL-U

1

A00

17 106Thursday, Feb ruary 25, 2016

A00

Vinaﬁx.com

RN1802

SRN1KJ-7-G P

4

SIO_RCIN#

SERIRQ

5

SPI_HOLD_ROM

SPI_WP_ROM

PCH strap pin:

Sampled at rising edge of RSMRST#

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SPI_WP_ROM[25]

SPI_CS_ROM_N0[24,25]

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

SPI_CLK_ROM[24,25]

SPI_SO_ROM[24,25]

SPI_SI_ROM[24,25]

SPI_HOLD_ROM[25 ]

HDD_FALL_INT[70] HDD_EN_PC H[60]

SIO_RCIN#[24]

SERIRQ[24]

R1806,R1807,R1808,R1809 merge to RN1803 2015/10/06 modify

RN1803

1 2 3 4 5

SRN10J-1-G P

1 2 1 2

8 7 6

R181110R2F-L-GP R181110R2F-L-GP R18120R0 402-PAD R18120R0 402-PAD

Main Func = PCH

D D

C C

R1835 and R1834 merge to RN1802 2015/10/06 modify

3D3V_S5_PCH

3D3V_S0

R1820

1 2

10KR2J-3-GP

R1821

1 2

10KR2J-3-GP

SERIRQ PH: PDG: 8.2k CRB: 10k

RCIN#: Frequency to Avoid: 33 MHz

1 2 3

GPP_C5/SML0ALER T#

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU

SPI_HOLD_CPU SPI_CS_CPU_N0

TP1801TPAD 14-OP-GP T P1801TPAD14- OP-GP

TP1804TPAD 14-OP-GP T P1804TPAD14- OP-GP TP1805TPAD 14-OP-GP T P1805TPAD14- OP-GP TP1806TPAD 14-OP-GP T P1806TPAD14- OP-GP

1

1 1 1

4

CPU_D1_TP

CPU_D4_TP CPU_D5_TP CPU_D6_TP

PCH Prim

3D3V_S5_PCH

DY

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

AW13

AY11

12

CPU1E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U-GP

R1822

R1822 1KR2J-1-GP

1KR2J-1-GP

R1823

R1823 1KR2J-1-GP

1KR2J-1-GP

SPI - FLASH

Strap

SPI - TOUCH

C LINK

071.SKYLA.000U

PCH strap pin:

BOOT HALT

SPI0_MOSI

This signal has a weak internal pull-up.

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

SKYLAKE_ULT

LPC

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

3

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

Strap

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

20140820 DAIVD

SPI_SI_CPU

LPC_LAD[3..0][24,68]

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCH Prim

LPC_LAD[3..0]

MEM_SMBCLK MEM_SMBDATA GPP_C2/SMBALER T#

SML0_SMBCLK SML0_SMBDATA GPP_C5/SML0ALER T#

SML1_SMBCLK SML1_SMBDATA GPP_B23/SML1ALERT #

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_LFRAME#_R SUS_STAT#/LPC PD#

PCI_CLK_LPC0 PCI_CLK_LPC1 CLKRUN#_R

PCI_CLK_LPC0 PCI_CLK_LPC1

3D3V_S5_PCH

12

R1824

DY

1KR2J-1-GP

12

R1825

DY

1KR2J-1-GP

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

SML1_SMBCLK [24,2 6,66] SML1_SMBDATA [24,2 6,66]

R1801

12

0R0402-PAD

R1819

1 2

0R0402-PAD

R1804 22R2J-2-GP

1 2

LPC

R1805 22R2J-2-GPR1805 22R2J- 2-GP

1 2

8 7 6

12

DY

RN1806

SRN0J-7-GP -U

LPC_LFRAME# [24,68]

CLKRUN# [24]

EC1802

EC1801

SC10P50V2JN-4GPDYEC1801

SC10P50V2JN-4GP

12

DY

LPC_LAD0_R

1

LPC_LAD1_R

2

LPC_LAD2_R

3

LPC_LAD3_R

45

SUS_STAT#/LPC PD#

CLKRUN#_R

SC10P50V2JN-4GPDYEC1802

SC10P50V2JN-4GP

2

3D3V_S5_PCH

R1814

12

DY

10KR2J-3-GP

R1818

8K2R2F-1-GP

1 2

CLK_PCI_LPC [68]

CLK_PCI_LPC_MEC [24]

3D3V_S0

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

MEM_SMBDATA

84.2N702.A3F

MEM_SMBCLK

SML1_SMBDATA SML1_SMBCLK SML0_SMBDATA SML0_SMBCLK

DVT1 0210, Reserve by Intel MOW

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

MEM_SMBCLK MEM_SMBDATA

3D3V_S0

2N7002KDW -GP

1

6

2345

Q1801

RN1807

8 7 6

SRN2K2J-4-G P

R1836

2K2R2J-2-GP

SRN2K2J-1-G P

4

RN1811

1

1 2 3 45

12

23 1

RN1810

4

SRN10KJ-5-G P

R1837150KR 2J-GP R1837150KR 2J-GP

23 1

PCH_SMBDAT A [12,13]

PCH_SMBCLK [12,13]

3D3V_S5_PCH

3D3V_S0

+V1.00A_SIP

12

10KR2J-3-GP

12

EE for DVT1 0212

RTC_X1

RTC_X2

C1803

C1803 SC3P50V2CN- 1-GP

SC3P50V2CN- 1-GP

1 2

TP1802 TPAD14-OP -GPT P1802 TPAD14-OP-G P

1

TP1803 TPAD14-OP -GPT P1803 TPAD14-OP-G P

1

TP1807 TPAD14-OP -GPT P1807 TPAD14-OP-G P

1

+V1.05S_AXCK_LCPLL

Q1802

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

D

(#514849)

R1816

Layout: Place at the open door area.

C1801

XTAL24_IN

12

RTC_AUX_S5

1

23

RN1801

RN1801 SRN20KJ-1-G P

SRN20KJ-1-G P

4

21

12

G1801

12

C1805

GAP-OPEN

C1806

SC1U10V2KX-1GP

2

SC1U10V2KX-1G P

23

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

R1810

XTAL24_OUT_RXTAL24_OUT

1 2

0R0402-PAD

DVT1 0212 for Vendor suggest

SUSCLK_R

SRTC_RST # RTC_RST#

SCD1U16V2KX-3GP

12

EC1806

DY

C1801

12

SC15P50V2JN-2- GP

X1801

X1801 XTAL-24MHZ- 81-GP

XTAL-24MHZ- 81-GP

82.30004.841

4 1

C1802

12

SC15P50V2JN-2- GP

EC1803

DY

1 2

SC4D7P50V2BN-GP

SCD1U16V2KX-3GP

12

EC1807

DY

Title

CPU_(LPC/SPI/SMBUS/CL/CLK)

Size Document Number Rev

A2

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Starload SKL-U

1

A00

18 106Thursday, Feb ruary 25, 2016

A00

B B

3D3V_S0

RN1812

CLKREQ_PCIE#3

1

8

CLKREQ_PEG#0

2

7

CLKREQ_PCIE#4

3

6

4 5

SRN10KJ-6-G P

CLKREQ_PCIE#5

1

8

CLKREQ_PCIE#1

2

7

CLKREQ_PCIE#2

3

6

4 5

RN1813

SRN10KJ-6-G P

A A

5

WLAN

CLK_PCIE_VGA#[66] CLK_PCIE_VGA[66]

CLKREQ_PEG#0[66]

PEG_CLK1_CPU #[66] PEG_CLK1_CPU[66 ] CLKREQ_PCIE#1[66]

CLKREQ_PEG#0

CLKREQ_PCIE#2

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

4

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U-GP

071.SKYLA.000U

CLOCK SIGNALS

SKYLAKE_ULT

10 OF 20

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

C1804

SC3P50V2CN- 1-GP

F43 E43

SUSCLK_R SUSCLK

BA17

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

RTC_X1

AM18

RTC_X2

AM20

SRTC_RST #

AN18

RTC_RST#

AM16

3

1 2

R1815 10M R2J-L-GPR 1815 10MR2J- L-GP

X1802

2 3

1 2

XTAL-32D768KH Z-67-GP

DVT1 0212 for Vendor suggest (change 3p)

PCIE_CLK_XDP_N PCIE_CLK_XDP_P

R1813

1 2

0R0402-PAD

R1803

1 2

2K7R2F-GP

Intel recommend: 2.71k ohm 1%

RTCRST_O N[24]

SCD1U16V2KX-3GP

41

EC1808

DY

Vinaﬁx.com

5

Main Func = PCH

D D

Strap pin:

Port B / Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

Sampled at rising edge of PCH_PWROK

*

These two signals have weak inte rnal pull-down.

C C

PCH strap pin:

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled a fter PLTRST# deasserts

Low = Default High = Enable

*

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

The internal pull-down is disabled a fter PLTRST# deasserts

*

High = Disable

4

0 = Port B is not detected . 1 = Port B is detected.

0 = Port C is not detected. 1 = Port C is detected.

HDA_SDIN0[27]

SPKR[27]

HDA_SYNC HDA_BITCL K HDA_SDO UT

HDA_RST #

3D3V_S0

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

1KR2J-1-G P

1KR2J-1-G P R2006

R2006

1 2

DY

CPU1G

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U-GP

071.SKYLA.000U

SPKR

3

7 OF 20

SKYLAKE_ULT

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

2

CPU_A16 _TP

SD_RCOM P

KB_LED_ BL_DET_R [65]

1

TP1902

R1901

1 2

200R2F-L -GP

TPAD14-O P-GP

1

R1908 0R0402-P ADR1908 0R0402-PAD

HDA_COD EC_SYNC[27]

1

TP1903

TPAD14-O P-GP

EC1901

B B

A A

EC1901

SC10P50 V2JN-4GP

12

DY

HDA_COD EC_BITCLK

1 2

DY

HDA_RST #

EC1902

EC1902 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

5

TPAD14-O P-GP

TP1903

HDA_COD EC_BITCLK[27] HDA_COD EC_SDOUT[27]

ME_FW P_EC[2 4]

R1907,R1912 merge to RN1902 2015/10/06 modify

4

1 2

R1911 0R0402-P ADR1911 0R0402-PAD

1 2

SRN33J-5 -GP-U

2 3 1

RN1902

R1909 1KR2J-1-G PR1 909 1K R2J-1-GP

1 2

HDA_SYNC

HDA_RST #HDA_RST #_R

HDA_BITCL K HDA_SDO UT

4

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document N umber Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Starload SKL-U

1

A00

19 10 6Thursday, February 25, 20 16

A00

Vinaﬁx.com

Main Func = PCH

5

EC2002

12

SC1KP50V2KX-1G P

RN2009

1 2 3

OPS

SRN10KJ-5-G P

3D3V_S0

D D

R204851KR2J-1-GP

1 2

DY

R204951KR2J-1-GP

1 2

DY

R204210KR2J-3-GP

1 2

DY

R204310KR2J-3-GP R204310KR2J-3-GP

1 2

R204410KR2J-3-GP R204410KR2J-3-GP

1 2

R204510KR2J-3-GP R204510KR2J-3-GP

1 2

R204610KR2J-3-GP R204610KR2J-3-GP

1 2

R204710KR2J-3-GP R204710KR2J-3-GP

1 2

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

The signal has a weak internal pull-down.

C C

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

DGPU_HOLD _RST# [66]

DGPU_HOLD _RST#

4

DGPU_PW R_EN

LPSS_UART2_R XD LPSS_UART2_T XD

BLUETOOTH _EN DBC_PANEL_E N FFS_INT2 KB_DET# IR_CAMERA_DET # SPK_DET#

GPU_EVENT#[66]

GC6_FB_EN[66]

Change to Dummy 20150402

R2003 0R2J-2-GP

R2003 0R2J-2-GP R2004 0R2J-2-GP

R2004 0R2J-2-GP

PTP

PCH Prim

3D3V_S5_PCH

12

R2007

DY

1KR2J-1-GP

GPP_B18/GSPI0_MOSI

12

R2019

DY

1KR2J-1-GP

1 2

GC6_20

1 2

GC6_20

DBC_PANEL_E N[55]

I2C0_SDA_TCH_ PAD[65] I2C0_SCL_TCH_P AD[65]

BLUETOOTH _EN[66]

IR_CAMERA_DET #[55]

SIO_EXT_WAKE #[24]

TP2018

TP2018 TPAD14-OP-G P

TPAD14-OP-G P

SPK_DET#[29]

KB_DET#[65]

4

GPU_EVENT_M CP# GC6_FB_EN_MC P VRAM_ID1

GPP_B18/GSPI0_MOSI

1

LPSS_UART2_R XD LPSS_UART2_T XD

GPP_B22

BOARD_ID2

CPU1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U-GP

071.SKYLA.000U

3

LPSS ISH

Strap

SKYLAKE_ULT

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_D11/ISH_SPI_MISO GPP_D12/ISH_SPI_MOSI

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

6 OF 20

GPP_D9/ISH_SPI_CS#

GPP_D10/ISH_SPI_CLK

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

USB_UART_S EL_D9 DGPU_HOLD _RST#

RTC_DET#

I2C0_SDA I2C0_SCL

I2C1_SDA I2C1_SCL

1.8V Only

UART0_TXD UART0_RTS # UART0_CTS #

BOARD_ID1

UART1_RTS # UART1_CTS #

ISH_KB_DISABLE GSEN_INT1_ISH GSEN_INT2_ISH GSEN2_INT1_ISH GSEN2_INT2_ISH GYRO_INT_ISH GYRO_DRDY_ISH

TP2006 TPAD14-OP -GPT P2006 TPAD14-OP-G P

1

R2021 0R2J-2-GP

1 2

ISH

R2020 0R2J-2-GP

1 2

ISH

DGPU_PW R_EN [66]

1

TP2012 TPAD14-OP- GPT P2012 TPAD14-OP-GP

1

TP2013 TPAD14-OP- GPT P2013 TPAD14-OP-GP

1

TP2014 TPAD14-OP- GPT P2014 TPAD14-OP-GP

FFS_INT2 [70]

1

TP2016 TPAD14-OP -GPT P2016 TPAD14-OP-G P

1

TP2017 TPAD14-OP -GPT P2017 TPAD14-OP-G P

R2022 0R0402-PADR2022 0R0402-PAD

1 2

R2023 0R0402-PADR2023 0R0402-PAD

1 2

R2024 0R0402-PADR2024 0R0402-PAD

1 2

R2025 0R0402-PADR2025 0R0402-PAD

1 2

R2026 0R0402-PADR2026 0R0402-PAD

1 2

R2027 0R0402-PADR2027 0R0402-PAD

1 2

R2028 0R0402-PADR2028 0R0402-PAD

1 2

2

RTC_DET# [25]

SENSOR_I2C_SD A [55,69,70] SENSOR_I2C_SC L [55,69,70]

1

3D3V_S0

RN2007

SRN1KJ-7-G P

I2C0_SCL I2C0_SDA

I2C1_SCL I2C1_SDA

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

KB_DISABLE [24,69] GSEN_INT1 [55,69] GSEN_INT2 [55,69] GSEN2_INT1_C [69,70] GSEN2_INT2_C [69,70] GYRO_INT_C [69,70] GYRO_DRDY [55,69]

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

SRN1KJ-7-G P

1 2 3

SRN2K2J-1-G P

2 3

DY

1

RN2008

4

3D3V_S5_PCH

R2039 10KR2J-3-GP

1 2

DY

R2040 10KR2J-3-GPR204 0 10KR2J-3-GP

1 2

R2041 10KR2J-3-GPR204 1 10KR2J-3-GP

1 2

B B

A A

RTC_DET# SIO_EXT_WAKE #

5

ME_SUS_PW R_ACK_R [17]

3D3V_S0 3D3V_S0 3D3V_S0

12

BIOS strap pin:

R2005

OPS

10KR2J-3-GP

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

BIOS UMA/DIS Strap pin

UMA

DIS

BOARD_ID2 VRAM_ID1

4

UMA

12

GPP_C11

BOARD_ID2

0

1

3

12

R2029

DY

10KR2J-3-GP

12

R2030

10KR2J-3-GP

DY

BOARD_ID1

BBY

ROR

12

R2010

R2010 10KR2J-3-GP

10KR2J-3-GP

12

R2009

R2009 10KR2J-3-GP

10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(LPSS/ISH)

Starload SKL-U

1

A00

20 106Thursday, Feb ruary 25, 2016

A00

Vinaﬁx.com

Main Func = PCH

5

4

3

2

1

D D

C2120

SC1U10V2KX-1GP

12

EC2101

DY

SCD1U25V2KX-GP

1D5V_S0

+V3.3A_SIP

C C

B B

R2102

R2102 0R2J-2-GP

0R2J-2-GP

R2101

0R0402-PAD

1 2

+VCCMPHYGTA ON_1P0_LS_SIP

DY

+VCCMPHYGTA ON_1P0_LS_SIP

+VCCPRIM_COR E

+VCCDSW _1P0

+V1.00A_SIP

+VCCAMPHYPLL_1P 0

+VCCAPLL_1P0

+V1.00A_SIP

+VCCPDSW _3P3

+VCCPAZIO

+V3.3A_SIP

+V1.00A_SIP

+V3.3A_SIP

C2105

SC1U10V2KX-1GP

12

+V1.00A_SIP

C2106

SC1U10V2KX-1GP

CPU1O

CPU POWER 4 OF 4

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKYLAKE-U-GP

Layout Note:

1uF:

SCD1U16V2KX-3GP

C2105 near V19 C2106 near AK17 C2107 near AG15 C2109 near Y16 C2110 near T16 C2111 near AJ19

CPU POWER 4 OF 4

SKYLAKE_ULT

1.8V Only

071.SKYLA.000U

AB19 AB20

P18

2.57A

AF18 AF19

V20 V21

AL1

K17

N15 N16 N17

P15 P16

K15 L15

V15

AB17

Y18

AD17 AD18

AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

C2111

C2109

C2110

C2107

SC1U10V2KX-1GP

SCD1U16V2KX-3GP

SC1U10V2KX-1GP

12

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

+V1.8A_SIP

+V3.3A_SIP

AK15 AG15 Y16 Y15 T16 AF16

+V1.8A_SIP

AD15

+V3.3A_SIP

V19

T1

+V1.00A_SIP

AA1

+V1.8A_SIP

AK17

+V3.3A_SIP

AK19 BB14

VCCRTCE XT

BB10

A14

K19

L21

N20

L19

A10

V0.85A_VID0

AN11

V0.85A_VID1

AN13

C2108

SC1U10V2KX-1GP

12

DY

+VCCPRTC _3P3

C2112 SC D1U16V2KX-3GPC2112 SCD 1U16V2KX-3GP

1 2

+V1.00A_SIP

+VCCCLK2

+V1.00A_SIP

+VCCCLK4

+VCCCLK5

+V1.00A_SIP

1 1

+VCCDSW _1P0

C2103

C2102

C2103

SC1U10V2KX-1GP

12

TP2101 TPAD14-OP -GPT P2101 TPAD14-OP-G P TP2102 TPAD14-OP -GPT P2102 TPAD14-OP-G P

SC1U10V2KX-1GP

+V1.00A_SIP+VCCPRIM_COR E

C2101

12

+VCCPRTC _3P3

C2118

12

Layout Note:

1uF:

C2104

C2121

SC1U10V2KX-1GP

12

C2101 near AB19

SC1U10V2KX-1GP

C2104 near K17 C2116 near A10 C2121 near AL1

SC1U10V2KX-1GP

12

SCD1U16V2KX-3GP

12

Layout Note:

C2117

SC1U10V2KX-1GP

C2117

SC1U10V2KX-1GP

0.1uF: C2118 near AK19 1uF: C2117 near Ak19

R2106

1 2

0R0603-PAD

R2107

1 2

0R0603-PAD

R2108

1 2

0R0603-PAD

R2109

1 2

0R0603-PAD

R2110

1 2

0R0603-PAD

R2111

1 2

0R0603-PAD

+VCCPRTC _3P3RTC_AUX_S5

+VCCAMPHYPLL_1P 0+VCCMPHYGTA ON_1P0_LS_SIP

+VCCAPLL_1P0+V1.00A_SIP

+VCCCLK2+V1.00A_SIP

+VCCCLK4+V1.00A_SIP

+VCCCLK5+V1.00A_SIP

12

C2122

SC22U6D3V3MX-1-GPDYC2122

SC22U6D3V3MX-1-GP

Layout Note:

1uF: C2116 near A10 22uF: C2115 near K19 C2119 near N20 C2122 near L19

3

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(POWER1)

Starload SKL-U

1

21 106Thursday, Feb ruary 18, 2016

A00

+VCCAMPHYPLL_1P 0

12

DY

A A

5

C2113

SC22U6D3V3MX-1-GPDYC2113

SC22U6D3V3MX-1-GP

Layout Note:

22uF: C2113 near K15

+VCCAPLL_1P0 +V1.00A_SIP

12

DY

4

C2114

SC22U6D3V3MX-1-GPDYC2114

SC22U6D3V3MX-1-GP

Layout Note:

22uF: C2113 near K15

12

C2116

+VCCCLK2

SC1U10V2KX-1GP

+VCCCLK4

+VCCCLK5

C2119

SC22U6D3V3MX-1-GPDYC2119

SC22U6D3V3MX-1-GP

C2115

SC22U6D3V3MX-1-GPDYC2115

SC22U6D3V3MX-1-GP

12

DY

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

D D

CPU1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKYLAKE-U-GP

C C

071.SKYLA.000U

SKYLAKE_ULT

SPARE

20 OF 20

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

B B

Wistron Corporation

A A

Title

CPU_(RSVD)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Starload SKL-U

22 106Thursday, February 18, 2016

1

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

CPU1Q

GND 2 OF 3

CPU1P

GND 1 OF 3

D D

TP2309TPAD14-O P-GP TP2 309TPAD14-O P-GP TP2311TPAD14-O P-GP TP2 311TPAD14-O P-GP TP2310TPAD14-O P-GP TP2 310TPAD14-O P-GP

C C

B B

1 1 1

A5_TP A67_TP A70_TP

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

SKYLAKE-U-GP

071.SKYLA.000U

GND 1 OF 3

SKYLAKE_ULT

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AV1_TP

1

TP2307TPAD14-O P-GP TP2 307TPAD14-O P-GP

AV71_TP

1

TP2304TPAD14-O P-GP TP2 304TPAD14-O P-GP

B71_TP

1

TP2312TPAD14-O P-GP TP2 312TPAD14-O P-GP TP2305TPAD14-O P-GP TP2 305TPAD14-O P-GP

TP2306TPAD14-O P-GP TP2 306TPAD14-O P-GP

1

BA1_TP

BA2_TP

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38

AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW60 AW62 AW64 AW66

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

VSS

AV1

VSS

AV68

VSS

AV69

VSS

AV70

VSS

AV71

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

AW6

VSS VSS VSS VSS VSS

AW8

VSS

AY66

VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS

BA10

VSS

BA14

VSS

BA18

VSS

BA2

VSS

BA23

VSS

BA28

VSS

BA32

VSS

BA36

VSS

F68

VSS

BA45

VSS

SKYLAKE-U-GP

071.SKYLA.000U

GND 2 OF 3

SKYLAKE_ULT

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

BA71_TP

BB67_TP BB70_TP C1_TP

E71_TP

1

TP2303 T PAD14-OP-GPTP2 303 TPA D14-OP-GP

1

TP2302 T PAD14-OP-GPTP2 302 TPA D14-OP-GP

1

TP2301 T PAD14-OP-GPTP2 301 TPA D14-OP-GP

1

TP2308 T PAD14-OP-GPTP2 308 TPA D14-OP-GP

1

TP2313 T PAD14-OP-GPTP2 313 TPA D14-OP-GP

CPU1R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(VSS)

Starload SKL-U

1

23 10 6Thursday, February 18, 20 16

A00

Vinaﬁx.com

5

Main Func = KBC

1D0V_S5

R2402

1 2

0R0402-PAD

Just for Starload placement 2015/09/23 modify

D D

3D3V_S5_KBC

C C

SPI_CLK_ROM[18,25]

Layout Note:

Need very close to EC

RN2412

KSO0

1

8

KSO1

2

7

KSO2

3

6

KSO3

4 5

SRN100KJ-5-GP

RN2409

KSO4

1

8

KSO5

2

7

KSO6

3

6

KSO7

4 5

SRN100KJ-5-GP

RN2410

KSO8

1

8

KSO10

2

7

KSO11

3

6

KSO12

4 5

SRN100KJ-5-GP

RN2411

KSO13

1

8

KSO14

2

7

KSO15

3

6

KSO16

4 5

SRN100KJ-5-GP

PLT_RST#[17,66,68]

2015/09/22 modify

SPI_SO_ROM[18,25]

R2404,R2406 merge to RN2406 2015/10/06 modify

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

RN2406

1 2 3

SRN10J-8-GP

3D3V_S5_KBC

Layout Note:

Need very close to EC

4

3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC

R2446

EC_VTT

12

C2406

SCD1U16V2KX-3GP

RN2403

1 2 3 4 5

SRN10KJ-6-GP

RN2404

1 2 3 4 5

SRN10KJ-6-GP

AZ5725-01FDR7G-GP

EC_SPI_CLK EC_SPI_MISO

3D3V_S5_KBC

DY

8 7 6

EMI DVT1 0210

C2402

1 2

R2450

R2450 100KR2J-1-GP

100KR2J-1-GP

KSO9

R2449

R2449 100KR2J-1-GP

100KR2J-1-GP

KSI0 KSI1 KSI2 KSI3

KSI4 KSI5 KSI6 KSI7

12

C2416

C2421

C2420

SCD1U16V2KX-3GP

Just for Starload placement 2015/09/23 modify

CLKRUN#[18]

R2510

12

10KR2F-2-GP

DY

SPI_SI_ROM[18,25]

INT#_Typec[37] RTCRST_ON[18]

SPI_CS_ROM_N0[18,25]

SIO_SLP_S4#[17,40,54]

SATA_LED#[43,64]

PCH_ALW_ON[41]

SIO_SLP_S0#[17,60]

INT_TP#[4,65]

VOL_UP#[66]

ALL_SYS_PWRGD[17,40]

RESET_OUT#[17,26]

1 2

0R0603-PAD

12

C2411

C2412

SCD1U16V2KX-3GP

KSO[0..16][65]

KSI[0..7][65]

CLK_TP_SIO[65] DAT_TP_SIO[65]

SIO_PWRBTN#[17]

PCH_RSMRST#[17]

LPC_LAD[3..0][18,68]

LPC_LFRAME#[18,68]

CLK_PCI_LPC_MEC[18]

SERIRQ[18]

SIO_RCIN#[18]

1 2

12

C2414

C2410

C2413

SCD1U16V2KX-3GP

C2428

SCD1U16V2KX-3GP

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 CAP_LED#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

SIO_EXT_SMI# TP_EN#

SIO_EXT_SCI#

EC_SPI_CLK EC_SPI_MOSI

R240510R2F-L-GP R240510R2F-L-GP

EC_SPI_MISO

USB_EN#

XTAL2 XTAL1

2015/09/22 modify

X2401

SC10P50V2JN-4GP

1 2

C2425

XTAL-32D768KHZ-83-GP

082.30003.0131

1 2

B B

R2418

R2418 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2408

CMP_VOUT1

R2417

100KR2J-1-GP

A A

Q2408

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

5

12

DY

2015/09/22 modify

Microchip: Use CL=9p Xtal，C = 10p

H_PROCHOT# [4,44,46]

12

C2403

AZ5725-01FDR7G-GP

EMI DVT1 0210

SC10P50V2JN-4GP

SC10P50V2JN-4GP C2424

C2424

1 2

4

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

RTC_AUX_S5

1 2

ECVBAT

12

KBC24

2

GPIO02 7/KSO00 /PVT_I O1

14

GPIO01 5/KSO01 /PVT_C S#

15

GPIO01 6/KSO02 /PVT_S CLK

16

GPIO01 7/KSO03 /PVT_I O0

37

GPIO04 5/BCM_INT 1#/KSO 04

38

GPIO04 6/BCM_DA T1/KSO 05

39

GPIO04 7/BCM_CL K1/KSO 06

50

GPIO02 5/KSO07 /PVT_I O2

46

GPIO05 5/PWM2/K SO08/P VT_IO3

68

GPIO10 2/KSO09 /CR_ST RAP

72

GPIO10 6/KSO10

74

GPIO11 0/KSO11

75

GPIO11 1/KSO12

76

GPIO11 2/PS2_C LK1A/K SO13

77

GPIO11 3/PS2_D AT1A/K SO14

86

GPIO12 5/KSO15

92

GPIO13 2/KSO16

93

GPIO14 0/KSO17

98

GPIO14 3/KSI0/D TR#

99

GPIO14 4/KSI1/D CD#

6

GPIO00 5/SMB00_ DATA/S MB00_DA TA18/K SI2

7

GPIO00 6/SMB00_ CLK/SMB0 0_CLK 18/KSI 3

104

GPIO14 7/KSI4/D SR#

105

GPIO15 0/KSI5/R I#

107

GPIO15 1/KSI6/R TS#

108

GPIO15 2/KSI7/C TS#

78

GPIO11 4/PS2_C LK0

79

GPIO11 5/PS2_D AT0

52

GPIO02 6/PS2_C LK1B

88

GPIO12 7/PS2_D AT1B

59

GPIO04 0/LAD0

60

GPIO04 1/LAD1

61

GPIO04 2/LAD2

62

GPIO04 3/LAD3

58

GPIO04 4/LFRAME #

56

GPIO06 4/LRESE T#

57

GPIO03 4/PCI_C LK

63

GPIO06 7/CLKRUN#

55

GPIO06 3/SER_I RQ

10

GPIO01 1/SMI#/EMI _INT#

49

GPIO06 0/KBRST

53

GPIO06 1/LPCPD #

66

GPIO10 0/EC_SC I#

32

GPIO12 6/SHD_SC LK

28

GPIO13 3/SHD_IO 0

29

GPIO13 4/SHD_IO 1

30

GPIO13 5/SHD_IO 2

31

GPIO13 6/SHD_IO 3

27

GPIO12 3/SHD_CS #

67

GPIO10 1/SPI_C LK

69

GPIO10 3/SPI_I O0

71

GPIO10 5/SPI_I O1

42

GPIO05 2/SPI_I O2

33

GPIO06 2/SPI_I O3

3

GPIO00 1/SPI_C S#/32K HZ_OUT

13

RESET_ IN#/GPIO 014

48

GPIO05 7/VCC_P WRGD

73

GPIO10 7/RESET _OUT#

125

XTAL2

123

XTAL1

071.01404.0B0E

3D3V_S5_KBC

R2480

R2480 100KR2J-1-GP

100KR2J-1-GP

ICSP_CLOCK

DY

R2414

ICSP_DATA

1 2

4K7R2J-2-GP

HOST_DEBUG_TX ICSP_CLR

SMBCLK1 SMBDA1

USBCHARGER_CB0 PCH_ALW_ON

PBAT_PRES#

SIO_EXT_SCI#

SIO_EXT_SMI#

4

R2472

R2472 0R0402-PAD

0R0402-PAD

43

103

122

VTR5VTR19VTR

VTR65VTR82VTR

VBAT

GPIO00 7/SMB01_ DATA/S MB01_DA TA18

GPIO01 0/SMB01_ CLK/SMB0 1_CLK 18

GPIO01 2/SMB02_ DATA/S MB02_DA TA18

GPIO01 3/SMB02_ CLK/SMB0 2_CLK 18

GPIO13 0/SMB03_ DATA/S MB03_DA TA18

GPIO13 1/SMB03_ CLK/SMB0 3_CLK 18

GPIO14 1/SMB04_ DATA/S MB04_DA TA18

GPIO14 2/SMB04_ CLK/SMB0 4_CLK 18

GPIO05 0/TACH0 GPIO05 1/TACH1

GPIO05 3/PWM0 GPIO05 4/PWM1

GPIO05 6/PWM3 GPIO03 0/BCM_INT 0#/PW M4 GPIO03 1/BCM_DA T0/PW M5 GPIO03 2/BCM_CL K0/PW M6

GPIO00 2/PWM7

GPIO15 7/LED0/T ST_CL K_OUT

GPIO11 6/TFDP_ DATA/UA RT_RX

GPIO11 7/TFDP_ CLK/UAR T_TX

GPIO03 5/SB-TSI _CLK

GPIO03 3/PECI_ DAT/SB _TSI_D AT

GPIO14 5/ICSP_ CLOCK

GPIO14 6/ICSP_ DATA

SYSPWR _PRES/G PIO00 3

VCI_OUT /GPIO03 6 VCI_IN1 #/GPIO1 62 VCI_IN0 #/GPIO1 63

VCI_OV RD_IN/GP IO164

GPIO16 0/DAC_0

GPIO16 1/DAC_1

GPIO12 4/CMP_VO UT0

GPIO02 0/CMP_VI N0

GPIO16 5/CMP_VR EF0

GPIO12 0/CMP_VO UT1

GPIO02 1/CMP_VI N1

GPIO16 6/CMP_VR EF1/UAR T_CLK

GPIO02 4/CMP_ST RAP0

GPIO02 3/ADC6/A 20M

VR_CAP18VSS17VSS51AVSS

VSS_VBAT

VSS

VSS64VSS

MEC1404-NU-D0-1-GP-U

84

112

124

100

EC_AGND

VR_CAP

12

C2418

SC1U10V2KX-1GP

R2445

1 2

0R0402-PAD

R2473 10KR2J-3-GPR2473 10KR2J-3-GP R2495 100KR2J-1-GP

R2495 100KR2J-1-GP

R2415 10KR2J-3-GPR2415 10KR2J-3-GP

Just for Starload placement 2015/09/23 modify

Layout Note:

EC_AGND

Connect GND and AGND planes via either 0R resistor or connect directly.

RN2402

1234

SRN4K7J-8-GP

1 2 1 2

DS3

1 2

VTR_33 _18

GPIO15 6/LED1 GPIO10 4/LED2

VREF_C PU

ICSP_MC LR

BGPO/GP IO004

DAC_VR EF

GPIO02 2/ADC5 GPIO15 3/ADC4 GPIO15 4/ADC3 GPIO15 5/ADC2 GPIO12 2/ADC1 GPIO12 1/ADC0

ADC_VR EF

3D3V_S5_KBC

12

C2423

SCD1U16V2KX-3GP

54

SMBDA1

8

SMBCLK1

9

SMBDA2

11

SMBCLK2

12

SMBDA3

89

SMBCLK3

91 96 97

FAN1_TACH

40 41

44 45

47

L_BKLT_EN_EC

34 35 36 4

BAT1_LED#

1

BAT2_LED#

106 70

80

HOST_DEBUG_TX

81

90

PECI_EC

94

EC_VTT

95

ICSP_CLOCK

101

ICSP_DATA

102

ICSP_CLR

87

119

+3VLP

120

ALWON

121

KB_CLOSE#_2_R

126

POWER_SW_IN#

127 128

23

DGPU_PWROK_KBC

24 22

CMP_VOUT0

85

CMP_VIN0

20

VCREF0

25

CMP_VOUT1

83

HW_ACAVIN_NB#

21

LCD_TST_EN

26

118 117 116

MODEL_ID

109

I_ADP

110

BOARD_ID

111

I_SYS

113

I_BATT

114 115

3D3V_S5_KBC

EC_AGND

Dummy R2422 & C2427 by EC control PCH_DPWROK 20150416

DB3

7 1

2 3

LPC

4 5 6 8

20.K0691.006

ACES-CON6-58-GP

SIO_EXT_SCI# [16]

SIO_EXT_SMI# [8]

R2462

R2462 0R0402-PAD

0R0402-PAD

1 2

3D3V_AUX_KBC_33

C2422

SCD1U16V2KX-3GP

12

R2443

R2443 33KR2F-GP

33KR2F-GP

DVT2

PCB_REV

BOARD_ID

12

R2444

C2408

100KR2F-L1-GP

1 2

EC_AGND

SCD1U16V2KX-3GP

For Typec SMBUS

1 2

SC100P50V2JN-3GP

R2437

C2405

43R2J-GP

12

DY

Need very close to EC, PDG: <0.5 inches.

R2471 0R2J-2-GP

12

OPS

C2429SCD1U16V2KX-3GP C2429SCD1U16V2KX-3GP

R2470 0R0402-PADR2470 0R0402-PAD

3D3V_S5_KBC

1 2

12

R2494 0R2J-2-GP

12

DY

Reserve resistor, 20141118

I_SYS

EC_AGND

12

C2427

I_BATT

C2441

EC_AGND

USBCHARGER_CB0 [34]

3

R2430

R2430 10KR2J-3-GP

10KR2J-3-GP

3D3V_S5_KBC

1 2

12

R2448

SCD01U50V2KX-1GP

KB_DISABLE [20,69]

PCH_DPWROK [17]

P_SYS [44,46]

BOOST_MON [44]

1 2

DY

RN2407

SRN10KJ-5-GP

LID_CL_SIO#

100.0K

100.0KRese rved 174.0K

3D3V_S0

1 2

Vref = 1.117 temp around 85

10KR2F-2-GP

2015/09/15 modify

HDMI_EC_DET# [57]

1234

D2402

D2402 RB751V-40H-GP

RB751V-40H-GP

K A

83.R2004.G8F

EVT (SA)

DVT1 (SB)

DVT2 (SC)

DVT3 (SD)

X-build (1)

Reserved

Reserved 1.65V

Reserved 1.358V100.0K 143.0K

Reserved

SMBDA1 [43,44] SMBCLK1 [43,44]

SYS_PWROK [17] PBAT_PRES# [43]

LID_CL_SIO# [70]

BKLGT_PWM [65] BEEP [27]

FAN1_PWM [26]

EC_WAKE# [17] PS_ID [43] VOL_DOWN# [66]

SIO_SLP_S3# [17,27,40,51,54]

ME_FWP_EC [19]

PTP_DIS# [65] H_PECI [4]

EC_MUTE# [27]

ALWON [40]

ACOK_IN [44]

USB_CHG_EN [34]

CMP_VOUT0 [26] CMP_VIN0_R [26]

PANEL_BKEN_EC [55] SIO_EXT_WAKE# [20]

CMP_VIN0_R [26]

DY

SC2200P50V2KX-2GP

12

DY

R2424

DGPU_PWROK [66]

20KR2F-L-GP

C2409

12

R2403 0R0402-PADR2403 0R0402-PAD

12

R2497

12

DY

0R2J-2-GP

R2422

12

DY

330R2J-3-GP

R2407 0R0402-PADR2407 0R0402-PAD

12

R2423

12

DY

330R2J-3-GP

Layout Note:

Need very close to EC

SC2200P50V2KX-2GP

Touch Panel PH internally.

TOUCH_PANEL_INTR#

R2429 10KR2J-3-GP

R2498,R2499 merge to RN2407 2015/10/06 modify

VOL_UP# VOL_DOWN#

Power Switch Logic(PSL)

KBC_PWRBTN#[66]

1 2

X00_0804

3

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORBOARD_ID VERSION A/D

3.0V

10.0K

2.75V

20.0K

2.48V

33.0K

47.0K

2.24V

64.9K

2.0V

76.8

1.87V

100.0K

1.204V

1.048V215.0K100.0 K

Change symbol part number, be cause origin symbol is DELL O BS part

D2403

D2403 RB751V-40H-GP

RB751V-40H-GP

KA

FAN_TACH1 [26]

83.R2004.G8F

eDP backlight Control from PCH

L_BKLT_EN_EC

3D3V_AUX_S5

12

R2463

R2463 1KR2J-1-GP

1KR2J-1-GP

12

R2454

R2454 100KR2J-1-GP

100KR2J-1-GP

HW_ACAVIN_NB#

For Typec charge detect modfy 2016/01/04

3D3V_S0

3D3V_S5

Just for Starload placement 2015/09/23 modify

LCD_TST_EN

USB_EN#

R2474 0R2J-2-GP

12

DY

R2475 0R0402-PADR2475 0R0402-PAD

12

I_ADP

12

C2435

EC_AGND

SC2200P50V2KX-2GP

Move schematic, 20141118

OVER_CURRENT_P8# [66]

DC_IN_OK [43]

12

R2421

330R2J-3-GP

20150116 2040Change symbol part number, be cause origin symbol is DELL O BS part

TOUCH_PANEL_INTR# [4,55]

ECVBAT

R2451

R2451 100KR2J-1-GP

R2432

1KR2J-1-GP

100KR2J-1-GP

1 2

POWER_SW_IN#

C2426

12

SC1U10V2KX-1GP

12

R2436

R2436 100KR2J-1-GP

100KR2J-1-GP

2

R2435

1 2

0R0402-PAD

R2419

1 2

0R0402-PAD

3D3V_S5

AD_IA [44]

2

12

R2434

R2434 100KR2J-1-GP

100KR2J-1-GP

MODEL_ID

L_BKLT_EN [8]

LCD_TST [55]

LCD_TST_EN [55]

USB_EN# [35,66]

64K9R2F-1-GP

C2407

SCD1U16V2KX-3GP

R2442

MODEL_ID

1 2

EC_AGND

KB_CLOSE#_2[70]

3D3V_S5

CHG_AMBER_LED#[64]

Q2412 and Q2413 merge

SMBDA2

SMBCLK2

MODEL_ID_DET(GPIO07) PULL-HIGH RESISTORPULL-LOW RESISTOR

Starlord_UMA_ROR

12

R2441

R2441 100KR2F-L1-GP

100KR2F-L1-GP

3D3V_S5_KBC

TBD

Starload_UMA_BBY

TBD

Starload_DIS_BBY Starload_17"_UMA

TBD TBD

Q2415

S

G

BAT1_LED#

3D3V_S5 3D3V_S5

24014/12/23 mod ify

3D3V_S0

R2489

R2489 100KR2J-1-GP

100KR2J-1-GP

1 2

CAP_LED#

SMBDA2

SMBCLK2

CCG2_I2C_SDA[37]

CCG2_I2C_SCL[37]

S

G

3D3V_S0

RN2603

SRN2K2J-1-GP

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

R2447 0R2J-2-GP

R2459 0R2J-2-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

Q2414

3D3V_S5_KBC

DS3

84.2N702.A3F

1 2

NON DS3

1 2

NON DS3

D

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Q2416

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

D

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

1

23

4

3 4

2

1

KB_CLOSE#_2_R

2N7002K-2-GP

84.2N702.J31

2N7002K-2-GP

84.2N702.J31

3D3V_S5_PCH

2N7002KDW-GP

6

DS3

Q2604

3D3V_S5_KBC

Q2605

TypeC

2N7002KDW-GP

1

100.0K

22.1K(64.22125 .6DL)

32.4K(64.32425 .6DL)

100.0K

49.9K(64.49925 .6DL) 2.201V

100.0K

64.9K(64.64925 .6DL)

100.0K

120K(64.12035 .6DL) 200K(64.20035 .6DL)

ECVBAT

R2496

R2496 100KR2J-1-GP

100KR2J-1-GP

1 2

LID_CL_SIO#

BATT_WHITE_LED# [64]

BAT2_LED#

1

2345

SML1_SMBDATA

SML1_SMBCLK

5

6

TP_EN#[65]

CAP_LED#_R [65]

SML1_SMBDATA [18,26,66]

SML1_SMBCLK [18,26,66]

Reserve by NON DS3 function 20150413

3D3V_S5_KBC

RN2604

SRN2K2J-1-GP

SMBDA3

SMBCLK3

Title

KBC Nuvoton NPCE285PA0DX

Size Document Number Rev

Size Document Number Rev A1

A1

Starload SKL-U

Thursday, February 25, 2016

Date: Sheet of

1

VOLTAGE

3.0V10.0K(64.10025.6D L)

2.702V

2.492V

2.001V

1.709V9 3.1K(64.93125. 6DL)

1.499V

1.099V100.0K

3D3V_S5

RN2405

1

8

2

7

3

6

4 5

SRN100KJ-5-GP

1

23

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

24 106

A00

Vinaﬁx.com

5

Main Func = SPI Flash

R2501

4K7R2J-2 -GP

SPI_WP _ROM_R

12

DY

3D3V_S5 _PCH

1 2

SPI Flash ROM(8M) for PCH

D D

SPI_CS_RO M_N0 SPI_SO_RO M_R SPI_WP _ROM_R

SPI_CS_RO M_N0[18,24]

SPI_SO_RO M[1 8,24] SPI_WP _ROM[18]

C C

SKT251

1

8

2

7

3 6

DY

4

5

SKT-G617 9HT0321-001-GP

62.10089.011

SRN10J-8 -GP

2 3 1

RN2503

R2507,R2508 merge to RN2503 2015/10/06 modify

3D3V_SP IVCC1

SPI_HOLD_ ROM_R SPI_CLK_R OM_R SPI_SI_ROM_R

EC2502

SC4D7P5 0V2BN-GP

SPI_SO_RO M_R SPI_WP _ROM_R

4

SPI25

1

S#

2

DQ1 W#/DQ2 VSS

HOLD#/DQ3

3 4

N25Q128 A13ESEC0F-GP

72.25128.0B1

VCC

DQ0

C

8 7 6 5

SC10U10 V5KX-2GP

3D3V_SP IVCC1

SPI_HOLD_ ROM_RSPI_SO_RO M_R SPI_CLK_R OM_R SPI_SI_ROM_R

12

DY

EC2501

SC4D7P50V2BN-GP

3D3V_S5 _PCH

3D3V_SP IVCC1

12

C2501

DY

R2503 10R2F-L-G PR2503 10R2F-L-G P

1 2

12

EC2503

DY

SC10P50 V2JN-4GP

3

12

R2515

R2515 0R0402-P AD

0R0402-P AD

12

C2502

DY

SCD1U16 V2KX-3GP

Change to Dummy 20150402

SPI_HOLD_ ROM [18 ]

SPI_CLK_R OM_R SPI_SI_ROM_R

RN2502

1

4

2 3

SRN10J-8 -GP

R2505,R2506 merge to RN2502 2015/10/06 modify

2

72.25128.0B1

SPI_CLK_R OM [18,24] SPI_SI_ROM [18,24]

QUAD/DUAL fast read DUAL fast readSource

O

O O

1

SFDP

O

B B

Main Func = RTC

RTC_AUX _S5+RTC_VC C 3D3V_AU X_S5

D2501

1

3

2

BAS40C-2 -GP

75.00040.07D

2nd = 75.00040.C7D

3rd = 75.00040.A7D

Q2505

A A

5

12

R2504

R2504 10MR2J-L -GP

10MR2J-L -GP

4

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

D

12

C2503

C2503 SCD47U1 0V2KX-GP

SCD47U1 0V2KX-GP

RTC_DET # [20]

3

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Thursday, February 25, 20 16

Date: Sheet of

2

Date: Sheet of

Flash/RTC

Starload SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

25 10 6

1

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = Thermal Sensor

3D3V_S0 3D3V_S0

1

23

RN2602

RN2602 SRN2K2J-1-G P

SRN2K2J-1-G P

7718

3D3V_S0

12

C2601

B

DY

12

C2606

C2606 SC470P50V3JN-2 GP

SC470P50V3JN-2 GP

DY

C2601

7718

SC10U6D3V3MX-GP

NCT7718_DXP

NCT7718_DXN

C2602

C2602 SCD1U16V2KX- 3GP

SCD1U16V2KX- 3GP

12

C2607

7718

SC2200P50V2KX-2G P

D D

84.03904.P11

2nd = 84.03904.T11

C

Q2603

CH3904PT-GP

7718

E

2.System Sensor, Put on palm rest

Layout Note:

C2607 close THM2601

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

3D3V_S0

C C

R2603 7K5R2F-1-GP

1 2

7718

R2604 7K5R2F-1-GP

1 2

7718

B B

ALERT#

T_CRIT#

SML1_SMBDATA[18,24,66]

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

SML1_SMBCLK[18,24,66]

THM261

1

VDD

SCL

2

7718

D+

SDA

3

DT_CRIT#4GND

NCT7718W -GP

74.07718.0B9

RESET_OUT #[17,24]

THERM_SYS_SHD N#

ALERT#

T_CRIT#

12

0R2J-2-GP

DY

R2601

2N7002KDW -GP

6

7718

Q2601

8 7

ALERT#

6 5

1

2345

Q2602

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

7718

4

12

DY

THM_SML1_DAT A

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DAT A

12

DY

C2609

C2608

SCD1U16V2KX-3GP

12

DY

C2610

SCD1U16V2KX-3GP

1 2

DY

R2615 0R2J- 2-GP

KBC T8

CMP_VOUT0

DY

PURE_HW _SHUTDOW N# [40]

DVT1 0210, for T8 function

3D3V_S5

R2602

1 2

0R0402-PAD

3D3V_S5_KBC3D 3V_S0

R2609

R2609 10R2F-L-GP

10R2F-L-GP

R2610

NTC-100K-8- GP

12

R2607 10KR2J-3-GPR2607 10K R2J-3-GP

1 2

R2608

R2608 27KR2F-L-GP

27KR2F-L-GP

DVT1 0210, for T8 function

C2612

12

SCD1U16V2KX- 3GP

Short pad change to 0 ohm , 20141118

Close to KBC VD_IN1 for system thermal sensorClose to Thermal sensor

VD_IN1_C

12

C2613

SC100P50V2JN-3 GP

5V_S0

FAN_TACH 1[24]

FAN1_PWM[ 24]

CMP_VOUT0 [24]

CMP_VIN0_R [24]

R2611

1 2

0R0402-PAD

R2612

1 2

0R0402-PAD

PWM FAN1

FAN_VCC_1

C2604

SC4D7U6D3V3KX-GP

C2604

SC4D7U6D3V3KX-GP

C2605

SCD1U16V2KX-3GP

C2605

SCD1U16V2KX-3GP

KA

D2601

RB551V30-1-GPDYD2601

RB551V30-1-GP

DY

AFTP2604AFTP2604

12

DY

FAN_VCC_1

FAN_TACH 1_C FAN_PWM 1_C

FAN_TACH 1_C

FAN_PWM 1_C

FAN_VCC_1

12

R26130R0402-PAD R26130R0402- PAD

1 2

R26140R0402-PAD R26140R0402- PAD

1 2

Layout Note:

Signal Routing Guideline: Trace width = 15mil

C2603

SC2200P50V2KX-2GPDYC2603

SC2200P50V2KX-2GP

FAN1

5

1

2 3 4

6

ACES-CON 4-29-GP

1

20.F1639.004

AFTP2601AFTP2601

1

AFTP2602AFTP2602

1

AFTP2603AFTP2603

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Number Rev

Size Document Number Rev A2

A2

Starload SKL-U

Thursday, Feb ruary 25, 2016

Thursday, Feb ruary 25, 2016 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

1

26 106

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = Audio

moat

5V_S0+5V_A VDD

R2703

3D3V_S0

1 2

0R0805-PAD

D D

C C

3D3V_S0

1D8V_S0

1D5V_S0

R2724

1 2

0R0402-PAD

moat

R2713 0R0402-PADR2713 0R0402-PAD

1 2

R2705

1 2

DY

R2710 0R2J-2-GP

1 2

DY

0R0805-PAD

1.5A

5V_S0 + 5V_PVDD

R2702

1 2

0R0805-PAD

R2704

1 2

0R0805-PAD

0R2J-2-GP

R2731

C2701

12

SCD1U16V2KX-3GP

Layout Note:

Close pin41

+3V_1D8V_AVDD

12

C2715

SC4D7U6D3V 3KX-GP

AUD_AGND

+3V_AVDD

CPVDD

12

C2724

SC4D7U6D3V 3KX-GP

Close pin 21

C2709

C2707

C2708

C2706

12

SC10U6D3V3MX-GP

Speaker trace width >40mil @ 2W4ohm speaker power

Close pin16

12

SCD1U16V2KX-3GP

12

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

Layout Note:

Close pin46

AUD_SENSE_A

AUD_AGND

Layout Note:

R2722

100KR2J-1-GP

AUD_AGND

Azalia I/F EMI

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

EC2708

EC2709

SC33P50V2JN-3GP

EMI suggest change to 33p

B B

2015/12/02

EC2709

12

DY

SC33P50V2JN-3G P

DMIC_DATA_R

SC33P50V2JN-3GP

+3V_AVDD

R2728

12

DY

100KR2J-1-GP

EC_MUTE#[24]

EC2701

12

DY

R2708

1 2

0R0402-PAD

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

Layout Note:

AUD_AGND

1 2

0R0402-PAD

C2705

1 2

R2725

Layout Note:

AUD_SENSE[29]

C2716

SC4D7U6D3V 3KX-GP

DMIC_DATA[55]

1 2

AUD_VREF

LDO1_CAP

+5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

+3V_AVDD

12

SC10U6D3V3MX- GP

+3V_AVDD

DMIC_CLK[55]

SC33P50V2JN-3G P

SC2D2U10V3KX- 1GP

C2702

1 2

R2711 100KR2J -1-GPR2 711 100KR2J-1-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

5V_S5

1 2

0R0402-PAD

Place close to Pin 1

EAPD#

C2723

DY

Close pin6

R2723

12

TP2702TP2702

RING2[29]

SLEEVE[29]

AUD_PC_BEEPAUD_PC_BEEP_R

LINE1_R[29]

LINE1_L[29]

5V_STB

R2709

200KR2F-L-GP

1

C2717

12

SCD1U16V2KX- 3GP

HDA27

37

38

39

40

41

42

43

44

45

46

47

48

49

ALC3253-CG-G P

12

COMBO-GPI

AVSS1

VREF

LDO1-CAP

AVDD1

PVDD1

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

PVDD2

5VSTB/AUXMODE

HP2/LINE2-JD/JD2

GND

AUD_SENSE_A

R27140R0402-PAD R27140R0402- PAD

1 2

R27160R0402-PAD R27160R 0402-PAD

1 2

MIC_CAP

C2713SC10U6D3V3MX-GP C2713SC10U6D3V3MX-G P

12

30

31

32

33

34

35

36

PCBEEP

MIC2-CAP

LINE2-L/PORT-E-L

LINE1-L/PORT-C-L

LINE2-R/PORT-E-R

LINE1-R/PORT-C-R

MIC2-R/PORT-F-R/SLEEVE

HP/LINE1-JD/JD11SPDIF-OUT/GPIO2/DMIC-DATA342PD3DVDD4GPIO0/DMIC-DATA125GPIO1/DMIC-CLK6DC-DET/EAPD7BCLK8SYNC9SDATA-IN10SDATA-OUT11DVDD-IO

EAPD#

DMIC_DATA_R

DMIC_CLK_R

DVSS

12

0R2J-2-GP

DY

R2732

26

27

28

29

MIC2-VREFO-L

MIC2-VREFO-R

HPOUT-L/PORT-I-L

MIC2-L/PORT-F-L/RING2

HPOUT2-R/PORT-B-R

HPOUT2-L/PORT-B-L

LINE1-VREFO-R-E/MONO

LINE1-VREFO-L-E

CODEC_SD OUT_R

HDA_CODE C_SDIN0

HDA_CODE C_SYNC

CODEC_BITC LK_R

25

CPVEE

HPOUT-R/PORT-I-R

CPVDD

AVSS2

LDO2-CAP

AVDD2

LDO3-CAP

12

C2719SCD1U16V 2KX-3GP C2719S CD1U16V2KX-3GP

12

CBN

CBP

+3V_AVDD

CPVEE

24

CBN

23

CBP

22

21

20

19

18

LDO2_CAP

17

16

15

14

13

MIC2_VREFO_R [29]

MIC2_VREFO_L [29]

AUD_HP1_JAC K_L [29]

AUD_HP1_JAC K_R [29]

C2703 SC1 U10V3KX-3GPC2703 SC 1U10V3KX-3GP

12

CPVDD

C2712 SC10U6D3V3MX- GPC2712 SC10U 6D3V3MX-GP

+3V_1D8V_AVDD

LDO3_CAP

C2718

12

SC10U6D3V3MX-GP

R2719 0R0402-PA DR2719 0R0 402-PAD

12

R2718 0R0402-PA DR2718 0R0 402-PAD

12

R2720 0R0402-PA DR2720 0R0 402-PAD

12

LINE1_VREFO_R [29]

LINE1_VREFO_L [29]

moat

HDA_CODE C_SDOUT [19]

HDA_SDIN0 [19]

HDA_CODE C_SYNC [19]

HDA_CODE C_BITCLK [19]

C2710

12

C2711

SCD1U16V2KX-3GP

AUD_AGND

SPKR[19]

BEEP[24]

R2703

1 2

0R0603-PAD

12

Layout Note:

Place close to Pin 40

AUD_AGND

SC4D7U6D3V3KX-GP

C2704

C2704 SC1U10V3KX-3G P

SC1U10V3KX-3G P

1 2

AUD_AGND

RN2701

2 3 1

SRN1KJ-7-G P

4

moat

EC2707 SC1KP50V2KX-1GP

1 2

DY

EC2706 SC1KP50V2KX-1GP

1 2

DY

EC2705 SCD1U25V2KX-GP

1 2

DY

EC2704 SC1KP50V2KX-1GP

1 2

DY

EC2703 SCD1U25V2KX-GP

1 2

DY

AUD_AGND

R2706

1 2

0R0805-PAD

Layout Note:

AUD_AGND

HDA_SPKR_R

2

KBC_BEEP_R

1

BAT54C-7-F- 3-GP

75.00054.E7D

2nd = 83.R2003.W81

3rd = 75.00054.A7D

4th = 83.R2003.V81

D2701

AUD_PC_BEEP _C

3

12

C2720

1 2

R2717

R2717 2K2R2J-2-GP

2K2R2J-2-GP

AUD_PC_BEEP _R

SCD1U16V2KX- 3GP

1D8V_S0+V1.8A

Q2702

DMP2130L-7-GP

S

C2714

C2714 SC1U10V2KX-1G P

SC1U10V2KX-1G P

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

DMP2130L-7-GP

D

G

12

C2721

SCD1U16V2KX-3GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Audio Codec ALC3246

Starload SKL-U

1

27 106Thursday, Fe bruary 25, 2016

A00

150mA

12

C2722

R2726

R2726 10KR2J-3-GP

10KR2J-3-GP

Q2701

SIO_SLP_S3#[17,24,40,51,54]

A A

G

S

5

2N7002K-2-GP

SCD1U16V2KX-3GP

1D8V_EN#

D

R2727

1 2

20KR2J-L2-GP

12

1D8V_EN_R#

Vinaﬁx.com

5

D D

C C

4

3

2

1

B B

A A

Title

Size Document Number Rev

A1

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Starload SKL-U

A00

28 106Thursday, February 18, 2016

Vinaﬁx.com

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

(

EL2902 BLM15PD 121SN1D-GP

D D

AUD_SPK _L+[27]

AUD_SPK _L-[27] AUD_SPK _R-[27 ] AUD_SPK _R+[27]

12

EL2902 BLM15PD 121SN1D-GP

EL2901 BLM15PD 121SN1D-GP

EL2901 BLM15PD 121SN1D-GP EL2903 BLM15PD 121SN1D-GP

EL2903 BLM15PD 121SN1D-GP EL2904 BLM15PD 121SN1D-GP

EL2904 BLM15PD 121SN1D-GP

12

(

( (

(

12

at high frequencies

at high frequencies Resistance element becomes dominant

Resistance element becomes dominant

12 12

at high frequencies

at high frequencies Resistance element becomes dominant

Resistance element becomes dominant

12

at high frequencies

at high frequencies Resistance element becomes dominant

Resistance element becomes dominant

at high frequencies

at high frequencies Resistance element becomes dominant

Resistance element becomes dominant

(

( (

(

AUD_SPK _L+_C

AUD_SPK _L-_C AUD_SPK _R-_C AUD_SPK _R+_C

12

Speaker

12

SPK1

7

1

2 3 4

SPK_DET #[20 ]

12

5 6

8

HR-CON6-1 -GP-U

20.F1804.006

CONN Pin

Pin1

Net name

SPK_L+

Pin2 SPK_L-

Pin3

Pin4

Pin5

SPK_R-

SPK_R+

SPK_DET#

Pin6 GND

EC2909

EC2904

EC2902

EC2901

SC100P50V2JN-3GP

EC2904

EC2903

AUD_SPK _L-_C

AUD_SPK _L+_C

SC100P50V2JN-3GP

AUD_SPK _R-_C

AUD_SPK _R+_C

AFTP290 1A FTP2901

1

AFTP290 2A FTP2902

1

AFTP290 3A FTP2903

1

AFTP290 4A FTP2904

1

EC2910

SC100P50V2JN-3GP

EC2909

EC2911

EC2912

SC100P50V2JN-3GP

EC2911

SC100P50V2JN-3GP

2015/11/26 modify by EMI suggest

C C

RN2901

1

MIC2_VREF O_R[27] MIC2_VREF O_L[27]

SRN2K2J -1-GP

RING2[27]

AUD_HP1 _JACK_L[27 ]

LINE1_L[27 ]

LINE1_VRE FO_L[27]

AUD_HP1 _JACK_R[27]

LINE1_R[27]

LINE1_VRE FO_R[27]

SLEEVE[27]

C2907

C2908

1 2

SC10U6D 3V3MX-GP

1 2

SC10U6D 3V3MX-GP

SRN2K2J -1-GP

LINE1-L_C

LINE1-L_R

4

2 3

R2907 0R0603-P ADR2907 0R0603-P AD R2922 0R0402-P ADR2922 0R0402-P AD R2912 2K2R2J-2 -GP

R2912 2K2R2J-2 -GP

R2909 0R0603-P ADR2909 0R0603-P AD R2921 0R0402-P ADR2921 0R0402-P AD R2913 2K2R2J-2 -GP

R2913 2K2R2J-2 -GP

1 2 1 2

DY

1 2 1 2

DY

12

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

EC2908

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

12

R2920

10KR2J-3-GPDYR2920

10KR2J-3-GP

12

DY

Universal Jack (Moved to I/O Board)

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

12

DY

12

R2919

SC100P50V2JN-3GPDYEC2906

SC100P50V2JN-3GP

10KR2J-3-GP

DY

EC2906

EC2905

SC100P50V2JN-3GPDYEC2905

SC100P50V2JN-3GP

12

DY

R29060 R0603-PAD R290 60R0603-PAD R29081 0R2F-L-GP R29 0810R2F-L-GP

1 2

R291010R2F-L-GP R 291010R2F-L-G P

1 2

R29110 R0603-PAD R291 10R0603-PAD

HPMIC1

12

RING2_R AUD_POR TA_L_R_B

AUD_POR TA_R_R_B SLEEVE_ R

SLEEVE_ R AUD_POR TA_L_R_B

JACK_PL UG JACK_PL UG_DET AUD_POR TA_R_R_B RING2_R

AUD_AGN D

HPMIC1

3 1

5 6 2 4

MS

Audio(IP/NK comb)

AUDIO-JK52 2-GP

022.10002.00D1

Delay circuit

B B

(JACK_PLUG_DET: on IO Board)

AUD_AGN D AUD_AG ND

JACK_PL UG_DET

10 mils

A A

12

AUD_AGN D

R2905

R2905 0R0402-P AD

0R0402-P AD

5

CLOSS TO HPMIC1

ED2903

AZ5725-01FDR7G-GP

ED2903

AZ5725-01FDR7G-GP

ED2902

AZ5725-01FDR7G-GP

ED2902

AZ5725-01FDR7G-GP

ED2901

AZ2025-01H-R7G-GP

ED2901

AZ2025-01H-R7G-GP

12

4

AZ5725-01FDR7G-GP

12

RING2_R

AUD_POR TA_L_R_B JACK_PL UG JACK_PL UG_DET

AUD_POR TA_R_R_B

SLEEVE_ R

ED2905

AZ5725-01FDR7G-GP

ED2905

AZ5725-01FDR7G-GP

ED2904

ED2906

AZ2025-01H-R7G-GP

ED2906

AZ2025-01H-R7G-GP

12

3

JACK_PL UG

R2923 0R0603-P ADR292 3 0R0603 -PAD

1 2

12

DY

AUD_AGN D

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

2

Date: Sheet of

Audio IO

Starload SKL-U

Thursday, February 25, 20 16

10 mils10 mils

C2902

C2902 SC10U6D 3V3MX-GP

SC10U6D 3V3MX-GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

29 10 6

1

AUD_SEN SE [27]

A00

Vinaﬁx.com

5

4

3

2

1

Main Func = Audio

D D

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

Starload SKL-U

Thursday, February 18, 2016

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

30 106

1

A00

Dell 3150 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual