SPECIFICATIONS
PARAMETER
DLD-100B Option A
DLD-100B Option B
Peak Output Current 30A, controlled by input high
voltage amplitude
40A, controlled by input high
voltage amplitude
Minimum Pulse Width (Typical)
12ns (12E-9S) 15ns (15E-9S)
Maximum Pulse Width at 5% Droop
1µs (1E-6S)
600ns (6E-7S)
Pulse Rise Time (10% to 90%) (Typical)
11ns (11E-9S)
18ns (18E-9S)
PRF (Pulse Recurrence Frequency), CW Single Shot to 1MHz, limited by maximum average current, con-
trolled by input trigger frequency (see tables below)
Gate (Trigger) In
+5V/50
Ω
Output pulse width and frequency follow gate’s width
and frequency
Support Power +12VDC to +15VDC at 60mA typical
DC HV Input 150V Maximum 60V Maximum
Throughput (Propagation) Delay <40ns, typically 35ns
MECHANICAL
Size 70mm (2.75”) W x 100mm (3.9”) L
ALL
SPECIFICATIONS MEASURED INTO A SHORTED OUTPUT
.
S
PECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
.
Technical Description
The DLD-100B is an open-frame, OEM module
designed for integration into the user‘s equipment.
The driver requires +12 to +15VDC support
power, a high voltage DC input (150VDC maximum for Option A, 60VDC maximum for Option
B), and a +5V gate signal. The amplitude of the
high voltage DC supply controls the amplitude of
the output current pulse. The output pulse width
and frequency follow the input gate’s width and
frequency.
To minimize cost, the driver is designed so that
the laser diode is floating on the voltage of the
drain of the output transistor.
The diode must be
electrically isolated from earth (chassis)
ground.
The cathode (-) connects to W1, and the
anode (+) connects to W2.
Gate
Drive
Circuitry
Control
Gate
(P1 - 6)
+12V
(P1 - 4)
+ High Voltage
Input
(P1 - 2)
Energy Sorage
Capacitors
Impedance
Matching Resistor
Laser Diode
(Floating)
Cathode (-) = W1
Anode (+) = W2
DE150-201N09
Power
MOSFET
DLD-100B Simplified Block Diagram