DECchip 21040 Hardware Reference Manual

DECchip 21040
Ethernet LAN Controller for PCI

Hardware Reference Manual

Order Number: EC–N0752–72

Revision/Update Information: This is a new manual.

Digital Equipment Corporation
Maynard, Massachusetts

May 1994

While Digital believes the information included in this publication is correct as of the date of
publication, it is subject to change without notice.

Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.

© Digital Equipment Corporation 1994.

All Rights Reserved.

DEC, DECchip, Digital, and the DIGITAL logo are trademarks of Digital Equipment Corporation.

All other trademarks and registered trademarks are the property of their respective holders.

This document was prepared using VAX DOCUMENT, Version 2.0.

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

1 Introduction

1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.3 Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

2 Signal Descriptions and Bus Commands

2.1 21040 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

2.3 Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

3 Registers

3.1 21040 Configuration Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1.1 Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . 3–2

3.1.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.1.2.1 Configuration ID Register (CFID) . . . . . . . . . . . . . . . . . . 3–2

3.1.2.2 Command and Status Configuration Register (CFCS) . . . 3–3

3.1.2.3 Configuration Revision Register (CFRV) . . . . . . . . . . . . . 3–7

3.1.2.4 Configuration Latency Timer Register (CFLT) . . . . . . . . . 3–8

3.1.2.5 Configuration Base I/O Address Register (CBIO) . . . . . . 3–9

3.1.2.6 Configuration Base Memory Address Register

(CBMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3.1.2.7 Configuration Interrupt Register (CFIT) . . . . . . . . . . . . . 3–11

3.1.2.8 Configuration Driver Area Register (CFDA) . . . . . . . . . . 3–12

3.2 Command and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

iii

3.2.1 Host CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

3.2.1.1 Bus Mode Register (CSR0) . . . . . . . . . . . . . . . . . . . . . . . . 3–14

3.2.1.2 Transmit Poll Demand (CSR1) . . . . . . . . . . . . . . . . . . . . . 3–18

3.2.1.3 Receive Poll Demand (CSR2) . . . . . . . . . . . . . . . . . . . . . . 3–19

3.2.1.4 Descriptor List Addresses (CSR3, CSR4) . . . . . . . . . . . . . 3–20

3.2.1.5 Status Register (CSR5) . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22

3.2.1.6 Operation Mode Register (CSR6) . . . . . . . . . . . . . . . . . . . 3–29

3.2.1.7 Interrupt Mask Register (CSR7) . . . . . . . . . . . . . . . . . . . 3–36

3.2.1.8 Missed Frame Counter (CSR8) . . . . . . . . . . . . . . . . . . . . . 3–40

3.2.1.9 Ethernet Address ROM Register (CSR9) . . . . . . . . . . . . . 3–41

3.2.1.10 Full-Duplex Register (CSR11) . . . . . . . . . . . . . . . . . . . . . 3–42

3.2.2 Serial Interface Attachment CSRs . . . . . . . . . . . . . . . . . . . . . 3–43

3.2.2.1 SIA Status Register (CSR12) . . . . . . . . . . . . . . . . . . . . . 3–44

3.2.2.2 SIA Connectivity Register (CSR13) . . . . . . . . . . . . . . . . . 3–46

3.2.2.3 SIA Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 3–50

3.2.2.4 SIA Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51

3.2.2.5 SIA Transmit and Receive Register (CSR14) . . . . . . . . . . 3–56

3.2.2.6 SIA Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 3–61

3.2.2.7 SIA General Register (CSR15) . . . . . . . . . . . . . . . . . . . . . 3–62

4 Host Communication Area

4.1 Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2 Descriptor Lists and Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2.1 Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4.2.1.1 Receive Descriptor 0 (RDES0) . . . . . . . . . . . . . . . . . . . . . 4–3

4.2.1.2 Receive Descriptor 1 (RDES1) . . . . . . . . . . . . . . . . . . . . . 4–8

4.2.1.3 Receive Descriptor 2 (RDES2) . . . . . . . . . . . . . . . . . . . . . 4–9

4.2.1.4 Receive Descriptor 3 (RDES3) . . . . . . . . . . . . . . . . . . . . . 4–11

4.2.1.5 Receive Descriptor Status Validity . . . . . . . . . . . . . . . . . . 4–12

4.2.2 Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.2.2.1 Transmit Descriptor 0 (TDES0) . . . . . . . . . . . . . . . . . . . 4–13

4.2.2.2 Transmit Descriptor 1 (TDES1) . . . . . . . . . . . . . . . . . . . . 4–17

4.2.2.3 Transmit Descriptor 2 (TDES2) . . . . . . . . . . . . . . . . . . . 4–20

4.2.2.4 Transmit Descriptor 3 (TDES3) . . . . . . . . . . . . . . . . . . . 4–20

4.2.2.5 Transmit Descriptor Status Validity . . . . . . . . . . . . . . . . . 4–21

4.2.3 Setup Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4.2.3.1 First Setup Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4.2.3.2 Subsequent Setup Frames . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4.2.3.3 Perfect Filtering Setup Frame Buffer . . . . . . . . . . . . . . . 4–22

4.2.3.4 Imperfect Filtering Setup Frame Buffer . . . . . . . . . . . . . 4–26

iv

5 Functional Description

5.1 Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2 Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.4 Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.5 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5.1 Descriptor Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5.2 Frame Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5.3 Receive Process Suspended . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5.5.4 Receive Process State Transitions . . . . . . . . . . . . . . . . . . . . . 5–7

5.6 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

5.6.1 Frame Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.6.2 Transmit Polling Suspended . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.6.3 Transmit Process State Transitions . . . . . . . . . . . . . . . . . . . . 5–10

5.7 Loopback Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.7.1 Internal Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.7.2 External Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.7.3 Driver Entering Loopback Mode . . . . . . . . . . . . . . . . . . . . . . 5–13

5.7.4 Driver Restoring Normal Operation . . . . . . . . . . . . . . . . . . . . 5–14

5.8 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14

6 Host Bus Operation

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.2 Bus Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

6.2.1 Slave Read Cycle (I/O or Memory Target) . . . . . . . . . . . . . . . 6–2

6.2.2 Slave Write Cycle (I/O or Memory Target) . . . . . . . . . . . . . . 6–3

6.2.3 Configuration Read and Write Cycles . . . . . . . . . . . . . . . . . . . 6–4

6.3 Bus Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.3.1 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

6.3.2 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

6.3.3 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

6.4 Termination Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

6.4.1 Slave-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

6.4.2 Master-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

6.4.2.1 21040-Initiated Termination . . . . . . . . . . . . . . . . . . . . . . 6–11

6.4.2.1.1 Normal Completion . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

6.4.2.1.2 Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

6.4.2.1.3 Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

6.4.2.2 Memory-Controller-Initiated Termination . . . . . . . . . . . . 6–13

6.4.2.2.1 Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

6.4.2.2.2 Target-Initiated Termination . . . . . . . . . . . . . . . . . . . 6–14

v

6.4.2.2.3 Target Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

6.5 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

6.6 Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

7 Network Interface

7.1 10BASE-T and AUI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.1.1 Receivers and Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

7.1.2 Manchester Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

7.1.3 Manchester Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

7.1.4 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

7.1.5 Jabber and Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

7.1.6 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

7.1.7 Auto Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2 Media Access Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.1.1 Ethernet and IEEE 802.3 Frames . . . . . . . . . . . . . . . . . . 7–4

7.2.1.2 Frame Format Description . . . . . . . . . . . . . . . . . . . . . . . . 7–5

7.2.2 Ethernet Reception Addressing . . . . . . . . . . . . . . . . . . . . . . . 7–7

7.2.3 Collision Detection and Implementation . . . . . . . . . . . . . . . . 7–8

7.2.4 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

7.2.5 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

7.3 Detailed Transmission Operation . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

7.3.1 Transmission Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

7.3.2 Frame Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

7.3.3 Initial Deferral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

7.3.4 Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7.3.5 Terminating Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7.3.6 Transmit Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

7.4 Detailed Receiving Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

7.4.1 Initiating Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

7.4.2 Preamble Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

7.4.3 Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

7.4.4 Frame Decapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

7.4.5 Terminating Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

7.4.6 Frame Reception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

7.4.7 Capture Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

7.4.7.1 What is Capture Effect? . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

7.4.7.2 Resolving Capture Effect . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

7.4.8 Back Pressure Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18

7.4.9 External SIA Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18

vi

A Joint Test Action Group Test Logic

A.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

A.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

A.2.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

A.2.2 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

A.2.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

A.2.4 Test Access Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

B DNA CSMA/CD Counters and Events Support

C Hash C Routine

D Technical Support, Ordering, and Associated Literature

D.1 Calling the DECchip Information Line for Information and

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

D.2 Ordering DECchip Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

D.3 Ordering Associated DECchip Literature . . . . . . . . . . . . . . . . . . . D–2

Index

Examples

4–1 Perfect Filtering Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4–2 Imperfect Filtering Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

Figures

1–1 DECchip 21040 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 1–4

2–1 DECchip 21040 Pinout Diagram (Top View) . . . . . . . . . . . . . 2–2

3–1 CFID Configuration ID Register . . . . . . . . . . . . . . . . . . . . . . 3–2

3–2 CFCS Command and Status Configuration Register . . . . . . . 3–4

3–3 CFRV Configuration Revision Register . . . . . . . . . . . . . . . . . 3–7

3–4 CFLT Configuration Latency Timer Register . . . . . . . . . . . . 3–8

3–5 CBIO Configuration Base I/O Address Register . . . . . . . . . . 3–9

3–6 CBMA Configuration Base Memory Address Register . . . . . . 3–10

3–7 CFIT Configuration Interrupt Register . . . . . . . . . . . . . . . . . 3–11

3–8 CFDA Configuration Driver Area Register . . . . . . . . . . . . . . 3–12

vii

3–9 CSR0 Bus Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

3–10 CSR1 Transmit Poll Demand . . . . . . . . . . . . . . . . . . . . . . . . 3–18

3–11 CSR2 Receive Poll Demand . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

3–12 CSR3 Receive List Base Address . . . . . . . . . . . . . . . . . . . . . 3–20

3–13 CSR4 Transmit List Base Address . . . . . . . . . . . . . . . . . . . . 3–21

3–14 CSR5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23

3–15 CSR6 Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . 3–29

3–16 CSR7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . 3–36

3–17 CSR8 Missed Frame Counter . . . . . . . . . . . . . . . . . . . . . . . . 3–40

3–18 CSR9 Ethernet Address ROM Register . . . . . . . . . . . . . . . . . 3–41

3–19 CSR11 Full-Duplex Register . . . . . . . . . . . . . . . . . . . . . . . . . 3–42

3–20 CSR12 SIA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3–44

3–21 CSR13 SIA Connectivity Register . . . . . . . . . . . . . . . . . . . . . 3–47

3–22 CSR14 SIA Transmit and Receive Register . . . . . . . . . . . . . . 3–57

3–23 CSR15 SIA General Register . . . . . . . . . . . . . . . . . . . . . . . . 3–62

4–1 Descriptor Ring and Chain Structures . . . . . . . . . . . . . . . . . . 4–2

4–2 Receive Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4–3 RDES0 Receive Descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4–4 RDES1 Receive Descriptor 1 . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4–5 RDES2 Receive Descriptor 2 . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4–6 RDES3 Receive Descriptor 3 . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4–7 Transmit Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4–8 TDES0 Transmit Descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4–9 TDES1 Transmit Descriptor 1 . . . . . . . . . . . . . . . . . . . . . . . . 4–17

4–10 TDES2 Transmit Descriptor 2 . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4–11 TDES3 Transmit Descriptor 3 . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4–12 Perfect Filtering Setup Frame Buffer Format . . . . . . . . . . . . 4–24

4–13 Imperfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4–14 Imperfect Filtering Setup Frame Format . . . . . . . . . . . . . . . . 4–27

6–1 Slave Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

6–2 Slave Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

6–3 Configuration Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6–4 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

6–5 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

6–6 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

6–7 21040-Initiated Retry Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

6–8 Normal Completion Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

viii

6–9 Master Abort Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

6–10 Abort Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

6–11 Termination Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

6–12 Parity Operation Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

7–1 Ethernet Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

7–2 Preamble Recognition Sequence . . . . . . . . . . . . . . . . . . . . . . . 7–13

Tables

2–1 Signal Pin Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

2–2 Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

3–1 Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . 3–2

3–2 CFID Configuration ID Register Description . . . . . . . . . . . . . 3–3

3–3 CFID Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3–4 CFCS Command and Status Configuration Register

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

3–5 CFCS Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3–6 CFRV Configuration Revision Register Description . . . . . . . 3–7

3–7 CFRV Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3–8 CFLT Configuration Latency Timer Register Description . . . 3–8

3–9 CFLT Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3–10 CBIO Configuration Base I/O Address Register

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3–11 CBIO Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3–12 CBMA Configuration Base Memory Address Register

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3–13 CBMA Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

3–14 CFIT Configuration Interrupt Register Description . . . . . . . . 3–11

3–15 CFIT Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

3–16 CFDA Configuration Driver Area Register Description . . . . . 3–12

3–17 CFDA Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

3–18 CSR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

3–19 CSR0 Bus Mode Register Description . . . . . . . . . . . . . . . . . . 3–16

3–20 Transmit Automatic Polling Bits . . . . . . . . . . . . . . . . . . . . . . 3–17

3–21 CSR0 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

3–22 Cache Address Alignment Bits . . . . . . . . . . . . . . . . . . . . . . . . 3–18

3–23 CSR1 Transmit Poll Demand Description . . . . . . . . . . . . . . . 3–18

ix

3–24 CSR1 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

3–25 CSR2 Receive Poll Demand Description . . . . . . . . . . . . . . . . . 3–19

3–26 CSR2 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20

3–27 CSR3 Receive List Base Address Description . . . . . . . . . . . . . 3–20

3–28 CSR4 Transmit List Base Address Description . . . . . . . . . . . 3–21

3–29 CSR3 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21

3–30 CSR4 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21

3–31 CSR5 Status Register Description . . . . . . . . . . . . . . . . . . . . . 3–24

3–32 Bus Error Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26

3–33 Transmit Process State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

3–34 Receive Process State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

3–35 CSR5 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28

3–36 CSR6 Operating Mode Register Description . . . . . . . . . . . . . . 3–30

3–37 Transmit Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–33

3–38 Filtering Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–34

3–39 CSR6 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–35

3–40 CSR7 Interrupt Mask Register Description . . . . . . . . . . . . . . 3–37

3–41 CSR7 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39

3–42 CSR8 Missed Frame Counter Description . . . . . . . . . . . . . . . 3–40

3–43 CSR8 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40

3–44 CSR9 Ethernet Address ROM Register Description . . . . . . . . 3–41

3–45 CSR9 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–42

3–46 CSR11 Full-Duplex Register Description . . . . . . . . . . . . . . . . 3–42

3–47 CSR11 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–43

3–48 CSR12 SIA Status Register Description . . . . . . . . . . . . . . . . . 3–44

3–49 CSR12 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–46

3–50 CSR13 SIA Connectivity Register Description . . . . . . . . . . . . 3–48

3–51 CSR13 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49

3–52 AUI—10BASE-T Selection Using SIA_Auto_Configuration

and

SIA_Pin_Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–50

3–53 Programming of SIA Modes Using CSR13, CSR14, and

CSR15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–50

3–54 External SIA Port Mode Selections . . . . . . . . . . . . . . . . . . . . 3–52

3–55 External SIA Output Multiplexer Selection . . . . . . . . . . . . . 3–53

3–56 CSR14 SIA Transmit and Receive Register Description . . . . . 3–58

3–57 CSR14 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–59

x

3–58 Twisted-Pair Compensation Behavior . . . . . . . . . . . . . . . . . . 3–60

3–59 Normal, Full-Duplex, and Loopback Programming . . . . . . . . 3–61

3–60 CSR15 SIA General Register Description . . . . . . . . . . . . . . . . 3–63

3–61 CSR15 Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–64

4–1 RDES0 Receive Descriptor 0 Description . . . . . . . . . . . . . . . . 4–5

4–2 RDES1 Receive Descriptor 1 Description . . . . . . . . . . . . . . . 4–9

4–3 RDES2 Receive Descriptor 2 Description . . . . . . . . . . . . . . . . 4–10

4–4 RDES3 Receive Descriptor 3 Description . . . . . . . . . . . . . . . 4–11

4–5 Receive Descriptor Status Validity . . . . . . . . . . . . . . . . . . . . . 4–12

4–6 TDES0 Transmit Descriptor 0 Description . . . . . . . . . . . . . . 4–15

4–7 TDES1 Transmit Descriptor 1 Description . . . . . . . . . . . . . . . 4–17

4–8 Filtering Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4–9 TDES2 Transmit Descriptor 2 Description . . . . . . . . . . . . . . . 4–20

4–10 TDES3 Transmit Descriptor 3 Description . . . . . . . . . . . . . . . 4–21

4–11 Transmit Descriptor Status Validity . . . . . . . . . . . . . . . . . . . . 4–21

5–1 Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5–2 Receive Process State Transitions . . . . . . . . . . . . . . . . . . . . . 5–7

5–3 Transmit Process State Transitions . . . . . . . . . . . . . . . . . . . . 5–10

7–1 Crystal Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . 7–3

7–2 Frame Format Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

7–3 Ethernet Receive Address Groups . . . . . . . . . . . . . . . . . . . . . 7–7

7–4 Destination Address Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

7–5 Capture Effect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

7–6 2-0 Backoff Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

A–1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

A–2 Boundary Scan Register Controls . . . . . . . . . . . . . . . . . . . . . A–5

B–1 CSMA/CD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

xi

Purpose and Audience

The DECchip 21040 Ethernet LAN Controller for PCI Hardware Reference
Manual describes the operation of the DECchip 21040 Ethernet LAN

Controller for PCI (also referred to as the 21040). This manual is for system
designers who use the 21040.

Manual Organization

This manual contains seven chapters, four appendices, and an index.

• Chapter 1, Introduction, includes a general description of the 21040. It
also provides an overview of the 21040 hardware components.

• Chapter 2, Signal Descriptions and Bus Commands, provides the physical
layout of the 21040 and describes each of the input and output signals.

• Chapter 3, Registers, provides a complete bit description of the 21040
command and status registers as well as the configuration registers.

• Chapter 4, Host Communication Area, describes how the 21040
communicates with the host using descriptor lists and data buffers.

• Chapter 5, Functional Description, describes reset commands, interrupt
handling, and startup. It also describes the transmit and receive processes.

Preface

• Chapter 6, Host Bus Operation, provides a description of the read, write,
and termination cycles.

• Chapter 7, Network Interface, describes the 10BASE-T and AUI interfaces.
It includes a complete description of media access control operations. It
also provides detailed transmitting and receiving operation information.

• Appendix A, Joint Test Action Group Test Logic, provides descriptions
of the testing, observing, and modifying circuit activity during normal
operation.

xiii

• Appendix B, DNA CSMA/CD Counters and Events Support, describes
features that support the driver in implementing and reporting the
specified counters and events.

• Appendix C, Hash C Routine, provides an example of a C routine that
generates a hash index for a given Ethernet address.

• Appendix D, Technical Support, Ordering, and Associated Literature,
contains information about technical support as well as ordering parts and
related documentation.

• The index provides an alphabetical list of topics described in this manual.
An entry with an f appended to the page number (for example, 21040
pinout diagram, 2-2f) indicates a figure reference. An entry with a t
appended to the page number (for example, Twisted-pair compensation
behavior, 3-60t) indicates a table reference.

Document Conventions

The values 1, 0, and X are used in some tables. X signifies a don’t care (1 or 0)
convention, which can be determined by the system designer.

xiv

This chapter provides a general description of the DECchip 21040 Ethernet
LAN Controller, its features and an overview of the hardware.

1.1 General Description

The DECchip 21040 is an Ethernet LAN controller that is based on the
peripheral component interconnect (PCI) local bus. The 21040 provides a
glueless connection to the PCI.

During host interface operation, the 21040 interfaces with the processor using
on-chip command and status registers (CSRs) and a shared host memory area,
set up mainly during initialization. This minimizes processor involvement in
the 21040 operation during normal reception and transmission. Bus traffic
is also minimized by filtering out received runt frames and by automatically
transmitting collided frames again without a repeated fetch from host memory.

During communication interface operation, the 21040 provides both an
attachment unit interface (AUI) and a twisted-pair interface, enabling a low
chip count connection to the two most popular Ethernet interfaces. The 21040
can sustain transmission or reception of minimal-sized back-to-back packets
at full line speed with a 9.6-microsecond interpacket gap. The 21040 can also
function in a full-duplex environment.

1

Introduction

1.2 Features

The 21040 has the following features:

• Offers a single-chip Ethernet controller for PCI local bus

Provides glueless connection to PCI bus

Contains on-chip integrated attachment unit interface (AUI) port and a
10BASE-T transceiver

• Supports full-duplex operation

1–1

• Provides clock speed up to 33 megahertz, with no wait states on PCI
master operation

• Enables powerful on-chip DMA with programmable, unlimited burst size
providing for low CPU utilization

• Implements unique, patent-pending, intelligent arbitration between
DMA channels that prevent underflow or overflow and are optimized for
full-duplex operation

• Contains two large (256-byte) independent receive and transmit FIFOs

• Supports either big or little endian byte ordering

• Implements joint test action group (JTAG) compatible test access port with
boundary-scan pins

• Provides full support of IEEE 802.3, ANSI 8802-3, and Ethernet standards

• Offers a unique, patented solution to Ethernet capture-effect problem

• Contains a variety of flexible address filtering modes

16 perfect addresses

512 hash-filtered multicast addresses and one perfect address

512 hash-filtered physical addresses and multicast addresses

Inverse perfect filtering

1–2

• Provides serial ROM interface for Ethernet ID address ROM

• Supports three LEDs: network activity, LinkPass, and AUI/10BASE-T

• Enables automatic detection and correction of 10BASE-T receive polarity

• Provides external and internal loopback capability

• Implements low power, 3.3-volts complimentary metal oxide semiconductor
(CMOS) device; interfaces to 5.0-volt or 3.3-volt logic

1.3 Hardware Overview

The following list describes the 21040 hardware components, and Figure 1–1
shows a block diagram of the 21040.

• PCI Interface—Includes all interface functions to the PCI bus; handles all

interconnect control signals, and executes PCI direct memory access (DMA)
and I/O transactions.

• DMA—Contains dual receive and transmit controller; supports bursts of up

to 32 longwords; handles data transfers between PCI memory and on-chip
memory.

• FIFOs—Contains dual 256-byte FIFOs for receive and transmit; supports

automatic packet deletion (runt packets or after a collision) and packet
re-transmission after a collision on transmit.

• TxM—Handles all CSMA/CD1MAC2transmit operations and transfers

data from transmit FIFO to the serial interface attachment (SIA) for
transmission.

• RxM—Handles all CSMA/CD receive operations and transfers the data

from the SIA to the receive FIFO.

• SIA—Performs physical layer operations; implements the AUI and

10BASE-T functions, including the Manchester encoder and decoder
functions.

1

Carrier-sense multiple access with collision detection

2

Media access control

1–3

Figure 1–1 DECchip 21040 Block Diagram

PCI

PCI Interface

32

Rx

FIFO

16

RxM TxM

1 1

Interface

Tx

FIFO

AUI

16

SIA Interface

TP

Interface

DMA

SROM

LEDs

Ethernet ID ROM

Network Activity
AUI/TP
LinkPass

External SIA

Interface

MLO-010132

1–4

Signal Descriptions and Bus Commands

This chapter describes the 21040 signals and lists the bus commands.

2.1 21040 Pinout

The 21040 is housed in the 120-pin plastic quad flat pack. The 21040 uses all
pins. Figure 2–1 shows the 21040 pinout.

2

2–1

Figure 2–1 DECchip 21040 Pinout Diagram (Top View)

VSS

AD<17>

AD<18>

AD<19>

VDD

AD<20>

AD<21>

VSS

AD<22>

AD<23>

AD<24>

AD<25>

VSS

AD<26>

AD<27>

VDD

AD<28>

AD<29>

VSS

AD<30>

AD<31>

9 8 7 6 5 4 3 2 1

0

VSS
AD<16>
AD<15>
AD<14>

VSS
AD<13>
AD<12>

VSS

VDD
AD<11>
AD<10>

VSS
AD<09>
AD<08>

VSS
AD<07>
AD<06>

VSS
AD<05>
AD<04>

VDD
AD<03>
AD<02>

VSS
AD<01>
AD<00>

TDO

VSS

TDI

TMS

IDSEL

3

292827262524232221201918171615141312111

0

31 120
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 91

616263646566676869707172737475767778798081828384858687889

DECchip

21040

VSS

C_BE_L<00>

C_BE_L<01>

C_BE_L<02>

C_BE_L<03>

VDD

DEVSEL_L

FRAME_L

119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92

8
9

0

VSS
VDD
STOP_L
PAR
IRDY_L
TRDY_L
REQ_L
VDD
PERR_L
SERR_L
VDD
VSS
INT_L
GNT_L
SCLK
SRST
SDIN
RST_L
VDD_CLAMP
CLK
VSS
VDD
XTAL2
XTAL1
VSS
IREF
VDDAC
VCAP_H
VDDAC
VDD

2–2

EXT_TCLK

EXT_TXEN

TCK

EXT_RXEN

EXT_RCLK

EXT_TX

EXT_CLSN

EXT_RX

VSS

AUI_RD-

VDD

AUI_CD-

VDD

AUI_RD+

TP_RD-

AUI_TP

AUI_CD+

TP_RD+

VDD

VSS

VDD

AUI_TD+

AUI_TD-

TP_TD++

VSS

TP_TD--

TP_TD+

TP_TD-

VSS

VSS

MLO-011314

2.2 Signal Descriptions

Table 2–1 provides a description of each of the signals used by the 21040.
These signals are listed alphabetically.

The following terms describe the 21040 pinout.

• Address phase
Address and appropriate bus command are driven during this cycle.

• Data phase
Data and the appropriate byte enable code are driven during this cycle.

• _L
All pin names with the _L suffix are only asserted low.

The following abbreviations are used in the tables in this section.

I = Input
O = Output
I/O = Input/output
O/D = Open drain

Note

Table 2–1 Signal Pin Reference

Signal Type Description

AD<31:00> I/O 32-bit multiplexed PCI address and data lines. Address

and data bits are multiplexed on the same pins. During
the first clock cycle of a transaction, AD<31:00> contains
a physical byte address (32 bits). During subsequent clock
cycles, AD<31:00> contains data. A 21040 bus transaction
consists of an address phase followed by one or more data
phases. The 21040 supports both read and write bursts.
Little and big endian byte ordering can be used.

AUI_CD– I Attachment unit interface receive collision differential

negative data.

AUI_CD+ I Attachment unit interface receive collision differential

positive data.

(continued on next page)

2–3

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

AUI_RD– I Attachment unit interface receive differential negative

AUI_RD+ I Attachment unit interface receive differential positive data.

AUI_TD– O Attachment unit interface transmit differential negative

AUI_TD+ O Attachment unit interface transmit differential positive

AUI_TP I Attachment unit interface and twisted-pair select line.

C_BE_L<03:00> I/O Bits 0 through 3 of the bus command and byte enable

CLK I The clock provides the timing for the 21040–related bus

DEVSEL_L I/O Device select is asserted when it is the target of the

data.

data.

data.

When asserted high, the attachment unit interface is
selected. When asserted low, the twisted-pair interface is
selected.

Software can override the pin selection (Section 3.2.2.3).

lines. Bus command and byte enable are multiplexed on
the same PCI pins. Table 2–2 lists the bus commands.

During the address phase of the transaction, C_BE_
L<03:00> provide the bus command.

During the data phase, C_BE_L<03:00> provide the byte
enable. The byte enable determines which byte lines carry
valid data. For example, C_BE_L<00> applies to byte 0,
and C_BE_L<03> applies to byte 3.

In all master and I/O operations, C_BE_L<03:00> contain
a value equal to a longword hexadecimal value of 0. In
configuration operations, C_BE_L<03:00> can contain any
value; 21040 supports byte, word, and longword operations.

transactions. All the other bus signals are sampled on
the rising edge of CLK. The clock range is between 16
megahertz and 33 megahertz.

current bus access. When the 21040 is the initiator of
the current bus access, it expects the target to assert
DEVSEL_L within 5 bus cycles, confirming the access. To
accomplish this, the 21040 asserts this signal in a medium
speed (within 2 bus cycles). If the target does not assert
DEVSEL_L within the required bus cycles, the 21040
aborts the cycle.

(continued on next page)

2–4

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

EXT_CLSN I/O Collision detect or test signals a collision occurrence on

EXT_RCLK I/O Receive clock or test pin carries the recovered receive

EXT_RX I/O Receive data or test pin carries the input receive data

EXT_RXEN I/O Receive enable or test pin signals activity on the Ethernet

EXT_TCLK I/O Transmit clock or test pin carries the transmit clock

EXT_TX I/O Transmit data or test pin carries the serial output data

the Ethernet cable to the 21040. It may be asserted and
deasserted asynchronously by the external SIA to the
receive clock.

This signal is an output to the AUI/TP LED. The LED is
on when AUI is selected. This pin can be used for SIA
testing features.

clock supplied by an external SIA. During idle periods, the
RCLK pin may be inactive. This pin can be used for SIA
testing features.

from the external SIA. The incoming data should be
synchronous with the RCLK signal.

This pin also outputs to the LinkPass LED. In 10BASE-T
mode, when LinkPass is detected, the LED is asserted
for a period of at least 300 milliseconds. In AUI mode, if
CSR12 bit 1 is asserted indicating no carrier, the LED is
deasserted for a period of 300 milliseconds. This pin can
be used for SIA testing features.

cable to the 21040. It is asserted when receive data is
present on the Ethernet cable and deasserted at the
end of a frame. It may be asserted and deasserted
asynchronously to the receive clock (RCLK) by the external
SIA.

This pin also interfaces with the network activity LED.
When any activity is detected in the network, the LED is
asserted for a period of at least 300 milliseconds. This pin
can be used for SIA testing features.

supplied by an external SIA. The clock must always be
active. This pin can be used for SIA testing features.

from the 21040. This data is synchronized to the TCLK
signal. This pin can be used for SIA testing features.

(continued on next page)

2–5

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

EXT_TXEN I/O Transmit enable or test pin signals the 21040 transmit-in-

FRAME_L I/O Cycle frame is driven by the 21040 (bus master) to indicate

GNT_L I Bus grant asserts to indicate to the 21040 that access to

IDSEL I Initialization device select asserts to act as a chip select

INT_L O/D Interrupt request asserts when one of the appropriate bits

IRDY_L I/O Initiator ready indicates the bus master’s ability to

IREF I Current reference input for the analog phase lock loop

progress to an external SIA. The pin is also used for SIA
testing features.

the beginning and duration of an access. FRAME_L
asserts to indicate the beginning of a bus transaction.
While FRAME_L is asserted, data transfers continue.
FRAME_L deasserts to indicate that the next data phase
is the final data phase transaction.

the bus is granted.

during configuration read or write transactions.

of CSR5 sets and causes an interrupt, provided that the
corresponding mask bit in CSR7 is not asserted. INT_L
deasserts by writing a 1 into the appropriate CSR5 bit.

If more than one interrupt bit is asserted in CSR5, the
host clears only the interrupt bit that was acknowledged,
INT_L deasserts for one cycle and then asserts again. This
process continues until all interrupts are acknowledged.

When deasserted, this pin should be pulled up by an
external resistor.

complete the current data phase of the transaction.
A data phase is completed on any clock when both IRDY_L

and target ready (TRDY_L) are asserted. Wait cycles are
inserted until both IRDY_L and TRDY_L are asserted
together.

When the 21040 is the bus master, IRDY_L is asserted
during write operations to indicate that valid data is
present on AD<31:00>. During read operations, the 21040
asserts IRDY_L to indicate that it is ready to accept data.

logic.

(continued on next page)

2–6

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

PAR I/O Parity is calculated by the 21040 as an even parity bit for

PERR_L I/O Parity error asserts when a data parity error is detected.

REQ_L O Bus request is asserted by the 21040 to indicate to the bus

RST_L I Resets the 21040 to its initial state. This signal must be

SCLK O Ethernet address ROM clock is used to clock data

SDIN I Ethernet address ROM data in is used to serially shift the

SERR_L O/D If an address parity error is detected and CFCS bit 31

SRST O Ethernet address ROM reset provides an asynchronous

the AD<31:00> and C_BE_L<03:00> lines.
During address and data phases, parity is calculated on all

the AD and C_BE_L lines whether or not any of these lines
carry meaningful information.

When the 21040 is the bus master and a parity error is
detected, the 21040 asserts both CSR5 bit 13 (system
error) and CFCS bit 8 (SERR_L enable) and completes the
current data burst transaction, then stops its operation.
After the host clears the system error, the 21040 continues
its operation.

When the 21040 is the bus target and a parity error is
detected, the 21040 asserts PERR_L.

arbiter that it wants to use the bus.

asserted for at least 10 active PCI clock cycles. When in
the reset state, all output pins are put into tristate and all
open drain (O/D) signals are floated.

information into the 21040.

Ethernet identification address from the serial ROM device
into the 21040.

(detected parity error) is enabled, 21040 asserts both
SERR_L (system error) and CFCS bit 30 (signal system
error).

When an address parity error is detected, system error
asserts two clocks after the failing address.

When deasserted, this pin should be pulled up by an
external resistor.

initialization of the serial ROM device.

(continued on next page)

2–7

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

STOP_L I/O Stop indicator indicates that the current target is

TCK I JTAG clock shifts state information and test data into and

TDI I JTAG data in is used to serially shift test data and

TDO O JTAG data out is used to serially shift test data and

TMS I JTAG test mode select controls the state operation of JTAG

TP_RD– I Twisted-pair negative differential receive data from the

TP_RD+ I Twisted-pair positive differential receive data from the

TP_TD–
TP_TD– –

TP_TD+
TP_TD+ +

O Twisted-pair negative differential transmit data. The

O Twisted-pair positive differential transmit data. The

requesting the bus master to stop the current transaction.
The 21040 responds to the assertion of STOP_L when it is

the bus master, either to disconnect, retry, or abort.

out of the 21040 during JTAG test operations (Appendix A).

instructions into the 21040 during JTAG test operations
(Appendix A).

instructions out of the 21040 during JTAG test operations
(Appendix A).

testing in the 21040 (Appendix A).

twisted-pair lines.

twisted-pair lines.

positive and negative differential transmit data outputs are
resistively combined outside the 21040 with equalization
to compensate for intersymbol interference on the twisted­pair medium.

positive and negative differential transmit data outputs are
resistively combined outside the 21040 with equalization
to compensate for intersymbol interference on the twisted­pair medium.

(continued on next page)

2–8

Table 2–1 (Cont.) Signal Pin Reference

Signal Type Description

TRDY_L I/O Target ready indicates the target agent’s ability to complete

VCAP_H I Capacitor input for analog phase lock loop logic.

VDD I 3.3-volt supply input voltage.

VDDAC I 3.3-volt supply input for analog phase lock loop logic.

VDD_CLAMP I Supplies +5-volt or 3.3-volt reference for the clamp logic.

1

VSS

XTAL1 I Crystal oscillator input.

XTAL2 O Crystal feedback output pin used for crystal connections

1

Device pins 90 and 96 are test pins used for Digital engineering evaluation of the 21040; they

must be tied to VSS for normal chip operation.

– Ground pin.

2.3 Bus Commands

the current data phase of the transaction.
A data phase is completed on any clock when both TRDY_L

and initiator ready (IRDY_L) are asserted. Wait cycles are
inserted until both IRDY_L and TRDY_L are asserted
together.

When the 21040 is the bus master, TRDY_L is asserted by
the bus slave on the read operation indicating that valid
data is present on AD<31:00>. During a write cycle, it
indicates that the target is prepared to accept data.

only. If this pin is unused, do not connect it.

Table 2–2 lists the bus commands.

Table 2–2 Bus Commands

C_BE_L<3:0> Command Type of Support

0000 Interrupt acknowledge Not supported

0001 Special cycle Not supported

0010 I/O read Supported as target

0011 I/O write Supported as target

(continued on next page)

2–9

Table 2–2 (Cont.) Bus Commands

C_BE_L<3:0> Command Type of Support

0100 Reserved –

0101 Reserved –

0110 Memory read Supported as initiator and target

0111 Memory write Supported as initiator and target

1000 Reserved –

1001 Reserved –

1010 Configuration read Supported as target

1011 Configuration write Supported as target

1100 Reserved –

1101 Memory write and invalidate Not supported

1110 Memory read long Not supported

1111 Postable memory write Not supported

2–10

This chapter describes the 21040 configuration registers as well as command
and status registers (CSRs). The 21040 uses eight configuration registers for
initialization and configuration. Configuration registers are used to identify
and query the 21040.

The 21040 contains 12 CSRs (CSR0 through CSR11) for communication with
the driver to the host. It communicates with the serial interface attachment
(SIA) using four additional command and status registers (CSR12 through
CSR15).

CSRs are located in the 21040 and are mapped in the host I/O or memory
address space. CSRs are used for the following:

Initialization
Pointers
Commands
Error reporting

3.1 21040 Configuration Operation

3

Registers

The 21040 enables a full software-driven initialization and configuration. This
permits the software to identify and query the 21040.

The 21040 treats configuration space write operations to registers that are
reserved as no-ops. That is, the access completes normally on the bus and the
data is discarded. Read accesses, to reserved or non-implemented registers,
complete normally and a data value of 0 is returned.

Software reset (CSR0<0>) has no effect on the configuration registers.
Hardware reset clears the configuration registers.

21040 supports byte, word, and longword accesses to the configuration area.

3–1

3.1.1 Configuration Register Mapping

Table 3–1 lists the definitions and addresses for the configuration registers.

Table 3–1 Configuration Register Mapping

Configuration Register Identifier I/O Address

Identification CFID xxxxxx00H

Command and status CFCS xxxxxx04H

Revision CFRV xxxxxx08H

Latency timer CFLT xxxxxx0CH

Base I/O address CBIO xxxxxx10H

Base memory address CBMA xxxxxx14H

Reserved – xxxxxx18H - xxxxxx38H

Interrupt CFIT xxxxxx3CH

Driver area CFDA xxxxxx40H

3.1.2 Configuration Registers

The 21040 implements eight configuration registers. These registers are
described in the following subsections.

3.1.2.1 Configuration ID Register (CFID)

The CFID register identifies the 21040. Figure 3–1 shows the CFID register
bit fields, and Table 3–2 describes the bit fields.

3–2

Figure 3–1 CFID Configuration ID Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Device ID Vendor ID

2

111111111

1

MLO-010312

0

Table 3–2 CFID Configuration ID Register Description

Field Description

31:16 Device ID

Provides the unique 21040 ID number (0002H).

15:0 Vendor ID

Specifies the manufacturer of the 21040 (1011H).

Table 3–3 lists the access rules for the CFID register.

Table 3–3 CFID Access Rules

Category Description

Value after hardware or software reset 00021011H

Read access rules –

Write access rules Writing has no effect

3.1.2.2 Command and Status Configuration Register (CFCS)

The CFCS register is divided into two sections: a command register
(CFCS<15:0>) and a status register (CFCS<31:16>).

The command register provides coarse control of the 21040’s ability to generate
and respond to PCI cycles. Writing 0 to this register, the 21040 logically
disconnects from the PCI bus for all accesses except configuration accesses.

The status register records status information for the PCI bus-related events.
The CFCS status bits do not clear when read. Writing 1 to these bits clears
them; writing 0 has no effect.

Figure 3–2 shows the CFCS bit fields, and Table 3–4 describes the bit fields.

3–3

Figure 3–2 CFCS Command and Status Configuration Register

Detected Parity Error

Signal System Error

Received Master Abort

Received Target Abort

DEVSEL Timing

Data Parity Report

Fast Back-to-Back

SERR_L Enable

Parity Error Response

Master Operation

Memory Space Access

I/O Space Access

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

MLO-011361

0

3–4

Table 3–4 CFCS Command and Status Configuration Register Description

Field Description

31 Detected Parity Error—status

When set, the 21040 detected a parity error, even if parity error handling is
disabled in parity error response (CFCS<6>).

30 Signal System Error—status

When set, the 21040 asserted the system error (SERR_L) pin.

29 Received Master Abort—status

When set, the 21040 terminated a transaction with master abort.

28 Received Target Abort—status

When set, the 21040 terminated a transaction with target abort.

26:25 DEVSEL Timing—status

Indicates the timing of the assertion of device select (DEVSEL_L). These bits are
set to 01 which indicates a medium assertion of DEVSEL_L.

24 Data Parity Report—status

This bit sets when the following three conditions are met:

• 21040 asserts parity error (PERR_L) or it senses the assertion of PERR_L by
another device.

• 21040 operates as a bus master for the operation that caused the error.

• Parity error response (CFCS<6>) is set.

23 Fast Back-to-Back—status

Always set by the 21040. This indicates that the 21040 is capable of accepting fast
back-to-back transactions that are not sent to the same bus device.

8 SERR_L Enable—command

When set, the 21040 asserts system error (SERR_L) when it detects a parity error
on the address.

6 Parity Error Response—command

When set, the 21040 asserts system error (CSR5<13>) after a parity error detection.

When reset, any detected parity error is ignored and the 21040 continues normal
operation.

Parity checking is disabled after reset.

(continued on next page)

3–5

Table 3–4 (Cont.) CFCS Command and Status Configuration Register Description

Field Description

2 Master Operation—command

When set, the 21040 is capable of acting as a bus master.

When reset, the 21040 capability to generate PCI accesses is disabled.

For normal 21040 operation, this bit must be set.

1 Memory Space Access—command

When set, the 21040 responds to memory space accesses.

When reset, the 21040 does not respond to memory space accesses.

0 I/O Space Access—command

When set, the 21040 responds to I/O space accesses.

When reset, the 21040 does not respond to I/O space accesses.

Table 3–5 lists the access rules for the CFCS register.

Table 3–5 CFCS Access Rules

Category Description

3–6

Value after hardware
reset

Read access rules –

Write access rules Written during configuration cycle.

All reserved bits are 0.

3.1.2.3 Configuration Revision Register (CFRV)

The CFRV register contains the 21040 revision number. Figure 3–3 shows the
CFRV bit fields, and Table 3–6 describes the bit fields.

Figure 3–3 CFRV Configuration Revision Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Base Class

Subclass

Step Number

Revision Number

2

111111111

1

MLO-011362

Table 3–6 CFRV Configuration Revision Register Description

Field Description

31:24 Base Class

Indicates the network controller and is equal to 2H.

23:16 Subclass

Indicates the Ethernet controller and is equal to 0H.

7:4 Step Number

Indicates the 21040 step number and is equal to 2H. This number is
incremented for subsequent 21040 steps.

3:0 Revision Number

Indicates the 21040 revision number and is equal to either 0H, 1H, 2H,
or 3H. This number is incremented for subsequent 21040 revisions within
the current step.

0

Table 3–7 lists the access rules for the CFRV register.

3–7

Table 3–7 CFRV Access Rules

Category Description

Value after hardware or software reset 0200FF20H, 0200FF21H,

Read access rules –

Write access rules Writing has no effect

3.1.2.4 Configuration Latency Timer Register (CFLT)

This register configures the 21040 bus latency timer. Figure 3–4 shows the
CFLT bit field, and Table 3–8 describes the bit field.

Figure 3–4 CFLT Configuration Latency Timer Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Configuration Latency Timer

2

Table 3–8 CFLT Configuration Latency Timer Register Description

Field Description

0200FF22H, or 0200FF23H

111111111

1

MLO-010315

0

3–8

15:8 Configuration Latency Timer

Specifies, in units of PCI bus clocks, the value of the latency timer of the

21040.

When the 21040 asserts FRAME_L, it enables its latency timer to count.
If the 21040 deasserts FRAME_L prior to count expiration, the content

of the latency timer is not valid. Otherwise, after the count expires,
the 21040 initiates transaction termination as soon as its GNT_L is
deasserted.

Table 3–9 lists the access rules for the CFLT register.

Table 3–9 CFLT Access Rules

Category Description

Value after software

All reserved bits are 0.

reset

Read access rules –

Write access rules Written once during configuration.

3.1.2.5 Configuration Base I/O Address Register (CBIO)

The CBIO register specifies the base I/O address for accessing the 21040 CSRs
(CSR0 through CSR15). For example, if the CBIO register is programmed to
1000H, the I/O address of CSR15 is equal to CBIO + CSR15-offset for a value
of 1078H (Table 3–18).

This register must be initialized prior to accessing any CSR.

Figure 3–5 shows the CBIO bit fields and Table 3–10 describes the bit fields.

Figure 3–5 CBIO Configuration Base I/O Address Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Configuration Base I/O Address

2

111111111

1

0

Memory I/O

MLO-011363

Table 3–10 CBIO Configuration Base I/O Address Register Description

Field Description

31:7 Configuration Base I/O Address

Defines the address assignment mapping of 21040 CSRs.

6:1 This field value is 0 when read.

0 I/O Space Indicator

Determines that the register maps into the I/O space. The value in this
field is 1. This is a read-only field.

3–9

Table 3–11 lists the access rules for the CBIO register.

Table 3–11 CBIO Access Rules

Category Description

Value after reset Software reset has no effect.

Read access rules –

Write access rules Written once during configuration.

3.1.2.6 Configuration Base Memory Address Register (CBMA)

The CBMA register specifies the base memory address for memory accesses to
the 21040 CSRs (CSR0 through CSR15).

This register must be initialized prior to accessing any CSR0 register.

Figure 3–6 shows the CBMA bit fields, and Table 3–12 describes the bit fields.

Figure 3–6 CBMA Configuration Base Memory Address Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

0

3–10

Configuration Memory Base Address

Memory Space Indicator

MLO-011364

Table 3–12 CBMA Configuration Base Memory Address Register Description

Field Description

31:7 Configuration Base Memory Address

Defines the address assignment mapping of the 21040 CSRs.

6:1 This field value is 0 when read.

0 Memory Space Indicator

Determines that the register maps into the memory space. The value in
this field is 0. This is a read-only field.

Table 3–13 lists the access rules for the CBMA register.

Table 3–13 CBMA Access Rules

Category Description

Value after reset Software reset has no effect.

Read access rules –

Write access rules Written once during configuration.

3.1.2.7 Configuration Interrupt Register (CFIT)

The CFIT register is divided into two sections: the interrupt line and the
interrupt pin. CFIT configures both the system’s interrupt line and the 21040
interrupt pin connection.

Figure 3–7 shows the CFIT bit fields, and Table 3–14 describes the bit fields.

Figure 3–7 CFIT Configuration Interrupt Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Interrupt Pin

Interrupt Line

2

111111111

1

MLO-011365

Table 3–14 CFIT Configuration Interrupt Register Description

Field Description

15:8 Interrupt Pin

Indicates which interrupt pin the 21040 uses. The 21040 uses INTA#,
and the read value is 01H.

7:0 Interrupt Line

Provides interrupt line routing information. The BIOS writes the routing
information into this field when it initializes and configures the system.

The value in this field indicates which input of the system interrupt
controller the 21040’s interrupt pin is connected to. The driver can use
this information to determine priority and vector information. Values in
this field are architecture-specific.

0

3–11

Table 3–15 lists the access rules for the CFIT register.

Table 3–15 CFIT Access Rules

Category Description

Value after reset Software reset has no effect.

Read access rules –

Write access rules –

3.1.2.8 Configuration Driver Area Register (CFDA)

The CFDA register can be used to store driver-specific information during
initialization. It has no effect on the 21040 operation.

Figure 3–8 shows the CFDA bit field, and Table 3–16 describes the bit field.

Figure 3–8 CFDA Configuration Driver Area Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Driver Special Use

2

111111111

1

MLO-011366

Table 3–16 CFDA Configuration Driver Area Register Description

Field Description

15:8 Driver Special Use

Read and write fields for the driver’s special use.

Table 3–17 lists the access rules for the CFDA register.

0

3–12

Table 3–17 CFDA Access Rules

Category Description

Value after reset Software reset has no effect.

Read access rules –

Write access rules –

3.2 Command and Status Registers

The 21040 contains 16 command and status registers, which can be accessed
by the host. Table 3–18 lists the CSR registers.

Table 3–18 CSR Mapping

Register Meaning

CSR0 Bus mode register 00H

CSR1 Transmit poll demand 08H

CSR2 Receive poll demand 10H

CSR3 Receive list base address 18H

CSR4 Transmit list base address 20H

CSR5 Status register 28H

CSR6 Operation mode register 30H

CSR7 Interrupt mask register 38H

CSR8 Missed frame counter 40H

CSR9 Ethernet ROM register 48H

CSR10 Reserved 50H

CSR11 Full-duplex register 58H

CSR12 SIA status register 60H

CSR13 SIA connectivity register 68H

CSR14 SIA transmit receive register 70H

CSR15 SIA general register 78H

Offset from CSR Base
Address (CBIO, CBMA)

The 21040 CSRs are located in the host I/O or memory address space.
The CSRs are quadword-aligned and can only be accessed using longword
instructions.

3–13

• Register access is only longword access; byte accesses to CSR0–
CSR15 are not supported. Accessing a non-longword address
register causes UNPREDICTABLE data results.

• Reserved bits must be written with 0. Reserved bits are
UNPREDICTABLE on read accesses.

• Retries on second data transactions occur in response to burst I/O
accesses.

CSRs are physically located in the chip. The host uses a single instruction
to access to a CSR. Most commonly used 21040 features are contained in the
CSRs.

3.2.1 Host CSRs

There are 12 CSRs (CSR0 through CSR11) used to communicate with the host.

3.2.1.1 Bus Mode Register (CSR0)

Figure 3–9 shows the CSR0 bit fields, and Table 3–19 describes the bit fields.
CSR0 establishes the bus operating modes.

Note

3–14

Figure 3–9 CSR0 Bus Mode Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

TAP - Transmit Automatic Polling

DAS - Diagnostic Address Space

CAL - Cache Alignment

PBL - Programmable Burst Length

BLE - Big/Little Endian

DSL - Descriptor Skip Length

BAR - Bus Arbitration

SWR - Software Reset

MLO-011327

0

3–15

Table 3–19 CSR0 Bus Mode Register Description

Field Description

18:17 TAP—Transmit Automatic Polling (read, write)

When set and the 21040 is in a suspended state because of a transmit buffer
unavailable, the 21040 performs a transmit automatic poll demand (Table 3–20).

16 DAS—Diagnostic Address Space (read, write)

When reset, CSR0 through CSR15 are mapped on I/O space and memory space
(21040 address space becomes 128 bytes).

When set, all 16 CSRs and all diagnostic registers are mapped on I/O and memory
space.

15:14 CAL—Cache Alignment (read, write)

Programmable address boundaries for data burst stop (Table 3–22). If the buffer is
not aligned, the 21040 executes the first transfer up to the address boundary, then
all transfers are aligned to the specified boundary.

13:8 PBL—Programmable Burst Length (read, write)

Indicates the maximum number of longwords to be transferred in one DMA
transaction. If PBL = 0, the 21040 burst is limited only by the amount of data
stored in the receive FIFO (at least 16 longwords) or by the amount of free space in
the transmit FIFO (at least 16 longwords) before issuing a bus request.

The PBL can be programmed with permissible values 0, 1, 2, 4, 8, 16, or 32. After
reset, the PBL default value is 0.

7 BLE—Big/Little Endian (read, write)

When set, the 21040 operates in big endian byte ordering mode. When reset, the
21040 operates in little endian byte ordering mode.

Big endian is applicable only for data buffers.
For example, the byte order in little endian of a data buffer is 12345678H, with

each digit representing a nibble. In big endian, the byte orientation is 78563412H.

6:2 DSL—Descriptor Skip Length (read, write)

Specifies the number of longwords to skip between two descriptors.

To improve performance, descriptors can be placed in a separate cache line and
should not have to be contiguous.

1 BAR—Bus Arbitration (read, write)

(continued on next page)

3–16

Table 3–19 (Cont.) CSR0 Bus Mode Register Description

Field Description

Selects the internal bus arbitration between the receive and transmit processes.
When set, a round robin arbitration scheme is applied resulting in equal sharing

between processes. When reset to 0, the receive process has priority over the
transmit process, unless the 21040 is currently transmitting (Section 5.2).

0 SWR—Software Reset (read, write)

When set, the 21040 resets all internal hardware.
When reset, duration should be at least 10 PCI clock cycles. After reset deassertion,

the first bus transaction to the 21040 should not be initiated before at least 50 more
PCI cycles elapse.

Software reset does not affect the configuration area.

Table 3–20 defines the transmit automatic polling bits.

Table 3–20 Transmit Automatic Polling Bits

CSR0<18:17> Time Intervals

00 No transmit automatic polling; CSR1 access should be used to poll

01 Transmit automatic polling every 200 microseconds.

10 Transmit automatic polling every 800 microseconds.

11 Transmit automatic polling every 1.6 milliseconds.

the transmit descriptor list.

Table 3–21 lists the CSR0 access rules.

Table 3–21 CSR0 Access Rules

Category Description

Value after reset FFF80000H.

Read access rules –

Write access rules To write, the transmit and receive processes must be

stopped. If one or both of the processes is not stopped,
the result is UNPREDICTABLE.

Table 3–22 defines the cache address alignment bits.

3–17

Table 3–22 Cache Address Alignment Bits

CSR0<15:14> Address Alignment

00 Not used

01 8-longword boundary alignment

10 16-longword boundary alignment

11 32-longword boundary alignment

3.2.1.2 Transmit Poll Demand (CSR1)

Figure 3–10 shows the CSR1 bit field, and Table 3–23 describes the bit field.

Figure 3–10 CSR1 Transmit Poll Demand

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

TPD - Transmit Poll Demand

2

Table 3–23 CSR1 Transmit Poll Demand Description

Field Description

0 TPD—Transmit Poll Demand (write)

When written with any value, the 21040 checks for frames to be transmitted. If
no descriptor is available, the transmit process returns to the suspended state
and CSR5<2> is not asserted. If the descriptor is available, the transmit process
resumes.

Table 3–24 lists the CSR1 access rules.

111111111

1

MLO-010299

0

3–18

Table 3–24 CSR1 Access Rules

Category Description

Value after reset FFFFFFFFH

Read access rules –

Write access rules Not effective if the transmit process is not in the suspended

state.

3.2.1.3 Receive Poll Demand (CSR2)

Figure 3–11 shows the CSR2 bit field, and Table 3–25 describes the bit field.

Figure 3–11 CSR2 Receive Poll Demand

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

RPD - Receive Poll Demand

2

Table 3–25 CSR2 Receive Poll Demand Description

0 RPD—Receive Poll Demand (write)

When written with any value, the 21040 checks for receive descriptors to be
acquired. If no descriptor is available, the receive process returns to the suspended
state and CSR5<7> is not asserted. If the descriptor is available, the receive
process resumes.

Table 3–26 lists the access rules for CSR2.

111111111

1

MLO-010300

0

3–19

Table 3–26 CSR2 Access Rules

Category Description

Value after reset FFFFFFFFH

Read access rules –

Write access rules Effective only if the receive process is in the suspended

state.

3.2.1.4 Descriptor List Addresses (CSR3, CSR4)

The CSR3 descriptor list address register is used for receive buffer descriptors,
and the CSR4 descriptor list address register is used for transmit buffer
descriptors. In both cases, the registers are used to point the 21040 to the start
of the appropriate descriptor list.

Figure 3–12 shows the CSR3 bit field, and Table 3–27 describes the bit field.

Note

The descriptor lists reside in physical memory space and must be
longword-aligned. The 21040 behaves unpredictably when the lists are

not longword-aligned.

Writing to either CSR3 or CSR4 is permitted only when its respective process
is in the stopped state. When stopped, the CSR3 and CSR4 registers must be
written before the respective START command is given (Section 3.2.1.6).

3–20

Figure 3–12 CSR3 Receive List Base Address

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

Start of Receive List

111111111

1

MLO-010301

Table 3–27 CSR3 Receive List Base Address Description

Field Description

31:2 Start of receive list (read, write)

1:0 Must be 00 (read, write)

0

Figure 3–13 shows the CSR4 bit field, and Table 3–28 describes the bit field.

Figure 3–13 CSR4 Transmit List Base Address

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

Start of Transmit List

111111111

1

MLO-010302

0

Table 3–28 CSR4 Transmit List Base Address Description

Field Description

31:2 Start of transmit list (read, write)

1:0 Must be 00 (read, write)

Table 3–29 lists the access rules for CSR3, and Table 3–30 lists the access rules
for CSR4.

Table 3–29 CSR3 Access Rules

Category Description

Value after reset UNPREDICTABLE

Read access rules –

Write access rules Receive process stopped

Table 3–30 CSR4 Access Rules

Category Description

Value after reset UNPREDICTABLE

Read access rules –

Write access rules Transmit process stopped

3–21

3.2.1.5 Status Register (CSR5)

The status register CSR5 contains all the status bits that the 21040 reports to
the host. CSR5 is usually read by the driver during interrupt service routine
or polling. Most of the fields in this register cause the host to be interrupted.
CSR5 bits are not cleared when read. Writing 1 to these bits clears them;
writing 0 has no effect. Each field can be masked (Section 3.2.1.7).

Figure 3–14 shows the CSR5 bit fields, and Table 3–31 describes the bit fields.

3–22

Figure 3–14 CSR5 Status Register

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

222222222

EB - Error Bits

TS - Transmission Process State

RS - Receive Process State

NIS - Normal Interrupt Summary

AIS - Abnormal Interrupt Summary

SE - System Error

LNF - Link Fail

FD - Full-Duplex Short Frame Received

AT - AUI/TP Pin

RWT - Receive Watchdog Time-Out

RPS - Receive Process Stopped

RU - Receive Buffer Unavailable

RI - Receive Interrupt

111111111

2

1

0

UNF - Transmit Underflow

TJT - Transmit Jabber Time-Out

TU - Transmit Buffer Unavailable

TPS - Transmit Process Stopped

TI - Transmit Interrupt

MLO-010303

3–23

Table 3–31 CSR5 Status Register Description

Field Description

25:23 EB—Error Bits (read)

Indicates the type of error that caused system error. Valid only when system error
CSR5<13> is set (Table 3–32). This field does not generate an interrupt.

22:20 TS—Transmit Process State (read)

Indicates the state of the transmit process (Table 3–33). This field does not
generate an interrupt.

19:17 RS—Receive Process State (read)

Indicates the state of the receive process (Table 3–34). This field does not generate
an interrupt.

16 NIS—Normal Interrupt Summary (read, write)

Normal interrupt summary bit. Its value is the logical OR of

CSR5<0>—Transmit interrupt
CSR5<2>—Transmit buffer unavailable
CSR5<6>—Receive interrupt

Unmasked bits affect only the normal interrupt summary CSR5<16> bit.

15 AIS—Abnormal Interrupt Summary (read, write)

Abnormal interrupt summary bits. Its value is the logical OR of

CSR5<1>—Transmit process stopped
CSR5<3>—Transmit jabber time-out
CSR5<5>—Transmit underflow
CSR5<7>—Receive buffer unavailable
CSR5<8>—Receive process stopped
CSR5<9>—Receive watchdog time-out
CSR5<10>—AUI/TP pin
CSR5<11>—Full-duplex short frame received
CSR5<12>—Link fail
CSR5<13>—System error

Unmasked bits affect only the abnormal interrupt summary CSR5<15> bit.

13 SE—System Error (read, write)

Indicates that a system error occurred (Table 3–32).

12 LNF—Link Fail (read, write)

Indicates that a link fail occurred in the twisted-pair lines. See link fail status
CSR12<2>.

3–24

(continued on next page)

Table 3–31 (Cont.) CSR5 Status Register Description

Field Description

11 FD—Full-Duplex Short Frame Received (read, write)

Indicates that the first full-duplex short frame was received. The driver should
wait for the second 64-byte full-duplex packet (Section 5.8).

The full-duplex auto configuration short packet is treated as any other runt frame
except that full-duplex short frame received CSR5<11> is asserted. (In pass bad
frame or promiscuous filtering modes, this packet is transferred to the host.)

10 AT—AUI/TP Pin (read, write)

Indicates that the SIA AUI/TP pin has changed position.

9 RWT—Receive Watchdog Time-Out (read, write)

Indicates that the receive watchdog timer expired, and another node is babbling on
the network. Current frame reception aborts while length error RDES0<14> and
last descriptor RDES0<8> assert. Receive interrupt CSR5<6> also asserts, and the
receive process remains in the running state.

8 RPS—Receive Process Stopped (read, write)

Indicates that the receive process is stopped. Table 5–2 explains the receive process
state transitions.

7 RU—Receive Buffer Unavailable (read, write)

Indicates that the next descriptor in the receive list is owned by the host and
cannot be acquired by the 21040. The reception process is suspended. To
resume processing receive descriptors, the host should change the ownership of
the descriptor and might issue a receive poll demand command. If no receive
poll demand is issued, the reception process resumes when the next recognized
incoming frame is received.

After the first assertion, CSR5<7> does not assert for any subsequent not owned
receive descriptors fetches. CSR5<R7> asserts only when the previous receive
descriptor was owned by the 21040.

6 RI—Receive Interrupt (read, write)

Indicates the completion of a frame reception. Specific frame status information
has been posted in the descriptor. The reception process remains in the running
state.

(continued on next page)

3–25

Table 3–31 (Cont.) CSR5 Status Register Description

Field Description

5 UNF—Transmit Underflow (read, write)

Indicates that the transmit FIFO had an underflow condition during the packet
transmission. The transmit process is placed in the suspended state, and underflow
error TDES0<1> is set.

3 TJT—Transmit Jabber Time-Out (read, write)

Indicates that the transmit jabber timer expired, meaning that the 21040
transmitter was babbling. The transmission process is aborted and placed in
the stopped state. This event causes the transmit jabber time-out TDES0<14> flag
to assert.

2 TU—Transmit Buffer Unavailable (read, write)

Indicates that the next descriptor on the transmit list is owned by the host and
cannot be acquired by the 21040. The transmission process is suspended. Table 5–3
explains the transmit process state transitions. To resume processing transmit
descriptors, the host should change the ownership bit of the descriptor, then issue a
transmit poll demand command, unless transmit automatic polling (Table 3–20) is
enabled.

1 TPS—Transmit Process Stopped (read, write)

Asserts when the transmit process enters the stopped state.

0 TI—Transmit Interrupt (read, write)

Indicates that a frame transmission was completed, while TDES1<31> is asserted
in the first descriptor of the frame.

3–26

Table 3–32 lists the bit codes for the bus error bits.

Table 3–32 Bus Error Bits

CSR5<25:23> Process State Recover Mechanism

000 Parity error 21040 software reset CSR0<0> = 1

001 Master abort System error CSR5<13> = 1 (Section 6.4.2.1.3)

010 Target abort System error CSR5<13> = 1 (Section 6.4.2.2.1)

011 Reserved –

1xx Reserved –

Table 3–33 lists the bit codes for the transmit process state.

Table 3–33 Transmit Process State

CSR5<22:20> Process State

000 Stopped—RESET command or transmit jabber expired

001 Running—Fetch transmit descriptor

010 Running—Wait for end of transmission

011 Running—Read buffer from memory, and queue the data into the

100 Reserved

101 Running—Setup packet

110 Suspended—Transmit FIFO underflow or an unavailable transmit

111 Running—Close transmit descriptor

transmit FIFO

descriptor

Table 3–34 lists the bit codes for the receive process state.

Table 3–34 Receive Process State

CSR5<19:17> Process State

000 Stopped—RESET or STOP RECEIVE command

001 Running—Fetch receive descriptor

010 Running—Check for end-of-receive packet before prefetch of next

011 Running—Wait for receive packet

100 Suspended—Unavailable receive buffer

101 Running—Close receive descriptor

110 Running—Flush the current frame from the receive FIFO because of

111 Running—Queue the receive frame from the receive FIFO into the

descriptor

unavailable receive buffer

receive buffer

Table 3–35 lists the access rules for CSR5.

3–27

Table 3–35 CSR5 Access Rules

Category Description

Value after reset FC000000H

Read access rules –

Write access rules CSR5 bits 0 through 16 are cleared by writing 1. Writing 0

to these bits has no effect. Writing to CSR5 bits 17 through
25 has no effect.

3–28

3.2.1.6 Operation Mode Register (CSR6)

CSR6 establishes the receive and transmit operating modes and commands.
CSR6 should be the last CSR to be written as part of initialization.
Figure 3–15 shows the CSR6 bit fields, and Table 3–36 describes the bit
fields.

Figure 3–15 CSR6 Operating Mode Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

CA - Capture Effect Enable

BP - Back Pressure

TR - Threshold Control Bits

ST - Start/Stop Transmission Command

FC - Force Collision Mode

OM - Operating Mode

FD - Full-Duplex Mode

FKD - Flaky Oscillator Disable

PM - Pass All Multicast

PR - Promiscuous Mode

SB - Start/Stop Backoff Counter

IF - Inverse Filtering

PB - Pass Bad Frames

2

111111111

1

0

HO - Hash-Only Filtering Mode

SR - Start/Stop Receive

HP - Hash/Perfect Receive Filtering Mode

MLO-011328

3–29

Table 3–36 CSR6 Operating Mode Register Description

Field Description

17 CA—Capture Effect Enable (read, write)

When set, enables the resolution of the capture effect on the network (Section 7.4.7).

When reset, the 21040 disables the resolution of the capture effect on the network.

This feature is not part of the IEEE 802.3 and Ethernet standards.

16 BP—Back Pressure (read, write)

When set, enables the transmit back pressure logic. When receive data buffers are
exhausted, the 21040 asserts the transmit carrier for a maximum period of 500
milliseconds. Upon back pressure, if a 21040 receive descriptor becomes available
(a receive poll demand was issued), the 21040 stops back pressure and fetches the
descriptor.

When reset, disables the transmit back pressure logic.

This feature is not part of the IEEE 802.3 and Ethernet standards.

15:14 TR—Threshold Control Bits (read, write)

Controls the selected threshold level for the 21040 transmit FIFO. Four threshold
levels are allowed (Table 3–37).

The threshold value has a direct impact on the 21040 bus arbitration scheme
(Section 5.2).

Transmission starts when the frame size within the transmit FIFO is larger
than the threshold. Full frames with a length less than the threshold are also
transmitted.

The transmit process must be in the stopped state to change these bits
(CSR6<15:14>).

13 ST—Start/Stop Transmission Command (read, write)

(continued on next page)

3–30

Table 3–36 (Cont.) CSR6 Operating Mode Register Description

Field Description

When set, the transmission process is placed in the running state, and the 21040
checks the transmit list at the current position for a frame to be transmitted.

Descriptor acquisition is attempted either from the current position in the list,
which is the transmit list base address set by CSR4, or from the position retained
when the transmit process was previously stopped. If no descriptor can be acquired,
the transmit process enters the suspended state.

If the current descriptor is not owned by the 21040, the transmission process enters
the suspended state, and transmit buffer unavailable CSR5<2> is set. The start
transmission command is honored only when the transmission process is stopped.
If the command is issued before setting CSR4, the 21040 will behave unpredictably.

When reset, the transmission process is placed in the stopped state after completing
the transmission of the current frame. The next descriptor position in the transmit
list is saved and becomes the current position when transmission is restarted.

The stop transmission command is honored only when the transmission process is
in either the running or suspended state (Table 5–3).

12 FC—Force Collision Mode (read, write)

Allows the collision logic to be tested. Meaningful only in internal loopback mode.
When set, a collision is forced during the next transmission attempt. This results
in 16 transmission attempts with excessive collision reported in the transmit
descriptor (TDES0<8>).

11:10 OM—Operating Mode (read, write)

Selects the 21040 main mode of operation (Table 3–59).

9 FD—Full-Duplex Mode (read, write)

When set, the 21040 operates in a full-duplex mode (Section 5.8). The 21040
transmits and receives functions simultaneously (Table 3–59).

Setting the 21040 to operate in full-duplex mode is allowed only if the transmit and
receive processes are in the stopped state, and the start/stop receive (CSR6<1>) and
start/stop transmission commands (CSR6<13>) are both set to 0.

While in full-duplex mode, heartbeat check is disabled, heartbeat fail TDES0<7>
should be ignored, and internal loopback is not allowed.

8 FKD—Flaky Oscillator Disable (read, write)

When set, indicates that the internal flaky oscillator is disabled; pseudo random
numbers are chosen instead of fully random numbers. This bit is set only for
diagnostic purposes.

7 PM—Pass All Multicast (read, write)

(continued on next page)

3–31

Table 3–36 (Cont.) CSR6 Operating Mode Register Description

Field Description

When set, indicates that all the incoming frames with a multicast destination
address (first bit in the destination address field is 1) are received. Incoming
frames with physical address destinations are filtered according to the CSR6<0>
bit.

6 PR—Promiscuous Mode (read, write)

When set, indicates that any incoming valid frame is received, regardless of its
destination address.

After reset, the 21040 wakes up in promiscuous mode.

5 SB—Start/Stop Backoff Counter (read, write)

When set, indicates that the internal backoff counter stops counting when any
carrier activity is detected. The 21040 backoff counter resumes when the carrier
drops. The earliest the 21040 starts its transmission is 9.6 microseconds after
carrier deassertion.

When reset, the internal backoff counter is not affected by the carrier activity.

This feature violates IEEE 802.3 and Ethernet standards.

4 IF—Inverse Filtering (read)

When set, the 21040 operates in an inverse filtering mode (Table 4–8).

3 PB—Pass Bad Frames (read, write)

When set, the 21040 operates in pass bad frame mode. All incoming frames that
passed the address filtering are received, including runt frames, collided fragments,
or truncated frames caused by FIFO overflow.

If any received bad frames are required, promiscuous mode (CSR6<6>) should be
set to 1.

2 HO—Hash-Only Filtering Mode (read)

When set, the 21040 operates in an imperfect address filtering mode for both
physical and multicast addresses (Table 4–8).

1 SR—Start/Stop Receive (read, write)

(continued on next page)

3–32

Table 3–36 (Cont.) CSR6 Operating Mode Register Description

Field Description

When set, the receive process is placed in the running state. The 21040 attempts
to acquire a descriptor from the receive list and processes incoming frames.

Descriptor acquisition is attempted from the current position in the list, which is
the address set by CSR3 or the position retained when the receive process was
previously stopped. If no descriptor is owned by the 21040, the receive process
enters the suspended state and receive buffer unavailable (CSR5<7>) sets.

The start reception command is honored only when the reception process has
stopped. If the command was issued before setting CSR3, the 21040 behaves
unpredictably.

When cleared, the receive process enters the stopped state after completing the
reception of the current frame. The next descriptor position in the receive list is
saved, and becomes the current position after the receive process is restarted. The
stop reception command is honored only when the receive process is in running or
suspended state (Section 5.5.4).

0 HP—Hash/Perfect Receive Filtering Mode (read)

When reset, the 21040 does a perfect address filter of incoming frames according to
the addresses specified in the setup frame (Table 4–8).

When set, the 21040 does imperfect address filtering of the incoming frame
according to the hash table specified in the setup frame.

Table 3–37 lists the threshold values in bytes.

Table 3–37 Transmit Threshold

CSR6<15:14> Threshold (Bytes)

00 72

01 96

10 128

11 160

3–33

Table 3–38 lists the codes to determine the filtering mode.

Table 3–38 Filtering Mode

CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode

0 0 0 0 0 16 perfect filtering

0 0 0 0 1 512-bit hash + 1 perfect filtering

0 0 0 1 0 512-bit hash for multicast and physical

0 0 0 1 1 Not applicable

0 0 1 0 0 Inverse filtering

0 0 1 0 1 Not applicable

0 0 1 1 0 Not applicable

0 0 1 1 1 Not applicable

0 1 0 0 0 Promiscuous

0 1 0 0 1 Promiscuous

0 1 0 1 0 Promiscuous

0 1 0 1 1 Not applicable

0 1 1 0 0 Not used

0 1 1 0 1 Not used

0 1 1 1 0 Not used

0 1 1 1 1 Not used

1 0 0 0 0 Pass all multicast

1 0 0 0 1 Pass all multicast

1 0 0 1 0 Pass all multicast

1 0 0 1 1 Not applicable

1 0 1 0 0 Not used

1 0 1 0 1 Not applicable

1 0 1 1 0 Not applicable

1 0 1 1 1 Not applicable

1 1 0 0 0 Promiscuous

1 1 0 0 1 Promiscuous

1 1 0 1 0 Promiscuous

addresses

(continued on next page)

3–34

Table 3–38 (Cont.) Filtering Mode

CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode

1 1 0 1 1 Not applicable

1 1 1 0 0 Not used

1 1 1 0 1 Not applicable

1 1 1 1 0 Not applicable

1 1 1 1 1 Not applicable

Table 3–39 describes the only conditions that permit change to a field when
modifying values to CSR6.

Table 3–39 CSR6 Access Rules

Category Description

Value after reset FFFC0040H

Read access rules –

Write access rules

* CSR6<11:10> Receive and transmit processes

* CSR6<12> Receive and transmit processes

* CSR6<3> Receive process stopped

* CSR6<15:14> Transmit process stopped

* CSR6<8> Transmit process stopped

* CSR6<9> Transmit process stopped

* CSR6<5> Receive and transmit processes

* CSR6<17> Receive and transmit processes

* CSR6<16> Receive and transmit processes

* Start_Receive CSR6<1>=1 CSR3 initialized

* Start_Transmit CSR6<13>=1 CSR4 initialized

* Stop_Receive CSR6<1>=0 Receive running or suspended

* Stop_Transmit CSR6<13>=0 Transmit running or suspended

stopped

stopped, internal_loopback mode

stopped

stopped

stopped

3–35

3.2.1.7 Interrupt Mask Register (CSR7)

The Interrupt Mask register (CSR7) masks the interrupts reported by CSR5
(Section 3.2.1.5). Setting a bit to 1 enables a corresponding interrupt. After a
hardware or software reset, all interrupts are disabled. Figure 3–16 shows the
CSR7 bit fields, and Table 3–40 describes the bit fields.

Figure 3–16 CSR7 Interrupt Mask Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

NIM - Normal Interrupt Summary Mask

AIM - Abnormal Interrupt Summary Mask

SEM - System Error Mask

LFM - Link Fail Mask

FDM - Full-Duplex Mask

ATM - AUI/TP Switch Mask

RWM - Receive Watchdog Time-Out Mask

RSM - Receive Stopped Mask

RUM - Receive Buffer Unavailable Mask

RIM - Receive Interrupt Mask

UNM - Underflow Interrupt Mask

TJM - Transmit Jabber Time-Out Mask

TUM - Transmit Buffer Unavailable Mask

2

111111111

1

0

3–36

TSM - Transmission Stopped Mask

TIM - Transmit Interrupt Mask

MLO-010305

Table 3–40 CSR7 Interrupt Mask Register Description

Field Description

16 NIM—Normal Interrupt Summary Mask (read, write)

When set, normal interrupt is posted.

When reset, no normal interrupt is posted. This bit (CSR7<16>) masks the
following bits:

CSR5<0>—Transmit interrupt
CSR5<2>—Transmit buffer unavailable
CSR5<6>—Receive interrupt

15 AIM—Abnormal Interrupt Summary Mask (read, write)

When set, abnormal interrupt is posted.

When reset, no abnormal interrupt is posted. This bit CSR7<15> masks the
following bits:

CSR5<1>—Transmit process stopped
CSR5<3>—Transmit jabber time-out
CSR5<5>—Transmit underflow
CSR5<7>—Receive buffer unavailable
CSR5<8>—Receive process stopped
CSR5<9>—Receive watchdog time-out
CSR5<10>—AUI/TP pin
CSR5<11>—Full-duplex short frame received
CSR5<12>—Link fail
CSR5<13>—System error

13 SEM—System Error Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
system error (CSR5<13>), the interrupt is posted.

When reset and system error (CSR5<13>) is set, the interrupt posting is disabled.

12 LFM—Link Fail Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and link
fail (CSR5<12>), the interrupt is posted.

When reset and link fail (CSR5<12>) is set, the interrupt posting is disabled.

11 FDM—Full-Duplex Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
full-duplex short frame received (CSR5<11>), the interrupt is posted.

When reset and full-duplex CSR5<11> is set, the interrupt posting is disabled.

(continued on next page)

3–37

Table 3–40 (Cont.) CSR7 Interrupt Mask Register Description

Field Description

10 ATM—AUI/TP Switch Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
AUI/TP pin (CSR5<10>), the interrupt is posted.

When reset and AUI/TP (CSR5<10>) is set, the interrupt posting is disabled.

9 RWM—Receive Watchdog Time-Out Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
receive watchdog time-out (CSR5<9>), the interrupt is posted.

When reset and receive watchdog time-out (CSR5<9>) is set, the interrupt posting
is disabled.

8 RSM—Receive Stopped Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
receive stopped (CSR5<8>), the interrupt is posted.

When reset and receive stopped (CSR5<8>) is set, the interrupt posting is disabled.

7 RUM—Receive Buffer Unavailable Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
receive buffer unavailable (CSR5<7>), the interrupt is posted.

When reset and receive buffer unavailable (CSR5<7>) is set, the interrupt posting
is disabled.

6 RIM—Receive Interrupt Mask (read, write)

When set together with normal interrupt summary mask (CSR7<16>) and receive
interrupt bit (CSR5<6>), the interrupt is posted.

When reset and receive interrupt (CSR5<6>) is set, the interrupt posting is
disabled.

5 UNM—Underflow Interrupt Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
transmit underflow (CSR5<5>), the interrupt is posted.

When reset and transmit underflow (CSR5<5>) is set, the interrupt posting is
disabled.

3 TJM—Transmit Jabber Time-Out Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
transmit jabber time-out (CSR5<3>), the interrupt is posted.

When reset and transmit jabber time-out (CSR5<3>) is set, the interrupt posting is
disabled.

(continued on next page)

3–38

Table 3–40 (Cont.) CSR7 Interrupt Mask Register Description

Field Description

2 TUM—Transmit Buffer Unavailable Mask (read, write)

When set together with normal interrupt summary mask (CSR7<16>) and transmit
buffer unavailable (CSR5<2>), the interrupt is posted.

When reset and transmit buffer unavailable (CSR5<2>) is set, the interrupt posting
is disabled.

1 TSM—Transmission Stopped Mask (read, write)

When set together with abnormal interrupt summary mask (CSR7<15>) and
transmission stopped (CSR5<1>), the interrupt is posted.

When reset and transmission stopped (CSR5<1>) is set, the interrupt posting is
disabled.

0 TIM—Transmit Interrupt Mask (read, write)

When set together with normal interrupt summary mask (CSR7<16>) and transmit
interrupt (CSR5<0>), the interrupt is posted.

When reset and transmit interrupt (CSR5<0>) is set, the interrupt posting is
disabled.

Table 3–41 lists the access rules for CSR7.

Table 3–41 CSR7 Access Rules

Category Description

Value after reset FFFE0000H

Read access rules –

Write access rules –

3–39

3.2.1.8 Missed Frame Counter (CSR8)

Figure 3–17 shows the CSR8 bit fields, and Table 3–42 describes the bit fields.

Figure 3–17 CSR8 Missed Frame Counter

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Missed Frame Overflow

Missed Frame Counter

2

111111111

1

MLO-010306

Table 3–42 CSR8 Missed Frame Counter Description

Field Description

16 Missed Frame Overflow (read)

Sets when the missed frame counter overflows; resets when CSR8 is read.

15:0 Missed Frame Counter (read)

Indicates the number of frames discarded because no host receive
descriptors were available. The counter clears when read.

Table 3–43 lists the access rules for CSR8.

Table 3–43 CSR8 Access Rules

Category Description

0

3–40

Value after reset FFFE0000H

Read access rules –

Write access rules Not possible

3.2.1.9 Ethernet Address ROM Register (CSR9)

This register provides an interface to the external Ethernet address ROM.
It contains a data byte that is serially read from the ROM. Each read access
causes 8-bit, serial, read cycles from the Ethernet address ROM. Writing to this
register resets the pointer of the Ethernet address ROM to its first location.

Figure 3–18 shows the Ethernet address ROM register, and Table 3–44
describes the register bit fields.

Figure 3–18 CSR9 Ethernet Address ROM Register

DN - Data Not Valid

DT - Data

Table 3–44 CSR9 Ethernet Address ROM Register Description

Field Description

31 DN—Data Not Valid

7:0 DT—Data

Table 3–45 lists the access rules for CSR9.

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

MLO-011329

When set, indicates that the byte transfer from the ROM is not
completed. Subsequent reads must be performed until this bit returns 0,
indicating that the data byte field is valid in CSR9<7:0>. Also, the ROM
pointer indicates the location of the next byte in ROM.

Contains the data byte read from the Ethernet address ROM.

0

3–41

Table 3–45 CSR9 Access Rules

Category Description

Value after reset UNPREDICTABLE

Read access rules –

Write access rules ROM pointer reset

3.2.1.10 Full-Duplex Register (CSR11)

This register contains a 16-bit value for received full-duplex auto configuration
support. Figure 3–19 shows the CSR11 bit fields, and Table 3–46 describes the
bit fields.

Figure 3–19 CSR11 Full-Duplex Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

Full-Duplex Auto Configuration Value

2

111111111

1

MLO-010309

Table 3–46 CSR11 Full-Duplex Register Description

Field Description

15:0 Full-Duplex Auto Configuration Value (read, write)

Contains the full-duplex auto configuration value. When this field is set,
the 21040 monitors received short frames with a maximum length of 80
bits: 64 bits for preamble and 16 bits of data. If the 16 bits of data match
this field, the full-duplex short frame CSR5<11> is set.

Table 3–47 lists the access rules for CSR11.

0

3–42

Table 3–47 CSR11 Access Rules

Category Description

Value after reset FFFF0000H

Read access rules Not possible

Write access rules Receive process stopped

3.2.2 Serial Interface Attachment CSRs

This section describes the four serial interface attachment (SIA) registers:
CSR12, CSR13, CSR14, and CSR15. This description includes different SIA
configurations and diagnostic programming. SIA status is maintained in
CSR12.

The SIA registers control the functionality and connectivity of the SIA features,
enabling various configurations and options. Some of the configurations are
used only for diagnostic and testing purposes. The AUI or 10BASE-T selection
is done in one of the following ways:

• SIA Auto Configuration—The SIA automatically configures to AUI or
10BASE-T according to the setup described in Table 3–52.

• SIA Pin Configuration—The SIA automatically configures to AUI or
10BASE-T according to the setup described in Table 3–52.

• SIA Full Programming—All three SIA registers (CSR13, CSR14, and
CSR15) are programmed with the values required to achieve functionality
for special configurations such as full-duplex, loopback, and diagnostic.

Note

Before changing any value in CSR13, CSR14, or CSR15, first perform
an SIA software reset by writing CSR13 with all zeros (CSR13 =
00000000H).

Any mode change from SIA_full_programming to SIA_auto_configuration
or SIA_pin_configuration must be preceded by setting all SIA registers
to their reset values. These values are as follows:

CSR13 = FFFF0000H
CSR14 = FFFFFFFFH
CSR15 = FFFF0000H

3–43

3.2.2.1 SIA Status Register (CSR12)

The SIA status register reads SIA pins and internal states. Figure 3–20 shows
the CSR12 bit fields, and Table 3–48 describes the bit fields.

Figure 3–20 CSR12 SIA Status Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

DAO - PLL All One

DAZ - PLL All Zero

DSP - PLL Self-Test Pass

DSD - PLL Self-Test Done

APS - Auto Polarity State

LKF - Link Fail Status

NCR - Network Connection Error

PAUI - PIN AUI_TP Indication

2

111111111

1

MLO-010310

Table 3–48 CSR12 SIA Status Register Description

Field Description

7 DAO—PLL All One

Diagnostic bit. When set, indicates that all phase lock loop (PLL) sampler
synchronizers are asserted high.

6 DAZ—PLL All Zero

Diagnostic bit. When set, indicates that all PLL sampler synchronizers are asserted
low.

5 DSP—PLL Self-Test Pass

PLL built-in integrity self-test status indicator (self-test start CSR15<12>).

0

(continued on next page)

3–44

Table 3–48 (Cont.) CSR12 SIA Status Register Description

Field Description

PLL self-test pass (CSR12<5>) is valid only if PLL self-test done (CSR12<4>) is
read as 1. If PLL self-test done (CSR12<4>) is 1 and PLL self-test pass (CSR12<5>)
is 1, the self-test is successful; otherwise, the self-test fails.

4 DSD—PLL Self-Test Done

Reset when PLL self-test is initiated. Set after self-test completes.

3 APS—Auto Polarity State

When set, the 10BASE-T polarity is positive. When reset, the 10BASE-T polarity
is negative. The received bit stream is inverted by the receiver. (Refer to auto
polarity enable CSR14<13> and set polarity plus CSR14<14>.)

2 LKF—Link Fail Status

When set, the 10BASE-T link test is in fail state. When reset, the 10BASE-T link
test is in pass state.

During link fail, the 21040 does not transmit any packet to the media. However,
any queued packets in the transmit list can be closed by the 21040 with the
following set:

TDES0<2>—Link fail
TDES0<10>—No carrier
TDES0<11>—Loss of carrier

The 21040 moves from the link fail state to the link pass state when it receives
two consecutive packets. The driver receives no indication about these packets.
Following this, no transmit packet is pending and no carrier is sensed.

1 NCR—Network Connection Error

This bit has two meanings:

• In AUI, when set, it indicates no carrier. The status resets itself during the
next transmission attempt.

• In 10BASE-T, this bit sets if no link pass state was established within

2.4 seconds from switching to 10BASE-T (indicating cable failure, for example).
If a link pass state was established within 2.4 seconds from switching to
10BASE-T, this bit resets.

0 PAUI—PIN AUI_TP Indication

When set, indicates that the external AUI_TP PIN is connected to the supply
voltage (VDD), requesting AUI interface. When reset, indicates that the external
AUI_TP PIN is connected to ground (VSS), requesting 10BASE-T interface.

Table 3–49 lists the access rules for CSR12.

3–45

Table 3–49 CSR12 Access Rules

Category Description

Value after reset FFFFFFC4H or FFFFFFC5H

Read access rules –

Write access rules Read-only register

3.2.2.2 SIA Connectivity Register (CSR13)

CSR13 contains the SIA connectivity control bits that permit the intercon­nection of different sections within the SIA to allow coverage of the required
operation and test options.

Figure 3–21 shows the CSR13 bit fields, and Table 3–50 describes the bit
fields.

3–46

Figure 3–21 CSR13 SIA Connectivity Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

OE57 - Output Enable 5 6 7

OE24 - Output Enable 2 4

OE13 - Output Enable 1 3

IE - Input Enable

SEL - External Port Output Multiplexer Select

ASE - APLL Start Enable

SIM - Serial Interface Input Multiplexer

ENI - Encoder Input Multiplexer

EDP - SIA PLL External Input Enable

AUI - 10BASE-T or AUI

CAC - CSR Auto Configuration

PS - Pin AUI/TP Selection

SRL - SIA Reset

MLO-011330

0

3–47

Table 3–50 CSR13 SIA Connectivity Register Description

Field Description

15 OE57—Output Enable 5 6 7

Diagnostic bit. When set, pins 5, 6, and 7 of the external SIA interface are selected
as outputs. When reset, these pins are selected as inputs (Table 3–54).

14 OE24—Output Enable 2 4

Diagnostic bit. When set, pins 2 and 4 of the external SIA interface are selected as
outputs. When reset, these pins are selected as inputs (Table 3–54).

13 OE13—Output Enable 1 3

Diagnostic bit. When set, pins 1 and 3 of the external SIA interface are selected as
outputs. When reset, these pins are selected as inputs (Table 3–54).

12 IE—Input Enable

Diagnostic bit. When set, all the pins that were selected as inputs by CSR13<15:13>
are enabled. When reset, all the pins that were selected as inputs by CSR13<15:13>
are disabled.

11:8 SEL—External Port Output Multiplexer Select

Diagnostic bit. These bits select the internal signals routed to the EXTERNAL_SIA
port. The routing control enables this port to resume different functions for normal
and diagnostic mode operation. (Table 3–55 lists the signals that can be routed to
the port.)

7 ASE—APLL Start Enable

Diagnostic bit. When set, enables the analog phase lock loop differential mode
starter. This bit is used for engineering purposes.

6 SIM—Serial Interface Input Multiplexer

Diagnostic bit. When set, enables the selection of the external SIA operating mode
(Table 3–53).

5 ENI—Encoder Input Multiplexer

Diagnostic bit. When reset, normal operation mode is selected. When set, it allows
direct driving of the encoder inputs from the EXTERNAL_SIA port (Table 3–54).

4 EDP—SIA PLL External Input Enable

Diagnostic bit. When set, enables direct driving of the PLL from the EXTERNAL_
SIA port (Table 3–54).

3 AUI—10BASE-T or AUI

(continued on next page)

3–48

Table 3–50 (Cont.) CSR13 SIA Connectivity Register Description

Field Description

When reset, forces the 21040 to select the 10BASE-T interface. When set to 1,
forces the 21040 to select the AUI interface. This bit is valid only if the AUI/TP pin
CSR13<1> is reset (Table 3–52).

2 CAC—CSR Auto Configuration

When set, forces CSR13, CSR14, and CSR15 into a predetermined value according
to the selection of AUI CSR13<3> bit. This bit is valid only if CSR13<1> is reset
(Table 3–52).

1 PS—Pin AUI/TP Selection

When set, forces CSR13, CSR14, and CSR15 into a predetermined value according
to the selection of the AUI_TP pin (Table 3–52).

0 SRL—SIA Reset

When reset, resets all the SIA functions and machines. This bit is valid only if the
AUI/TP pin selection CSR13<1> and CSR auto configuration CSR13<2> are both
reset.

Table 3–51 lists the access rules for CSR13.

Table 3–51 CSR13 Access Rules

Category Description

Value after reset FFFF0000H.

Read access rules If either AUI/TP pin selection CSR13<1> or CSR auto

Write access rules CSR13 should be reset to 00000000H before writing to any

configuration CSR13<2> is set, the value of CSR13 reflects
the internal states rather than the values written into the
CSR.

SIA CSR and released with or after the last CSR write.

3–49

3.2.2.3 SIA Operational Modes

The following four bits are used to determine the AUI and 10BASE-T
modes of operation. Using these four bits in SIA_auto_configuration or
SIA_pin_configuration format overrides all other CSR13, CSR14, and CSR15
bits (Table 3–52).

CSR13<3>—10BASE-T or AUI selection
CSR13<2>—CSR auto configuration
CSR13<1>—Pin AUI/TP selection
CSR13<0>—SIA reset

Table 3–52 AUI—10BASE-T Selection Using SIA_Auto_Configuration and

SIA_Pin_Configuration

CSR13<1> CSR13<2> CSR13<3> AUI_TP Pin Setting

1 X X VDD AUI Mode—SIA_pin_configuration

1 X X VSS TP Mode—SIA_pin_configuration

0 1 1 X AUI Mode—SIA_auto_configuration

0 1 0 X TP Mode—SIA_auto_configuration

Table 3–53 lists the programming of the different SIA modes using CSR13,
CSR14, and CSR15. The states of operating mode CSR6<11:10> and full­duplex mode CSR6<9> are also identified.

Table 3–53 Programming of SIA Modes Using CSR13, CSR14, and CSR15

Mode CSR13 CSR14 CSR15 CSR6<11:10> CSR6<9> Note

10BASE-T
normal

10BASE-T
normal

10BASE-T
normal

10BASE-T
full-duplex

3–50

8F01H FFFFH 0000H 00 0 LEDs enabled.

EF01H FFFFH 0000H 00 0 External SIA

port enabled for
diagnostics.

0F01H FFFFH 0000H 00 0 External SIA port

disabled.

8F01H FFFDH 0000H 00 1 See Section 5.8.

(continued on next page)

Table 3–53 (Cont.) Programming of SIA Modes Using CSR13, CSR14, and CSR15

Mode CSR13 CSR14 CSR15 CSR6<11:10> CSR6<9> Note

10BASE-T
internal
loopback

10BASE-T
external
loopback

AUI normal 8F09H 0705H 0006H 00 0 LEDs enabled.

AUI normal EF09H 0705H 0006H 00 0 External SIA

AUI normal 0F09H 0705H 0006H 00 0 External SIA port

AUI external
loopback

External SIA 3041H 0000H 0006H 00 0 —

Internal
loopback

8F01H FEFBH 0000H 10 0 See Section 5.7.

8F01H F9FDH 0000H 10 0 See Section 5.7.

port enabled for
diagnostics.

disabled.

8F09H 0705H 0006H 10 0 See Section 5.7.

xxxxH xxxxH xxxxH 01 0 See Section 5.7.

3.2.2.4 SIA Port Configurations

The following list contains three sets of output enable bits that control the
external SIA port interface.

OE57—Output enable bits 5, 6, and 7 (CSR13<15>)
OE24—Output enable bits 2 and 4 (CSR13<14>)
OE13—Output enable bits 1 and 3 (CSR13<13>)

The SIA port contains three sub-ports. Each sub-port can be used as either an
input or output sub-port regardless of how the other sub-ports are configured.
Each configuration enables the external SIA port to reflect different functional
interfaces for different configurations of the SIA section, mainly for diagnostics.
Table 3–54 lists the external SIA port mode selections.

3–51

Table 3–54 External SIA Port Mode Selections

Mode Pin Name

Port
Number CSR13<15:12> Function

Normal (no
LEDs)

Normal (LEDs) – – 1000 Internal 10BASE-T and AUI

External SIA – – 0011 External chip eliminates need

– – 0000 Internal 10BASE-T and AUI

interfaces are on.

EXT_TXEN 1 Tristate, no input

EXT_TCLK 2 Tristate, no input

EXT_TX 3 Tristate, no input

EXT_RCLK 4 Tristate, no input

EXT_RXEN 5 Tristate, no input

EXT_RX 6 Tristate, no input

EXT_CLSN 7 Tristate, no input

interfaces are on.

EXT_TXEN 1 Tristate, no input

EXT_TCLK 2 Tristate, no input

EXT_TX 3 Tristate, no input

EXT_RCLK 4 Tristate, no input

EXT_RXEN 5 Output—network activity

LED

EXT_RX 6 Output—LinkPass LED

EXT_CLSN 7 Output—AUI/10BASE-T LED

for internal SIA functions.

EXT_TXEN 1 Output

EXT_TCLK 2 Input

EXT_TX 3 Output

EXT_RCLK 4 Input

EXT_RXEN 5 Input

EXT_RX 6 Input

EXT_CLSN 7 Input

(continued on next page)

3–52

Table 3–54 (Cont.) External SIA Port Mode Selections

Mode Pin Name

Port
Number CSR13<15:12> Function

Trace – – 1110 Different internal signals are

EXT_TXEN 1 Output—multiplexed signals

EXT_TCLK 2 Output—multiplexed signals

EXT_TX 3 Output—multiplexed signals

EXT_RCLK 4 Output—multiplexed signals

EXT_RXEN 5 Output—multiplexed signals

EXT_RX 6 Output—multiplexed signals

EXT_CLSN 7 Output—multiplexed signals

reflected through the port
(Table 3–55).

The following four select lines for the output multiplexer enable the routing of
56 internal SIA signals to the external SIA port.

SEL0 (CSR13<8>)
SEL1 (CSR13<9>)
SEL2 (CSR13<10>)
SEL3 (CSR13<11>)

Table 3–55 lists the external SIA output multiplexer selection.

Table 3–55 External SIA Output Multiplexer Selection

CSR13<11:8> Pin Name

Port
Number Signal Name Function

00XX – – – 21040—SIA interface

signals (external SIA mode)

EXT_TXEN 1 jab_txen

EXT_TCLK 2 tclk

EXT_TX 3 jab_txd

EXT_RCLK 4 rclk

EXT_RXEN 5 rxen

(continued on next page)

3–53

Table 3–55 (Cont.) External SIA Output Multiplexer Selection

CSR13<11:8> Pin Name

EXT_RX 6 rx

EXT_CLSN 7 clsn

01XX – – – Diagnostics—SIA interface

EXT_TXEN 1 decmx_rxd

EXT_TCLK 2 tlp_reset

EXT_TX – decmx_rxen

EXT_RCLK 4 dmux_rxen

EXT_RXEN 5 tp_cmp_out

EXT_RX – poslp_detect_set

EXT_CLSN 7 neglp_detect_set

1111 – – – LED and external driver

EXT_TXEN 1 aui_txen

EXT_TCLK 2 sndlnk

EXT_TX 3 tp_txen

EXT_RCLK 4 clk419_4304m

EXT_RXEN 5 xver_active

EXT_RX 6 link_pass

EXT_CLSN 7 lcsr13_aui

100X – – – PLL diagnostic signals

EXT_TXEN 1 wp_all<5>

EXT_TCLK 2 wp_all<6>

EXT_TX 3 wp_all<7>

EXT_RCLK 4 wp_all<8>

EXT_RXEN 5 wp_all<9>

EXT_RX 6 wp_all<10>

EXT_CLSN 7 wp_all<11>

Port
Number Signal Name Function

signals

signals (AUI or TP mode
with LEDs)

(continued on next page)

3–54

Table 3–55 (Cont.) External SIA Output Multiplexer Selection

CSR13<11:8> Pin Name

101X – – – PLL diagnostic signals

EXT_TXEN 1 apll_cphase<5>

EXT_TCLK 2 Reserved

EXT_TX 3 Reserved

EXT_RCLK 4 Reserved

EXT_RXEN 5 Reserved

EXT_RX 6 Reserved

EXT_CLSN 7 Reserved

1100 – – – SIA-RxM diagnostic signals

EXT_TXEN 1 poslpulse

EXT_TCLK 2 poseoframe

EXT_TX 3 neglpulse

EXT_RCLK 4 negeoframe

EXT_RXEN 5 colpulsm_on

EXT_RX 6 rcvpulsp_on

EXT_CLSN 7 rcvpulsp_on

1101 – – – SIA-RxM machine

EXT_TXEN 1 aui_clsn

EXT_TCLK 2 rcv_pulse

EXT_TX 3 clr_dtct

EXT_RCLK 4 col_pulsem

EXT_RXEN 5 rcvff1

EXT_RX 6 rcvff2

EXT_CLSN 7 rcvff4

1110 – – – Link test and other

EXT_TXEN 1 plsmaxtmr2

EXT_TCLK 2 plsmintmr2

Port
Number Signal Name Function

diagnostic signals

diagnostic signals

(continued on next page)

3–55

Table 3–55 (Cont.) External SIA Output Multiplexer Selection

CSR13<11:8> Pin Name

EXT_TX 3 plsendcnt

EXT_RCLK 4 eoftmr

EXT_RXEN 5 txwatch_exp$ss

EXT_RX 6 rlocked$ss

EXT_CLSN 7 aui_tpc$ss

Port
Number Signal Name Function

3.2.2.5 SIA Transmit and Receive Register (CSR14)

CSR14 configures the SIA transmitter and receiver operating modes.
Figure 3–22 shows the CSR14 bit fields, and Table 3–56 describes the bit
fields. This register is mainly used for diagnostic purposes.

3–56

Figure 3–22 CSR14 SIA Transmit and Receive Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

2

111111111

1

SPP - Set Polarity Plus

APE - Auto Polarity Enable

LTE - Link Test Enable

SQE - Signal Quality (Heartbeat) Generate Enable

CLD - Collision Detect Enable

CSQ - Collision Squelch Enable

RSQ - Receive Squelch Enable

CPEN - Compensation Enable

LSE - Link Pulse Send Enable

DREN - Driver Enable

LBK - Loopback Enable

ECEN - Encoder Enable

MLO-011369

0

3–57

Table 3–56 CSR14 SIA Transmit and Receive Register Description

Field Description

14 SPP—Set Polarity Plus

When reset and auto polarity enable (CSR14 <13>) is reset, the polarity of the
incoming data is switched. This feature can be used by the driver to reverse
polarity of incoming packets; otherwise, this bit should be set. This bit is valid only
in 10BASE-T mode.

13 APE—Auto Polarity Enable

When set and link test enable CSR14<12> is also set, the auto polarity function
logic is enabled (Section 7.1.7). When reset, the polarity is determined by set
polarity plus (CSR14<14>). When link test enable (CSR14<12>) is reset, this bit
(CSR14<13>) should be also reset. This bit is valid only in 10BASE-T mode.

12 LTE—Link Test Enable

When set, the link test function logic is enabled. In AUI mode, it should be reset.
In 10BASE-T mode, resetting this bit forces the link test function to link pass state.

11 SQE—Signal Quality (Heartbeat) Generate Enable

Controls the signal quality (SQE) generator ability to imitate external medium
attachment unit (MAU) behavior. When set, a short heartbeat signal is
generated after the conclusion of a transmitted packet. In 10BASE-T mode, SQE
(CSR14<11>) should be set; otherwise, a heartbeat fail (TDES0<7>) is set. In AUI
mode, SQE (CSR14<11>) should be reset.

10 CLD—Collision Detect Enable

When set, the collision detect logic is enabled.

9 CSQ—Collision Squelch Enable

When set, the AUI collision receivers are active. This bit is valid only when AUI is
selected.

8 RSQ—Receive Squelch Enable

When set, the AUI or 10BASE-T receivers are active in accordance with the
selected mode.

5:4 CPEN—Compensation Enable

Table 3–58 defines twisted-pair compensation behavior. This bit is valid only in
10BASE-T mode.

3 LSE—Link Pulse Send Enable

When set, the link pulse generator is enabled. In AUI mode, this bit should be
reset.

(continued on next page)

3–58

Table 3–56 (Cont.) CSR14 SIA Transmit and Receive Register Description

Field Description

2 DREN—Driver Enable

When set, the transmit SIA driver is enabled for AUI or 10BASE-T operation.
When reset, the transmit driver is disabled, preventing the data and link pulse
transmission to the external wires.

1 LBK—Loopback Enable

Enables loopback operation in SIA (Table 3–59 and Section 5.7.3).

0 ECEN—Encoder Enable

When set, the transmit data encoder is enabled, and the encoded data is transferred
to the output drivers. When reset, the transmit data encoder is disabled, and the
encoded data is blocked from propagating to the output drivers.

Table 3–57 lists the access rules for CSR14.

Table 3–57 CSR14 Access Rules

Category Description

Value after reset FFFFFFFFH.

Read access rules In both SIA_auto_configuration and SIA_pin_configuration

Write access rules CSR14 should be reset to 00000000H before writing any SIA

modes, a CSR14 read reflects internal states, rather than
the values written into the CSR.

CSR and released with or just after last CSR write.

3–59

Table 3–58 lists the compensation field (CSR14<5:4>) definitions.

Table 3–58 Twisted-Pair Compensation Behavior

CSR14<5:4>
Value Transmitter Output

00, 01 Compensation Disabled Mode—Twisted-pair driver does not

10 High Power Mode—Twisted-pair driver drives only high-differential

11 Normal Compensation Mode—Driver compensates for 10 megahertz

compensate for 10 megahertz versus 5 megahertz media attenuation
(differential voltages are bound between 1.5 volts and 2.1 volts).

voltage (between 2.2 volts and 2.8 volts).

versus 5 megahertz media attenuation by driving high-differential
voltage for transients and driving low if the signal is stable for more
than 50 nanoseconds.

3–60

3.2.2.6 SIA Mode Programming

Table 3–59 lists normal, full-duplex, and loopback programming. To monitor
these modes, the following signals are used in the table.

CSR6<11:10>—Operating mode
CSR6<9>—Full-duplex operating mode
CSR14<1>—Loopback enable
CSR14<10>—Collision detect enable
CSR14<8>—Receive squelch enable

Table 3–59 Normal, Full-Duplex, and Loopback Programming

Mode Note

CSR6
<11:10>

CSR6
<9>

CSR14
<1>

CSR14
<10>

CSR14
<8>

TP normal Packets are looped back from

TP full-duplex Loopback is disabled at SIA

TP on-chip
loopback

TP off-chip
loopback

AUI normal The external MAU performs

AUI external
loopback

External SIA
normal

External SIA
loopback

Internal
loopback

encoder output to PLL input.

level allowing PLL to lock onto
incoming packets.

Packets are looped back from
encoder output to decoder input.

Requires external shunt for
board testing.

loopback, but the receive and
transmit machines do not work
simultaneously.

Diagnostic checks up-to-MAU
path integrity. If collision, no
comparison is done.

The external MAU performs
loopback, but the receive and
transmit machines do not work
simultaneously.

Diagnostic checks up-to-MAU
path integrity. If collision, no
comparison is done.

For internal diagnostics on any
mode. The transmit packet is
looped back at the MAC level.

00 0 1 1 1

00 1 0 X 1

10 0 1 0 0

10 0 0 0 1

00 0 0 1 1

10 0 0 1 1

00 0 0 0 0

10 0 0 0 0

01 0 X X X

3–61

Note

Internal loopback is not permitted while in full-duplex mode.

3.2.2.7 SIA General Register (CSR15)

Figure 3–23 shows the CSR15 bit fields, and Table 3–60 describes the bit fields. This
register is mainly used for diagnostic purposes.

Figure 3–23 CSR15 SIA General Register

222222222

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

FRL - Force Receiver Low

DPST - PLL Self-Test Start

FLF - Force Link Fail

FUSQ - Force Unsquelch

TSCK - Test Clock

RWR - Receive Watchdog Release

RWD - Receive Watchdog Disable

JCK - Jabber Clock

HUJ - Host Unjab

JBD - Jabber Disable

2

111111111

1

MLO-010343

0

3–62

Table 3–60 CSR15 SIA General Register Description

Field Description

13 FRL—Force Receiver Low

Testing feature that forces the RX input to PLL samplers to a constant low. It is
used to detect stacked samplers.

12 DPST—PLL Self-Test Start

Testing feature that starts the PLL built-in integrity self-test. The status of the
test result is marked by PLL self-test done (CSR12<4>) and PLL self-test pass
(CSR12<5>) respectively.

11 FLF—Force Link Fail

Testing feature that forces a link fail state and resets both link test and auto
polarity detector.

9 FUSQ—Force Unsquelch

Testing feature that asserts the receiver RCVEN signal for testing purposes.

8 TSCK—Test Clock

Testing feature that affects certain SIA clocks. When test clock is asserted, it
increases, by 1024, all SIA clocks with a cycle time longer than 2 microseconds, to
increase events during product testing. Test clock assertion also causes the jabber
timer to expire 1000 times faster (transmitted packet is retried and not stopped.)

5 RWR—Receive Watchdog Release

Defines the time interval no carrier from receive watchdog expiration until re­enabling the receive channel. When set, the receive watchdog is released 40- to
48-bit-times from the last carrier deassertion. When reset, the receive watchdog is
released 16- to 24-bit-times from the last carrier deassertion.

4 RWD—Receive Watchdog Disable

When set, the receive watchdog counter is disabled. Receive carriers longer than
2560 bytes are guaranteed to cause the watchdog counter to time-out. Packets
shorter than 2048 bytes are guaranteed to pass.

2 JCK—Jabber Clock

When set, transmission is cut after 2048 to 2560 bytes are transmitted (1.6
to 2.0 milliseconds). When reset, transmission is cut after 26 milliseconds to
33 milliseconds.

1 HUJ—Host Unjab

Defines the time interval between transmit jabber expiration until re-enabling of
the transmit channel. When set, the transmit channel is released immediately
after the jabber expiration. When reset, the transmit jabber is released 365 to 420
milliseconds after jabber expiration.

0 JBD—Jabber Disable

When set, the transmit jabber function is disabled.

3–63

Table 3–61 lists the access rules for CSR15.

Table 3–61 CSR15 Access Rules

Category Description

Value after reset FFFF0000H.

Read access rules In SIA_auto_configuration and SIA_pin_configuration

Write access rules CSR15 should be reset to 00000000H before writing any SIA

modes, CSR15 read reflects internal states, rather than
the values written into the CSR.

CSR and released with or just after the last CSR write.

3–64

Host Communication Area

Descriptor lists and data buffers, collectively called the host communication
area, reside in the host memory and manage the actions and status related to
buffer management.

4.1 Data Communication

The 21040 and the driver communicate through two data structures:

• Command and status registers (CSRs) described in Chapter 3.

• Descriptor lists and data buffers described in this chapter.

4.2 Descriptor Lists and Data Buffers

The 21040 transfers frame data to and from the receive and transmit buffers
in host memory. Descriptors that reside in the host memory act as pointers to
these buffers.

There are two descriptor lists, one for receive and one for transmit. The base
address of each list is written into CSR3 and CSR4, respectively. A descriptor
list is forward-linked (either implicitly or explicitly). The last descriptor may
point back to the first entry to create a ring structure. Explicit chaining of
descriptors is accomplished by setting the second address chained in both
the receive and transmit descriptors (RDES1<24> and TDES1<24>). The
descriptor lists reside in the host physical memory address space. Each
descriptor can point to a maximum of two buffers. This enables two buffers to
be used, physically addressed, and not contiguous in memory (Figure 4–1).

4

A data buffer consists of either an entire frame or part of a frame, but it cannot
exceed a single frame. Buffers contain only data; buffer status is maintained in
the descriptor. Data chaining refers to frames that span multiple data buffers.
Data chaining can be enabled or disabled. Data buffers reside in host physical
memory space.

4–1

Figure 4–1 Descriptor Ring and Chain Structures

Ring Structure

Buffer 1

Descriptor 0

Buffer 2

Buffer 1

Descriptor 1

Buffer 2

Buffer 1

Descriptor N

Buffer 2

Chain Structure

Buffer 1

Descriptor 0

4–2

Buffer 1

Descriptor 1

Next Descriptor

MLO-010317

4.2.1 Receive Descriptors

Figure 4–2 shows the receive descriptor format.

Descriptors and receive buffer addresses must be longword-aligned.

Providing two buffers, two byte-count buffers, and two address pointers in
each descriptor enables the adapter port to be compatible with various types of
memory management schemes.

Figure 4–2 Receive Descriptor Format

31 0

RDES0

O

W

N

Note

Status

RDES1

RDES2

RDES3

Control Bits Byte Count Buffer 2 Byte Count Buffer 1

Buffer Address 1

Buffer Address 2

4.2.1.1 Receive Descriptor 0 (RDES0)

RDES0 contains the received frame status, the frame length, and the descriptor
ownership information. Figure 4–3 shows the RDES0 bit fields, and Table 4–1
describes the bit fields.

MLO-010318

4–3

Figure 4–3 RDES0 Receive Descriptor 0

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

OWN - Own Bit

FL - Frame Length

ES - Error Summary

LE - Length Error

DT - Data Type

RF - Runt Frame

MF - Multicast Frame

FS - First Descriptor

LS - Last Descriptor

TL - Frame Too Long

CS - Collision Seen

FT - Frame Type

RJ - Receive Watchdog

222222222

2

111111111

1

0

DB - Dribbling Bit

CE - CRC Error

OF - Overflow

4–4

MLO-010319

Table 4–1 RDES0 Receive Descriptor 0 Description

Field Description

31 OWN—Own Bit

When set, indicates that the descriptor is owned by the 21040. When reset,
indicates that the descriptor is owned by the host. The 21040 clears this bit either
when it completes the frame reception or when the buffers that are associated with
this descriptor are full.

30:16 FL—Frame Length

Indicates the length in bytes of the received frame including the cyclic redundancy
check (CRC).

This field is valid only when last descriptor (RDES<8>) is set and length error
(RDES0<14>) is reset.

15 ES—Error Summary

Indicates the logical OR of the following RDES0 bits:

RDES0<0>—Overflow
RDES0<1>—CRC error
RDES0<6>—Collision seen
RDES0<7>—Frame to long
RDES0<11>—Runt frame
RDES0<14>—Length error

This field is valid only when last descriptor (RDES<8>) is set.

14 LE—Length Error

When set, indicates a frame truncation caused by a frame that does not fit within
the current descriptor buffers and indicates that the 21040 does not own the next
descriptor. The frame is truncated.

This field is valid only when last descriptor (RDES<8>) is set.

13:12 DT—Data Type

This field is valid only when last descriptor (RDES<8>) is set.

(continued on next page)

4–5

Table 4–1 (Cont.) RDES0 Receive Descriptor 0 Description

Field Description

Indicates the type of frame the buffer contains.

00—Serial received frame.

01—Internal loopback frame.

10—External loopback frame or serial received frame. The 21040 does not
differentiate between loopback and serial received frames; therefore, this
information is global and reflects only the operating mode (CSR6<11:10>).

11—Reserved.

11 RF—Runt Frame

When set, indicates that this frame was damaged by a collision or premature
termination before the collision window had passed. Runt frames are passed on to
the host only if the pass bad frames bit (CSR6<3>) is set.

This field is valid only when last descriptor (RDES<8>) is set and overflow
(RDES0<0>) is reset.

10 MF—Multicast Frame

When set, indicates that this frame has a multicast address.
This field is valid only when last descriptor (RDES<8>) is set.

9 FS—First Descriptor

When set, indicates that this descriptor contains the first buffer of a frame.

If the buffer size of the first buffer is 0, the second buffer contains the beginning
of the frame. If the buffer size of the second buffer is also 0, the second descriptor
contains the beginning of the frame.

8 LS—Last Descriptor

When set, indicates that the buffers pointed to by this descriptor, are the last
buffers of the frame.

7 TL—Frame Too Long

When set, indicates that the frame length exceeds the maximum Ethernet specified
size of 1518 bytes.

This field is valid only when last descriptor (RDES<8>) is set.

4–6

Note

Frame too long is only a frame length indication and does not cause any
frame truncation.

(continued on next page)

Table 4–1 (Cont.) RDES0 Receive Descriptor 0 Description

Field Description

6 CS—Collision Seen

When set, indicates that the frame was damaged by a collision that occurred after
the 64 bytes following the start frame delimiter (SFD). This is a late collision.

This field is valid only when last descriptor (RDES<8>) is set.

5 FT—Frame Type

When set, indicates that the frame is an Ethernet type frame (frame length field is
greater than 1500 bytes). When clear, indicates that the frame is an IEEE 802.3
frame.

This field is not valid for runt frames of less than 14 bytes.
This field is valid only when last descriptor (RDES<8>) is set.

4 RJ—Receive Watchdog

When set, indicates that the receive watchdog timer expired while receiving the
current packet with length greater than 2048–2560 bytes. Receive watchdog
time-out (CSR5<9>) is set.

When RDES0<4> is set, the frame length field in RDES0<30:16> is not valid and
length error (RDES0<14>) is not set.

This field is valid only when last descriptor (RDES<8>) is set.

2 DB—Dribbling Bit

When set, indicates that the frame contained a non-integer multiple of 8 bits. This
error is reported only if the number of dribbling bits in the last byte is greater
than 2. This field is not valid if either collision seen (RDES0<6>) or runt frame
RDES0<11> are set.

This field is valid only when last descriptor (RDES<8>) is set.

1 CE—CRC Error

When set, indicates that a cyclic redundancy check (CRC) error occurred on the
received frame.

The CRC check is performed independent of a dribbling bit (RDES0<2>) error.
However, only whole bytes are run through the CRC logic. Consequently, received
frames with up to 6 dribbling bits cause this bit to be set.

This field is valid only when last descriptor (RDES<8>) is set.

0 OF—Overflow

(continued on next page)

4–7

Table 4–1 (Cont.) RDES0 Receive Descriptor 0 Description

Field Description

When set, indicates received data in this descriptor’s buffer were truncated due to
FIFO overflow. This generally occurs if 21040 bus requests are not granted before
the internal receive FIFO fills up.

This field is valid only when last descriptor (RDES<8>) is set.

4.2.1.2 Receive Descriptor 1 (RDES1)

Figure 4–4 shows the RDES1 bit fields, and Table 4–2 describes the bit fields.

Figure 4–4 RDES1 Receive Descriptor 1

33

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

RER - Receive End of Ring

RCH - Second Address Chained

RBS2 - Buffer 2 Size

RBS1 - Buffer 1 Size

222222222

2

111111111

1

0

MLO-010320

4–8