DEC Digital Alpha VME 4/224, Digital Alpha VME 4/288 User Manual

Digital Alpha VME 4/224 and 4/288Single-BoardComputers

UserGuideandTechnicalDescription

Order Number: EK–DAVME–TD. B01

This manual describes the Digital Alpha VME 4 module. It provides conﬁguration and installation procedures and describes the module’s built-in features, including the console code and diagnostics.

Revision/Update Information: This manual supersedes the Digital

Alpha VME 4/224 and 4/288 Single-Board Computers User Guide and Technical Description,

EK–DAVME–TD. A01.

Digital Equipment Corporation Maynard, Massachusetts

First Printing, July 1996 Revised, September 1996

Printed in U.S.A. The information in this document is subject to change without notice and should not be construed

as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

FCC Notice:

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.

Warning!

This is a Class A product. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.

Achtung!

Dieses ist ein Gerät der Funkstörgrenzwertklasse A. In Wohnbereichen können bei Betrieb dieses Gerätes Rundfunkstörungen auftreten, in welchen Fällen der Benutzer für entsprechende Gegenmaßnahmen verantwortlich ist.

Attention!

Ceci est un produit de Classe A. Dans un environment domestique, ce produit risque de créer des interférences radioélectriques, il appartiendra alors à l’utilisateur de prendre les mesures spéciﬁques appropriées.

Canadian EMC Notice:

‘‘This Class [A] Digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.’’

‘‘Cet appareil numerique de la class [A] respecte toutes les exigences du Reglement sur le materiel broilleur du Canada.’’

DECpc, Digital, OpenVMS, ThinWire, ULTRIX, VAX, and the DIGITAL logo. The following are third-party trademarks: DALLAS is a registered trademark of Dallas Systems Corporation.

Futurebus/Plus is a registered trademark of Force Computers GMBH, Germany. IBM is a registered trademark of International Business Machines Corporation. Intel is a trademark of Intel Corporation. NCR is a registered trademark of National Cash Register Company. OSF and OSF/1 are registered trademarks of Open Software Foundation, Inc. UNIX is a registered trademark licensed exclusively by X/Open Company Ltd. VIC64 is a trademark of Cypress Semiconductor Corporation. VxWorks is a registered trademark of Wind River Systems, Inc.

All other trademarks and registered trademarks are the property of their respective holders.

S3320

Contents

Preface ................................................ xxi

1 Product Overview

1.1 Product Description .............................. 1–1

1.2 Functional Speciﬁcations . . . ....................... 1–1

1.3 Physical and Environmental Requirements ............ 1–4

2 Installation Procedures

2.1 Unpacking ..................................... 2–1

2.2 Installation .................................... 2–6

2.2.1 Installing the PMC I/O Companion Card ........... 2–23

2.3 Diagnostics..................................... 2–27

2.4 Troubleshooting . . ............................... 2–29

2.5 Repair and Warranty Information ................... 2–32

2.5.1 Return to Digital Hardware Maintenance .......... 2–32

2.5.2 Hardware Warranty ........................... 2–32

2.5.2.1 Availability ............................... 2–32

2.5.2.2 Return-to-Digital Process .................... 2–33

2.5.2.3 Response Time ............................ 2–33

2.5.2.4 Eligible Parts ............................. 2–33

2.5.2.5 Purchaser Responsibility .................... 2–33

2.5.2.6 Pre-Call Checklist . . ....................... 2–34

2.5.3 Software Maintenance . . ....................... 2–34

2.5.4 Field Replaceable Units and Order Numbers . . ...... 2–35

iii

3 Operating the Digital Alpha VME 4 Computer

3.1 Controls and Indicators ........................... 3–1

3.2 Console Mode ................................... 3–3

3.2.1 Entering Console Mode . ....................... 3–3

3.2.2 Exiting Console Mode . . ....................... 3–3

3.3 Environment Variables............................ 3–3

3.4 Booting an Operating System ...................... 3–7

3.5 Updating Firmware .............................. 3–7

4 Diagnostics

4.1 Overview ...................................... 4–1

4.2 Operating Environments . . . ....................... 4–1

4.2.1 POST Diagnostics ............................ 4–1

4.2.2 Console Prompt Diagnostics ..................... 4–2

4.3 Diagnostic Test Descriptions ....................... 4–2

4.3.1 Available Console Diagnostics ................... 4–2

4.3.2 SROM Initialization Countdown . . ............... 4–4

4.3.3 Console POST Descriptions ..................... 4–5

POST Non-Volatile RAM Diagnostic . . ............... 4–6

POST Memory Diagnostic . . ....................... 4–7

4.3.4 Console Diagnostic Test Descriptions .............. 4–8

Heartbeat Timer Test ............................. 4–9

Interval Timer Tests ............................. 4–10

DECchip 21040 Ethernet Controller Tests ............. 4–16

DALLAS DS1386 RAMiﬁed Watchdog Timekeeper

Tests. . . ....................................... 4–18

Local Area Network Address ROM Test ............... 4–22

NCR 53C810 PCI-SCSI I/O Processor Tests ............ 4–24

Watchdog Timer Interrupt Test ..................... 4–27

VME Interface Tests ............................. 4–28

4.4 Initialization Sequence ............................ 4–30

5 System Address Mapping

5.1 CPU Address Mapping to PCI Space . . ............... 5–1

5.1.1 Cacheable Memory Space (0x000000000 to

0x0FFFFFFFF) .............................. 5–4

5.1.2 Noncacheable Memory Space (0x100000000 to

0x17FFFFFFF) .............................. 5–4

5.1.3 DECchip 21071-CA CSR Space (0x180000000 to

0x19FFFFFFF) .............................. 5–4

5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to

0x1AFFFFFFF) .............................. 5–5

5.1.5 PCI Interrupt Acknowledge/Special Cycle Space

(0x1B0000000 to 0x1BFFFFFFF) . . ............... 5–5

5.1.6 PCI Sparse I/O Space (0x1C0000000 to

0x1DFFFFFFF) .............................. 5–5

5.1.7 PCI Conﬁguration Space (0x1E0000000 to

0x1FFFFFFFF) .............................. 5–8

5.1.7.1 PCI Conﬁguration Cycles to Primary Bus

Targets. . . ............................... 5–9

5.1.7.2 PCI Conﬁguration Cycles to Secondary Bus

Targets. . . ............................... 5–10

5.1.8 PCI Sparse Memory Space (0x200000000 to

0x2FFFFFFFF) .............................. 5–11

5.1.9 PCI Dense Memory Space (0x300000000 to

0x3FFFFFFFF) .............................. 5–14

5.2 PCI-to-Physical Memory Addressing . . ............... 5–15

6 Cache and Memory Subsystem

6.1 System Bus Interface ............................. 6–4

6.1.1 Arbitration on the System Bus ................... 6–4

6.1.2 System Bus Controller . . ....................... 6–4

6.1.3 Decoding Addresses ........................... 6–4

6.2 Bcache Control . . . ............................... 6–5

6.3 Memory Controller ............................... 6–5

6.3.1 Memory Organization . . ....................... 6–6

6.3.2 Memory Address Generation .................... 6–7

6.3.3 Support for Memory Page Mode . . ............... 6–7

6.3.4 Minimizing Read Latency ...................... 6–7

6.3.5 Transaction Scheduler . . ....................... 6–7

6.3.6 Programmable Memory Timing . . . ............... 6–7

6.3.7 Presence Detect Logic . . ....................... 6–8

6.4 Error Handling . . ............................... 6–8

6.5 Address Space of Control/Status Registers ............. 6–8

6.6 Description of CSRs .............................. 6–11

6.6.1 General Control Register ....................... 6–11

6.6.2 Error and Diagnostic Status Register ............. 6–13

6.6.3 Tag Enable Register ........................... 6–16

6.6.4 Error Low Address Register ..................... 6–18

6.6.5 Error High Address Register .................... 6–19

6.6.6 LDx_L Low Address Register .................... 6–19

6.6.7 LDx_L High Address Register ................... 6–20

6.6.8 Memory Control Registers ...................... 6–20

6.6.8.1 Presence Detect Low-Data Register ............ 6–20

6.6.8.2 Presence Detect High-Data Register ........... 6–21

6.6.8.3 Base Address Registers ..................... 6–21

6.6.8.4 Conﬁguration Registers ..................... 6–22

6.6.8.5 Bank Set Timing Registers . . . ............... 6–24

6.6.8.6 Global Timing Register ..................... 6–27

6.6.8.7 Refresh Timing Register .................... 6–28

6.7 Data Path ..................................... 6–30

6.7.1 Memory Read Buffer . . . ....................... 6–31

6.7.2 I/O Read Buffer and Merge Buffer . ............... 6–31

6.7.3 I/O Write and DMA Read Buffer . . ............... 6–31

6.7.4 DMA Write Buffer ............................ 6–31

6.7.5 Memory Write Buffer . . . ....................... 6–32

6.7.6 Error Handling .............................. 6–32

7 PCI Host Bridge

7.1 Interface to the System Bus . ....................... 7–2

7.1.1 Decoding Physical Addresses .................... 7–2

7.1.2 Buffering System Bus Transactions ............... 7–3

7.1.3 Burst Length and Prefetching for the System Bus .... 7–3

7.2 Interface to the PCI bus ........................... 7–3

7.2.1 Decoding PCI Addresses ....................... 7–3

7.2.2 Buffering PCI Transactions ..................... 7–3

7.2.3 Burst Length and Prefetching for PCI bus .......... 7–4

7.3 Features ....................................... 7–4

7.3.1 Burst Order . . ............................... 7–4

7.3.2 Parity Support .............................. 7–4

7.3.3 Data Coherency .............................. 7–5

7.3.4 Interrupts . . . ............................... 7–6

7.3.5 Exclusive Access ............................ 7–6

7.3.6 Bus Parking . . ............................... 7–6

7.3.7 Retry Timeout ............................... 7–7

7.3.8 PCI Master Timeout . . . ....................... 7–7

7.3.9 Address Stepping in Conﬁguration Cycles .......... 7–7

7.4 Address Space of Control/Status Registers ............. 7–7

7.5 Description of CSRs .............................. 7–9

7.5.1 Diagnostic Control/Status Register ............... 7–9

7.5.2 PCI Error Address Register ..................... 7–13

7.5.3 System Bus Error Address Register ............... 7–14

7.5.4 Dummy Registers 1 Through 3 . . . ............... 7–15

7.5.5 Translated Base Registers 1 and 2 . ............... 7–15

7.5.6 PCI Base Registers 1 and 2 ..................... 7–16

7.5.7 PCI Mask Registers 1 and 2 .................... 7–17

7.5.8 Host Address Extension Register 0 ............... 7–18

7.5.9 Host Address Extension Register 1 ............... 7–18

7.5.10 Host Address Extension Register 2 ............... 7–19

7.5.11 PCI Master Latency Timer Register............... 7–20

7.5.12 TLB Tag Registers 0 Through 7 . . . ............... 7–20

7.5.13 TLB Data Registers 0 Through 7 . . ............... 7–21

7.5.14 Translation Buffer Invalidate All Register:

0x1A0000400 . ............................... 7–22

8 PCI bus

8.1 Ethernet Controller .............................. 8–3

8.1.1 PCI Conﬁguration Registers .................... 8–3

8.1.2 Ethernet Controller CSRs ...................... 8–4

8.1.3 PCI Cycles . . . ............................... 8–5

8.1.4 Ethernet Address ............................. 8–6

8.2 SCSI Controller . . ............................... 8–6

8.2.1 Connection and Termination .................... 8–6

8.2.2 SCSI ID .................................... 8–7

8.2.3 Programming . ............................... 8–7

8.2.4 PCI Conﬁguration Registers .................... 8–7

8.2.5 SCSI Control Status Registers ................... 8–8

8.3 PCI I/O Companion Card . . . ....................... 8–11

9 Nbus

9.1 Nbus Address Space .............................. 9–1

9.1.1 SIO Chip PCI Conﬁguration Space ............... 9–2

9.1.1.1 PCI Control Register ....................... 9–3

9.1.1.2 ISA Controller Recovery Timer Register . . ...... 9–4

9.1.1.3 ISA Clock Divisor Register................... 9–4

9.2 Module Registers . ............................... 9–4

vii

9.2.1 Module Display Control Register . ............... 9–5

9.2.2 Module Conﬁguration Register................... 9–6

9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4 .... 9–8

9.2.4 Memory Conﬁguration Registers 0, 1, 2, 3 and Memory

Identiﬁcation Register . . ....................... 9–8

9.2.5 Reset Reason Registers . ....................... 9–12

9.2.6 Heartbeat Register ............................ 9–14

9.2.7 Module Control Register 1 ..................... 9–14

9.2.8 Bcache Conﬁguration Register ................... 9–16

9.3 ROM ......................................... 9–17

9.4 Super I/O Chip . . . ............................... 9–18

9.4.1 Serial Port Channels A and B ................... 9–18

9.4.2 Super I/O Register Address Space . ............... 9–19

9.5 Keyboard and Mouse Controller ..................... 9–21

9.6 TOY Clock ..................................... 9–22

9.6.1 TOY Clock Timekeeping Registers . ............... 9–23

9.6.2 TOY Clock Command Register ................... 9–24

9.7 Interval Timing Registers . . ....................... 9–25

9.7.1 Interval Timing Control Register . . ............... 9–26

9.7.2 Timer Registers .............................. 9–28

9.7.3 Timer Modes . ............................... 9–29

9.7.4 Interrupts . . . ............................... 9–31

9.7.5 Timer Interrupt Status Registers . . ............... 9–32

9.8 Watchdog Timer . . ............................... 9–33

9.9 Nonvolatile RAM . ............................... 9–36

10 VME Interface

10.1 VMEbus Master . . ............................... 10–2

10.1.1 Outbound Scatter-Gather Mapping ............... 10–4

10.1.1.1 Address Modiﬁer . . . ....................... 10–6

10.1.1.2 Read-Modify-Write . . ....................... 10–6

10.1.2 Data Transfers ............................... 10–7

10.1.2.1 Single Mode Transfers ...................... 10–7

10.1.2.2 Block Mode Transfers....................... 10–7

10.1.3 Requesting the VMEbus. ....................... 10–9

10.2 VMEbus Slave . . ............................... 10–9

10.2.1 Decoding Addresses . . . ....................... 10–10

10.2.2 Inbound Scatter-Gather Entries . . . ............... 10–12

viii

10.2.3 Interprocessor Communication ................... 10–14

10.2.3.1 Interprocessor Communication Registers . . ...... 10–14

10.2.3.2 Interprocessor Communication Global Switches. . . 10–14

10.2.3.3 Interprocessor Communication Module

Switches . . ............................... 10–15

10.3 System Controller Operation ....................... 10–17

10.3.1 Arbitrating the VMEbus ....................... 10–18

10.3.1.1 Requesting the VMEbus..................... 10–18

10.3.1.2 Releasing the VMEbus ...................... 10–19

10.3.2 System Clock Output . . . ....................... 10–21

10.3.3 Timeout Timers .............................. 10–21

10.3.3.1 Arbitration Timers . . ....................... 10–21

10.3.3.2 VMEbus Transfer Timers .................... 10–22

10.3.3.3 Local Bus Transfer Timer ................... 10–23

10.3.4 VMEbus Interrupt Handling .................... 10–23

10.4 Byte Swapping . . . ............................... 10–26

10.4.1 DC7407 Byte Swapping . ....................... 10–26

10.4.2 VIC64 Byte Swapping . . ....................... 10–27

10.5 Initializing the VME Interface ...................... 10–30

10.5.1 VME PCI Conﬁguration Registers . ............... 10–30

10.5.2 Programming Scatter-Gather RAM ............... 10–31

10.5.3 Conﬁguring the VIC64 . . ....................... 10–32

10.6 Summary of VME Interface Registers . ............... 10–37

10.7 VME Subsystem Restrictions (as of 03-Jun-94) . . . ...... 10–40

10.7.1 Collision of VIC64 Master Write Posting with Master

Block Transfers .............................. 10–40

10.7.2 VIC64 Errata: A16 Master Cycles During

Interleave................................... 10–40

11 System Interrupts

11.1 System Interrupts ............................... 11–1

11.1.1 Xilinx Interrupt Controller ...................... 11–2

11.1.2 VIC64 Chip System Interrupt Controller ........... 11–4

11.1.2.1 Basic Operation ........................... 11–5

11.1.3 VIC64 Chip Interrupt Sources ................... 11–6

11.1.3.1 Local Device Interrupts ..................... 11–6

11.1.3.2 VMEbus Interrupt Requests . . ............... 11–7

11.1.3.3 Status/Error Interrupts ..................... 11–8

11.1.4 SIO Chip Programmable Interrupt Controller . ...... 11–11

11.1.4.1 Nonmaskable System Events . . ............... 11–11

11.1.4.2 NMI Status and Control Register ............. 11–12

11.1.4.3 EPIC Interrupt ........................... 11–13

11.2 Module Reset ................................... 11–13

12 Console Primer

12.1 About the Console ............................... 12–1

12.1.1 Console Features ............................ 12–1

12.1.2 Command Overview . . . ....................... 12–2

12.1.3 Shell Operators .............................. 12–3

12.1.4 Using Flow Control ........................... 12–4

12.2 Getting Information About the System ............... 12–5

12.3 Getting Help ................................... 12–6

12.4 Examining and Depositing to Memory or System Registers

.............................................. 12–7

12.4.1 Accessing Memory ............................ 12–9

12.4.2 Examining Registers . . . ....................... 12–10

12.5 Using Pipes and grep to Filter Output . ............... 12–12

12.6 Using I/O Redirection (>) . . ....................... 12–12

12.7 Running Commands in Background . . ............... 12–13

12.7.1 Monitoring Status ............................ 12–13

12.7.2 Killing a Process ............................. 12–14

12.8 Creating Scripts . ............................... 12–14

12.9 Copying Scripts Over the Network . . . ............... 12–15

13 Console Commands

13.1 Console Commands .............................. 13–1

13.1.1 Special Keys . . ............................... 13–1

13.1.2 Command Line Characteristics . . . ............... 13–2

13.1.3 Radix Control . ............................... 13–2

13.1.4 Console Command Dictionary ................... 13–3

alloc . . ....................................... 13–4

boot . . . ....................................... 13–6

break . . ....................................... 13–14

cat ........................................... 13–15

chmod . ....................................... 13–16

chown . ....................................... 13–18

clear . . ....................................... 13–19

clear_log ...................................... 13–20

date . . . ....................................... 13–21

deposit ....................................... 13–23

dynamic ...................................... 13–28

echo . . . ....................................... 13–30

eval . . . ....................................... 13–32

examine ...................................... 13–34

exer . . . ....................................... 13–40

exit . . . ....................................... 13–49

false . . ....................................... 13–50

free . . . ....................................... 13–51

grep . . . ....................................... 13–52

hd ........................................... 13–55

help . . . ....................................... 13–57

init_ev . ....................................... 13–59

initialize ...................................... 13–60

kill . . . ....................................... 13–61

line . . . ....................................... 13–62

ls ............................................ 13–63

memexer ...................................... 13–64

memtest ...................................... 13–65

net .......................................... 13–72

ps ........................................... 13–75

pwrup . ....................................... 13–76

rm ........................................... 13–77

sa ........................................... 13–78

semaphore ..................................... 13–79

set ........................................... 13–80

setled ........................................ 13–83

set reboot srom . . ............................... 13–84

set toy sleep ................................... 13–85

sh ........................................... 13–86

show . . ....................................... 13–88

show conﬁg .................................... 13–90

show device .................................... 13–91

show hwrpb .................................... 13–93

show led ...................................... 13–94

show map ..................................... 13–95

show_log ...................................... 13–96

sleep . . ....................................... 13–98

sort . . . ....................................... 13–99

sp ........................................... 13–100

start . . ....................................... 13–101

stop . . . ....................................... 13–102

update . ....................................... 13–103

A Module Connector Pinouts

A.1 CPU Connector Pinouts ........................... A–1

A.2 I/O Type 1 Card Connector Pinouts . . . ............... A–1

A.2.1 VMEbus (J1) Connector Pinouts . . ............... A–2

A.2.2 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A.2.3 Ethernet (J9) Connector Pinouts . . ............... A–4

A.3 Primary Breakout Module Connector Pinouts .......... A–4

A.4 Secondary Breakout Module Connector Pinouts . . . ...... A–6

A.4.1 Keyboard and Mouse (J1) Connector Pinouts . . ...... A–7

A.4.2 Parallel Port (J6) Connector Pinouts .............. A–8

A.5 PMC I/O Companion Card Connector Pinouts .......... A–9

Index

Figures

1–1 Digital Alpha VME 4 Block Diagram .............. 1–3

2–1 Digital Alpha VME 4 Module Components.......... 2–2

2–2 Digital Alpha VME 4 Module Layout .............. 2–7

2–3 I/O Module Layout ............................ 2–8

2–4 Installing the Main Memory Modules ............. 2–11

2–5 Cache Memory Modules . ....................... 2–13

2–6 Installing the Digital Alpha VME 4 Module. . . ...... 2–15

2–7 Alpha VME 4 Primary Breakout Module ........... 2–16

2–8 Primary Breakout Module Jumpers ............... 2–17

2–9 Connecting the SCSI Cable to the Primary Breakout

Module ..................................... 2–18

2–10 Installing the Primary Breakout Module ........... 2–19

2–11 Secondary Breakout Module Jumpers ............. 2–20

2–12 Connecting the Secondary Breakout Module to the

Primary Breakout Module ..................... 2–21

2–13 Connecting Network and Console Terminal Cables . . . 2–22

2–14 PMC I/O Companion Card Layout . ............... 2–23

xii

2–15 Connecting the PMC I/O Companion Card.......... 2–26

2–16 Installing the PMC I/O Companion Card ........... 2–27

3–1 Controls and Indicators . ....................... 3–2

4–1 Loopback Descriptions for Interval Timer Test 3 and

4.......................................... 4–15

4–2 LAN Address ROM Format ..................... 4–23

4–3 SROM Test Flows............................. 4–30

4–4 Console POST Flows . . . ....................... 4–31

4–5 Console POST Flows . . . ....................... 4–32

5–1 System Bus Address Map ...................... 5–2

5–2 PCI Sparse I/O Space Address Translation . . . ...... 5–6

5–3 PCI Memory Space Address Translation ........... 5–12

5–4 PCI Target Window Compare Scheme ............. 5–17

5–5 Scatter-Gather Map Page Table Entry in Memory .... 5–19

5–6 Scatter-Gather Map Translation of PCI Bus Address to

System Bus Address . . . ....................... 5–21

6–1 Cache and Memory Subsystem . . . ............... 6–1

6–2 Address and Data Paths of Cache and Memory ...... 6–2

6–3 21071-CA Block Diagram ....................... 6–3

6–4 Cache Subsystem fora2MBCache ............... 6–5

6–5 Maximum and Minimum DIMM Bank Layouts ...... 6–6

6–6 General Control Register: 0x180000000............ 6–11

6–7 Error and Diagnostic Status Register:

0x180000020 . ............................... 6–14

6–8 Tag Enable Register: 0x180000060 ............... 6–16

6–9 Error Low Address Register: 0x180000080 . . . ...... 6–19

6–10 Error High Address Register: 0x1800000A0 . . ...... 6–19

6–11 LDx_L Low Address Register: 0x1800000C0 . . ...... 6–20

6–12 LDx_L High Address Register: 0x1800000E0 . ...... 6–20

6–13 Presence Detect Low-Data Register: 0x180000280 . . . 6–21 6–14 Presence Detect High-Data Register: 0x180000260 . . . 6–21

6–15 Bank 0 Base Address Register: 0x180000800 . ...... 6–22

6–16 Conﬁguration Registers for Bank Set 0:

0x180000A00 . ............................... 6–22

6–17 Bank Set 0 Timing Register A: 0x180000C00 . . ...... 6–25

6–18 Bank Set 0 Timing Register B: 0x180000E00 . . ...... 6–26

6–19 Global Timing Register: 0x180000200 ............. 6–28

xiii

6–20 Refresh Timing Register: 0x180000220 ............ 6–29

6–21 Block Diagram of the DECchip 21071-BA .......... 6–30

7–1 PCI Host Bridge .............................. 7–1

7–2 DECchip 21071-DA Block Diagram ............... 7–2

7–3 Diagnostic Control/Status Register: 0x1A0000000 .... 7–10

7–4 PCI Error Address Register: 0x1A0000020 . . . ...... 7–14

7–5 System Bus Error Address Register: 0x1A0000040 . . . 7–14 7–6 Translated Base Registers 1, 2: 0x1A00000C0,

0x1A00000E0 . ............................... 7–15

7–7 PCI Base Registers 1 and 2: 0x1A0000100,

0x1A0000120 . ............................... 7–16

7–8 PCI Mask Registers 1 and 2: 0x1A0000140,

0x1A0000160 . ............................... 7–17

7–9 Host Address Extension Register 0: 0x1A0000180.... 7–18

7–10 Host Address Extension Register 1: 0x1A00001A0 . . . 7–18 7–11 Host Address Extension Register 2: 0x1A00001C0 . . . 7–19 7–12 PCI Master Latency Timer Register: 0x1A00001E0. . . 7–20 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to

0x1A00002E0 . ............................... 7–21

7–14 TLB Data Registers 0 Through 7: 0x1A0000300 to

0x1A00003E0 . ............................... 7–21

8–1 PCI Bus and Interfaces to the I/O Subsystem . ...... 8–2

8–2 PCI Conﬁguration Registers .................... 8–4

8–3 DECchip 21040-AA CSR9 (ENET ROM Register) .... 8–6

8–4 PCI Conﬁguration Block ....................... 8–8

9–1 Nbus and Nbus Resources ...................... 9–1

9–2 SIO Conﬁguration Block ....................... 9–3

9–3 Module Display Control Register . . ............... 9–6

9–4 Display Character Set . . ....................... 9–6

9–5 Module Conﬁguration Register................... 9–7

9–6 Memory Conﬁguration Registers 0-3 .............. 9–9

9–7 Memory Identiﬁcation Register . . . ............... 9–10

9–8 Reset Reason Registers . ....................... 9–13

9–9 Module Control Register 1 ...................... 9–15

9–10 Bcache Conﬁguration Register ................... 9–16

9–11 Flash ROM Layout/Addressing . . . ............... 9–18

9–12 TOY Clock Command Register ................... 9–24

9–13 82C54 Control Byte ........................... 9–26

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9–14 82C54 Timer Data Access ...................... 9–28

9–15 Timer Clocking ............................... 9–31

9–16 Timer Interrupt Status Register . . ............... 9–32

9–17 Watchdog Timer Registers ...................... 9–34

9–18 Watchdog Timer TOY Clock Command Register ..... 9–34

9–19 Watchdog Timer Module Control Register .......... 9–35

9–20 NVRAM Access .............................. 9–36

10–1 VME Interface Block Diagram ................... 10–1

10–2 Mapping Window_1 and Window_2 ............... 10–3

10–3 Mapping Pages From PCI to VME ............... 10–4

10–4 Outbound Scatter-Gather Entry . . . ............... 10–5

10–5 VIC Block Transfer Control Register .............. 10–8

10–6 Mapping Pages of Memory from VMEbus to PCI

Bus........................................ 10–10

10–7 Address Decoding ............................. 10–11

10–8 Base and Mask Register ....................... 10–11

10–9 Inbound Scatter-Gather Entry With A32 Address

Mapping .................................... 10–12

10–10 VME Interface Processor Page Monitor CSR . . ...... 10–13

10–11 VIC Arbiter/Requester Conﬁguration Register ...... 10–18

10–12 VIC Release Control Register.................... 10–20

10–13 VMEbus Transfer Timeout Register ............... 10–22

10–14 VIC Interrupt Request/Status Register ............ 10–24

10–15 VMEbus Interrupt Vector Base Registers .......... 10–25

10–16 VMEbus Interrupter Interrupt Control Register ..... 10–25

10–17 Swap Modes . . ............................... 10–27

10–18 Big Endian VME Byte Lane Formats ............. 10–28

11–1 Block Diagram of the Interrupt Logic ............. 11–2

11–2 Interrupt/Mask Register #1 ..................... 11–3

11–3 Interrupt/Mask Register #2 ..................... 11–3

11–4 Interrupt/Mask Register #3 ..................... 11–4

11–5 Interrupt/Mask Register #4 ..................... 11–4

11–6 Generic ICR . . ............................... 11–5

11–7 Device ICRs . . ............................... 11–7

11–8 VIC Local Interrupt Vector Base Register .......... 11–7

11–9 VME IRQ* ICRs.............................. 11–8

11–10 DMA Status ICR ............................. 11–9

11–11 VIC Error Group ICR. . . ....................... 11–10

11–12 VMEbus Interrupter ICR ....................... 11–10

11–13 VIC Error Group Interrupt Vector Base Register ..... 11–11

11–14 NMI Status and Control Register . ............... 11–12

A–1 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A–2 Ethernet (J9) Connector Pinouts . . ............... A–4

A–3 Primary Breakout Module Connector Pinouts . ...... A–6

A–4 Secondary Breakout Module Connector Pinouts...... A–7

A–5 Keyboard and Mouse (J1) Pinouts . ............... A–8

A–6 Parallel Port (J6) Connector Pinouts .............. A–9

A–7 PMC I/O Companion Card Mouse (J2) and Keyboard

(J3) Connector Pinouts . . ....................... A–10

Tables

1–1 Digital Alpha VME 4 Functional Speciﬁcations ...... 1–2

1–2 Physical and Environmental Speciﬁcations . . . ...... 1–4

1–3 Typical Peak Power Supply Current and Module

Power Dissipation ............................ 1–5

2–1 Digital Alpha VME 4 Hardware Kit Items.......... 2–3

2–2 Digital Alpha VME 4 Memory Modules ............ 2–4

2–3 Digital Alpha VME 4 Cache Memory Modules . ...... 2–4

2–4 Additional Hardware Installation Items ........... 2–5

2–5 Digital Alpha VME 4 Module Conﬁguration

Switches .................................... 2–9

2–6 Supported Switch Settings for Digital Alpha VME 4

Modules in Slot 1 (System Controller) ............. 2–9

2–7 Supported Switch Settings for Digital Alpha VME

4 Modules in Other Than Slot 1 (Nonsystem

Controller) . . . ............................... 2–10

2–8 Digital Alpha VME 4 Memory Conﬁgurations . ...... 2–12

2–9 J9 Cache Jumper Settings ...................... 2–13

2–10 J10 Cache Jumper Settings ..................... 2–14

2–11 SROM Test Numbers and Descriptions ............ 2–28

2–12 Console Code Test Letters and Names ............. 2–29

2–13 Troubleshooting .............................. 2–31

2–14 Products With a 1 Year Return to Digital Warranty. . 2–32

2–15 Field Replaceable Units and Order Numbers . . ...... 2–35

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3–1 Controls and Indicators . ....................... 3–2

3–2 Environment Variable Summary . . ............... 3–4

4–1 Console Diagnostic Tests ....................... 4–3

5–1 System Bus Address Space Description ............ 5–3

5–2 PCI Sparse I/O Space Byte Enable Generation ...... 5–7

5–3 PCI Conﬁguration Space Deﬁnition ............... 5–8

5–4 PCI Address Decoding for Primary Bus Conﬁguration

Accesses .................................... 5–9

5–5 PCI Sparse Memory Space Byte Enable Generation . . 5–13

5–6 PCI Target Window Enables .................... 5–16

5–7 PCI Target Address Translation—Direct Mapped .... 5–18

5–8 Scatter-Gather Map Address .................... 5–20

6–1 CSR Register Addresses for DECchip 21071-CA ..... 6–9

6–2 General Control Register ....................... 6–12

6–3 Error and Diagnostic Status Register ............. 6–14

6–4 Cache Size Tag Enable Values ................... 6–17

6–5 Maximum Memory Tag Enable Values ............. 6–18

6–6 Conﬁguration Register for Banks 0 and 1 .......... 6–23

6–7 Timing Register A ............................ 6–25

6–8 Timing Register B ............................ 6–27

6–9 Global Timing Register . ....................... 6–28

6–10 Refresh Timing Register ....................... 6–29

7–1 DECchip 21071-DA CSR Addresses ............... 7–7

7–2 Diagnostic Control/Status Register ............... 7–10

7–3 PCI Error Address Register ..................... 7–14

7–4 System Bus Error Address Register ............... 7–15

7–5 Translated Base Registers 1 and 2 . ............... 7–16

7–6 PCI Base Registers 1 and 2 ..................... 7–16

7–7 PCI Mask Registers 1 and 2 .................... 7–18

7–8 Host Address Extension Register 1 ............... 7–19

7–9 Host Address Extension Register 2 ............... 7–19

7–10 PCI Master Latency Timer Register............... 7–20

7–11 TLB Tag Registers 0 Through 7 . . . ............... 7–21

7–12 TLB Data Registers 0 Through 7 . . ............... 7–22

8–1 Ethernet Controller CSRs ...................... 8–5

8–2 SCSI Controller CSRs . . ....................... 8–9

9–1 PCI Control Register . . . ....................... 9–3

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9–2 Module Conﬁguration Register................... 9–7

9–3 DIMM Identiﬁcation . . . ....................... 9–9

9–4 Presence Detect .............................. 9–11

9–5 ID Bits ..................................... 9–12

9–6 Memory DIMM Conﬁguration Bit . ............... 9–12

9–7 Reset Reason Registers . ....................... 9–13

9–8 Module Control Register ....................... 9–15

9–9 Bcache Size and Speed Decode ................... 9–17

9–10 Super I/O Register Address Space Map ............ 9–19

9–11 Integrated Device Electronics Register Addresses .... 9–21

9–12 Keyboard and Mouse Controller Addresses . . . ...... 9–22

9–13 TOY Clock Timekeeping Registers . ............... 9–23

9–14 TOY Clock Command Register ................... 9–24

9–15 Timer Interface Registers....................... 9–26

9–16 Interval Timing Control Register . . ............... 9–27

9–17 Timer Modes . ............................... 9–29

9–18 Timer Interrupt Status Register . . ............... 9–32

9–19 Watchdog Timer TOY Clock Command Register ..... 9–35

10–1 Formation of Address Modiﬁer Codes from

Scatter-Gather Entry . . . ....................... 10–6

10–2 VIC Block Transfer Control Register .............. 10–8

10–3 VME Address . ............................... 10–12

10–4 PCI Address . . ............................... 10–13

10–5 VME Interface Processor Page Monitor CSR . . ...... 10–14

10–6 Interprocessor Communication Register Map Through

VIF_ABR ................................... 10–15

10–7 Arbiter/Requester Conﬁguration Register .......... 10–19

10–8 VIC Release Control Register.................... 10–20

10–9 VMEbus Transfer Timeout Register ............... 10–22

10–10 VIC Interrupt Request/Status Register ............ 10–24

10–11 VMEbus Interrupter Interrupt Control Register ..... 10–25

10–12 Swap Modes . . ............................... 10–26

10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for

Various Swap Modes . . . ....................... 10–29

10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# Translation . . . 10–30

10–15 Access to PCI Memory Addresses . . ............... 10–31

10–16 VME_IF_BASE + ............................. 10–37

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11–1 Table of CPU Interrupt Assignments .............. 11–1

11–2 VIC64 Chip Interrupt Ranking . . . ............... 11–6

11–3 VME IRQ ICR Priority Assignments .............. 11–8

11–4 NMI Status and Control Register Bits ............. 11–12

12–1 Commonly Used Commands..................... 12–2

12–2 Console Shell Operators ....................... 12–3

12–3 Digital Alpha VME 4 Console Command Summary

........................................... 12–18

A–1 VMEbus (J1) Connector . ....................... A–2

A–2 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A–3 Ethernet (J9) Connector Pinouts . . ............... A–4

A–4 Primary Breakout Module Connector Pinouts . ...... A–4

A–5 Keyboard and Mouse (J1) Connector .............. A–8

A–6 Parallel Port (J6) Connector ..................... A–8

A–7 PMC I/O Companion Card Mouse (J2) Connector .... A–10

A–8 PMC I/O Companion Card Keyboard (J3)

Connector ................................... A–10

xix

Preface

Purpose of this Manual

Intended Audience

This manual is for OEM system integrators who have extensive knowledge of single-board computers (SBCs). Their task is to integrate Digital Alpha VME 4 modules into their own systems. The system integrators need information about the Digital Alpha VME 4 module’s physical and environmental speciﬁcations and performance. They also need information, such as register descriptions, to program the module.

A secondary audience consists of manufacturing technicians who install the module and ﬁeld technicians who diagnose problems and replace modules.

This manual does not explain how to use speciﬁc operating system programming interfaces. For this information, see the appropriate operating system documentation.

Structure of this Manual

This manual consists of 13 chapters, an appendix, and an index.

• Chapter 1, Product Overview, provides a general product description, lists product features and functional speciﬁcations, and identiﬁes physical and environmental requirements.

• Chapter 2, Installation Procedures, explains how to unpack and install the Digital Alpha VME 4 module. This chapter also introduces diagnostics and troubleshooting and provides repair and warranty information.

xxi

• Chapter 3, Operating the Digital Alpha VME 4 Computer, explains how to use the Digital Alpha VME 4 module’s controls and indicators, introduces console mode and environment variables, and provides pointers to information on booting operating systems and updating ﬁrmware.

• Chapter 4, Diagnostics, describes the Digital Alpha VME 4 power-on self-test (POST) diagnostics and ROM based diagnostics (RBDs).

• Chapter 5, System Address Mapping, describes the mapping of 34-bit processor physical address space to memory and I/O space addresses. This chapter also includes discussions on address translations.

• Chapter 6, Cache and Memory Subsystem, describes the cache and memory subsystem. This chapter includes discussions on error handling and describes the subsystem’s address space and registers.

• Chapter 7, PCI Host Bridge, describes the PCI host bridge that resides between the PCI local bus and the system bus. This chapter discusses the interfaces to the system bus and PCI bus and describes the related address space and registers.

• Chapter 8, PCI bus, describes the PCI bus, the base of the I/O subsystem. The chapter describes the various I/O devices and their registers.

• Chapter 9, Nbus, decribes the Digital Alpha VME 4 module’s Nbus. The discussion includes the Nbus address space and registers. This chapter also includes information on ROM, the Super I/O chip, the keyboard and mouse controller, the time-of-year (TOY) clock, interval timer registers, the watchdog timer, and nonvolatile RAM (NVRAM).

• Chapter 10, VME Interface, describes the interface that handles the VMEbus and its interacations with the PCI bus. The chapter describes master and slave address spaces, address mapping, registers, and communication. The chapter also discusses system controller operation, byte swapping addressing, and interface initialization.

• Chapter 11, System Interrupts, describes Digital Alpha VME 4 system interrupts and how the module can be reset.

• Chapter 12, Console Primer, introduces you to the Digital Alpha VME 4 console and explains how to use basic console commands.

• Chapter 13, Console Commands, describes the Digital Alpha VME 4 console commands.

• Appendix A, Module Connector Pinouts, provides pinout information for the Digital Alpha VME 4 module connectors.

xxii

Conventions

This section deﬁnes terminology, abbreviations, and other conventions used in this manual.

Abbreviations

• Register access The following list describes the register bit and ﬁeld abbreviations:

Bit/Field Abbreviation Description

MBZ (must be zero) Bits and ﬁelds speciﬁed as MBZ must be zero. RO (read only) Bits and ﬁelds speciﬁed as RO can be read but not

RW (read/write) Bits and ﬁelds speciﬁed as RW can be read and

WO (write only) Bits and ﬁelds speciﬁed as WO can be written but not

• Binary multiples The abbreviations K, M, and G (kilo, mega, and giga) represent binary

multiples and have the following values:

K= M= G=

(1024)

(1,048,576)

(1,073,741,824)

written.

read.

For example:

2 KB = 2 kilobytes = 4 MB = 4 megabytes = 8 GB = 8 gigabytes =

Addresses

Unless otherwise noted, addresses and offsets are hexadecimal values.

Bit Notation

Multiple-bit ﬁelds can include contiguous and noncontiguous bits contained in angle brackets (<>). Multiple contiguous bits are indicated by a pair of numbers separated by a colon ( :). For example, <9:7,5,2:0> speciﬁes bits 9, 8, 7, 5, 2, 1, and 0. Similarly, single bits are frequently indicated with angle brackets. For example, <27> speciﬁes bit 27.

232 432 832

bytes bytes bytes

xxiii

Caution

Cautions indicate potential damage to equipment or loss of data.

Data Field Size

The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data ﬁeld of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword.

Data Units

The following data unit terminology is used throughout this manual.

Term Words Bytes Bits Other

Byte 1/2 1 8 — Word 1 2 16 — Longword/Dword 2 4 32 Longword Quadword 4 8 64 2 Longwords Octaword 8 16 128 2 Quadwords Hexword 16 32 256 2 Octawords

Examples

The prompts, input, and output in examples are shown in a monospaced font. Interactive input is differentiated from prompts and system output with bold type. For example:

>>> echo This is a test. This is a test.

Ellipsis points indicate that a portion of an example is omitted.

Keyboard Keys

The following keyboard key conventions are used throughout this manual.

Convention Example

Control key sequences are represented as Ctrl/x. Press

Ctrl

while you simultaneously press the x key.

In plain text, key names match the name on the actual key.

In tables, key names match the name of the actual key and appear in a box.

xxiv

Ctrl/C

Return key

Return

Names and Symbols

The following table lists typographical conventions used for names of various items throughout this manual.

Items Example

Bits sysBus<32:2> Commands boot command Command arguments address argument Command options -sb option Environment variables AUTO_ACTION Environment variable values HALT Files and pathnames Pins LIRQ pin Register symbols VIP_ICR register Signals iogrant signal Variables n, x, mydev

/usr/foo/bar

Note

Notes emphasize particularly important information.

Numbering

Numbers are decimal or hexadecimal unless otherwise indicated. The preﬁx 0x indicates a hexadecimal number. For example, 19 is decimal, but 0x19 and 0x19A are hexadecimal (see also Addresses). Otherwise, the base is indicated by a subscript; for example,

100

is a binary number.

Ranges and Extents

Ranges are speciﬁed by a pair of numbers separated by two periods (..) and are inclusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3, and 4.

Extents are speciﬁed by a pair of numbers in angle brackets (<> ) separated by a colon ( :) and are inclusive. Bit ﬁelds are often speciﬁed as extents. For example, bits <7:3> speciﬁes bits 7, 6, 5, 4, and 3.

Register ﬁgures have bit and ﬁeld position numbering starting at the right (low-order) and increasing to the left (high-order).

Memory ﬁgures have addresses starting at the top and increasing toward the bottom.

xxv

Syntax

The following syntax elements are used throughout this manual. Do not type the syntax elements when entering information.

Element Example Description

[] [-ﬁle ﬁlename] The enclosed items are optional.

| - | + | = Choose one of two or more items. Select

{} {- | + | =} You must specify one (and only one) of the

() — You must specify the enclosed items

... arg . . . You can repeat the preceding item one or

one of the items unless the items are optional.

enclosed items.

together.

more times.

UNPREDICTABLE and UNDEFINED

In this manual, the terms UNPREDICTABLE and UNDEFINED are used. Their meanings are different and must be carefully distinguished.

In particular, only privileged software (that is, software running in kernel mode) can trigger UNDEFINED operations. Unprivileged software cannot trigger UNDEFINED operations. However, either privileged or unprivileged software can trigger UNPREDICTABLE results or occurrences.

UNPREDICTABLE results or occurrences do not disrupt the basic operation of the processor. The processor continues to execute instructions in its normal manner. In contrast, UNDEFINED operations can halt the processor or cause it to lose information.

The terms UNPREDICTABLE and UNDEFINED can be further described as follows:

• UNPREDICTABLE

Results or occurrences speciﬁed as UNPREDICTABLE might vary from moment to moment, implementation to implementation, and instruction to instruction within implementations. Software can never depend on results speciﬁed as UNPREDICTABLE.

An UNPREDICTABLE result might acquire an arbitrary value subject to a few constraints. Such a result might be an arbitrary function of the input operands or of any state information that is accessible to the process in its current access mode. UNPREDICTABLE results may be unchanged from their previous values.

xxvi

Operations that produce UNPREDICTABLE results might also produce exceptions.

An occurrence specifed as UNPREDICTABLE might happen or not based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and, in particular, must not constitute a security hole.

Speciﬁcally, UNPREDICTABLE results must not depend upon, or be a function of the contents of memory locations or registers that are inaccessible to the current process in the current access mode.

Also, operations that might produce UNPREDICTABLE results must not write or modify the contents of memory locations or registers to which the current process in the current access mode does not have access. They must also not halt or hang the system or any of its components.

For example, a security hole would exist if some UNPREDICTABLE result depended on the value of a register in another process, on the contents of processor temporary registers left behind by some previously running process, or on a sequence of actions of different processes.

• UNDEFINED

Operations speciﬁed as UNDEFINED can vary from moment to moment, implementation to implementation, and instruction to instruction within implementations. The operation can vary in effect from nothing, to stopping system operation.

UNDEFINED operations can halt the processor or cause it to lose information. However, UNDEFINED operations must not cause the processor to hang, that is, reach an unhalted state from which there is no transition to a normal state in which the machine executes instructions. Only privileged software (that is, software running in kernel mode) can trigger UNDEFINED operations.

xxvii

For More Information

Document Order Number Company

CY7C9640 Speciﬁcation Cypress

DECchip 21040–AA Speciﬁcation EC–N0752–72 Digital Equipment

DECchip 21064–AA Microprocessor Hardware Reference Manual

DECchip 21072–AA Core Logic Chip Set EC–N0648–72 Digital Equipment

Digital UNIX Installation Guide AA–PS2DD–TE Digital Equipment

Intel SIO82378 Chip Speciﬁcation Intel Corp. Internetworking with TCP/IP, Vol I,

Principles, Protocols and Architecture, Second

edition, Prentice Hall.

PCI Local Bus Speciﬁcation Intel Corp. NCR 53C810 Speciﬁcation National Cash

NCR 53C720 Programming Guide National Cash

SIO Chip (82378ZB) and 8259 Data Sheets Intel Corp. VIC64 Speciﬁcation Cypress

VxWorks Digital AXPvme Single-Board Computers Hardware Supplement

VxWorks Programmer’s Guide AA–Q3YLB–TE Digital Equipment

EC–N0079–72 Digital Equipment

AA-QA5HA-TE Digital Equipment

Semiconductor Corp.

Corp.

Semiconductor Corp.

Corp.

xxviii

Product Overview

1.1 Product Description

The Digital Alpha VME 4/224 and 4/288 MHz single-board computers are based on the 21064A Alpha processor chip. The Digital Alpha VME 4/224 comes preconﬁgured with 512 KB cache, and the Digital Alpha VME 4/288 comes preconﬁgured with 2 MB cache.

The board utilizes the Peripheral Component Interconnect (PCI) as the on-board bus for the interconnection of high performance SCSI, Ethernet, and VME interfaces, as well as the connection of industry-standard PCI mezzanine cards (PMCs—IEEE P1386.1 standard).

The Digital Alpha VME 4 processors are supported by the VxWorks for Alpha and Digital UNIX operating systems.

1.2 Functional Speciﬁcations

Table 1–1 lists the Digital Alpha VME 4 processor functional speciﬁcations. Figure 1–1 is a block diagram of the Digital Alpha VME 4 processor.

Product Overview 1–1

Table 1–1 Digital Alpha VME 4 Functional Speciﬁcations

Item Description

Alpha AXP processor 21064A Alpha processor with on-chip 16 KB instruction and 16

Peformance At 288 MHz, 238.51 SPECfp92, 188.84 SPECint92, 5.44

Network features DECchip 21040 PCI Ethernet controller DMA (bus master),

Network Interconnect 10BASE-T Ethernet (twisted pair). Memory Cache - 512 KB or 2 MB using cache modules.

SCSI-2 NCR 53C810 PCI based SCSI-2 processor single-ended 8-bit

Serial and parallel interfaces

Clocks and timers Real-time clock with battery backup.

VMEbus High performance PCI to VME64 interface chip capable of

PCI expansion Accepts one double-width or two single-width PCI mezzanine

Physical 6U VME form factor requiring two adjacent slots. Three

KB data caches IEEE and VAX ﬂoating point.

SPECfp95, and 4.69 SPECint95.

256 byte send and receive FIFO, double bandwidth with full duplex Ethernet (PCI based).

Main memory ECC protected 8, 16, 32, 64, and 128 MB using memory DIMMS on 128-bit data bus with single-bit error detection. Accessible from the CPU, PCI, and VMEbus. 4 MB ﬂash EPROM. 32 KB NVRAM.

with DMA, up to 10 MB transfer rate with connection through the VMEbus P2 connector.

Two asynchronous DEC423 ports, 75 to 19200 baud through front panel MMJ connectors. Keyboard and mouse support for graphics options on either the secondary breakout module or the PMC I/O companion card. Extended parallel port through the secondary breakout module.

Three 16-bit timers. Watchdog timer with programmable reset.

DMA transfers, implemented with the VIC64 interface chip.

card (PMC) modules with optional I/O companion card.

adjacent slots are required with the optional PMC I/O companion card.

1–2 Product Overview

+ 412 hidden pages

DEC Digital Alpha VME 4/224, Digital Alpha VME 4/288 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual