DEC Digital Alpha VME 4/224, Digital Alpha VME 4/288 User Manual

Digital Alpha VME 4/224 and
4/288Single-BoardComputers

UserGuideandTechnicalDescription

Order Number: EK–DAVME–TD. B01

This manual describes the Digital Alpha VME 4 module. It provides
configuration and installation procedures and describes the module’s
built-in features, including the console code and diagnostics.

Revision/Update Information: This manual supersedes the Digital

Alpha VME 4/224 and 4/288
Single-Board Computers User
Guide and Technical Description,

EK–DAVME–TD. A01.

Digital Equipment Corporation
Maynard, Massachusetts

First Printing, July 1996
Revised, September 1996

Printed in U.S.A.
The information in this document is subject to change without notice and should not be construed

as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no
responsibility for any errors that may appear in this document.

FCC Notice:

This equipment has been tested and found to comply with the limits for a Class A digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference when the equipment is operated in a commercial environment. This
equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in
accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference, in which
case the user will be required to correct the interference at his own expense.

Warning!

This is a Class A product. In a domestic environment this product may cause radio interference in
which case the user may be required to take adequate measures.

Achtung!

Dieses ist ein Gerät der Funkstörgrenzwertklasse A. In Wohnbereichen können bei Betrieb
dieses Gerätes Rundfunkstörungen auftreten, in welchen Fällen der Benutzer für entsprechende
Gegenmaßnahmen verantwortlich ist.

Attention!

Ceci est un produit de Classe A. Dans un environment domestique, ce produit risque de créer des
interférences radioélectriques, il appartiendra alors à l’utilisateur de prendre les mesures spécifiques
appropriées.

Canadian EMC Notice:

‘‘This Class [A] Digital apparatus meets all requirements of the Canadian Interference-Causing
Equipment Regulations.’’

‘‘Cet appareil numerique de la class [A] respecte toutes les exigences du Reglement sur le materiel
broilleur du Canada.’’

© Digital Equipment Corporation 1996.
All Rights Reserved.
The following are trademarks of Digital Equipment Corporation: Alpha AXP, DECchip, DECnet,

DECpc, Digital, OpenVMS, ThinWire, ULTRIX, VAX, and the DIGITAL logo.
The following are third-party trademarks:
DALLAS is a registered trademark of Dallas Systems Corporation.

Futurebus/Plus is a registered trademark of Force Computers GMBH, Germany.
IBM is a registered trademark of International Business Machines Corporation.
Intel is a trademark of Intel Corporation.
NCR is a registered trademark of National Cash Register Company.
OSF and OSF/1 are registered trademarks of Open Software Foundation, Inc.
UNIX is a registered trademark licensed exclusively by X/Open Company Ltd.
VIC64 is a trademark of Cypress Semiconductor Corporation.
VxWorks is a registered trademark of Wind River Systems, Inc.

All other trademarks and registered trademarks are the property of their respective holders.

S3320

Contents

Preface ................................................ xxi

1 Product Overview

1.1 Product Description .............................. 1–1

1.2 Functional Specifications . . . ....................... 1–1

1.3 Physical and Environmental Requirements ............ 1–4

2 Installation Procedures

2.1 Unpacking ..................................... 2–1

2.2 Installation .................................... 2–6

2.2.1 Installing the PMC I/O Companion Card ........... 2–23

2.3 Diagnostics..................................... 2–27

2.4 Troubleshooting . . ............................... 2–29

2.5 Repair and Warranty Information ................... 2–32

2.5.1 Return to Digital Hardware Maintenance .......... 2–32

2.5.2 Hardware Warranty ........................... 2–32

2.5.2.1 Availability ............................... 2–32

2.5.2.2 Return-to-Digital Process .................... 2–33

2.5.2.3 Response Time ............................ 2–33

2.5.2.4 Eligible Parts ............................. 2–33

2.5.2.5 Purchaser Responsibility .................... 2–33

2.5.2.6 Pre-Call Checklist . . ....................... 2–34

2.5.3 Software Maintenance . . ....................... 2–34

2.5.4 Field Replaceable Units and Order Numbers . . ...... 2–35

iii

3 Operating the Digital Alpha VME 4 Computer

3.1 Controls and Indicators ........................... 3–1

3.2 Console Mode ................................... 3–3

3.2.1 Entering Console Mode . ....................... 3–3

3.2.2 Exiting Console Mode . . ....................... 3–3

3.3 Environment Variables............................ 3–3

3.4 Booting an Operating System ...................... 3–7

3.5 Updating Firmware .............................. 3–7

4 Diagnostics

4.1 Overview ...................................... 4–1

4.2 Operating Environments . . . ....................... 4–1

4.2.1 POST Diagnostics ............................ 4–1

4.2.2 Console Prompt Diagnostics ..................... 4–2

4.3 Diagnostic Test Descriptions ....................... 4–2

4.3.1 Available Console Diagnostics ................... 4–2

4.3.2 SROM Initialization Countdown . . ............... 4–4

4.3.3 Console POST Descriptions ..................... 4–5

POST Non-Volatile RAM Diagnostic . . ............... 4–6

POST Memory Diagnostic . . ....................... 4–7

4.3.4 Console Diagnostic Test Descriptions .............. 4–8

Heartbeat Timer Test ............................. 4–9

Interval Timer Tests ............................. 4–10

DECchip 21040 Ethernet Controller Tests ............. 4–16

DALLAS DS1386 RAMified Watchdog Timekeeper

Tests. . . ....................................... 4–18

Local Area Network Address ROM Test ............... 4–22

NCR 53C810 PCI-SCSI I/O Processor Tests ............ 4–24

Watchdog Timer Interrupt Test ..................... 4–27

VME Interface Tests ............................. 4–28

4.4 Initialization Sequence ............................ 4–30

iv

5 System Address Mapping

5.1 CPU Address Mapping to PCI Space . . ............... 5–1

5.1.1 Cacheable Memory Space (0x000000000 to

0x0FFFFFFFF) .............................. 5–4

5.1.2 Noncacheable Memory Space (0x100000000 to

0x17FFFFFFF) .............................. 5–4

5.1.3 DECchip 21071-CA CSR Space (0x180000000 to

0x19FFFFFFF) .............................. 5–4

5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to

0x1AFFFFFFF) .............................. 5–5

5.1.5 PCI Interrupt Acknowledge/Special Cycle Space

(0x1B0000000 to 0x1BFFFFFFF) . . ............... 5–5

5.1.6 PCI Sparse I/O Space (0x1C0000000 to

0x1DFFFFFFF) .............................. 5–5

5.1.7 PCI Configuration Space (0x1E0000000 to

0x1FFFFFFFF) .............................. 5–8

5.1.7.1 PCI Configuration Cycles to Primary Bus

Targets. . . ............................... 5–9

5.1.7.2 PCI Configuration Cycles to Secondary Bus

Targets. . . ............................... 5–10

5.1.8 PCI Sparse Memory Space (0x200000000 to

0x2FFFFFFFF) .............................. 5–11

5.1.9 PCI Dense Memory Space (0x300000000 to

0x3FFFFFFFF) .............................. 5–14

5.2 PCI-to-Physical Memory Addressing . . ............... 5–15

6 Cache and Memory Subsystem

6.1 System Bus Interface ............................. 6–4

6.1.1 Arbitration on the System Bus ................... 6–4

6.1.2 System Bus Controller . . ....................... 6–4

6.1.3 Decoding Addresses ........................... 6–4

6.2 Bcache Control . . . ............................... 6–5

6.3 Memory Controller ............................... 6–5

6.3.1 Memory Organization . . ....................... 6–6

6.3.2 Memory Address Generation .................... 6–7

6.3.3 Support for Memory Page Mode . . ............... 6–7

6.3.4 Minimizing Read Latency ...................... 6–7

6.3.5 Transaction Scheduler . . ....................... 6–7

6.3.6 Programmable Memory Timing . . . ............... 6–7

6.3.7 Presence Detect Logic . . ....................... 6–8

6.4 Error Handling . . ............................... 6–8

v

6.5 Address Space of Control/Status Registers ............. 6–8

6.6 Description of CSRs .............................. 6–11

6.6.1 General Control Register ....................... 6–11

6.6.2 Error and Diagnostic Status Register ............. 6–13

6.6.3 Tag Enable Register ........................... 6–16

6.6.4 Error Low Address Register ..................... 6–18

6.6.5 Error High Address Register .................... 6–19

6.6.6 LDx_L Low Address Register .................... 6–19

6.6.7 LDx_L High Address Register ................... 6–20

6.6.8 Memory Control Registers ...................... 6–20

6.6.8.1 Presence Detect Low-Data Register ............ 6–20

6.6.8.2 Presence Detect High-Data Register ........... 6–21

6.6.8.3 Base Address Registers ..................... 6–21

6.6.8.4 Configuration Registers ..................... 6–22

6.6.8.5 Bank Set Timing Registers . . . ............... 6–24

6.6.8.6 Global Timing Register ..................... 6–27

6.6.8.7 Refresh Timing Register .................... 6–28

6.7 Data Path ..................................... 6–30

6.7.1 Memory Read Buffer . . . ....................... 6–31

6.7.2 I/O Read Buffer and Merge Buffer . ............... 6–31

6.7.3 I/O Write and DMA Read Buffer . . ............... 6–31

6.7.4 DMA Write Buffer ............................ 6–31

6.7.5 Memory Write Buffer . . . ....................... 6–32

6.7.6 Error Handling .............................. 6–32

7 PCI Host Bridge

7.1 Interface to the System Bus . ....................... 7–2

7.1.1 Decoding Physical Addresses .................... 7–2

7.1.2 Buffering System Bus Transactions ............... 7–3

7.1.3 Burst Length and Prefetching for the System Bus .... 7–3

7.2 Interface to the PCI bus ........................... 7–3

7.2.1 Decoding PCI Addresses ....................... 7–3

7.2.2 Buffering PCI Transactions ..................... 7–3

7.2.3 Burst Length and Prefetching for PCI bus .......... 7–4

7.3 Features ....................................... 7–4

7.3.1 Burst Order . . ............................... 7–4

7.3.2 Parity Support .............................. 7–4

7.3.3 Data Coherency .............................. 7–5

7.3.4 Interrupts . . . ............................... 7–6

7.3.5 Exclusive Access ............................ 7–6

7.3.6 Bus Parking . . ............................... 7–6

7.3.7 Retry Timeout ............................... 7–7

vi

7.3.8 PCI Master Timeout . . . ....................... 7–7

7.3.9 Address Stepping in Configuration Cycles .......... 7–7

7.4 Address Space of Control/Status Registers ............. 7–7

7.5 Description of CSRs .............................. 7–9

7.5.1 Diagnostic Control/Status Register ............... 7–9

7.5.2 PCI Error Address Register ..................... 7–13

7.5.3 System Bus Error Address Register ............... 7–14

7.5.4 Dummy Registers 1 Through 3 . . . ............... 7–15

7.5.5 Translated Base Registers 1 and 2 . ............... 7–15

7.5.6 PCI Base Registers 1 and 2 ..................... 7–16

7.5.7 PCI Mask Registers 1 and 2 .................... 7–17

7.5.8 Host Address Extension Register 0 ............... 7–18

7.5.9 Host Address Extension Register 1 ............... 7–18

7.5.10 Host Address Extension Register 2 ............... 7–19

7.5.11 PCI Master Latency Timer Register............... 7–20

7.5.12 TLB Tag Registers 0 Through 7 . . . ............... 7–20

7.5.13 TLB Data Registers 0 Through 7 . . ............... 7–21

7.5.14 Translation Buffer Invalidate All Register:

0x1A0000400 . ............................... 7–22

8 PCI bus

8.1 Ethernet Controller .............................. 8–3

8.1.1 PCI Configuration Registers .................... 8–3

8.1.2 Ethernet Controller CSRs ...................... 8–4

8.1.3 PCI Cycles . . . ............................... 8–5

8.1.4 Ethernet Address ............................. 8–6

8.2 SCSI Controller . . ............................... 8–6

8.2.1 Connection and Termination .................... 8–6

8.2.2 SCSI ID .................................... 8–7

8.2.3 Programming . ............................... 8–7

8.2.4 PCI Configuration Registers .................... 8–7

8.2.5 SCSI Control Status Registers ................... 8–8

8.3 PCI I/O Companion Card . . . ....................... 8–11

9 Nbus

9.1 Nbus Address Space .............................. 9–1

9.1.1 SIO Chip PCI Configuration Space ............... 9–2

9.1.1.1 PCI Control Register ....................... 9–3

9.1.1.2 ISA Controller Recovery Timer Register . . ...... 9–4

9.1.1.3 ISA Clock Divisor Register................... 9–4

9.2 Module Registers . ............................... 9–4

vii

9.2.1 Module Display Control Register . ............... 9–5

9.2.2 Module Configuration Register................... 9–6

9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4 .... 9–8

9.2.4 Memory Configuration Registers 0, 1, 2, 3 and Memory

Identification Register . . ....................... 9–8

9.2.5 Reset Reason Registers . ....................... 9–12

9.2.6 Heartbeat Register ............................ 9–14

9.2.7 Module Control Register 1 ..................... 9–14

9.2.8 Bcache Configuration Register ................... 9–16

9.3 ROM ......................................... 9–17

9.4 Super I/O Chip . . . ............................... 9–18

9.4.1 Serial Port Channels A and B ................... 9–18

9.4.2 Super I/O Register Address Space . ............... 9–19

9.5 Keyboard and Mouse Controller ..................... 9–21

9.6 TOY Clock ..................................... 9–22

9.6.1 TOY Clock Timekeeping Registers . ............... 9–23

9.6.2 TOY Clock Command Register ................... 9–24

9.7 Interval Timing Registers . . ....................... 9–25

9.7.1 Interval Timing Control Register . . ............... 9–26

9.7.2 Timer Registers .............................. 9–28

9.7.3 Timer Modes . ............................... 9–29

9.7.4 Interrupts . . . ............................... 9–31

9.7.5 Timer Interrupt Status Registers . . ............... 9–32

9.8 Watchdog Timer . . ............................... 9–33

9.9 Nonvolatile RAM . ............................... 9–36

10 VME Interface

10.1 VMEbus Master . . ............................... 10–2

10.1.1 Outbound Scatter-Gather Mapping ............... 10–4

10.1.1.1 Address Modifier . . . ....................... 10–6

10.1.1.2 Read-Modify-Write . . ....................... 10–6

10.1.2 Data Transfers ............................... 10–7

10.1.2.1 Single Mode Transfers ...................... 10–7

10.1.2.2 Block Mode Transfers....................... 10–7

10.1.3 Requesting the VMEbus. ....................... 10–9

10.2 VMEbus Slave . . ............................... 10–9

10.2.1 Decoding Addresses . . . ....................... 10–10

10.2.2 Inbound Scatter-Gather Entries . . . ............... 10–12

viii

10.2.3 Interprocessor Communication ................... 10–14

10.2.3.1 Interprocessor Communication Registers . . ...... 10–14

10.2.3.2 Interprocessor Communication Global Switches. . . 10–14

10.2.3.3 Interprocessor Communication Module

Switches . . ............................... 10–15

10.3 System Controller Operation ....................... 10–17

10.3.1 Arbitrating the VMEbus ....................... 10–18

10.3.1.1 Requesting the VMEbus..................... 10–18

10.3.1.2 Releasing the VMEbus ...................... 10–19

10.3.2 System Clock Output . . . ....................... 10–21

10.3.3 Timeout Timers .............................. 10–21

10.3.3.1 Arbitration Timers . . ....................... 10–21

10.3.3.2 VMEbus Transfer Timers .................... 10–22

10.3.3.3 Local Bus Transfer Timer ................... 10–23

10.3.4 VMEbus Interrupt Handling .................... 10–23

10.4 Byte Swapping . . . ............................... 10–26

10.4.1 DC7407 Byte Swapping . ....................... 10–26

10.4.2 VIC64 Byte Swapping . . ....................... 10–27

10.5 Initializing the VME Interface ...................... 10–30

10.5.1 VME PCI Configuration Registers . ............... 10–30

10.5.2 Programming Scatter-Gather RAM ............... 10–31

10.5.3 Configuring the VIC64 . . ....................... 10–32

10.6 Summary of VME Interface Registers . ............... 10–37

10.7 VME Subsystem Restrictions (as of 03-Jun-94) . . . ...... 10–40

10.7.1 Collision of VIC64 Master Write Posting with Master

Block Transfers .............................. 10–40

10.7.2 VIC64 Errata: A16 Master Cycles During

Interleave................................... 10–40

11 System Interrupts

11.1 System Interrupts ............................... 11–1

11.1.1 Xilinx Interrupt Controller ...................... 11–2

11.1.2 VIC64 Chip System Interrupt Controller ........... 11–4

11.1.2.1 Basic Operation ........................... 11–5

11.1.3 VIC64 Chip Interrupt Sources ................... 11–6

11.1.3.1 Local Device Interrupts ..................... 11–6

11.1.3.2 VMEbus Interrupt Requests . . ............... 11–7

11.1.3.3 Status/Error Interrupts ..................... 11–8

11.1.4 SIO Chip Programmable Interrupt Controller . ...... 11–11

11.1.4.1 Nonmaskable System Events . . ............... 11–11

11.1.4.2 NMI Status and Control Register ............. 11–12

11.1.4.3 EPIC Interrupt ........................... 11–13

ix

11.2 Module Reset ................................... 11–13

12 Console Primer

12.1 About the Console ............................... 12–1

12.1.1 Console Features ............................ 12–1

12.1.2 Command Overview . . . ....................... 12–2

12.1.3 Shell Operators .............................. 12–3

12.1.4 Using Flow Control ........................... 12–4

12.2 Getting Information About the System ............... 12–5

12.3 Getting Help ................................... 12–6

12.4 Examining and Depositing to Memory or System Registers

.............................................. 12–7

12.4.1 Accessing Memory ............................ 12–9

12.4.2 Examining Registers . . . ....................... 12–10

12.5 Using Pipes and grep to Filter Output . ............... 12–12

12.6 Using I/O Redirection (>) . . ....................... 12–12

12.7 Running Commands in Background . . ............... 12–13

12.7.1 Monitoring Status ............................ 12–13

12.7.2 Killing a Process ............................. 12–14

12.8 Creating Scripts . ............................... 12–14

12.9 Copying Scripts Over the Network . . . ............... 12–15

13 Console Commands

13.1 Console Commands .............................. 13–1

13.1.1 Special Keys . . ............................... 13–1

13.1.2 Command Line Characteristics . . . ............... 13–2

13.1.3 Radix Control . ............................... 13–2

13.1.4 Console Command Dictionary ................... 13–3

alloc . . ....................................... 13–4

boot . . . ....................................... 13–6

break . . ....................................... 13–14

cat ........................................... 13–15

chmod . ....................................... 13–16

chown . ....................................... 13–18

clear . . ....................................... 13–19

clear_log ...................................... 13–20

date . . . ....................................... 13–21

deposit ....................................... 13–23

dynamic ...................................... 13–28

x

echo . . . ....................................... 13–30

eval . . . ....................................... 13–32

examine ...................................... 13–34

exer . . . ....................................... 13–40

exit . . . ....................................... 13–49

false . . ....................................... 13–50

free . . . ....................................... 13–51

grep . . . ....................................... 13–52

hd ........................................... 13–55

help . . . ....................................... 13–57

init_ev . ....................................... 13–59

initialize ...................................... 13–60

kill . . . ....................................... 13–61

line . . . ....................................... 13–62

ls ............................................ 13–63

memexer ...................................... 13–64

memtest ...................................... 13–65

net .......................................... 13–72

ps ........................................... 13–75

pwrup . ....................................... 13–76

rm ........................................... 13–77

sa ........................................... 13–78

semaphore ..................................... 13–79

set ........................................... 13–80

setled ........................................ 13–83

set reboot srom . . ............................... 13–84

set toy sleep ................................... 13–85

sh ........................................... 13–86

show . . ....................................... 13–88

show config .................................... 13–90

show device .................................... 13–91

show hwrpb .................................... 13–93

show led ...................................... 13–94

show map ..................................... 13–95

show_log ...................................... 13–96

sleep . . ....................................... 13–98

sort . . . ....................................... 13–99

xi

sp ........................................... 13–100

start . . ....................................... 13–101

stop . . . ....................................... 13–102

update . ....................................... 13–103

A Module Connector Pinouts

A.1 CPU Connector Pinouts ........................... A–1

A.2 I/O Type 1 Card Connector Pinouts . . . ............... A–1

A.2.1 VMEbus (J1) Connector Pinouts . . ............... A–2

A.2.2 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A.2.3 Ethernet (J9) Connector Pinouts . . ............... A–4

A.3 Primary Breakout Module Connector Pinouts .......... A–4

A.4 Secondary Breakout Module Connector Pinouts . . . ...... A–6

A.4.1 Keyboard and Mouse (J1) Connector Pinouts . . ...... A–7

A.4.2 Parallel Port (J6) Connector Pinouts .............. A–8

A.5 PMC I/O Companion Card Connector Pinouts .......... A–9

Index

Figures

1–1 Digital Alpha VME 4 Block Diagram .............. 1–3

2–1 Digital Alpha VME 4 Module Components.......... 2–2

2–2 Digital Alpha VME 4 Module Layout .............. 2–7

2–3 I/O Module Layout ............................ 2–8

2–4 Installing the Main Memory Modules ............. 2–11

2–5 Cache Memory Modules . ....................... 2–13

2–6 Installing the Digital Alpha VME 4 Module. . . ...... 2–15

2–7 Alpha VME 4 Primary Breakout Module ........... 2–16

2–8 Primary Breakout Module Jumpers ............... 2–17

2–9 Connecting the SCSI Cable to the Primary Breakout

Module ..................................... 2–18

2–10 Installing the Primary Breakout Module ........... 2–19

2–11 Secondary Breakout Module Jumpers ............. 2–20

2–12 Connecting the Secondary Breakout Module to the

Primary Breakout Module ..................... 2–21

2–13 Connecting Network and Console Terminal Cables . . . 2–22

2–14 PMC I/O Companion Card Layout . ............... 2–23

xii

2–15 Connecting the PMC I/O Companion Card.......... 2–26

2–16 Installing the PMC I/O Companion Card ........... 2–27

3–1 Controls and Indicators . ....................... 3–2

4–1 Loopback Descriptions for Interval Timer Test 3 and

4.......................................... 4–15

4–2 LAN Address ROM Format ..................... 4–23

4–3 SROM Test Flows............................. 4–30

4–4 Console POST Flows . . . ....................... 4–31

4–5 Console POST Flows . . . ....................... 4–32

5–1 System Bus Address Map ...................... 5–2

5–2 PCI Sparse I/O Space Address Translation . . . ...... 5–6

5–3 PCI Memory Space Address Translation ........... 5–12

5–4 PCI Target Window Compare Scheme ............. 5–17

5–5 Scatter-Gather Map Page Table Entry in Memory .... 5–19

5–6 Scatter-Gather Map Translation of PCI Bus Address to

System Bus Address . . . ....................... 5–21

6–1 Cache and Memory Subsystem . . . ............... 6–1

6–2 Address and Data Paths of Cache and Memory ...... 6–2

6–3 21071-CA Block Diagram ....................... 6–3

6–4 Cache Subsystem fora2MBCache ............... 6–5

6–5 Maximum and Minimum DIMM Bank Layouts ...... 6–6

6–6 General Control Register: 0x180000000............ 6–11

6–7 Error and Diagnostic Status Register:

0x180000020 . ............................... 6–14

6–8 Tag Enable Register: 0x180000060 ............... 6–16

6–9 Error Low Address Register: 0x180000080 . . . ...... 6–19

6–10 Error High Address Register: 0x1800000A0 . . ...... 6–19

6–11 LDx_L Low Address Register: 0x1800000C0 . . ...... 6–20

6–12 LDx_L High Address Register: 0x1800000E0 . ...... 6–20

6–13 Presence Detect Low-Data Register: 0x180000280 . . . 6–21
6–14 Presence Detect High-Data Register: 0x180000260 . . . 6–21

6–15 Bank 0 Base Address Register: 0x180000800 . ...... 6–22

6–16 Configuration Registers for Bank Set 0:

0x180000A00 . ............................... 6–22

6–17 Bank Set 0 Timing Register A: 0x180000C00 . . ...... 6–25

6–18 Bank Set 0 Timing Register B: 0x180000E00 . . ...... 6–26

6–19 Global Timing Register: 0x180000200 ............. 6–28

xiii

6–20 Refresh Timing Register: 0x180000220 ............ 6–29

6–21 Block Diagram of the DECchip 21071-BA .......... 6–30

7–1 PCI Host Bridge .............................. 7–1

7–2 DECchip 21071-DA Block Diagram ............... 7–2

7–3 Diagnostic Control/Status Register: 0x1A0000000 .... 7–10

7–4 PCI Error Address Register: 0x1A0000020 . . . ...... 7–14

7–5 System Bus Error Address Register: 0x1A0000040 . . . 7–14
7–6 Translated Base Registers 1, 2: 0x1A00000C0,

0x1A00000E0 . ............................... 7–15

7–7 PCI Base Registers 1 and 2: 0x1A0000100,

0x1A0000120 . ............................... 7–16

7–8 PCI Mask Registers 1 and 2: 0x1A0000140,

0x1A0000160 . ............................... 7–17

7–9 Host Address Extension Register 0: 0x1A0000180.... 7–18

7–10 Host Address Extension Register 1: 0x1A00001A0 . . . 7–18
7–11 Host Address Extension Register 2: 0x1A00001C0 . . . 7–19
7–12 PCI Master Latency Timer Register: 0x1A00001E0. . . 7–20
7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to

0x1A00002E0 . ............................... 7–21

7–14 TLB Data Registers 0 Through 7: 0x1A0000300 to

0x1A00003E0 . ............................... 7–21

8–1 PCI Bus and Interfaces to the I/O Subsystem . ...... 8–2

8–2 PCI Configuration Registers .................... 8–4

8–3 DECchip 21040-AA CSR9 (ENET ROM Register) .... 8–6

8–4 PCI Configuration Block ....................... 8–8

9–1 Nbus and Nbus Resources ...................... 9–1

9–2 SIO Configuration Block ....................... 9–3

9–3 Module Display Control Register . . ............... 9–6

9–4 Display Character Set . . ....................... 9–6

9–5 Module Configuration Register................... 9–7

9–6 Memory Configuration Registers 0-3 .............. 9–9

9–7 Memory Identification Register . . . ............... 9–10

9–8 Reset Reason Registers . ....................... 9–13

9–9 Module Control Register 1 ...................... 9–15

9–10 Bcache Configuration Register ................... 9–16

9–11 Flash ROM Layout/Addressing . . . ............... 9–18

9–12 TOY Clock Command Register ................... 9–24

9–13 82C54 Control Byte ........................... 9–26

xiv

9–14 82C54 Timer Data Access ...................... 9–28

9–15 Timer Clocking ............................... 9–31

9–16 Timer Interrupt Status Register . . ............... 9–32

9–17 Watchdog Timer Registers ...................... 9–34

9–18 Watchdog Timer TOY Clock Command Register ..... 9–34

9–19 Watchdog Timer Module Control Register .......... 9–35

9–20 NVRAM Access .............................. 9–36

10–1 VME Interface Block Diagram ................... 10–1

10–2 Mapping Window_1 and Window_2 ............... 10–3

10–3 Mapping Pages From PCI to VME ............... 10–4

10–4 Outbound Scatter-Gather Entry . . . ............... 10–5

10–5 VIC Block Transfer Control Register .............. 10–8

10–6 Mapping Pages of Memory from VMEbus to PCI

Bus........................................ 10–10

10–7 Address Decoding ............................. 10–11

10–8 Base and Mask Register ....................... 10–11

10–9 Inbound Scatter-Gather Entry With A32 Address

Mapping .................................... 10–12

10–10 VME Interface Processor Page Monitor CSR . . ...... 10–13

10–11 VIC Arbiter/Requester Configuration Register ...... 10–18

10–12 VIC Release Control Register.................... 10–20

10–13 VMEbus Transfer Timeout Register ............... 10–22

10–14 VIC Interrupt Request/Status Register ............ 10–24

10–15 VMEbus Interrupt Vector Base Registers .......... 10–25

10–16 VMEbus Interrupter Interrupt Control Register ..... 10–25

10–17 Swap Modes . . ............................... 10–27

10–18 Big Endian VME Byte Lane Formats ............. 10–28

11–1 Block Diagram of the Interrupt Logic ............. 11–2

11–2 Interrupt/Mask Register #1 ..................... 11–3

11–3 Interrupt/Mask Register #2 ..................... 11–3

11–4 Interrupt/Mask Register #3 ..................... 11–4

11–5 Interrupt/Mask Register #4 ..................... 11–4

11–6 Generic ICR . . ............................... 11–5

11–7 Device ICRs . . ............................... 11–7

11–8 VIC Local Interrupt Vector Base Register .......... 11–7

11–9 VME IRQ* ICRs.............................. 11–8

11–10 DMA Status ICR ............................. 11–9

xv

11–11 VIC Error Group ICR. . . ....................... 11–10

11–12 VMEbus Interrupter ICR ....................... 11–10

11–13 VIC Error Group Interrupt Vector Base Register ..... 11–11

11–14 NMI Status and Control Register . ............... 11–12

A–1 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A–2 Ethernet (J9) Connector Pinouts . . ............... A–4

A–3 Primary Breakout Module Connector Pinouts . ...... A–6

A–4 Secondary Breakout Module Connector Pinouts...... A–7

A–5 Keyboard and Mouse (J1) Pinouts . ............... A–8

A–6 Parallel Port (J6) Connector Pinouts .............. A–9

A–7 PMC I/O Companion Card Mouse (J2) and Keyboard

(J3) Connector Pinouts . . ....................... A–10

Tables

1–1 Digital Alpha VME 4 Functional Specifications ...... 1–2

1–2 Physical and Environmental Specifications . . . ...... 1–4

1–3 Typical Peak Power Supply Current and Module

Power Dissipation ............................ 1–5

2–1 Digital Alpha VME 4 Hardware Kit Items.......... 2–3

2–2 Digital Alpha VME 4 Memory Modules ............ 2–4

2–3 Digital Alpha VME 4 Cache Memory Modules . ...... 2–4

2–4 Additional Hardware Installation Items ........... 2–5

2–5 Digital Alpha VME 4 Module Configuration

Switches .................................... 2–9

2–6 Supported Switch Settings for Digital Alpha VME 4

Modules in Slot 1 (System Controller) ............. 2–9

2–7 Supported Switch Settings for Digital Alpha VME

4 Modules in Other Than Slot 1 (Nonsystem

Controller) . . . ............................... 2–10

2–8 Digital Alpha VME 4 Memory Configurations . ...... 2–12

2–9 J9 Cache Jumper Settings ...................... 2–13

2–10 J10 Cache Jumper Settings ..................... 2–14

2–11 SROM Test Numbers and Descriptions ............ 2–28

2–12 Console Code Test Letters and Names ............. 2–29

2–13 Troubleshooting .............................. 2–31

2–14 Products With a 1 Year Return to Digital Warranty. . 2–32

2–15 Field Replaceable Units and Order Numbers . . ...... 2–35

xvi

3–1 Controls and Indicators . ....................... 3–2

3–2 Environment Variable Summary . . ............... 3–4

4–1 Console Diagnostic Tests ....................... 4–3

5–1 System Bus Address Space Description ............ 5–3

5–2 PCI Sparse I/O Space Byte Enable Generation ...... 5–7

5–3 PCI Configuration Space Definition ............... 5–8

5–4 PCI Address Decoding for Primary Bus Configuration

Accesses .................................... 5–9

5–5 PCI Sparse Memory Space Byte Enable Generation . . 5–13

5–6 PCI Target Window Enables .................... 5–16

5–7 PCI Target Address Translation—Direct Mapped .... 5–18

5–8 Scatter-Gather Map Address .................... 5–20

6–1 CSR Register Addresses for DECchip 21071-CA ..... 6–9

6–2 General Control Register ....................... 6–12

6–3 Error and Diagnostic Status Register ............. 6–14

6–4 Cache Size Tag Enable Values ................... 6–17

6–5 Maximum Memory Tag Enable Values ............. 6–18

6–6 Configuration Register for Banks 0 and 1 .......... 6–23

6–7 Timing Register A ............................ 6–25

6–8 Timing Register B ............................ 6–27

6–9 Global Timing Register . ....................... 6–28

6–10 Refresh Timing Register ....................... 6–29

7–1 DECchip 21071-DA CSR Addresses ............... 7–7

7–2 Diagnostic Control/Status Register ............... 7–10

7–3 PCI Error Address Register ..................... 7–14

7–4 System Bus Error Address Register ............... 7–15

7–5 Translated Base Registers 1 and 2 . ............... 7–16

7–6 PCI Base Registers 1 and 2 ..................... 7–16

7–7 PCI Mask Registers 1 and 2 .................... 7–18

7–8 Host Address Extension Register 1 ............... 7–19

7–9 Host Address Extension Register 2 ............... 7–19

7–10 PCI Master Latency Timer Register............... 7–20

7–11 TLB Tag Registers 0 Through 7 . . . ............... 7–21

7–12 TLB Data Registers 0 Through 7 . . ............... 7–22

8–1 Ethernet Controller CSRs ...................... 8–5

8–2 SCSI Controller CSRs . . ....................... 8–9

9–1 PCI Control Register . . . ....................... 9–3

xvii

9–2 Module Configuration Register................... 9–7

9–3 DIMM Identification . . . ....................... 9–9

9–4 Presence Detect .............................. 9–11

9–5 ID Bits ..................................... 9–12

9–6 Memory DIMM Configuration Bit . ............... 9–12

9–7 Reset Reason Registers . ....................... 9–13

9–8 Module Control Register ....................... 9–15

9–9 Bcache Size and Speed Decode ................... 9–17

9–10 Super I/O Register Address Space Map ............ 9–19

9–11 Integrated Device Electronics Register Addresses .... 9–21

9–12 Keyboard and Mouse Controller Addresses . . . ...... 9–22

9–13 TOY Clock Timekeeping Registers . ............... 9–23

9–14 TOY Clock Command Register ................... 9–24

9–15 Timer Interface Registers....................... 9–26

9–16 Interval Timing Control Register . . ............... 9–27

9–17 Timer Modes . ............................... 9–29

9–18 Timer Interrupt Status Register . . ............... 9–32

9–19 Watchdog Timer TOY Clock Command Register ..... 9–35

10–1 Formation of Address Modifier Codes from

Scatter-Gather Entry . . . ....................... 10–6

10–2 VIC Block Transfer Control Register .............. 10–8

10–3 VME Address . ............................... 10–12

10–4 PCI Address . . ............................... 10–13

10–5 VME Interface Processor Page Monitor CSR . . ...... 10–14

10–6 Interprocessor Communication Register Map Through

VIF_ABR ................................... 10–15

10–7 Arbiter/Requester Configuration Register .......... 10–19

10–8 VIC Release Control Register.................... 10–20

10–9 VMEbus Transfer Timeout Register ............... 10–22

10–10 VIC Interrupt Request/Status Register ............ 10–24

10–11 VMEbus Interrupter Interrupt Control Register ..... 10–25

10–12 Swap Modes . . ............................... 10–26

10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for

Various Swap Modes . . . ....................... 10–29

10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# Translation . . . 10–30

10–15 Access to PCI Memory Addresses . . ............... 10–31

10–16 VME_IF_BASE + ............................. 10–37

xviii

11–1 Table of CPU Interrupt Assignments .............. 11–1

11–2 VIC64 Chip Interrupt Ranking . . . ............... 11–6

11–3 VME IRQ ICR Priority Assignments .............. 11–8

11–4 NMI Status and Control Register Bits ............. 11–12

12–1 Commonly Used Commands..................... 12–2

12–2 Console Shell Operators ....................... 12–3

12–3 Digital Alpha VME 4 Console Command Summary

........................................... 12–18

A–1 VMEbus (J1) Connector . ....................... A–2

A–2 Console (J6) and Serial (J7) Connector Pinouts ...... A–3

A–3 Ethernet (J9) Connector Pinouts . . ............... A–4

A–4 Primary Breakout Module Connector Pinouts . ...... A–4

A–5 Keyboard and Mouse (J1) Connector .............. A–8

A–6 Parallel Port (J6) Connector ..................... A–8

A–7 PMC I/O Companion Card Mouse (J2) Connector .... A–10

A–8 PMC I/O Companion Card Keyboard (J3)

Connector ................................... A–10

xix

Preface

Purpose of this Manual

This manual describes the Digital Alpha VME 4 module. It provides configuration
and installation procedures and describes the module’s built-in features, including
the console code and diagnostics.

Intended Audience

This manual is for OEM system integrators who have extensive knowledge of
single-board computers (SBCs). Their task is to integrate Digital Alpha VME 4
modules into their own systems. The system integrators need information about
the Digital Alpha VME 4 module’s physical and environmental specifications
and performance. They also need information, such as register descriptions, to
program the module.

A secondary audience consists of manufacturing technicians who install the
module and field technicians who diagnose problems and replace modules.

This manual does not explain how to use specific operating system programming
interfaces. For this information, see the appropriate operating system
documentation.

Structure of this Manual

This manual consists of 13 chapters, an appendix, and an index.

• Chapter 1, Product Overview, provides a general product description, lists
product features and functional specifications, and identifies physical and
environmental requirements.

• Chapter 2, Installation Procedures, explains how to unpack and install the
Digital Alpha VME 4 module. This chapter also introduces diagnostics and
troubleshooting and provides repair and warranty information.

xxi

• Chapter 3, Operating the Digital Alpha VME 4 Computer, explains how to
use the Digital Alpha VME 4 module’s controls and indicators, introduces
console mode and environment variables, and provides pointers to information
on booting operating systems and updating firmware.

• Chapter 4, Diagnostics, describes the Digital Alpha VME 4 power-on self-test
(POST) diagnostics and ROM based diagnostics (RBDs).

• Chapter 5, System Address Mapping, describes the mapping of 34-bit
processor physical address space to memory and I/O space addresses. This
chapter also includes discussions on address translations.

• Chapter 6, Cache and Memory Subsystem, describes the cache and memory
subsystem. This chapter includes discussions on error handling and describes
the subsystem’s address space and registers.

• Chapter 7, PCI Host Bridge, describes the PCI host bridge that resides
between the PCI local bus and the system bus. This chapter discusses the
interfaces to the system bus and PCI bus and describes the related address
space and registers.

• Chapter 8, PCI bus, describes the PCI bus, the base of the I/O subsystem.
The chapter describes the various I/O devices and their registers.

• Chapter 9, Nbus, decribes the Digital Alpha VME 4 module’s Nbus. The
discussion includes the Nbus address space and registers. This chapter also
includes information on ROM, the Super I/O chip, the keyboard and mouse
controller, the time-of-year (TOY) clock, interval timer registers, the watchdog
timer, and nonvolatile RAM (NVRAM).

• Chapter 10, VME Interface, describes the interface that handles the VMEbus
and its interacations with the PCI bus. The chapter describes master and
slave address spaces, address mapping, registers, and communication. The
chapter also discusses system controller operation, byte swapping addressing,
and interface initialization.

• Chapter 11, System Interrupts, describes Digital Alpha VME 4 system
interrupts and how the module can be reset.

• Chapter 12, Console Primer, introduces you to the Digital Alpha VME 4
console and explains how to use basic console commands.

• Chapter 13, Console Commands, describes the Digital Alpha VME 4 console
commands.

• Appendix A, Module Connector Pinouts, provides pinout information for the
Digital Alpha VME 4 module connectors.

xxii

Conventions

This section defines terminology, abbreviations, and other conventions used in
this manual.

Abbreviations

• Register access
The following list describes the register bit and field abbreviations:

Bit/Field Abbreviation Description

MBZ (must be zero) Bits and fields specified as MBZ must be zero.
RO (read only) Bits and fields specified as RO can be read but not

RW (read/write) Bits and fields specified as RW can be read and

WO (write only) Bits and fields specified as WO can be written but not

• Binary multiples
The abbreviations K, M, and G (kilo, mega, and giga) represent binary

multiples and have the following values:

K=
M=
G=

10

2

(1024)

20

2

(1,048,576)

30

2

(1,073,741,824)

written.

written.

read.

For example:

2 KB = 2 kilobytes =
4 MB = 4 megabytes =
8 GB = 8 gigabytes =

Addresses

Unless otherwise noted, addresses and offsets are hexadecimal values.

Bit Notation

Multiple-bit fields can include contiguous and noncontiguous bits contained in
angle brackets (<>). Multiple contiguous bits are indicated by a pair of numbers
separated by a colon ( :). For example, <9:7,5,2:0> specifies bits 9, 8, 7, 5, 2, 1,
and 0. Similarly, single bits are frequently indicated with angle brackets. For
example, <27> specifies bit 27.

232
432
832

10

20

30

bytes
bytes
bytes

xxiii

Caution

Cautions indicate potential damage to equipment or loss of data.

Data Field Size

The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field
of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a
NATURALLY ALIGNED longword.

Data Units

The following data unit terminology is used throughout this manual.

Term Words Bytes Bits Other

Byte 1/2 1 8 —
Word 1 2 16 —
Longword/Dword 2 4 32 Longword
Quadword 4 8 64 2 Longwords
Octaword 8 16 128 2 Quadwords
Hexword 16 32 256 2 Octawords

Examples

The prompts, input, and output in examples are shown in a monospaced font.
Interactive input is differentiated from prompts and system output with bold
type. For example:

>>> echo This is a test.
This is a test.

Ellipsis points indicate that a portion of an example is omitted.

Keyboard Keys

The following keyboard key conventions are used throughout this manual.

Convention Example

Control key sequences are represented as Ctrl/x. Press

Ctrl

while you simultaneously press the x key.

In plain text, key names match the name on the actual
key.

In tables, key names match the name of the actual key
and appear in a box.

xxiv

Ctrl/C

Return key

Return

Names and Symbols

The following table lists typographical conventions used for names of various
items throughout this manual.

Items Example

Bits sysBus<32:2>
Commands boot command
Command arguments address argument
Command options -sb option
Environment variables AUTO_ACTION
Environment variable values HALT
Files and pathnames
Pins LIRQ pin
Register symbols VIP_ICR register
Signals iogrant signal
Variables n, x, mydev

/usr/foo/bar

Note

Notes emphasize particularly important information.

Numbering

Numbers are decimal or hexadecimal unless otherwise indicated. The prefix
0x indicates a hexadecimal number. For example, 19 is decimal, but 0x19 and
0x19A are hexadecimal (see also Addresses). Otherwise, the base is indicated by
a subscript; for example,

100

is a binary number.

2

Ranges and Extents

Ranges are specified by a pair of numbers separated by two periods (..) and are
inclusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3,
and 4.

Extents are specified by a pair of numbers in angle brackets (<> ) separated by a
colon ( :) and are inclusive. Bit fields are often specified as extents. For example,
bits <7:3> specifies bits 7, 6, 5, 4, and 3.

Register and Memory Figures

Register figures have bit and field position numbering starting at the right
(low-order) and increasing to the left (high-order).

Memory figures have addresses starting at the top and increasing toward the
bottom.

xxv

Syntax

The following syntax elements are used throughout this manual. Do not type the
syntax elements when entering information.

Element Example Description

[] [-file filename] The enclosed items are optional.

| - | + | = Choose one of two or more items. Select

{} {- | + | =} You must specify one (and only one) of the

() — You must specify the enclosed items

... arg . . . You can repeat the preceding item one or

one of the items unless the items are
optional.

enclosed items.

together.

more times.

UNPREDICTABLE and UNDEFINED

In this manual, the terms UNPREDICTABLE and UNDEFINED are used. Their
meanings are different and must be carefully distinguished.

In particular, only privileged software (that is, software running in kernel mode)
can trigger UNDEFINED operations. Unprivileged software cannot trigger
UNDEFINED operations. However, either privileged or unprivileged software can
trigger UNPREDICTABLE results or occurrences.

UNPREDICTABLE results or occurrences do not disrupt the basic operation
of the processor. The processor continues to execute instructions in its normal
manner. In contrast, UNDEFINED operations can halt the processor or cause it
to lose information.

The terms UNPREDICTABLE and UNDEFINED can be further described as
follows:

• UNPREDICTABLE

Results or occurrences specified as UNPREDICTABLE might vary from
moment to moment, implementation to implementation, and instruction
to instruction within implementations. Software can never depend on
results specified as UNPREDICTABLE.

An UNPREDICTABLE result might acquire an arbitrary value subject
to a few constraints. Such a result might be an arbitrary function of the
input operands or of any state information that is accessible to the process
in its current access mode. UNPREDICTABLE results may be unchanged
from their previous values.

xxvi

Operations that produce UNPREDICTABLE results might also produce
exceptions.

An occurrence specifed as UNPREDICTABLE might happen or not based
on an arbitrary choice function. The choice function is subject to the same
constraints as are UNPREDICTABLE results and, in particular, must not
constitute a security hole.

Specifically, UNPREDICTABLE results must not depend upon, or be
a function of the contents of memory locations or registers that are
inaccessible to the current process in the current access mode.

Also, operations that might produce UNPREDICTABLE results must not
write or modify the contents of memory locations or registers to which the
current process in the current access mode does not have access. They
must also not halt or hang the system or any of its components.

For example, a security hole would exist if some UNPREDICTABLE
result depended on the value of a register in another process, on the
contents of processor temporary registers left behind by some previously
running process, or on a sequence of actions of different processes.

• UNDEFINED

Operations specified as UNDEFINED can vary from moment to moment,
implementation to implementation, and instruction to instruction within
implementations. The operation can vary in effect from nothing, to
stopping system operation.

UNDEFINED operations can halt the processor or cause it to lose
information. However, UNDEFINED operations must not cause the
processor to hang, that is, reach an unhalted state from which there is no
transition to a normal state in which the machine executes instructions.
Only privileged software (that is, software running in kernel mode) can
trigger UNDEFINED operations.

xxvii

For More Information

Document Order Number Company

CY7C9640 Specification Cypress

DECchip 21040–AA Specification EC–N0752–72 Digital Equipment

DECchip 21064–AA Microprocessor Hardware
Reference Manual

DECchip 21072–AA Core Logic Chip Set EC–N0648–72 Digital Equipment

Digital UNIX Installation Guide AA–PS2DD–TE Digital Equipment

Intel SIO82378 Chip Specification Intel Corp.
Internetworking with TCP/IP, Vol I,

Principles, Protocols and Architecture, Second

edition, Prentice Hall.

PCI Local Bus Specification Intel Corp.
NCR 53C810 Specification National Cash

NCR 53C720 Programming Guide National Cash

SIO Chip (82378ZB) and 8259 Data Sheets Intel Corp.
VIC64 Specification Cypress

VxWorks Digital AXPvme Single-Board
Computers Hardware Supplement

VxWorks Programmer’s Guide AA–Q3YLB–TE Digital Equipment

EC–N0079–72 Digital Equipment

AA-QA5HA-TE Digital Equipment

Semiconductor
Corp.

Corp.

Corp.

Corp.

Corp.

Register Co.

Register Co.

Semiconductor
Corp.

Corp.

Corp.

xxviii

1

Product Overview

1.1 Product Description

The Digital Alpha VME 4/224 and 4/288 MHz single-board computers are based
on the 21064A Alpha processor chip. The Digital Alpha VME 4/224 comes
preconfigured with 512 KB cache, and the Digital Alpha VME 4/288 comes
preconfigured with 2 MB cache.

The board utilizes the Peripheral Component Interconnect (PCI) as the on-board
bus for the interconnection of high performance SCSI, Ethernet, and VME
interfaces, as well as the connection of industry-standard PCI mezzanine cards
(PMCs—IEEE P1386.1 standard).

The Digital Alpha VME 4 processors are supported by the VxWorks for Alpha and
Digital UNIX operating systems.

1.2 Functional Specifications

Table 1–1 lists the Digital Alpha VME 4 processor functional specifications.
Figure 1–1 is a block diagram of the Digital Alpha VME 4 processor.

Product Overview 1–1

Table 1–1 Digital Alpha VME 4 Functional Specifications

Item Description

Alpha AXP processor 21064A Alpha processor with on-chip 16 KB instruction and 16

Peformance At 288 MHz, 238.51 SPECfp92, 188.84 SPECint92, 5.44

Network features DECchip 21040 PCI Ethernet controller DMA (bus master),

Network Interconnect 10BASE-T Ethernet (twisted pair).
Memory Cache - 512 KB or 2 MB using cache modules.

SCSI-2 NCR 53C810 PCI based SCSI-2 processor single-ended 8-bit

Serial and parallel
interfaces

Clocks and timers Real-time clock with battery backup.

VMEbus High performance PCI to VME64 interface chip capable of

PCI expansion Accepts one double-width or two single-width PCI mezzanine

Physical 6U VME form factor requiring two adjacent slots. Three

KB data caches IEEE and VAX floating point.

SPECfp95, and 4.69 SPECint95.

256 byte send and receive FIFO, double bandwidth with full
duplex Ethernet (PCI based).

Main memory ECC protected 8, 16, 32, 64, and 128 MB using
memory DIMMS on 128-bit data bus with single-bit error
detection. Accessible from the CPU, PCI, and VMEbus.
4 MB flash EPROM.
32 KB NVRAM.

with DMA, up to 10 MB transfer rate with connection through
the VMEbus P2 connector.

Two asynchronous DEC423 ports, 75 to 19200 baud through
front panel MMJ connectors.
Keyboard and mouse support for graphics options on either the
secondary breakout module or the PMC I/O companion card.
Extended parallel port through the secondary breakout module.

Three 16-bit timers.
Watchdog timer with programmable reset.

DMA transfers, implemented with the VIC64 interface chip.

card (PMC) modules with optional I/O companion card.

adjacent slots are required with the optional PMC I/O
companion card.

1–2 Product Overview

Figure 1–1 Digital Alpha VME 4 Block Diagram

Cache and

Memory

Controller

64

Data Path

4 chips

Bcache

CPU

sysBus 128 Bits

128

memdata

Main

Memory

CPU Board

I/O Board

PCI Host

Bridge

(21071-DA)

PCI-VME

Bridge

VME Connectors

PCI to

Nbus

Bridge

32

epiData

PCI Bus 32 Bits

SCSI

Controller

Interrupt

Controller

Super

I/O

Nbus 8 Bits

Keyboard

and Mouse

Controller

Ethernet

Controller

Flash

(DS1386)

TOY Clock

Watchdog Timer

NVRAM

Interval

Timer



PCI to

PCI Bridge

PCI/PMC

option 0 slot

PMC Expander Card

PCI/PMC

option 1 slot

ML013270

Product Overview 1–3

1.3 Physical and Environmental Requirements

The Digital Alpha VME 4 module requires a VME chassis with sufficient cooling.
You must have at least 200 linear feet/minute (lfm) of airflow at an ambient
temperature of not more than 40°C (104°F) across the processor heatsink.

Table 1–2 shows the physical and environmental specifications for the Digital
Alpha VME 4 module. Table 1–3 shows the power supply current and power
dissipation for the Digital Alpha VME 4 module. Stresses beyond those specified
may cause permanent damage to the module.

Table 1–2 Physical and Environmental Specifications

Characteristic Specification

Industry standard VME 6U module
Operating temperature 0°C to 40°C (32°F to 104°F)
Storage temperature –40°C to 66°C (–40°F to 151°F)
Temperature change 20°C/hour (36°F/hour)
Relative humidity 5% to 95% (noncondensing)
Airflow 200 lfm minimum at 40°C ambient inlet air temperature,

Vibration: Operating in a suitable enclosure

over the large square processor heatsink and cache

0.5 g Pk 22.1–260 Hz

0.25 g Pk 200–500 Hz

1–4 Product Overview

Table 1–3 Typical Peak Power Supply Current and Module Power Dissipation

CPU Modules
w/128 MB Memory

Alpha VME 4/224 12.0 A 0.2 A 0.01 A 62 W
Alpha VME 4/288 13.5 A 0.2 A 0.01 A 70 W

Amps
@5V

Amps @ 12 V
(note 1)

Amps

0

12 V

@

Module Heat
Dissipation

Options Amps

SCSI Termination 0.8 A max. 0.0 A N/A 4 W max.
PMC Option Slot

Budget

@5V

3.0 A max. N/A N/A 15 W max.

Amps
@12V

Amps

0

12 V

@

Power
Dissipation

Notes

Power and heat dissipation assumes nominal voltages (5.0 V, 12.0 V, and

0

12

V). Power numbers are based on actual measured data. Add 10% to

the current and power values for a worst-case power and heat scenario.
SCSI Termination is enabled by default. You can disable this option by

resetting the jumper on the primary breakout module as explained in
Section 8.2.1.

For more information about the PMC option slot budget, see the
documentation supplied with your PMC option.

Product Overview 1–5

2

Installation Procedures

This chapter describes how to unpack, configure, install, and verify proper
operation of the Digital Alpha VME 4 module.

2.1 Unpacking

Your Digital Alpha VME 4 hardware kit contains the items listed in Table 2–1.
Save the original packing material in case a factory return is necessary.

Caution

You must install the primary breakout module (54-24663-01) included
in your hardware kit (see Figure 2–7). Applying power to the Digital
Alpha VME 4 module WITHOUT that primary breakout module in place,
or WITH the breakout module included with the AXPvme 160, 166, or
230 (P/N 54–22605–01) in place may damage your backplane, the Digital
Alpha VME 4 module, or both.

Figure 2–1 shows the Digital Alpha VME 4 module and its options.

Installation Procedures 2–1

Figure 2–1 Digital Alpha VME 4 Module Components

1

2

3

4

7

5

6

MLO-013240

!

Optional PMC I/O companion card

"

I/O module

#

Digital Alpha VME 4 module

$

Memory modules

%

Cache memory modules

&

Secondary breakout module

'

Primary breakout module

Table 2–1 lists Digital Alpha VME 4 hardware kit items. The kits in Table 2–1
contain hardware only. The option you receive may also include software licenses
or software, depending on what is ordered.

2–2 Installation Procedures

Table 2–1 Digital Alpha VME 4 Hardware Kit Items

Item Part Number

Digital Alpha VME 4/224 Kit

Digital Alpha VME 4 module I/O assembly 70–32976–04 (includes 512 KB cache)

(54–24325–04 + 54–24319–01)

1

Digital Alpha VME 4 Primary breakout module

54–24663–01
Digital Alpha VME 4 Secondary breakout module 54–24729–01
Alpha VME 4/228 and 4/288 Single-Board

EK–DAVME–TD
Computers User’s Guide and Technical
Description

Antistatic wriststrap 12–36175–01

Digital Alpha VME 4/288 Kit

Digital Alpha VME 4 module I/O assembly 70-32976-02 (includes 2 MB cache)

(54–24325–02 + 54–24319–01)

1

Digital Alpha VME 4 Primary breakout module

54–24663–01
Digital Alpha VME 4 Secondary breakout module 54–24729–01
Alpha VME 4/228 and 4/288 Single-Board

EK–DAVME–TD
Computers User Guide and Technical Description

Antistatic wriststrap 12–36175–01

Optional PMC I/O Companion Card

PMC I/O Companion Card 54–24665–01
Y cable 17-04230-01

1

Installation necessary for operation of VME 4 module I/O assembly.

To install the Digital Alpha VME 4 module, you must also have one or more of the
memory and cache module sets listed in Tables 2–2 and 2–3. Each kit contains
two modules.

Installation Procedures 2–3

Table 2–2 Digital Alpha VME 4 Memory Modules

Memory Size
(MB) Kit Number Part Number

16 EBMXM-DB 54–24659–AB
32 EBMXM-EB 54–24659–AA
64 EBMXM-FB 54–24645–AA

Table 2–3 Digital Alpha VME 4 Cache Memory Modules

Memory Size Kit Number Part Number Quantity

512 KB EBMXC–BA 54–24685–AA 2
2 MB EBMXC–DB 54–24683–AA 2

Depending on how you plan to use the Digital Alpha VME 4 system, you may
need one or more of the items listed in Table 2–4 that are not part of the Digital
Alpha VME 4 kit.

In order to attach a local disk, a 50-pin IDC SCSI cable is required and must be
properly terminated. The exact cable requirements depend upon the enclosure,
disk mounting, and so forth. A PC ‘‘internal SCSI cable’’ will work if you are
connecting to an internal disk and the cable has a SCSI terminator, or if the last
disk (or other SCSI device) has an internal terminator. You can use the Digital
SCSI cables listed in Table 2–4 for this purpose.

To attach a printer to the parallel port of the secondary breakout module (54­24729-01), use any standard parallel port printer cable that has a 26 pin IDC
connector on one end (for example, 17-04060-01). When you connect the cable,
make sure pin 1 of the cable is on pin 1 of the connector that is mounted on the
breakout module.

2–4 Installation Procedures

Table 2–4 Additional Hardware Installation Items

Item Supplier Part Number

Serial line cable for console and auxiliary
terminals

IEEE 802.3 Twisted-pair transceiver to ThinWire Digital DETTR–AA
IEEE 802.3 Twisted-pair transceiver to twisted-

pair
10BASET loopback connector Digital 12-35619-01

SCSI 20.32 cm (8 in), 30.48 cm (12 in), or 53.34
cm (21 in) cable with a 50-pin female IDC
connector for connection to the Alpha VME
breakout module and a female IEEE (Champ)
connector for connection to external drives

2

SCSI 102.87 cm (40.5 in) cable with six 50-pin
female IDC connectors and an included 50-pin
IDC SCSI terminator for connection to the Alpha
VME breakout module and up to 4 internal drives
with the terminator on the last connector

SCSI 220.98 cm (87 in) cable with five 50-pin
female IDC connectors for connection to the
Alpha VME breakout module and up to 4 internal
drives and a female IEEE (Champ) connector for
connection to external drives

2

Parallel port cable (example) Digital 17-04060-01

Digital BC16E– nn

Digital DETTR–BB

(H4082-AA)

Digital 17-01244-01, -02, -03

Digital 17–03459–02

Digital 17-03036-01

1

1

The nn = cable length.

2

A Champ SCSI terminator (PN H8574-A) might be required if external drives are not connected.

Installation Procedures 2–5

2.2 Installation

To install the Digital Alpha VME 4 module, perform the following steps:

1. Select two adjacent slots in your VME backplane for the Digital Alpha VME

4 module. If you are installing a PMC I/O companion card, you will need to
select three adjacent slots. Refer to Section 2.2.1 for instructions on how to
install the PMC I/O companion card.

Caution

Static electricity can destroy the circuits on the modules in your Digital
Alpha VME 4 kit. When you handle modules wear the antistatic
wriststrap with the wire clipped to the frame of your VME chassis. Also,
place the modules on top of the conductive plastic bags they came in while
you work.

Note

There must be sufficient space on the back of the VME backplane slot or
slots selected to install the primary breakout module. The Digital Alpha
VME 4 primary breakout module requires a minimum of 38.1 mm (1.5
in).

Figure 2–2 and Figure 2–3 show the layout of Digital Alpha VME 4 and the
I/O modules.

2–6 Installation Procedures

Figure 2–2 Digital Alpha VME 4 Module Layout

8

7

2 MB

A

C

B

6

512 KB

512 KB 2 MB

45

A

C

B

3

D
C
B
A

D
C
B
A

9

1

2

MLO-013237

!

Cache memory connectors

"

Memory connectors

#

Cache configuration select jumper (J9)

$

Power and VME slave activity/watchdog timeout LEDs

%

Status display

&

Cache memory size and speed select jumper (J10)

'

I/O module connector

(

VME connectors

)

SROM (8 pin)

Installation Procedures 2–7

Figure 2–3 I/O Module Layout

5 6

4321

9

10

2134

!

Console serial port

"

Auxiliary serial port

#

Reset/halt switch

$

Twisted pair Ethernet connector

%

Connector to CPU module (on back of I/O module)

&

Debug jumper (not installed for normal operation)

8

OPEN

7

OFF
ON

MLO-013238

'

Configuration switchpack

(

PMC I/O companion card connector

)

Ethernet Address ROM

+>

NVRAM/TOY clock

2–8 Installation Procedures

2. Set the configuration switches on the I/O module as outlined in Table 2–5,

Table 2–6, and Table 2–7. Also refer to Figure 2–3 for the configuration
switch location.

Table 2–5 Digital Alpha VME 4 Module Configuration Switches

Switch Setting Function

1 Closed Supplies +5 V from the VMEbus +5 V Standby signal to the time-

of-year (TOY) clock and the nonvolatile random-access memory
(NVRAM) to supplement the internal battery when the Digital
Alpha VME 4 module is turned off.

Open Does not supply power from the VMEbus +5 V Standby signal. The

internal battery will last for about 10 years with the Digital Alpha
VME 4 module power turned off.

2 Closed Enables writing of flash ROMs under program control.

Open Disables writing of flash ROMs.

3 Closed Resets the Digital Alpha VME 4 module on VMEbus Reset signal.

Open Does not reset the Digital Alpha VME 4 module on VMEbus Reset

signal.

4 Closed Digital Alpha VME 4 module is VMEbus system controller.

Open Digital Alpha VME 4 module is not VMEbus system controller.

Table 2–6 Supported Switch Settings for Digital Alpha VME 4 Modules in Slot 1

(System Controller)

Switch Setting

1 Closed
2 Open
3 Open
4 Closed

1

1

1

These switches are required to be in the indicated positions for reliable system operation during a

VMEbus Reset.

Installation Procedures 2–9

Table 2–7 Supported Switch Settings for Digital Alpha VME 4 Modules in Other

Than Slot 1 (Nonsystem Controller)

Switch Setting

1 Closed
2 Open
3 Closed
4 Open

1

These switches are required to be in the indicated positions (one opened, one closed) for reliable

system operation during a VMEbus Reset.

1

1

3. Install the memory module on your Digital Alpha VME 4 module (Figure 2–4)

in the following manner:

• Populate bank 0 first, then bank 1, if necessary.

• Memory installed in a bank must be the same size and speed.

• Align pin 1 of the memory module with pin 1 on the connector. The
position of the orientation notches (see#in Figure 2–4) assure proper
connectivity.

2–10 Installation Procedures

Figure 2–4 Installing the Main Memory Modules

1

2

4

!

Memory bank 0 slots A and B

"

Memory bank 1 slots A and B

#

Orientation notches

$

Memory connector

3

MLO-013246

Table 2–8 shows all possible valid memory configurations.

Installation Procedures 2–11

Table 2–8 Digital Alpha VME 4 Memory Configurations

Memory Size
(MB)

16 8 8
328888
32 16 16
48 8 8 16 16
64 16 16 16 16
64 32 32
96 16 16 32 32
96 32 32 16 16
128 32 32 32 32

Bank 0
Slot A

Bank 0
Slot B

Bank 1
Slot A

Bank 1
Slot B

4. Cache memory DIMMs are installed on your Digital Alpha VME 4 module by
Digital. Pin 1 of the DIMM is aligned with pin 1 on the cache connector. The
position of the orientation notch on the cache memory DIMM in Figure 2–5
(see!) denotes the location of pin 1.

2–12 Installation Procedures

Figure 2–5 Cache Memory Modules

1

2

MLO-013245

!

Orientation notch

"

Cache memory connector

5. The J9 and J10 jumpers are preconfigured for your Digital Alpha VME 4
module by Digital. Table 2–9, Table 2–10, and Figure 2–2 show jumper
settings and locations for informational purposes only.

Table 2–9 J9 Cache Jumper Settings

Size A B C D

512 KB Out Out In In
2 MB Out Out In In

Installation Procedures 2–13

Table 2–10 J10 Cache Jumper Settings

A B C Total Size Speed

In In In Disable cache
In In Out Reserved
In Out In 2 MB 12 ns
In Out Out Reserved
Out In In 512 KB 15 ns
Out In Out Reserved
Out Out In Reserved
Out Out Out Reserved

Note

If you are installing the PMC I/O companion card, proceed to Section 2.2.1
later in this chapter and complete the installation instructions before
continuing on to step 6.

6. Install the Digital Alpha VME 4 module into the VME chassis (refer to
Figure 2–6). Note that the module requires two adjacent backplane slots.
Secure the module with screws as shown in callout!.

2–14 Installation Procedures

Figure 2–6 Installing the Digital Alpha VME 4 Module

1

MLO-013236

Caution

You must install the primary breakout module (54-24663-01) included
in your hardware kit (see Figure 2–7). Applying power to the Digital
Alpha VME 4 module WITHOUT that primary breakout module in place,
or WITH the breakout module included with the AXPvme 160, 166, or
230 (P/N 54–22605–01) in place may damage your backplane, the Digital
Alpha VME 4 module, or both. Also, do not press on the LED window
when you install the module.

Installation Procedures 2–15

Figure 2–7 Alpha VME 4 Primary Breakout Module

!

Part Number: 54-22605-01

6

4

2

5

3

1

Part Number: 54-24663-01

MLO-013263

7. Set the SCSI termination jumper on the breakout module (refer to
Figure 2–8).

The SCSI bus must be terminated at each end. In most installations, the
breakout module is one end of the SCSI bus and the far end of the SCSI
ribbon cable is the other end of the SCSI bus. In this case, enable the SCSI
termination by placing the jumper across pins 1 and 3 (default).

If the breakout module is not at the end of the SCSI bus, disable the SCSI
termination by placing the jumper across pins 3 and 5.

8. Set the watchdog signal jumper on the breakout module (refer to Figure 2–8).
The Digital Alpha VME 4 module supplies an external watchdog reset signal

that you can connect to a monitoring device. If you make no connection to
this external signal, the setting of the jumper makes no difference.

Setting the jumper across pins 4 and 6 (default) provides an internal 2 kOhm
to +5 V pullup for this signal. Setting the jumper across pins 2 and 4 provides
no pullup. This allows you to attach a monitoring device that operates at a
different voltage level. The monitoring device must provide voltage and
a pullup resistor that do not exceed the output specifications of a 74LS05

2–16 Installation Procedures

component. The monitoring device must also be connected to the same
ground reference as the Digital Alpha VME 4 module.

The external watchdog reset signal is on pin C10 of the VMEbus J3 (P2)
connector on the breakout module. This signal is low during normal operation
and high during a watchdog timer reset (provided that pullup power is
connected).

Figure 2–8 Primary Breakout Module Jumpers

SCSI Termination

Enabled

5 3 1

6 4 2

Watchdog Pullup

SCSI Termination

Disabled

5 3 1

6 4 2

Watchdog No Pullup

9. If your Digital Alpha VME 4 system has SCSI devices, connect the SCSI cable
to the primary breakout module (refer to Figure 2–9).

MLO-013261

Installation Procedures 2–17

Figure 2–9 Connecting the SCSI Cable to the Primary Breakout Module

MLO-013241

10. Install the primary breakout module (refer to Figure 2–10). Ensure that the
breakout module is installed behind the slots occupied by the Digital Alpha
VME 4 module (as shown).

Caution

Running the Digital Alpha VME 4 module when it is not in the same slots
as the correct breakout module (refer to Figure 2–10) may damage your
backplane, the Digital Alpha VME 4 module, or both.

Never insert a module other than an Digital Alpha VME 4 module into a
slot opposite the breakout module. The breakout module feeds power to
several of the user-defined pins on the P2 backplane connector. This may
damage another VME module.

It is recommended that the slot number and type of breakout module be
recorded to ensure that the Digital Alpha VME 4 modules are always
installed into a slot with the appropriate breakout module.

2–18 Installation Procedures

Figure 2–10 Installing the Primary Breakout Module

MLO-013264

11. A secondary breakout module is included in the hardware kit, which you can
connect to the primary breakout module. If you use the secondary breakout
module, set the jumpers on that module as shown in Figure 2–11.

An incremental clearance of at least 56.25 mm (2.25 inches) is required to
install the secondary breakout module.

Note

Installation Procedures 2–19

Figure 2–11 Secondary Breakout Module Jumpers

3

Keyboard / Mouse

Disabled

3 1

4 2

4

!

Mouse and keyboard connector

"

Mouse and keyboard Y cable (17-04230-01)

3 1

4 2

Keyboard / Mouse

Enabled

3 1

4 2

2

3 1

4 2

1

MLO-013353

#

Keyboard and mouse jumper configurations

$

Parallel port (see Appendix A for pinouts)

12. Connect the secondary breakout module to the primary breakout module as
shown in Figure 2–12.

2–20 Installation Procedures

Figure 2–12 Connecting the Secondary Breakout Module to the Primary

Breakout Module

1 2

MLO-013266

!

Primary breakout module (54-24663-01)

"

Secondary breakout module (54-24729-01)

13. Connect the network cable (if any) to the twisted-pair Ethernet connector. See
Figure 2–13. Associated with the Ethernet connector are devices to convert
from twisted pair to ThinWire (P/N DETTR–AA). See Table 2–4.

14. Connect the console terminal cable to the Digital Alpha VME 4 module (refer
to Figure 2–13).

15. If you have an auxiliary terminal, connect it now. Set your console terminal
to a speed of 9600 bits/second, an 8-bit data word, and no parity.

Installation Procedures 2–21

Figure 2–13 Connecting Network and Console Terminal Cables

1 2 3

MLO-013352

!

Network

"

Console

#

Auxiliary

16. Insert blank panels into the vacant slots of the VME chassis. This improves
airflow and reduces electromagnetic interference (EMI) radiation.

17. Your installation is complete and power can be turned on.

18. When you turn power on, the Power LED lights (refer to Figure 3–1) and the
Digital Alpha VME 4 module runs its power-up self-test display (POST). This
takes about 30 seconds.

The POST runs a number of tests that show their status on the LED display.
These tests complete successfully when the display counts down to zero.

The POST then runs a number of additional tests that display their status
on the console terminal. These tests have completed successfully when the
console prompt appears (>>>) and the LED displays a rotating bar. For more
information on the POST, refer to the diagnostics chapter.

2–22 Installation Procedures

2.2.1 Installing the PMC I/O Companion Card

Figure 2–14 shows the layout of the PMC I/O companion card.

Note

To install the PMC I/O companion card with the Digital Alpha VME 4,
you must have three adjacent slots available.

Figure 2–14 PMC I/O Companion Card Layout

9

7

3.3 V

5.0 V

8

6

2

!

I/O module connector (on back of PMC I/O companion card)

"

PCI-to-PCI bridge chip

10

1345

MLO-013366

#

Power LED

$

Keyboard connector

%

Mouse connector

&

Debug socket

Installation Procedures 2–23

'

Signaling level jumper (jumper MUST be set to 5.0 V)

(

PMC option slots

)

VME connectors

+>

I/O-to-P2 signal connector

Caution

Perform the following steps gently to avoid damage to the modules.

1. Make sure the signaling-level jumper on the PMC I/O companion card is set
for 5.0 V, as show in Figure 2–14.

2. Install any user-supplied PMC options.

3. Carefully, align the ball connector on the bottom edge of the PMC I/O
companion card handle into the slot on the top edge of the Digital Alpha
VME 4 handle as shown in Figure 2–15. Note the orientation of the heat
sink.

4. Raise the PMC I/O companion card up at a slight angle from the I/O module
and slide the connecting edges together until the connector on the bottom of
the PMC I/O companion card is aligned with its mating connector on the top
side of the I/O module as shown in Figure 2–15.

You must align the connector precisely. If the alignment is not precise,
the force required for normal connector mating is sufficient to damage the
connector housing and pins.

5. Carefully press down on the module causing the two connectors to mate and
four standoffs to anchor as shown in Figure 2–15.

6. Install the Digital Alpha VME 4 module into three adjacent slots in the VME
chassis as shown in Figure 2–16.

Digital recommends that you back out the captive screws on the front
panel until they are fully engaged by the press-fit shoulder washer before

2–24 Installation Procedures

Caution

Caution

seating the Alpha VME module in the VME chassis. If you do not retract
the screws completely:

• The Alpha VME module might not seat properly.

• The press-fit shoulder washer that holds the screw washer in
place might become disengaged if you apply excessive pressure to
the front panel.

7. Tighten the six screws on the handles as shown in Figure 2–16.

8. If being used, connect the mouse and keyboard cables at the locations shown
in Figure 2–14.

Installation Procedures 2–25

Figure 2–15 Connecting the PMC I/O Companion Card

2–26 Installation Procedures

MLO-013265

Figure 2–16 Installing the PMC I/O Companion Card

1

MLO-013411

9. Return to step 6 in Section 2.2 for instructions on installing the Digital
Alpha VME 4 module into the VME chassis and setting up and installing the
breakout modules.

2.3 Diagnostics

When you turn on the power or toggle the Reset switch, the Digital Alpha VME
4 module runs its POST. The module runs a series of tests stored in the serial
read-only memory (SROM) and then runs a series of console code tests stored in
the flash ROMs. The SROM tests display their test number on the LED display
during execution. If an SROM test fails, the LED display flashes the failing test
number. Refer to Table 2–11 for a list of SROM test numbers and functions.

Installation Procedures 2–27

Table 2–11 SROM Test Numbers and Descriptions

LED Display COM1 Meaning

8 - Nbus bus has been reset and SIO configured.
7 7.. COM1 port has been initialized (9600 baud).
6 6.. BIU_CTL register has been programmed according to

5 5.. Main memory DIMMs have been configured according to

4 4.. Bcache has been initialized and put on line.
3 3.. Bcache and all memory has been scrubbed to valid error

2 2.. Firmware image has been loaded from the flash ROM.

1 1.. The debug jumper is about to be checked. If the

0 0 Written by the PAL reset entry point. This indicates that

the cache configuration jumpers, but Bcache is not on
line.

PD bits. Memory is alive but not scrubbed.

checking/correction (ECC).

Image starts at 0X8000.

jumper is IN, then the initialization process traps to
the minidebugger.

the firmware has been decompressed and is starting.

Note

Use of a graphic mode console option may preclude the display of initial
POSTs. See the documentation supplied with your graphics option for
details.

The console code tests display their test names and results on the console
terminal. The console code tests also display their test letter on the LED display
as they are being executed. If a console code test fails, the LED display flashes
the letter of the failing test. Table 2–12 lists console code test letters and test
names.

2–28 Installation Procedures

Table 2–12 Console Code Test Letters and Names

Test Letter Test Name

A SCSI control and status register (CSR) test
B Heartbeat timer test
C Interval timer test
D DS1386 nonvolatile RAM tests
E Auxiliary Universal Asynchronous Receiver/Transmitter (UART) test
F Ethernet address ROM test
G Ethernet internal and external loopback tests
H Watchdog timer test
I VME interface processor/VIC64 test

After the POST completes and the system is idle, the console outputs a ‘‘rotating
bar’’ to the LED display.

Refer to Chapter 4 for more information about these tests.

2.4 Troubleshooting

The Digital Alpha VME 4 modules include extensive diagnostic (POST)
capabilities that are normally executed on power-up. These include both
SROM and flash ROM-based code.

SROM-based diagnostics are always executed on power-up and use decreasing
numeric codes (8, 7, ...1) to indicate status on the dot matrix display. All SROM­based tests must pass successfully before the flash ROM-based diagnostics and
console diagnostics are run. If one or more SROM diagnostics fail, the flash
ROM-based diagnostics and the console diagnostics will not be loaded and a
single>prompt will be displayed on the console terminal. The code of the failing
diagnostic will be on the dot matrix display. Additional information appears on
the console terminal if present.

Once the SROM diagnostics complete successfully, the flash ROM diagnostics will
be loaded, decompressed and executed. Flash ROM diagnostics use an ascending
(A, B, ..., I) character-based code to indicate progress. If one or more flash ROM­based diagnostics fail, the code representing the FIRST error will remain on the
dot matrix display and alternate between dim and bright intensity.

Installation Procedures 2–29

If all SROM and flash ROM-based diagnostics pass, and an auto_action1boot
command has been set, the

>>>

console prompt appears on the console terminal

and the dot matrix display will display a ‘‘rotating bar.’’
Note that a problem in the PMC I/O companion card that hangs the PCI bus

signal lines could cause diagnostics to report problems throughout the I/O
subsystem and in the PCI controller of the processor chip. If you have a PMC I/O
companion card installed and you are experiencing diagnostic failures, remove it
and repeat the POST.

It is important to remember that the dot matrix display is useable by operating
system software and by user applications as well. Once the system is booted, the
dot matrix display is no longer under control of the console code and may change.
The console will automatically clear the display before booting any image.

Table 2–13 lists symptoms and corrective actions that can be used for
troubleshooting the Digital Alpha VME 4 modules. Refer to the Troubleshooting
chapter of this manual for more information about troubleshooting procedures.

1

See Table 3–2

2–30 Installation Procedures

Table 2–13 Troubleshooting

Symptom Corrective Action

No LEDs lit, no console prompts. Check power. If 5 V power is out of

Green LED on, blank dot matrix display,
and no console prompts

Green LED on, dot matrix displays the
number 5 on power-up.

Green LED on, dot matrix displays the
number 0 on power-up.

Green LED on, dot matrix displays a
flashing letter A on power-up.

Green LED on, dot matrix displays a
flashing letter D on power-up.

Green LED on, dot matrix displays a
flashing letter F on power-up.

Green LED on, dot matrix displays a
flashing letter G on power-up.

Green LED on, dot matrix displays a
flashing letter I on power-up.

Diagnostics pass but the SCSI tests take
an inordinate amount of time (greater
than 10 seconds).

Diagnostics pass but there are no (or
unreadable) characters displayed on the
console.

specification, the module will be held in reset.
Check the seating of SROM (8-pin socketed

device near PCI port). See Figure 2–2.
Check the seating of the memory modules.

Ensure that the console terminal is not in
‘‘hold screen’’ mode.

Check the SCSI termination, the seating of
the Digital Alpha VME 4 module, the seating
of the breakout module, the seating of the
SCSI cable, and the seating of other SCSI
devices.

Check that the TOY/NVRAM device is seated
properly (see Figure 2–3).

Check the seating of the Network Address
ROM (see Figure 2–3).

Check the seating of the twisted pair cable
and the nearest network transceiver.

Check the seating of the Digital Alpha VME
4 module, the seating of the breakout module,
and the seating of other VME devices.

Check the SCSI termination, the seating of
the Digital Alpha VME 4 module, the seating
of the breakout module, the seating of the
SCSI cable, and the seating of other SCSI
devices.

Check the console terminal connections, and
settings (9600 baud, 8-bits, no parity). The
terminal should be plugged into the (CON)
port.

Installation Procedures 2–31

2.5 Repair and Warranty Information

2.5.1 Return to Digital Hardware Maintenance

The following products come with a 1 year Return to Digital warranty as
described in the following sections:

Table 2–14 Products With a 1 Year Return to Digital Warranty

Product Order Number

Alpha VME 4/224, SBC EBV14-AA
Alpha VME 4/224, UNIX Development EBV14-ZA
Alpha VME 4/224, UNIX Runtime EBV14-RA
Alpha VME 4/224, VxWorks Runtime EBV14-XA
Alpha VME 4/288, SBC EBV14-AE
Alpha VME 4/288, UNIX Development EBV14-ZE
Alpha VME 4/288, UNIX Runtime EBV14-RE
Alpha VME 4/288, VxWorks Runtime EBV14-XE
16 MB Memory DIMM, 80-bits, 70 ns EBMXM-DB
32 MB Memory DIMM, 80-bits, 70 ns EBMXM-EB
64 MB Memory DIMM, 80-bits, 70 ns EBMXM-FB
PMC I/O Companion Card EBV1P-AA

2.5.2 Hardware Warranty

Your Digital Alpha VME 4 system comes with a limited warranty, consisting
of Return to Digital hardware support. The warranty provides free repair or
replacement of the system or option field replaceable unit through the Digital
Customer Support Center.

2.5.2.1 Availability

Warranty support is available worldwide. Proof of purchase or ownership of
equipment, including serial numbers, may be required.

2–32 Installation Procedures

2.5.2.2 Return-to-Digital Process

To return products under warranty, contact the Digital Customer Support Center
in your particular geography. The Customer Support Center provides you with
a Return Material Authorization (RMA#) and an address to which to send the
defective material. You are responsible for sending the product to the address
provided and for prepaying transportation costs associated with returning the
product to the nearest Digital return center. Digital pays transportation costs
when the product is returned to you.

In the U.S., call 1-800-354-9000 to get information on returning the product.
Elsewhere in the world, contact the nearest Digital Customer Support Center.

2.5.2.3 Response Time

Digital uses an advanced exchange replacement process through the Customer
Support Center. Turnaround is two days from receipt at the Customer Support
Center.

A defective field replaceable unit must be received by the Digital Support Center
within 10 days of shipment of the unit. If the unit is not received within 10 days,
you will be billed for the replacement part at full country list price.

2.5.2.4 Eligible Parts

Field replaceable units, as defined by Digital, are the only parts eligible for
coverage. Field replaceable units in need of repair due to improper treatment or
use are not eligible for return. Improper treatment includes, but is not limited to,
lifted or burnt etches or delamination due to non-Digital repair or modification.

If you return a field replaceable unit that is not eligible for repair, Digital may
demand return of any replacement unit or charge you for full list price value of
the replacement unit. Digital will return the ineligible field replaceable unit to
you upon receipt of payment or the replacement unit.

Replacement field replaceable units will be at the current revision level and may
be refurbished. In the event that newly installed field engineering change orders
cause an incompatibility or other interference within your system, you accept
responsibility of such incompatibility or interference.

2.5.2.5 Purchaser Responsibility

It is your responsibility to:

• Install the equipment.

• Diagnose faults and disassemble equipment on returns of field replaceable
units.

• Properly package and prepay transportation costs of field replaceable units
sent to Digital.

Installation Procedures 2–33

• Assume all risk of loss or damage to field replaceable units in transit to
Digital.

2.5.2.6 Pre-Call Checklist

To allow Digital to assist you quickly and efficiently, consult the following
checklist before calling Digital or your authorized reseller:

1. Consult your product user documentation to assure that your system features
are properly configured.

2. Execute the customer diagnostics provided with the product, if applicable, and
record the information.

3. Consult your user documentation for more details on operation of the product.

4. Determine the product model number and serial number to enable processing
of warranty support.

2.5.3 Software Maintenance

Digital software products are warranted to conform to the applicable Software
Product Description. This means that Digital will remedy any conformance that
you report during the warranty period.

Warranty of third party software products sold by Digital is as designated in
the Software Product Description. The term of the warranty, and the manner
in which Digital will remedy any non-conformance is specified in the Software
Product Description or the price list. All other software is provided "as is". Digital
does not warranty that the execution of the software shall be uninterrupted
or error free. Digital does not warranty the form or content of third party
distributed software or documentation, both of which Digital provides "as is".
Certain third party distributed software is warranted by the third party.

2–34 Installation Procedures

2.5.4 Field Replaceable Units and Order Numbers

Table 2–15 lists the available field replacable units and their associated order
numbers.

Table 2–15 Field Replaceable Units and Order Numbers

Saleable Number

EBV14-*A

EBV14-*E

EBV1P-AA

EBMXM-DB 54-24659-AB 16 MB (2x8) DIMM Set
EBMXM-EB 54-24659-AA 32 MB (2x16) DIMM Set
EBMXM-FB 54-24645-AA 64 MB (2x32) DIMM Set

1

Order Number Description

70-32976-04 224 MHz Single Board Computer — 2 board

set, 512 KB cache
54-24729-01 VME Secondary Breakout Module
54-24663-01 VME Primary Breakout Module

70-32976-02 288 MHz Single Board Computer — 2 board

set, 2 MB cache
54-24729-01 VME Secondary Breakout Module
54-24663-01 VME Primary Breakout Module

54-24665-01 PMC I/O Companion Card
17-04230-01 Cable, Y-Adapter, IBM ThinkPAD

1

An asterisk (*) indicates any of the four possible letters (A, Z, R, or X).

Installation Procedures 2–35

Operating the Digital Alpha VME 4

Computer

3.1 Controls and Indicators

Figure 3–1 shows the front panel controls and indicators of the Digital Alpha
VME 4 module and Table 3–1 describes their function.

3

Operating the Digital Alpha VME 4 Computer 3–1

Figure 3–1 Controls and Indicators

1

2 3 4

Table 3–1 Controls and Indicators

Control or Indicator Description

!

"

#

$

Reset/Halt switch A switch that resets the Digital Alpha VME 4

Status display A display that shows which test is running during

VME Slave Activity
/Watchdog Timeout LED

Power LED A green LED that is lit when the power is on.

MLO-013262

system when pressed in the Reset (up) direction.
When pressed in the Halt (down) direction this
switch halts the operating system and the module
enters console mode.

the POST. After that, the display is under the
software control of the operating system or an
application program.

An amber LED with two functions. The LED
flashes when the Digital Alpha VME 4 module
is accessed as a slave by another device on the
VMEbus. The LED lights continuously when the
watchdog timer has timed out.

Note: The LED can appear to light continuously
when the module is receiving slave accesses. Since
the LED glows for 1/3 of a second each time it
flashes, three slave accesses per second could make
the LED light continuously.

3–2 Operating the Digital Alpha VME 4 Computer

3.2 Console Mode

Sections 3.2.1 and 3.2.2 explain how a Digital Alpha VME 4 system enters and
exits console mode.

3.2.1 Entering Console Mode

A Digital Alpha VME 4 module enters console mode automatically when the
POST is finished. A Digital Alpha VME 4 module also enters console mode when:

• You press the Reset/Halt switch on the front panel.

Caution

Depending on the operating system and applications running at the time,
this could damage application files that are open and have not been saved.

• The module receives a VMEbus Reset signal and configuration switch 3 on
the module is enabled.

Caution

Depending on the operating system and applications running at the time,
this could damage application files.

• You use the operating system command to enter console mode.

• The operating system executes a HALT instruction.

• The operating system encounters a fatal error.

3.2.2 Exiting Console Mode

You can exit console mode by issuing the boot, start,orcontinue command. For
more information, use the help command or see Chapter 13.

3.3 Environment Variables

From the console, you can configure your Digital Alpha VME 4 system by setting
the values of environment variables. You set the values of environment variables
by using the console command set. You can also display the current settings of
environment variables by using the show command.

Operating the Digital Alpha VME 4 Computer 3–3

Note

Do not change the settings of the environment variables without
understanding the implications of the changes.

Table 3–2 lists the environment variables with descriptions.

Table 3–2 Environment Variable Summary

Variable Description

AUTO_ACTION Defines the action of the console following an error, halt, or

BOOT_DEV Specifies the device list to be used by the last, or currently in

BOOT_FILE Specifies the file name to be used when a bootstrap requires

BOOT_OSFLAGS Specifies arguments to be passed to system software when

BOOTDEF_DEV Specifies the device list from which bootstrapping is to be

BOOTED_DEV Specifies devices to be used by the last or currently in progress

BOOTED_FILE Specifies the file name to be used by the last or currently in

BOOTED_OSFLAGS Specifies arguments to be passed to system software during the

CHAR_SET Specifies current console terminal character-set encoding.
CONSOLE Specifies whether console input and output are to use the

D_BELL Specifies whether the bell is to sound on error.
D_CLEANUP Specifies whether cleanup code is to be executed at the end of

D_COMPLETE Specifies whether a diagnostic completion message is to be

power-up.

progress, bootstrap attempt.

a file name, when the bootstrap is not the result of a boot
command, or when no file name is specified with the boot
command.

the bootstrap is not the result of a boot command or when no
arguments are specified with the boot command.

attempted when no path is specified with the boot command.

bootstrap attempt.

progress bootstrap attempt.

last or currently in progress bootstrap attempt.

console serial line or a graphics console, if present.

diagnostics.

displayed.

(continued on next page)

3–4 Operating the Digital Alpha VME 4 Computer

Table 3–2 (Cont.) Environment Variable Summary

Variable Description

D_EOP Specifies whether end-of-pass messages are to be displayed.
D_GROUP Specifies the diagnostic group to be executed.
D_HARDERR Defines the action that is to be taken following a hard error

D_OPER Specifies whether an operator is present.
D_PASSES Specifies the diagnostic pass count.
D_REPORT Specifies the level of information to be provided by diagnostic

D_SOFTERR Defines the action that is to be taken following soft error

D_STARTUP Specifies whether a diagnostic startup message is to be

D_TRACE Specifies whether trace messages are to be displayed.
DUMP_DEV Specifies that a device is to write operating system crash

ENABLE_AUDIT Specifies whether audit trail messages are to be generated

EWA0_ARP_TRIES Specifies the number of transmissions to be attempted before

EWA0_BOOTP_FILE Specifies a generic file name to be included in an Internet Boot

EWA0_BOOTP_
SERVER

EWA0_BOOTP_TRIES Specifies the number of transmissions that are to be

EWA0_DEF_GINETADDR Specifies the initial value for EWA0_GINETADDR when

EWA0_DEF_INETADDR Specifies the initial value for EWA0_INETADDR when the

EWA0_DEF_INETFILE Specifies the initial value for EWA0_INETFILE when the

detection.

error reports.

detection.

displayed.

dumps.

during bootstrap.

the Internet Address Resolution Protocol (ARP) fails.

Protocol (BOOTP) request.
Specifies a server name to be included in a BOOTP request.

attempted before BOOTP fails.

the interface’s internal Internet database is initialized from
BOOTP (EWA0_INET_INIT is set to BOOTP).

interface’s internal Internet database is initialized from
BOOTP (EWA0_INET_INIT is set to BOOTP).

interface’s internal Internet database is initialized from
BOOTP (EWA0_INET_INIT is set to BOOTP).

(continued on next page)

Operating the Digital Alpha VME 4 Computer 3–5

Table 3–2 (Cont.) Environment Variable Summary

Variable Description

EWA0_DEF_SINETADDR Specifies the initial value for EWA0_SINETADDR when

EWA0_INET_INIT Specifies whether the interface’s internal Internet database is

EWA0_LOOP_COUNT Specifies the number of times each message is looped.
EWA0_LOOP_INC Specifies the amount the message size is to be increased from

EWA0_LOOP_PATT Specifies the type of data pattern that is to be used for

EWA0_LOOP_SIZE Specifies the size of the loop data to be used.
EWA0_LP_MSG_NODE Specifies the number of messages to be sent to each node

EWA0_MODE Specifies the operating mode of the embedded Ethernet

EWA0_PROTOCOLS Specifies the network protocol to be enabled for booting and

EWA0_TFTP_TRIES Specifies the number of transmissions that are to be attempted

LANGUAGE Specifies the current console terminal language (integer ID).
LANGUAGE_NAME Specifies the current console terminal language.
LICENSE Specifies whether a software license is in effect.
MODE Specifies whether diagnostics are to be run when the firmware

PAL Specifies versions of VMS and OSF PALcode in the firmware.
TGA_SYNC_GREEN Specifies a hexadecimal byte indicating whether video

TTY_DEV Specifies the current console terminal unit.
VERSION Specifies the version of the console code firmware.

the interface’s internal Internet database is initialized from
BOOTP (EWA0_INET_INIT is set to BOOTP).

to be initialized from non-volatile RAM (NVRAM) or from a
network server (by way of BOOTP).

message to message.

loopback.

originally.

controller. Valid settings include TWISTED-PAIR and FULL
(full-duplex twisted pair).

other functions.

before the Trivial File Transfer Protocol (TFTP) fails.

is initialized. Set to FASTBOOT or NOFASTBOOT.

synchronization should be driven on the green channel for
up to eight TGA video cards. Video card 0 corresponds to
bit 0, card 1 to bit 1, and so on. Used with the CONSOLE
environment variable.

(continued on next page)

3–6 Operating the Digital Alpha VME 4 Computer

Table 3–2 (Cont.) Environment Variable Summary

Variable Description

VME_A32_BASE Specifies the base address of VMEbus A32 space.
VME_A32_SIZE Specifies the size of VMEbus A32 space.
VME_A24_BASE Specifies the base address of VMEbus A24 space.
VME_A24_SIZE Specifies the size of VMEbus A24 space.
VME_A16_BASE Specifies the base address of VMEbus A16 space.
VME_CONFIG Specifies the VME setup mode.
VX_BOOTLINE Specifies the name of the file to be used for the VxWorks

bootstrap.

3.4 Booting an Operating System

For information on booting the Digital UNIX operating system or VxWorks for
Alpha kernel, see the operating system documentation. If you are booting the
Digital UNIX operating sytem, see the Digital UNIX Installation Guide. If you
are booting the VxWorks for Alpha kernel, see the VxWorks: Digital Alpha VME

Single-Board Computers Hardware Supplement and the VxWorks Programmer’s
Guide.

3.5 Updating Firmware

For information on updating the Digital Alpha VME 4 firmware, see the

Digital Alpha VME 4/244 and 4/288 Single-Board Computer Firmware Update
Procedures shipped with the firmware release and either the VxWorks Digital
Alpha VME Single-Board Computers Hardware Supplement or the Digital UNIX
Installation Guide.

Operating the Digital Alpha VME 4 Computer 3–7

4

Diagnostics

4.1 Overview

This chapter describes the Digital Alpha VME 4 power-on self-test (POST)
diagnostics and additional ROM-based diagnostics (RBDs).

Diagnostics for the Digital Alpha VME 4 system provide a fast, high coverage
suite of POSTs to be invoked automatically at power-on and system reset. In
addition to the POSTs, there are RBDs that provide additional testing and fault
isolation. You invoke RBDs at the console prompt from the console terminal.
You can use diagnostic environment variables to gain more control of the test
environment.

4.2 Operating Environments

The Digital Alpha VME 4 diagnostics are invoked under two distinct mechanisms:

• Power-on and/or system reset

• By an operator at the console prompt

4.2.1 POST Diagnostics

The diagnostic reset environment is entered as a result of power being applied to
the system or, reset being applied to a previously running system. In this mode,
a sequence of RBDs is executed without user intervention.

Once the SROM code has been loaded into the 8 KB internal instruction cache,
a very basic system initialization is performed in preparation for starting the
console firmware. After enough of the system has been initialized, the flash ROM­based console is loaded into system memory and execution is transferred to it.
During this phase of console startup, several more diagnostics are automatically
invoked and executed without operator intervention.

The system LED display indicates progress of the SROM initialization. The
display counts down from 8 to 1.

Diagnostics 4–1

Failures detected by the SROM-based tests are indicated by the test sequence
halting and the LED display permanently showing the failing test number.
A detailed dump of internal registers, program counter, expected and actual
data is performed either through the serial port of the 21064 or through the
console Universal Asynchronous Receiver/Transmitter (UART). If the Intel SIO is
successfully configured and the console UART test passes, the SROM does all I/O
through the console UART; otherwise, it is through the 21064 serial port/pin.

Failures detected beyond the SROM do not halt the reset sequence, but rather,
the display freezes at the first failing test, and the sequence attempts to continue
to console mode. An attempt is also made to write the diagnostic log to the
console terminal.

You can affect the POST sequence by using certain user-selectable, control
parameters (implemented as environment variables) that allow the initialization
to continue, despite the existence of some errors that you may not wish to treat
as fatal.

4.2.2 Console Prompt Diagnostics

You can invoke some diagnostics directly from the console terminal, and you can
control them by using command options and diagnostic environment variables.
These tests may require operator intervention.

4.3 Diagnostic Test Descriptions

4.3.1 Available Console Diagnostics

Table 4–1 shows the console diagnostic tests and the commands you can use to
invoke them. You can invoke the majority of these tests at the console prompt.

4–2 Diagnostics

Table 4–1 Console Diagnostic Tests

HW Under Test Command

Memory and Cache

- Memory exerciser test memtest or mem_ex

Network Interface

- DECchip 21040 network interface

internal loopback test

- DECchip 21040 network interface

external loopback test

- DECchip 21040 network interface control

/status register (CSR) test

- DECchip 21040 network interface CSR

test

- DECchip 21040 network interface CSR

test

NVRAM + TOY Clock

- NVRAM test ds1386_diag -t 1

- NVRAM test ds1386_diag -t 2

- NVRAM test ds1386_diag -t 3

- Time-of-year (TOY) clock register test ds1386_diag -t 4

- TOY clock register test ds1386_diag -t 5

niil_diag -t 1

niil_diag -t 2

nicsr_diag -t 1

nicsr_diag -t 2

nicsr_diag -t 3

SCSI

- SCSI device test ncr810 -t 1

- SCSI device test ncr810 -t 2

- SCSI device test ncr810 -t 3

- SCSI device test ncr810 -t 4

- SCSI device test ncr810 -t 5

- SCSI device test ncr810 -t 6

- SCSI device test ncr810 -t 7

(continued on next page)

Diagnostics 4–3

Table 4–1 (Cont.) Console Diagnostic Tests

HW Under Test Command

- SCSI device exer exer dk

Timers

- Heartbeat timer test hbeat_diag -t 1

- Interval timer test i8254 -t 1

- Interval timer test i8254 -t 2

- Interval timer test i8254 -t 3*

- Interval timer test i8254 -t 4*

- Interval timer test i8254 -t 5

- Interval timer test i8254 -t 6

- Watchdog timer test wdog_diag -t 1

* Requires external loopback connector
configured as shown in Figure 4–1.

VMEbus Interface Tests

- VIP PCI configuration register test vip_diag -t 1

- VIP register write/read test vip_diag -t 2

- VIC register write/read test vip_diag -t 3

- Scatter-gather RAM test vip_diag -t 4

MISC

- Ethernet hardware address test enet_diag -t 1

- Ethernet hardware address test enet_diag -t 2

4.3.2 SROM Initialization Countdown

During SROM initialization, the LED ASCII display executes a countdown that
indicates the progress of the initialization. The console serial output also reports
this countdown if the CONSOLE environment variable is set to SERIAL. The
countdown is structured as follows:

4–4 Diagnostics

LED Display

8 – Nbus bus has been reset and system I/O (SIO) configured.
7 7.. COM1 port has been initialized (9600 baud).
6 6.. BIU_CTL register has been programmed according to the

5 5.. Main memory controller has been configured according

4 4.. Bcache has been initialized and enabled.
3 3.. Bcache and main memory have been scrubbed to valid

2 2.. Firmware image has been loaded from the flash ROM.

1 1.. Debug jumper is about to be checked. If jumper is IN,

0 0 Written by the console firmware in PAL reset entry point.

Output on
Console Meaning

cache configuration jumpers, but Bcache was not enabled.

to the DIMM PD/ID bits. Memory is alive but was not
scrubbed.

error checking/correction (ECC).

Image starts at 0x8000.

then trap to the mini-debugger.

Indicates that the firmware has been decompressed and is
starting.

4.3.3 Console POST Descriptions

This section provides details on the POST that are run during system
initialization.

Diagnostics 4–5

POST Non-Volatile RAM Diagnostic

POST Non-Volatile RAM Diagnostic

The POST Non-Volatile RAM (NVRAM) diagnostic test verifies the module’s
NVRAM. It performs a data integrity test, through power cycles, and a write
/read/compare of specific NVRAM locations used for diagnostics. It also checks
for uninitialized NVRAM by comparing the stored checksum with the calculated
checksum.

Description

This test executes at the beginning of console boot before the console drivers and
devices have been initialized.

Test Name: None; executes on power-on

4–6 Diagnostics

POST Memory Diagnostic

POST Memory Diagnostic

The POST memory diagnostic test verifies system memory. It runs with ECC
enabled. If the test detects a memory error that cannot be corrected with ECC, it
logs the error in the error logging area of NVRAM.

Description

See also memtest in Chapter 13.

Note

This test is dependent upon the setting of the console MODE environment
variable. Setting mode to FASTBOOT evokes a quick verify test of the
memory, and NOFASTBOOT evokes a full test of memory.

This test executes at the beginning of console boot before the console drivers and
devices have been initialized.

This test provides the following coverage:
Memory bits Stuck bits, bit transition fault, or bit

coupling fault.

Decoder logic An address selects no memory, two or

more addresses select the same memory
cell, or one address selects more than one

cell.
Sense amplifier logic Stuck fault or coupling fault.
Component and path coverage The CPU memory control logic, etch from

the CPU to the daughter card connectors,

etch from the CPU backup cache control

to the backup cache and from backup

cache to the memory bus. The daughter

card is assumed good since it is tested

separately in manufacturing.
Test Name: None; executes on power-on.

Diagnostics 4–7

4.3.4 Console Diagnostic Test Descriptions

This section provides details on the tests, which are available to the console, that
you might run during system initialization testing or run from the console.

4–8 Diagnostics

Heartbeat Timer Test

Heartbeat Timer Test

The heartbeat timer diagnostic test verifies that a heartbeat interrupt is
generated at the correct interval (1024 Hz) and is properly dismissed by way
of the module clear heartbeat register.

This test checks the following logic:

• Heartbeat timer and interrupt delivery mechanism

• Module clear heartbeat register

Heartbeat Timer Test

Console Command: hbeat_diag -t 1
Command Option:

-dd: print detailed test information on each pass.

Miscellaneous Notes

• This is a POST diagnostic.

• The test expects timer interrupts to be enabled. If they are not enabled, an

interrupt count of zero results.

• You cannot run this test concurrently with other tests.

Diagnostics 4–9

Interval Timer Tests

Interval Timer Tests

The interval timer tests test the functionality of the 8254 interval timer chip and
surrounding external circuitry, including latches, programmable-array logic (PAL)
devices and printed circuit board module etch.

Since all three interval timers of the 8254 chip have different external
configurations, several tests are required for complete test coverage.

The intent of the tests is to verify that timers 0, 1, and 2 can generate a CPU
interrupt, if properly enabled, at the programmed frequency.

These tests require that you properly program both timer 0 and 1 and connect
them externally for successful operation.

Timer 2 Terminal Count Test

This test exercises Timer 2 with the timer interrupts enabled. In the Digital
Alpha VME 4 design, the gate input for Timer 2 is always enabled and the clock
input is connected to a 10 MHz (100 ns period) clock source.

Timer 2 is programmed to mode 0, interrupt on terminal count. After the timer is
initially programmed to mode 0 and loaded with a count value, the OUT output is
low and remains low until the internal count value reaches zero. When the count
value reaches zero, OUT output is asserted high and remains high until timer
2 is reprogrammed. The event of OUT transitioning from low to high should
generate a CPU interrupt.

The interrupt service routine (ISR) invoked due to the timer generated interrupt
sets a global flag indicating the interrupt took place and that software was
dispatched to the correct point.

Console Command: i8254_diag -t 1
Miscellaneous Notes

• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt

status register at address 0x4010) are not writable directly. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don’t Care.

• A read of the interrupt status register at address 0x4014 causes both

interrupt status bits (bits 0 and 1) to be cleared.

• Due to hardware limitations on interrupt detection, the value programmed

into timer 2 must be greater than 2.

4–10 Diagnostics

Interval Timer Tests

• See the Intel 8254 interval timer sheet for more details.

Timer 2 Square Wave Test

This test exercises timer 2. In the Digital Alpha VME 4 design, the gate input for
timer 2 is always enabled and the clock input is connected to a 10 MHz (100 ns
period) clock source.

Timer 2 is programmed to mode 3, square wave mode. After the timer is initially
programmed for mode 3 and then loaded with a count value, the OUT output
produces a continuous, square wave output whose period is equal to the count
value multiplied by the period of the clock input. The count values are chosen
such that they check stuck NDATA lines.

The event of OUT transitioning from low to high should generate a CPU
interrupt, provided the timer 2 interrupt enable bit is set.

The ISR invoked due to the timer generated interrupt increments an interrupt
counter and sets a global flag indicating the interrupt took place and that
software was dispatched to the correct point. The test verifies that the
interrupt count is within a certain range, based on the count value the timer
was programmed with and the duration of time that interrupts were enabled.

Console Command: i8254_diag -t 2
Miscellaneous Notes

• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt

status register at address 0x4010) are not directly writable. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don’t Care.

• A read of the interrupt status register at address 0x4014 causes both

interrupt status bits (bits 0 and 1) to be cleared.

• Due to hardware limitations on interrupt detection, the value programmed

into timer 2 must be greater than 2.

• See the Intel 8254 interval timer sheet for more details.

3 Timers Loopback Test

This test exercises timer 2, timer 1, and timer 0. In the Digital Alpha VME 4
design, the gate input for timer 2 and timer 1 is always enabled and the clock
input is connected to a 10 MHz (100 ns period) clock source. Timer 0 accepts its
input through a P2 loopback connector to which the outputs of timers 1 and 2 are
tied. Timer 2 is the gate input and timer 1 provides the clock.

Diagnostics 4–11

Interval Timer Tests

This test essentially emulates the realtime time provider and slave scheme found
in the Realtime Clock and Interval Device Driver functional specification.

Note

A VMEbus P2 loopback connector is required. See Figure 4–1 for a
description of the loopback connections.

Using the -lp option enables the timers indefinitely, making the module the
master time provider for test #4.

Timer 2 and timer 1 are programmed to mode 3, square wave mode. Timer 0
is programmed to mode 1. After the timers are initially programmed with the
appropriate mode and then loaded with a count value, the OUT output produces
a continuous, square wave output whose period is equal to the count value
multiplied by the period of the clock input. In this test timer 2 provides a major
clock which basically provides the start time of timer 0, and timer 1 produces
a much faster clock called the minor clock, which controls the rate that timer 0
counts down.

Timer 0 is the only interrupt that is enabled during this test. The event of OUT
transitioning from low to high should generate a CPU interrupt.

The ISR invoked due to the timer generated interrupt increments an interrupt
counter and sets a global flag indicating the interrupt took place and that
software was dispatched to the correct point. The test verifies that the interrupt
occurs, and that no more than one interrupt occurs per major clock cycle.

Console Command: i8254_diag -t 3
Command Options:

• -np: no print option; if specified no P2 connector message is printed

• -lp: prevents timers from being stopped at the end of the test; required before

invoking Test #4.

Timer 0 Loopback Test

This test exercises only timer 0. Timer 0 accepts its clock and gate input from the
P2 loopback connector. In this test, the Timer 0 inputs on the P2 connector can
be driven by a master Alpha VME board running test 3 with -lp specified on the
command line. See Figure 4–1.

This test essentially emulates the slave system found in the Realtime Clock and
Interval Device Driver functional specification.

4–12 Diagnostics

Interval Timer Tests

This test enables only timer 0 as done in test 3 but does not use timer 1 or
timer 2. The clock and gate come from the timers on the master Digital Alpha
VME 4 module. Timer 0 interrupts when the gate is received and its count is
decremented to 0.

Note

A VMEbus P2 loopback connector is required. See Figure 4–1 for a
description of the loopback connections.

Console Command: i8254_diag -t 4
Command Option:

-np: no print option; if specified no P2 connector message is printed

Miscellaneous Note

Test #3 must be invoked, with the -lp option, on the master module prior to
invoking this test.

Timer 2 Interrupt Test

This test exercises timer 2 with the timer interrupt disabled. In the Digital Alpha
VME 4 design, the gate input for timer 2 is always enabled and the clock input is
connected to a 10 MHz (100 ns period) clock source.

Timer 2 is programmed to mode 0, interrupt on terminal count. After the timer is
initially programmed to mode 0 and loaded with a count value, the OUT output is
low and remains low until the internal count value reaches zero. When the count
value reaches zero, OUT output is asserted high and remains high until timer 2
is reprogrammed. The event of OUT transitioning from low to high should set the
timer 2 status bit and not generate a CPU interrupt.

The ISR global flag is checked verifying that the ISR was not invoked. The timer
2 status bit is checked to indicate the interrupt took place.

Console Command: i8254_diag -t 5
Miscellaneous Notes

• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt

status register at address 0x4010) are not directly writable. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don’t Care.

• A read of the interrupt status register at address 0x4014 causes both

interrupt status bits (bits 0 and 1) to be cleared.

Diagnostics 4–13

Interval Timer Tests

• Due to hardware limitations on interrupt detection, the value programmed

into timer 2 must be greater than 2.

• See the Intel 8254 interval timer sheet for more details.

Timer 1 Interrupt Test

This test verifies the interrupt path of timer 1 (periodic RT timer).
Timer 1 is programmed to mode 3, square wave mode. After the timer is initially

programmed to mode 3 and loaded with a count value, the OUT output is low
and remains low until the internal count value reaches zero. When the count
value reaches zero, OUT output is asserted high and remains high until timer 1
is reprogrammed.

A global interrupt count flag is checked verifying whether the interrupt service
routine was invoked.

Console Command: i8254_diag -t 6

4–14 Diagnostics

Interval Timer Tests

Figure 4–1 Loopback Descriptions for Interval Timer Test 3 and 4

Configuration for Interval Timer test 3

To make a loopback for test 3 connect pin C11 to C14. With a second jumper,
connect C12 to C13.

(VMEbus P2 Connector)

row C

B
A

Configuration for Interval Timer test 4 (MASTER/SLAVE Alpha VME)

For test 4, the MASTER signals must be the input for the second Alpha VME
module. Connect pins C11 and C14 of the MASTER to C14 of the SLAVE.
With a second jumper, connect C12 and C13 of the MASTER to C13 of the
SLAVE.

(VMEbus P2 Connector, SLAVE)

row C

B
A

14 13 12 11

14 13

(VMEbus P2 Connector, MASTER)

C
B
A

14 13 12 11

ML013463

Diagnostics 4–15

DECchip 21040 Ethernet Controller Tests

DECchip 21040 Ethernet Controller Tests

These diagnostics verify that the internal and external loopback mechanisms
are properly operating in the DECchip 21040 Ethernet controller chip as well as
performing writes and reads to all configuration registers.

Ethernet Internal Loopback Test

The NI internal loopback test transmits Ethernet packets from the transmit ring
in main memory, loops them back at the MAC layer and returns them to the
receive ring in main memory. No traffic is put on the network cable.

The NI external loopback test transmits Ethernet packets from the transmit ring
in main memory and places them on the network medium (twisted pair cable). It
concurrently listens to the line which carries its own transmissions and returns
them to the receive ring in main memory. Received packets not identified as test
packets are discarded for the duration of the test.

Note

To run the external loopback test, you must use a 10baseT loopback
connector (H4082-AA). The external loopback test does not run if the
device is connected to an open network.

These two tests check the following logic respectively:

• The device’s internal logic up to but not including the Ethernet transmission

logic.

• The on-chip transmit/receive circuitry and the passive external components

that connect to the twisted pair interface.

Console Command

• For internal loopback: niil_diag -t 1

• For external loopback: niil_diag -t 2

Command Option:

-dd: print detailed test information on each pass.

4–16 Diagnostics

DECchip 21040 Ethernet Controller Tests

DECchip 21040 PCI Configuration Register Dump

This test reads the PCI configuration registers of the DECchip 21040 and prints
them to the standard output.

Console Command: nicsr_diag -t 1

DECchip 21040 Control/Status Register Dump

This test reads the CSRs of the DECchip 21040 and prints them to the standard
output.

Console Command: nicsr_diag -t 2

DECchip 21040 Configuration Register Test

This test performs writes and reads to the chip’s configuration registers with data
patterns of all 1s, all 0s, and alternating 1s and 0s. Upon exiting, the test returns
the configuration registers to their initial values.

Console Command: nicsr_diag -t 3
Command Option:

-dd: print detailed test information on each pass.

Miscellaneous Note

This test runs only on power-on.

Diagnostics 4–17

DALLAS DS1386 RAMified Watchdog Timekeeper Tests

DALLAS DS1386 RAMified WatchdogTimekeeper Tests

The DS1386 consists of 32 KB of NVRAM and a realtime clock. This diagnostic
tests each of these features on an individual basis. The diagnostic tests the
DS1386, decoders, and printed circuit board module etch.

The functionality of the watchdog feature is to be tested in a separate diagnostic.
No alarm features are tested, since the alarms are not used.

Tests 1 through 3 exercise the NVRAM. Tests 4 and 5 exercise the realtime clock.

The NVRAM is tested on a page basis; there are 128 pages each containing 256
bytes. The NVRAM, therefore, contains 128 pages. However, the first page has
reserved addresses for the realtime clock registers.

NVRAM March I Test

This test writes, reads, and compares all 32 KB of NVRAM with data patterns
of all 1s, all 0s, alternating 1s and 0s, and shifting 1s and 0s. If the quick verify
option is set (default) only the first location of each page is tested. The no quick
verify option tests every location (32 KB) of the NVRAM.

Note

The contents of the NVRAM are overwritten by this diagnostic and
restored on test completion. If the module is reset during this test, the
NVRAM contents are undefined.

Console Command: ds1386_diag -t 1
Command Options:

• -dd: print detailed test information on each pass.

• -nqv: test every location in NVRAM, default is to test 1 location per 256 byte

page.

Miscellaneous Note

This diagnostic is an extended test.

4–18 Diagnostics

DALLAS DS1386 RAMified Watchdog Timekeeper Tests

NVRAM Address-On-Address Test

The NVRAM locations in the DS1386 are byte wide. Therefore, you do not
have enough room to write the unique address into each corresponding location.
However, this test writes the unique page offset to its corresponding location in
NVRAM.

This test writes, reads, and compares all 32 KB of NVRAM using this unique
page offset for test data. If the quick verify option is set (default) only the first
location of each page is tested. The no quick verify option tests every location (32
KB) of the NVRAM.

Note

The contents of the NVRAM are overwritten by this diagnostic and
restored on test completion. If the module is reset during this test the
NVRAM contents are undefined.

Console Command: ds1386_diag -t 2
Command Options:

• -dd: print detailed test information on each pass.

• -nqv: test every location in NVRAM, default is to test 1 location per 256 byte

page.

Miscellaneous Note

This diagnostic is an extended test.

NVRAM March II Test

This test verifies NVRAM addressing by marching (write, read, and compare) a
0x00 byte value through a field of 0xFF. Each iteration reads the entire 32 KB
for background pattern of 0xFF. If the quick verify option is set (default) only the
first location of each page is tested. The no quick verify, -nqv, option tests every
location (32 KB) of the NVRAM.

Note

The contents of the NVRAM are overwritten by this diagnostic and
restored on test completion. If the module is reset during this test the
NVRAM contents are undefined.

Diagnostics 4–19

DALLAS DS1386 RAMified Watchdog Timekeeper Tests

Console Command: ds1386_diag -t 3
Command Options:

• -dd: print detailed test information on each pass.

• -nqv: test every location in NVRAM, default is to test 1 location per 256 byte

page.

Miscellaneous Note

This diagnostic is an extended test.

TOY Clock Bitwalk Test

This diagnostic does a walking 1, walking 0, and A5 register test on the time-of­year (TOY) clock registers. It also tests the rollover cases associated with keeping
time.

The watchdog reset enable bit in the module control register is set to zero to
ensure that a watchdog expiration does not cause a hardware reset to occur.
Secondly, the contents of the command register is saved and the transfer enable
bit is set to 0 to disable updates to the registers while the diagnostic is in
progress.

The diagnostic bit patterns are then walked through all 14 registers. Next, the
seconds, minutes, hours, day, month, and year registers are programmed such
that the next clock tick rolls over for each of these parameters. The updates to
the registers are started and updated for a three second time period. After the
three second update period, the registers are then examined to verify that each
parameter did indeed roll over to the appropriate value.

The diagnostic cleans up by reenabling the watchdog reset bit in the module
control register and restoring the original contents of the TOY clock command
register.

Note

The current date and time has to be reset after invoking this diagnostic
test since approximately 3 seconds of time is lost for each pass.

4–20 Diagnostics

DALLAS DS1386 RAMified Watchdog Timekeeper Tests

Console Command: ds1386_diag -t 4
Command Option:

-dd: print detailed test information on each pass.

Miscellaneous Note

This diagnostic is an extended test.

TOY Clock Time Advancement Test

This diagnostic is a power-on diagnostic. It verifies that the TOY clock registers
are advancing with clock ticks.

The test reads the current value of the seconds register. Then the test sleeps for

1.2 seconds and reads the seconds register again expecting it to have incremented
with the exception of the rollover case. The rollover case is where the seconds
register advanced from 59 to 0. If the rollover case is encountered, the test sleeps
for another second and reads the register again. This is repeated four times.

Console Command: ds1386_diag -t 5
Command Option:

-dd: print detailed test information on each pass.

Miscellaneous Note

This diagnostic is a POST diagnostic.

Diagnostics 4–21

Local Area Network Address ROM Test

Local Area Network Address ROM Test

This diagnostic tests the integrity of the Local Area Network (LAN) address
ROM, decoders, and printed circuit board module etch. The LAN address ROM
contains the Ethernet station address of the module.

LAN Address ROM Dump

This diagnostic dumps the contents of the 32 octets within the LAN address ROM
to the screen. No verification of the data is performed.

Console Command: enet_diag -t 1
Command Options:

• -dd: enables printing LAN address ROM to screen

• -np: no print, if specified, LAN address ROM is not printed to screen

Miscellaneous Notes

• The LAN address ROM octets must be read by using longword aligned byte

accesses.

• This diagnostic is an extended test.

LAN Address ROM Verification Test

This test verifies the format of the data in the LAN address ROM. It verifies
that the octets are ordered appropriately and that the checksums are correctly
calculated based on the LAN address.

Console Command: enet_diag -t 2
Command Option:

-dd: enables printing LAN ROM address to screen

Miscellaneous Notes

• The LAN address ROM octets must be read by using longword aligned byte

accesses.

• This test is considered a POST diagnostic.

4–22 Diagnostics