DEC 21171 Technical Reference Manual

DECchip21171CoreLogicChipset
TechnicalReferenceManual

Order Number: EC–QE18B–TE

Revision/Update Information: Preliminary—This document supersedes

the DECchip 21171 Core Logic

Chipset Technical Reference Manual

(EC–QE18A–TE).

Digital Equipment Corporation
Maynard, Massachusetts

September 1995

While Digital believes the information in this publication is correct as of the date of publication,
it is subject to change without notice.

Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor
do the descriptions contained in this publication imply granting of licenses to make, use, or sell
equipment or software in accordance with the description.

© Digital Equipment Corporation 1995. All rights reserved.
Printed in U.S.A.

DEC, DECchip, Digital, Digital Semiconductor, OpenVMS, VAX DOCUMENT, and the
DIGITAL logo are trademarks of Digital Equipment Corporation.

Digital Semiconductor is a Digital Equipment Corporation business.

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Windows NT is a trademark of Microsoft Corporation.

All other trademarks and registered trademarks are the property of their respective owners.

This document was prepared using VAX DOCUMENT Version 2.1.

Contents

Preface ..................................................... xiii

1 DECchip 21171 Core Logic Chipset Overview

1.1 Features . ........................................... 1–1

1.2 System Overview . . ................................... 1–2

1.2.1 DECchip 21171 Core Logic Chipset Microarchitecture ...... 1–4

1.3 CIA Microarchitecture ................................. 1–4

1.4 DSW Microarchitecture ................................ 1–6

1.5 System Clocks ....................................... 1–7

1.6 DECchip 21171 Core Logic Chipset Characteristics . .......... 1–8

Part I DECchip 21171-CA (CIA) Information

2 DECchip 21171-CA Pin Descriptions

2.1 DECchip 21171-CA Pin List . . ........................... 2–1

2.2 DECchip 21171-CA Signal Descriptions . ................... 2–3

2.2.1 sysBus Signals . ................................... 2–3

2.2.2 PCI Local Bus Signals . . ........................... 2–4

2.2.3 IOD Bus Signals .................................. 2–7

2.2.4 Memory Control Signals . ........................... 2–10

2.2.5 Phase-Locked Loop Signals .......................... 2–11

2.2.6 Miscellaneous Power Signals ......................... 2–11

2.2.7 Miscellaneous Signals . . . ........................... 2–12

2.2.8 Reserved Signals .................................. 2–12

2.2.9 DECchip 21171-CA Pin Name List (Alphabetic) . .......... 2–13

2.2.10 DECchip 21171-CA Pin Assignment List (Alphanumeric) . . . 2–19

2.3 DECchip 21171-CA Mechanical Specifications ............... 2–24

iii

3 DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description ........... 3–1

3.1.1 System Functional Units ............................ 3–1

3.1.2 CIA Functional Units ............................... 3–3

3.1.2.1 21164 Instruction and Address Logic ................ 3–4

3.1.2.2 PCI Data Path Logic ............................ 3–4

3.1.2.3 Memory Logic . ................................ 3–6

3.1.2.4 I/O Address Logic ............................... 3–6

3.1.2.5 DMA Address Logic ............................. 3–7

3.2 CIA Transactions ..................................... 3–7

3.2.1 21164 Read Miss Transaction. ........................ 3–8

3.2.2 21164 Read Miss with Victim Transaction ............... 3–8

3.2.3 21164 Read Transaction to Noncacheable Space . . . ....... 3–9

3.2.4 21164 Write Transaction to Noncacheable Space . . . ....... 3–11

3.2.5 DMA Transactions . ................................ 3–12

3.2.6 DMA Read Transaction ............................. 3–14

3.2.7 DMA Read Transaction (Prefetch) ..................... 3–14

3.2.8 DMA Write Transaction ............................. 3–15

3.3 System Data Coherency Issues . . ........................ 3–16

3.3.1 Basic Properties of the System........................ 3–16

3.3.2 Post and Run I/O Write Data Coherency ................ 3–17

3.4 CIA Memory ras_h, cas_h, and Address Operation . . . ....... 3–18

3.4.1 Traditional Mapping of 21164 Address to Memory

Address . ........................................ 3–18

3.4.2 CIA Mapping of 21164 Address to Memory Address ....... 3–20

3.5 MB and LOCK Instructions ............................. 3–25

3.5.1 MB Instruction .................................... 3–25

3.5.2 LOCK Instruction . ................................ 3–25

3.5.3 Locks to Uncached Space ............................ 3–27

4 DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers ............................ 4–1

4.1.1 DECchip 21171-CA General Registers . . ................ 4–2

4.1.2 DECchip 21171-CA Diagnostic Registers ................ 4–2

4.1.3 DECchip 21171-CA Performance Monitor Registers . ....... 4–3

4.1.4 DECchip 21171-CA Error Registers .................... 4–3

4.1.5 DECchip 21171-CA System Configuration Registers ....... 4–4

4.1.6 DECchip 21171-CA PCI Address and Scatter-Gather

Registers ........................................ 4–5

4.1.7 DECchip 21171-CA Address Translation Registers . ....... 4–6

4.2 DECchip 21171-CA General Registers ..................... 4–8

iv

4.2.1 CIA Revision Register (CIA_REV) . . ................... 4–8

4.2.2 PCI Latency Register (PCI_LAT) . . . ................... 4–9

4.2.3 CIA Control Register (CIA_CTRL) . . ................... 4–10

4.2.4 Hardware Address Extension Memory Register

(HAE_MEM) . . ................................... 4–14

4.2.5 Hardware Address Extension I/O Register (HAE_IO) ...... 4–16

4.2.6 Configuration Register (CFG)......................... 4–17

4.2.7 CIA Acknowledgment Enable Register (CACK_EN) ........ 4–18

4.3 DECchip 21171-CA Diagnostic Registers ................... 4–19

4.3.1 CIA Diagnostic Control Register (CIA_DIAG) . . .......... 4–19

4.3.2 Diagnostic Check Register (DIAG_CHECK) .............. 4–21

4.4 DECchip 21171-CA Performance Monitor Registers . .......... 4–22

4.4.1 Performance Monitor Register (PERF_MONITOR) ........ 4–22

4.4.2 Performance Control Register (PERF_CONTROL) ......... 4–23

4.5 DECchip 21171-CA Error Registers ....................... 4–26

4.5.1 CPU Error Information Register 0 (CPU_ERR0) .......... 4–26

4.5.2 CPU Error Information Register 1 (CPU_ERR1) .......... 4–27

4.5.3 CIA Error Register (CIA_ERR) ....................... 4–28

4.5.4 CIA Status Register (CIA_STAT) . . . ................... 4–32

4.5.5 CIA Error Mask Register (ERR_MASK)................. 4–34

4.5.6 CIA Syndrome Register (CIA_SYN) . ................... 4–35

4.5.7 CIA Memory Port Status Register 0 (MEM_ERR0) ........ 4–37

4.5.8 CIA Memory Port Status Register 1 (MEM_ERR1) ........ 4–38

4.5.9 PCI Error Register 0 (PCI_ERR0) . . ................... 4–41

4.5.10 PCI Error Register 1 (PCI_ERR1) . . ................... 4–44

4.5.11 PCI Error Register 2 (PCI_ERR2) . . ................... 4–45

4.6 DECchip 21171-CA System Configuration Registers .......... 4–46

4.6.1 Memory Configuration Register (MCR) ................. 4–46

4.6.2 Memory Base Address Register n (MBAn)............... 4–49

4.6.3 Memory Timing Information Register n (TMGn).......... 4–52

4.7 DECchip 21171-CA PCI Address and Scatter-Gather

Registers ........................................... 4–60

4.7.1 Scatter-Gather Translation Buffer Invalidate Register

(TBIA) .......................................... 4–60

4.7.2 Window Base Register (Wn_BASE) . ................... 4–61

4.7.3 Window Mask Register n (Wn_MASK) .................. 4–63

4.7.4 Translated Base Register n (Tn_BASE) ................. 4–65

4.7.5 Window Base DAC Register (W_DAC) .................. 4–68

4.8 DECchip 21171-CA Address Translation Registers . .......... 4–69

4.8.1 Lockable Translation Buffer Tag n Registers (LTB_TAGn). . . 4–69

4.8.2 Translation Buffer Tag n Register (TB_TAGn)............ 4–70

4.8.3 Translation Buffer m Page n Registers (TBm_PAGEn) ..... 4–72

v

5 DECchip 21171-CA Power-Up and Initialization

5.1 Power-Up . . . ........................................ 5–1

5.2 Internal Reset ....................................... 5–1

5.3 State of Pins on Reset Assertion . ........................ 5–1

5.4 Configuration after Reset Deassertion ..................... 5–3

6 DECchip 21171-CA Address Mapping

6.1 Address Mapping Overview ............................. 6–1

6.1.1 21164 Address Space Configuration Supported by the

CIA ............................................ 6–2

6.1.1.1 21164 Access to Address Space .................... 6–3

6.1.1.2 PCI Access to Address Space ...................... 6–4

6.2 21164 Address Space . . ................................ 6–7

6.2.1 PCI Dense Memory Space . . . ........................ 6–9

6.2.2 PCI Sparse Memory Space . . . ........................ 6–11

6.2.3 PCI Sparse I/O Space ............................... 6–18

6.2.4 PCI Configuration Space ............................ 6–22

6.2.4.1 Device Select (IDSEL) . . . ........................ 6–25

6.2.4.2 PCI Special/Interrupt Acknowledge Cycles ........... 6–28

6.2.4.3 Hardware-Specific and Miscellaneous Register Space . . . 6–29

6.3 PCI to Physical Memory Addressing ...................... 6–29

6.3.1 Address Mapping Windows . . ........................ 6–29

6.3.1.1 PCI Device Address Space ........................ 6–31

6.3.1.2 Address Mapping Example ....................... 6–32

6.3.2 Direct Mapped Addressing . . . ........................ 6–34

6.3.3 Scatter-Gather Addressing . . . ........................ 6–35

6.3.3.1 Scatter-Gather Translation Lookaside Buffer (TLB) ..... 6–37

6.3.3.1.1 Scatter-Gather TLB Hit Process ................ 6–39

6.3.3.1.2 Scatter-Gather TLB Miss Process ............... 6–39

6.3.4 Suggested Use of a PCI Window ...................... 6–41

6.3.4.1 Peripheral Component Architecture Compatibility

Addressing and Holes . . . ........................ 6–42

6.3.4.2 Memory Chip Select Signal mem_cs_l .............. 6–42

vi

Part II DECchip 21171-BA (DSW) Information

7 DECchip 21171-BA Pin Descriptions

7.1 DECchip 21171-BA Pin List . . ........................... 7–1

7.2 DECchip 21171-BA Signal Descriptions . ................... 7–2

7.2.1 sysBus Signals . ................................... 7–3

7.2.2 IOD Bus Signals .................................. 7–3

7.2.3 MEMDATA Bus Signals . . ........................... 7–6

7.2.4 Phase-Locked Loop Signals .......................... 7–6

7.2.5 Miscellaneous Signals . . . ........................... 7–7

7.2.6 DECchip 21171-BA Pin Name List (Alphabetic) . .......... 7–9

7.2.7 DECchip 21171-BA Pin Assignment List (Numeric) ........ 7–12

7.3 DECchip 21171-BA Mechanical Specifications ............... 7–16

8 DECchip 21171-BA Architecture Overview

8.1 DSW Functional Units ................................. 8–1

8.1.1 Victim Buffer—64 Bytes . . ........................... 8–3

8.1.2 I/O Read Buffer (IOR)—32 Bytes . . . ................... 8–3

8.1.3 I/O Write (IOW) Buffers—4 * 32 Bytes ................. 8–4

8.1.4 DMA Buffer Sets .................................. 8–4

8.1.4.1 Flush Buffer ................................... 8–5

8.1.4.2 PCI Buffer . ................................... 8–5

A Technical Support and Ordering Information

A.1 Technical Support . ................................... A–1

A.2 Ordering Digital Semiconductor Products .................. A–1

A.3 Ordering Associated Third-Party Literature ................ A–2

Index

Examples

3–1 21164 and PCI Device Lock Contention ................. 3–26

vii

Figures

1–1 DECchip 21171 Core Logic Chipset System Block

Diagram . ........................................ 1–3

1–2 CIA Block Diagram ................................ 1–5

1–3 DSW Block Diagram ............................... 1–7

2–1 DECchip 21171-CA Package Dimensions ................ 2–25

3–1 System Functional Block Diagram ..................... 3–2

3–2 CIA Functional Block Diagram ....................... 3–3

3–3 Address Space Overview ............................ 3–13

3–4 Traditional Mapping to a Memory Address .............. 3–18

3–5 Traditional Victim Cache to Memory Correspondence ...... 3–19

3–6 Modified Mapping to a Memory Address ................ 3–20

3–7 CIA Victim Cache to Memory Correspondence ............ 3–21

3–8 CIA Mapping to a Memory Address .................... 3–22

3–9 Memory Address Maps for 128-Bit Data Path ............ 3–23

3–10 Memory Address Maps for 256-Bit Data Path ............ 3–24

4–1 CIA Revision Register (87.4000.0080) . . ................ 4–8

4–2 PCI Latency Register (87.4000.00C0) . . . ................ 4–9

4–3 CIA Control Register (87.4000.0100) . . . ................ 4–10

4–4 Hardware Address Extension Memory Register

(87.4000.0400) .................................... 4–14

4–5 Hardware Address Extension I/O Register (87.4000.0440) . . . 4–16

4–6 Configuration Register (87.4000.0480) . . ................ 4–17

4–7 CIA Acknowledgment Enable Register (87.4000.0600) ...... 4–18

4–8 CIA Diagnostic Control Register (87.4000.2000) . . . ....... 4–19

4–9 Diagnostic Check Register (87.4000.3000) ............... 4–21

4–10 Performance Monitor Register (87.4000.4000) ............ 4–22

4–11 Performance Control Register (87.4000.4040) ............ 4–23

4–12 CPU Error Information Register 0 (87.4000.8000) . . ....... 4–26

4–13 CPU Error Information Register 1 (87.4000.8040) . . ....... 4–27

4–14 CIA Error Register (87.4000.8200) ..................... 4–29

4–15 CIA Status Register (87.4000.8240) .................... 4–32

4–16 CIA Error Mask Register (87.4000.8280) ................ 4–34

4–17 CIA Syndrome Register (87.4000.8300) . ................ 4–35

4–18 CIA Memory Port Status Register 0 (87.4000.8400) . ....... 4–37

4–19 CIA Memory Port Status Register 1 (87.4000.8440) . ....... 4–38

4–20 PCI Error Register 0 (87.4000.8800) . . . ................ 4–41

viii

4–21 PCI Error Register 1 (87.4000.8840) ................... 4–44

4–22 PCI Error Register 2 (87.4000.8880) ................... 4–45

4–23 Memory Configuration Register (87.5000.0000) . .......... 4–46

4–24 Memory Base Address Register n ..................... 4–49

4–25 Memory Timing Information Register n ................. 4–52

4–26 Memory Read Timing Sample ........................ 4–55

4–27 Memory Write Timing Sample ........................ 4–56

4–28 Scatter-Gather TBIA Register (87.6000.0100) . . .......... 4–60

4–29 Window Base Register n ............................ 4–61

4–30 Window Mask Register n ............................ 4–63

4–31 Translated Base Register n .......................... 4–65

4–32 Window Base DAC Register (87.6000.07C0) .............. 4–68

4–33 Lockable Translation Buffer Tag n Registers . . . .......... 4–69

4–34 Translation Buffer Tag n Registers . ................... 4–71

4–35 Translation Buffer m Page n Registers ................. 4–73

6–1 21164 Address Space ............................... 6–1

6–2 21164 Address Space Configuration . ................... 6–2

6–3 Address Space Overview . ........................... 6–3

6–4 Address Mapping Overview .......................... 6–4

6–5 21164 and DMA Read and Write Transactions. . .......... 6–6

6–6 Dense Space Address Generation . . . ................... 6–10

6–7 PCI Memory Sparse Space Address Generation

(Region 1) ........................................ 6–15

6–8 PCI Memory Sparse Space Address Generation

(Region 2) ........................................ 6–16

6–9 PCI Memory Sparse Space Address Generation

(Region 3) ........................................ 6–17

6–10 PCI Sparse I/O Space Address Translation (Region A) ...... 6–18

6–11 PCI Sparse I/O Space Address Translation (Region B) ...... 6–19

6–12 PCI Configuration Space Definition . ................... 6–23

6–13 21164 System PCI Bus Hierarchy Example .............. 6–27

6–14 PCI DMA Address Example .......................... 6–32

6–15 PCI Target Window Compare ......................... 6–33

6–16 Direct Mapped Translation .......................... 6–34

6–17 Scatter-Gather PTE Format .......................... 6–36

6–18 Scatter-Gather Associative TLB ....................... 6–38

6–19 Scatter-Gather Map Translation . . . ................... 6–40

ix

6–20 Default PCI Window Allocation ....................... 6–41

6–21 Memory Chip Select Signal (mem_cs_l) Decode Area ...... 6–44

6–22 Memory Chip Select Signal (mem_cs_l) Logic ............ 6–45

7–1 DECchip 21171-BA Package Dimensions ................ 7–16

8–1 DSW Functional Block Diagram ...................... 8–2

Tables

1 Register Field Notation ............................. xv

2 Unnamed Register Field Notation ..................... xvi

3 Data Units ....................................... xvii

1–1 DECchip 21171-CA (CIA) Chip Characteristics ........... 1–8

1–2 DECchip 21171-BA (DSW) Chip Characteristics . . . ....... 1–8

2–1 DECchip 21171-CA Pin List . . ........................ 2–1

2–2 ioc_h<6:0> Control Functions ........................ 2–7

2–3 cmc_h<8:0> Control Functions ....................... 2–8

2–4 Var Encodings for CMC Command 0 . . . ................ 2–9

2–5 Var Encodings for CMC Commands 0, 8, A, and B . ....... 2–9

2–6 Var Encodings for CMC Commands 2, 3, 4, 5, 6, and 7 ..... 2–9

2–7 DSW Operating Modes .............................. 2–12

2–8 DECchip 21171-CA Pin Names (Alphabetic) ............. 2–13

2–9 DECchip 21171-CA Pin Assignment (Alphanumeric) ....... 2–19

2–10 DECchip 21171-CA Package Dimensions ................ 2–26

3–1 PCI Commands Recognized by the CIA . ................ 3–5

3–2 CIA Prefetch Strategy .............................. 3–14

4–1 DECchip 21171-CA General Registers . . ................ 4–2

4–2 DECchip 21171-CA Diagnostic Registers ................ 4–2

4–3 DECchip 21171-CA Performance Monitor Registers . ....... 4–3

4–4 DECchip 21171-CA Error Registers .................... 4–3

4–5 DECchip 21171-CA System Configuration Registers ....... 4–4

4–6 DECchip 21171-CA PCI Address and Scatter-Gather

Registers ........................................ 4–5

4–7 DECchip 21171-CA Address Translation Registers . ....... 4–6

4–8 CIA Revision Register .............................. 4–8

4–9 PCI Latency Register............................... 4–9

4–10 CIA Control Register ............................... 4–11

4–11 CPU and I/O Flush Request. . ........................ 4–13

x

4–12 PCI READ Prefetch Algorithm ........................ 4–13

4–13 HAE_MEM High-Order Sparse-Space Bits .............. 4–15

4–14 Hardware Address Extension Memory Register . .......... 4–15

4–15 Hardware Address Extension I/O Register ............... 4–16

4–16 Configuration Register . . . ........................... 4–17

4–17 CIA Acknowledgment Enable Register .................. 4–18

4–18 CIA Diagnostic Control Register . . . ................... 4–19

4–19 Diagnostic Check Register ........................... 4–21

4–20 Performance Monitor Register ........................ 4–22

4–21 Performance Control Register ........................ 4–23

4–22 PERF_CONTROL Low/High Select Encodings . . .......... 4–24

4–23 CPU Error Information Register 0 . . ................... 4–26

4–24 CPU Error Information Register 1 . . ................... 4–27

4–25 CIA Error Register ................................. 4–30

4–26 CIA Status Register ................................ 4–32

4–27 CIA Error Mask Register . ........................... 4–34

4–28 CIA Syndrome Register . . ........................... 4–36

4–29 ECC Syndromes for Single-Bit Errors .................. 4–36

4–30 CIA Memory Port Status Register 0. ................... 4–37

4–31 CIA Memory Port Status Register 1. ................... 4–38

4–32 Memory Port Command Field (MEM_PORT_CMD) ........ 4–39

4–33 Memory Sequencer State Field (SEQ_ST) ............... 4–39

4–34 Encoded Set Select Field (SET_SEL_ENC) .............. 4–40

4–35 PCI Error Register 0 ............................... 4–42

4–36 PCI Error Register 1 ............................... 4–44

4–37 PCI Error Register 2 ............................... 4–45

4–38 Memory Configuration Register ....................... 4–47

4–39 Memory Base Address Register n ..................... 4–50

4–40 Memory Timing Information Register n ................. 4–53

4–41 Memory Timing Parameters, Encoded Values . . .......... 4–54

4–42 Memory Control Signals Timing Limits ................. 4–57

4–43 Memory Address Timing Limits ....................... 4–58

4–44 Memory Data Timing Limits ......................... 4–59

4–45 Scatter-Gather Translation Buffer Invalidate Register . . . . . 4–60

4–46 Window Base Register n ............................ 4–62

4–47 Window Mask Register n ............................ 4–64

4–48 Translated Base Register n .......................... 4–65

xi

4–49 PCI Address Translation—Scatter-Gather Mapping

Enabled . ........................................ 4–66

4–50 PCI Address Translation—Scatter-Gather Mapping

Disabled . ........................................ 4–67

4–51 Window Base DAC Register . . ........................ 4–68

4–52 Lockable Translation Buffer Tag n Registers ............. 4–70

4–53 Translation Buffer Tag n Registers .................... 4–71

4–54 Translation Buffer m Page n Registers . ................ 4–73

5–1 CIA Pin State During Reset . . ........................ 5–2

5–2 CIA Pin State After Reset . . . ........................ 5–3

5–3 Registers Initialized by SROM Code . . . ................ 5–4

6–1 21164 Address Space ............................... 6–7

6–2 int4_valid_h<3:0> and addr_h<4:3> for Sparse Space Write

Transactions...................................... 6–13

6–3 PCI Memory Sparse Space Read/Write Encodings . . ....... 6–14

6–4 HAE_MEM High Order Sparse Space Bits .............. 6–15

6–5 PCI I/O Sparse Space Read/Write Encodings ............. 6–20

6–6 CIA PCI and (E)ISA I/O Map . ........................ 6–21

6–7 PCI Configuration Space Read/Write Encodings . . . ....... 6–24

6–8 Generating IDSEL Pin Signals ....................... 6–25

6–9 Primary 64-Bit PCI IDSEL Mapping . . . ................ 6–28

6–10 Hardware-Specific Register Address Space .............. 6–29

6–11 PCI Target Window MASK Register (Wn_MASK) . . ....... 6–30

6–12 Direct-Mapped PCI Target Address Translation........... 6–35

6–13 Scatter-Gather Mapped PCI Target Address Translation .... 6–37

6–14 PCI Window Power-Up Configuration . . ................ 6–42

7–1 DECchip 21171-BA Pin List . . ........................ 7–1

7–2 ioc_h<6:0> Control Functions ........................ 7–4

7–3 cmc_h<8:0> Control Functions ....................... 7–4

7–4 Var Encodings for CMC Command 0 . . . ................ 7–5

7–5 Var Encodings for CMC Commands 0, 8, A, and B . ....... 7–5

7–6 Var Encodings for CMC Commands 2, 3, 4, 5, 6, and 7 ..... 7–6

7–7 IOD Bus and MEMDATA Bus Data Width Selection ....... 7–7

7–8 DSW Operating Modes .............................. 7–8

7–9 DECchip 21171-BA Pin Assignment List (Alphabetic) ...... 7–9

7–10 DECchip 21171-BA Pin Assignment (Numeric) ........... 7–13

7–11 DECchip 21171-BA Package Dimensions ................ 7–18

xii

Purpose and Audience

The document is a support and reference document for engineers using the
Alpha 21164 microprocessor to design uniprocessor systems.

Organization

This document contains the following parts, chapters, and appendix:

• Chapter 1, DECchip 21171 Core Logic Chipset Overview, provides an
overview of the DECchip 21171-AA core logic chipset features.

Part I—DECchip 21171-CA (CIA) Information

• Chapter 2, DECchip 21171-CA Pin Descriptions, provides control, I/O
interface, and address chip (CIA) pin descriptions.

• Chapter 3, DECchip 21171-CA Architecture Overview, provides the CIA
architecture overview.

• Chapter 4, DECchip 21171-CA Control and Status Registers, provides a
programmer’s reference for control and status registers (CSRs).

• Chapter 5, DECchip 21171-CA Power-Up and Initialization, provides
information on the behavior of CIA during power-up and initialization.

Preface

• Chapter 6, DECchip 21171-CA Address Mapping, provides information on
system address mapping.

Part II—DECchip 21171-BA (DSW) Information

• Chapter 7, DECchip 21171-BA Pin Descriptions, provides data switch chip
(DSW) pin descriptions.

• Chapter 8, DECchip 21171-BA Architecture Overview, provides an overview
of the DSW architecture.

xiii

• Appendix A, Technical and Ordering Information, provides information
on how to obtain technical support and how to order products and
documentation.

Document Conventions

This section describes the abbreviation and notation conventions used
throughout this guide.

Numbering

All numbers are decimal or hexadecimal unless otherwise specified. In cases
of ambiguity, a subscript indicates the radix of nondecimal numbers. For
example, 19 is decimal, but 1916and 19A are hexadecimal.

UNPREDICTABLE and UNDEFINED Definitions

Results specified as UNPREDICTABLE may vary from moment to moment,
implementation to implementation, and instruction to instruction within
implementations. Software can never depend on results specified as
UNPREDICTABLE.

Operations specified as UNDEFINED may vary from moment to moment,
implementation to implementation, and instruction to instruction within
implementations. The operation may vary from nothing to stopping system
operation. UNDEFINED operations must not cause the processor to hang, that
is, reach a state from which there is no transition to a normal state where the
machine can execute instructions.

xiv

Note the distinction between results and operations. Nonprivileged software
cannot invoke UNDEFINED operations.

Ranges

Ranges are specified by a pair of numbers separated by two periods (..) and are
inclusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3,
and 4.

Extents

Extents are specified by a pair of numbers in angle brackets (<>) separated by
a ( :) and are inclusive. For example, bits <7:3> specifies an extent including
bits 7, 6, 5, 4, and 3.

Must Be Zero

Fields specified as must be zero (MBZ) must never be filled by software with a
non-zero value. If the processor encounters a non-zero value in a field specified
as MBZ, a reserved operand exception occurs.

Should Be Zero

Fields specified as should be zero (SBZ) should be filled by software with a zero
value. These fields may be used at some future time. Non-zero values in SBZ
fields produce UNPREDICTABLE results.

Register and Memory Figures

Register figures have bit and field position numbering starting at the right
(low-order) and increasing to the left (high-order). Memory figures have
addresses starting at the top and increasing toward the bottom.

Register Field Notation

Register figures and tabulated descriptions have a mnemonic that indicates the
bit or field characteristic as described in Table 1.

Table 1 Register Field Notation

Notation Description

RW A read-write bit or field. The value can be read and written by software,

RO A read-only bit or field. The value can be read by software, microcode,

WO A write-only bit. The value can be written by software and microcode.

WZ A write-only bit or field. The value can be written by software or

WC A write-to-clear bit. The value can be read by software or microcode.

RC A read-to-clear field. The bit is written by hardware and remains

microcode, or hardware.

or hardware. The bit is written by hardware. Software or microcode
write operations to this bit are ignored.

The bit is read by hardware. Read operations to this bit by software or
microcode return an UNPREDICTABLE result.

microcode. The bit is read by hardware. Read operations to this bit by
software or microcode return a zero.

Software or microcode write operations with a 1 to this bit cause the bit
to be cleared by hardware. Software or microcode write operations with
a 0 to this bit do not modify the state of the bit.

unchanged until the bit is read. The bit can be read by software or
microcode, at which point hardware can write a new value into the
field.

xv

Other register fields that are unnamed may be labeled as specified in Table 2.

Table 2 Unnamed Register Field Notation

Notation Description

0 A 0 in a bit position indicates a register bit that is read as a 0 and is

1 A 1 in a bit position indicates a register bit that is read as a 1 and is

x An x in a bit position indicates a register bit that does not exist in

ignored on a write operation.

ignored on a write operation.

hardware. The value is UNPREDICTABLE when read and is ignored
on a write operation.

Bit Notation

Multiple bit fields are shown as extents (see Extents).

Warning

Warning provides information to prevent personal injury.

Caution

Caution indicates potential damage to equipment or data.

Note

Note provides general information that could be helpful.

xvi

Data Units

Table 3 defines the data unit terminology used throughout this manual.

Table 3 Data Units

Term Words Bytes Bits Other

Byte 1 — 8 —
Word 1 2 16 —
Tribyte — 3 24 —
Longword 2 4 32 —
Quadword 4 8 64 —
Octaword 8 16 128 Single read fill; that is, the cache space

Hexword 16 32 256 Cache block, cache line. The space

that can be filled in a single read access.
It takes two read accesses to fill one
Bcache line (see Hexword).

allocated to a single cache block.

Signal Name References

Signal names in text are printed in boldface lowercase. Mixed-case and
uppercase signal naming conventions are ignored. These two examples
illustrate the conventions used in this document:

• MEM_WE_L[1] is shown as mem_we_l<1>.

• TEST_MODE[1] is shown as test_mode_h<1>.

xvii

DECchip 21171 Core Logic Chipset

The DECchip 21171 core logic chipset (21171) is used to support the Alpha
21164 microprocessor (21164) in high-performance uniprocessor systems. The
chipset includes an interface to the 64-bit peripheral component interconnect
(PCI) bus, and associated control and data paths for the 21164, memory, and
backup cache (Bcache). Little discrete logic is needed on the module.

1.1 Features

The DECchip 21171 core logic chipset has the following features.

• Central processing unit—Supports Alpha 21164 microprocessor

• Components

One DECchip 21171-CA chip—The control, I/O interface, and address
chip (CIA) has 383 pins and is in a plastic pin grid array (PPGA)
package.

Four DECchip 21171-BA chips—The data switch chip (DSW) has 208
pins and is in a plastic quad flat pack (PQFP) package.

1

Overview

• Data paths

64-bit, ECC-protected data path between CIA and DSW
128-bit ECC-protected data path between the 21164 and DSW
256-bit ECC-protected memory data path between DSW and memory

• Timing

Supports all 21164 clock frequencies
Supports system clock frequencies up to 33 MHz (PCI clock)
PCI clock, cache, and memory clock period are an integer multiple of

the 21164 clock period

Preliminary Edition—Subject to Change—September 1995 1–1

DECchip 21171 Core Logic Chipset Overview

1.1 Features

• Bcache

Third-level cache for the 21164
Cache size from 2MB to 64MB
Write-back, ECC-protected cache

• Memory

Supports up to 8GB of ECC-protected physical memory
Industry-standard memory array configurations

• High-performance PCI

64-bit multiplexed address and data
64-bit PCI address handling
Scatter-gather map support
No glue logic required to connect PCI-compliant devices

1.2 System Overview

To build a system, such as that shown in Figure 1–1, with the DECchip 21171
core logic chipset, the following additional components are required:

• Alpha 21164 microprocessor

• Bcache

• Memory arrays

• Serial ROM (SROM) (for 21164)

• Circuit to generate input clock for 21164

• Circuit to generate input clock for 21171

• Support logic

PCI interrupt controller
PCI arbiter
Reset logic
Console ROM logic and flash ROM

1–2 Preliminary Edition—Subject to Change—September 1995

DECchip 21171 Core Logic Chipset Overview

1.2 System Overview

• PCI peripheral devices

Figure 1–1 DECchip 21171 Core Logic Chipset System Block Diagram

DECchip 21171

Bcache

Index

Alpha 21164

Microprocessor

SROM

sysBus
Data

sysBus Address
and Command

Core Logic Chipset

Four DECchip

21171-BAs

(Four DSWs)

IOD Bus

DECchip

21171-CA

(CIA)

MEMDATA Bus

Memory

Arrays

Memory Control
(ras, cas, and so on.)

PCI Bus

LJ-04214.AI

The MEMDATA bus provides a 256-bit, ECC-protected data path between the
four data path slices (DSWs) and the memory arrays. Each bit slice (DSW)
connects to 64 bits of the MEMDATA bus.

The input/output data (IOD) bus provides a 64-bit, ECC-protected data path
between the CIA and DSW chips.

The 21164 is connected to the CIA and DSW by the sysBus. The sysBus
contains address, data, and command signal lines. The sysBus is the 21164
interface bus with several additional signals to handle direct memory access
(DMA) transactions through the CIA and DSW.

Systems built with the DECchip 21171 core logic chipset have the capability
to support up to 8GB of memory. The chipset supports the following industry
standard dynamic RAMs (DRAM) in the memory arrays:

1MB336 2MB336
4MB336 8MB336

Preliminary Edition—Subject to Change—September 1995 1–3

DECchip 21171 Core Logic Chipset Overview

1.2 System Overview

1.2.1 DECchip 21171 Core Logic Chipset Microarchitecture

As shown in Figure 1–1, the DECchip 21171 core logic chipset consists of the
CIA and four DSW application-specific integrated circuits (ASICs).

• DECchip 21171-CA (CIA), 383-pin PPGA: Provides control functions to
main memory, and a bridge to the 64-bit PCI bus. In addition, the CIA
provides all control functions for the DSW and part of the I/O data path.

• DECchip 21171-BA (DSW), 208-pin PQFP: A bit slice ASIC (four required),
provides the data path between the 21164, main memory, Bcache, and the
CIA, and part of the I/O data path.

1.3 CIA Microarchitecture

The CIA provides control functions to main memory and the PCI interface. As
shown in Figure 1–2, the CIA is divided into the following major functional
logic blocks.

The instruction and address logic accepts commands from the 21164 and
directs instructions to either the memory port or the I/O port. A 3-entry 21164
instruction queue provides buffering in the event that the memory and I/O
ports are busy. A flush address register is also provided to allow DMA read
and write operations to interrogate a supported Bcache for the most recent
data.

The memory logic provides the row and column addresses for the supported
memory banks and all memory control functions (row address select [ras],
column address select [cas], write-enable, and so on). In addition, the memory
logic provides control signals to the DSW to initiate data transactions to and
from memory.

The I/O address logic handles I/O read and write addresses. The decode
logic extracts the PCI address from the dense or sparse space 21164 address
encoding, generates PCI I/O read or write addresses, and passes them to the
PCI data path logic. The I/O logic can also increment the current address each
data cycle. The incremented address provides a pointer to the next data item
to be transferred to or from the I/O read/write buffers.

A 3-entry I/O address queue is provided together with a single-entry current
address register. These components allow four I/O write operations to be
outstanding. The DSW chip provides four corresponding I/O write data
buffers.

1–4 Preliminary Edition—Subject to Change—September 1995

DECchip 21171 Core Logic Chipset Overview

Figure 1–2 CIA Block Diagram

1.3 CIA Microarchitecture

Address

Path

Alpha 21164

Microprocessor

sysBus

Address/Command
Path

SROM

DECchip 21171-CA (CIA)

DMA Read/Write and

Instruction and

Address Logic

I/O Port

Memory

Logic

Memory
Control
Functions

Memory Arrays IOD Bus

TLB Miss Address

I/O Address

Logic

PCI I/O

Read/Write

Address

DMA Address

PCI Data

Path Logic

(To/From DSW)

Logic

PCI
Bus

LJ-04215.AI

In addition, a bypass path is provided for the special case of a dense space I/O
write transaction with all 32 data bytes valid.

The PCI data path logic provides the interface to the 64-bit PCI, and contains
a portion of the data path control logic. Its major functions are to provide:

• ECC code generation on data transactions to the DSW

• ECC code check and correction on data transactions from the DSW

• I/O read/write addresses to the PCI

• Buffers for all I/O and DMA read and write data transactions

Preliminary Edition—Subject to Change—September 1995 1–5

DECchip 21171 Core Logic Chipset Overview

1.3 CIA Microarchitecture

The DMA address logic converts PCI addresses to 21164 memory address
space. Two address conversion methods are provided:

• A direct path where a base offset is concatenated with the PCI address

• A scatter-gather map, which maps any 8KB PCI page to any 8KB memory
space page

The scatter-gather map translation lookaside buffer (TLB) has eight entries,
with each entry containing four consecutive page table entries (PTEs).

1.4 DSW Microarchitecture

The DSW provides bidirectional data paths between the 21164, the memory
arrays, and the CIA, as shown in Figure 1–3. Four DSW chips, using a bit
slice design, provide the complete data path.

The majority of the DSW logic is comprised of data buffers and multiplexers.
The CIA, using two encoded control fields, directs data flow to and from the
DSW.

The victim buffer has a 64-byte single-entry buffer to contain victim data
during a 21164 memory read transaction that generates a victim. Victim data
is saved in the buffer, allowing the read transaction to fetch read data from
memory and send it to the 21164. Later the victim data is written to memory.

The memory interface contains the data-out register and the data-in register.
The data-out register buffers either 21164 victim data to memory, or DMA
write data to memory. The data-in register accepts 21164 memory read data.
The DSW clocks the register on optimum 15-ns clocks to minimize memory
latency.

The I/O write buffer consists of four 32-byte buffers. The four buffers allow
the chipset to sustain maximum bandwidth on a large copy operation from
memory, through the 21164, to I/O space.

The 32-byte I/O read buffer is provided to assemble the 128-bit data required
by the 21164 from the 64-bit data transfers from the IOD bus (CIA-DSW
interface).

The DMA read/write buffers consist of two identical buffers (DMA buffer 0 and
DMA buffer 1). Each buffer consists of three, 64-byte, single-entry data buffers
used to hold data from memory, Bcache, and the PCI. When a buffer is written,
its data valid bits are asserted, along with data, to the buffer. The valid bits
are used to select appropriate read/write data.

1–6 Preliminary Edition—Subject to Change—September 1995

Figure 1–3 DSW Block Diagram

DECchip 21171 Core Logic Chipset Overview

1.4 DSW Microarchitecture

Alpha 21164

Microprocessor

SROM

Four DECchip 21171-BAs (Four DSWs)

Victim Buffer

21164 Read Data

21164

Interface

I/O

Write Buffer

I/O Write
Data Path

I/O

Read Buffer

IOD Bus Interface

IOD Bus (To/From CIA)

Memory

Arrays

Memory

Interface

DMA

Buffer

LJ-04216.AI

1.5 System Clocks

The 21164 internal clock will be divided by a programmable value to create an
output clock, sys_clk_out1_h, which is used as the system clock. The divisor
must produce a clock between 25 MHz and 33 MHz.

The system designer must supply a circuit to maintain stability of the system
clock and distribute it to PCI devices.

The system clock can be used as a source for a circuit that generates a clock
for (E)ISA devices.

Preliminary Edition—Subject to Change—September 1995 1–7

DECchip 21171 Core Logic Chipset Overview

1.6 DECchip 21171 Core Logic Chipset Characteristics

1.6 DECchip 21171 Core Logic Chipset Characteristics

Table 1–1 and Table 1–2 list the characteristics of the CIA and DSW chips.

Table 1–1 DECchip 21171-CA (CIA) Chip Characteristics

Characteristic Specification

Power supply Vss 0.0 V, Vdd 5 V ±5%
Operating temperature Tj maximum = 70°C (154°F)
Storage temperature range –55°C (–67°F) to 125°C (257°F)
Power dissipation

@Vdd = 5.25 V, Freq = 33 MHz

Table 1–2 DECchip 21171-BA (DSW) Chip Characteristics

Characteristic Specification

2.75 W maximum

Power supply Vss 0.0 V, Vdd 5 V ±5%
Operating temperature Tj maximum = 100°C (212°F)
Storage temperature range –55°C (–67°F) to 125°C (257°F)
Power dissipation

@Vdd = 5.25 V, Freq = 33 MHz

1–8 Preliminary Edition—Subject to Change—September 1995

1.0 W maximum

PartI

DECchip 21171-CA (CIA) Information

Part I contains five chapters that provide information about the DECchip
21171-CA (CIA) chip. The following table lists the topics described in each
chapter:

Chapter Description

2 Pin signals
3 Architecture
4 Control and status registers
5 Power-up and initialization
6 System address mapping

DECchip 21171-CA Pin Descriptions

This chapter provides a description of the DECchip 21171-CA pin signals.

2.1 DECchip 21171-CA Pin List

Table 2–1 lists the pin signals grouped by function. The information in the
Type column identifies a signal as input (I), output (O), bidirectional (B), or
power (P).

Table 2–1 DECchip 21171-CA Pin List

Signal Name Quantity Type Signal Name Quantity Type

sysBus Signals (55 Total)

addr_cmd_par_h 1Baddr_h<39,34:4> 32 B
addr_res_h<1:0> 2Icmd_h<3:0> 4B
addr_bus_req_h 1Bcack_h 1O
dack_h 1Oerror_h
fill_h 1Ofill_id_h 1B
fill_error_h 1Oidle_bc_h 1O
int4_valid_h<3:0> 4Iint_h
tag_dirty_h 1Otag_ctl_par_h 1O
victim_pending 1I— ——

2

1

1

1O

1O

IOD Bus Signals (88 Total)

cmc_h<8:0> 9Oioc_h<6:0> 7O
iod_h<63:0> 64 B iod_e_h<7:0> 8B

1

See Section 2.2.1.

(continued on next page)

Preliminary Edition—Subject to Change—September 1995 2–1

DECchip 21171-CA Pin Descriptions

2.1 DECchip 21171-CAPin List

Table 2–1 (Cont.) DECchip 21171-CA Pin List

Signal Name Quantity Type Signal Name Quantity Type

Memory Control Signals (42 Total)

mem_ack_l 1Omem_addr_h<12:0> 13 O
set_sel_h<15:0> 16 O ras_h<3:0> 4O
cas_h<3:0> 4Omem_we_l<1:0> 2O
mem_en_h 1Omem_req_l 1I

PCI Local Bus Signals (88 Total)

ad_h<63:0> 64 B cbe_l<7:0> 8B
par_h 1Bpar64_h 1B
req64_l 1Back64_l 1B
frame_l 1Birdy_l 1B
devsel_l 1Btrdy_l 1B
stop_l 1Bperr_l 1B
serr_l 1Breq_l 1O
rst_l 1Ognt_l 1I
mem_cs_l 1Ilock_l 1I

Phase-Locked Loop Signals (4 Total)

pll_agnd_h 1Opll_clk_h 1I
pll_lp1_h 1Ipll_vss_h 1I
pll_test_h<3:0> 4I— ——

Miscellaneous Power Signals

(4 Total)

aux_vdd_h 1Paux_vss_h 1P
pll_vdd_h 1Ppll_lp2_h 1P

Miscellaneous Signals (8 Total)

count_out_h 1Odebug_h<1:0> 2I
scan_in_h 1Isys_rst_l 1I
test_mode_h<1:0> 2Itest_or_scan_out_h 1O

2–2 Preliminary Edition—Subject to Change—September 1995

(continued on next page)

DECchip 21171-CA Pin Descriptions

2.1 DECchip 21171-CA Pin List

Table 2–1 (Cont.) DECchip 21171-CA Pin List

Signal Name Quantity Type Signal Name Quantity Type

Reserved Signals (2 Total)

gru_ack_h 1Igru_sel_h 1O

Pin Totals

Total input pins:
Total output pins:
Total bidirectional pins:

Total signal pins:

21

72
196
—­289

Total signal pins:
Total PWR5 pins:
Total GND pins:
Total miscellaneous power pins:
Total spare pins:
Total reserved pins:

Total pins:

289

36

51

4
1

2
—­383

2.2 DECchip 21171-CA Signal Descriptions

This section provides a description of the pin function. Signal descriptions are
grouped by function and correspond to the pin list (see Table 2–1).

Note

The Alpha 21164 microprocessor uses the rising edge of
sys_clk_out1_h (clk1R) as a reference when generating and sampling
the system interface signals.

2.2.1 sysBus Signals

The Alpha 21164 Microprocessor Hardware Reference Manual defines and
describes sysBus signals in detail, except for int_h and error_h. Those two
signals are described here.

Preliminary Edition—Subject to Change—September 1995 2–3

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

int_h

The int_h pin is connected to 21164 pin irq<0>. The CIA asserts int_h to
notify the 21164 that the CIA has detected a corrected ECC error.

error_h

The error_h pin is connected to 21164 pin irq<3>. The CIA asserts this
signal line to notify the 21164 that the CIA has detected an error other than a
corrected ECC error.

2.2.2 PCI Local Bus Signals

The PCI local bus signals

ack64_l

Acknowledge 64-bit transfer—Asserted by the device that has decoded its
address as the target of the current access, indicating that the target device is
willing to transfer 64-bit data.

ad_h<63:0>

The 64-bit address and 64 bits of data are multiplexed on these signal lines.
The upper 32 bits (<63:32>) are reserved except for those transfers where
req_64_l is asserted.

cbe_l<7:0>

Bus command and byte enable are multiplexed on the same signal lines.
During an address phase (when using the DAC command and when req_64_l
is aserted) the bus command is transferred on cbe_l<7:0>. During a data
phase these lines carry the byte enable bits, indicating which bytes have
meaningful data.

devsel_l

When asserted, indicates that the asserting device has decoded its address as
the target of the current access. As an input, devsel_l indicates whether any
device on the bus has been selected.

frame_l

The cycle frame signal is asserted by the current master to indicate the
beginning and duration of an access. When frame_l is deasserted, the final
phase of the access has started.

gnt_l

Assertion of gnt_l indicates that access to the bus has been granted. This is a
point-to-point signal. Every master has its own grant line.

2–4 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

irdy_l

Assertion of irdy_l (initiator ready) indicates that the bus master is ready
to complete the current phase of the transaction. Signal irdy_l is used in
conjunction with trdy_l. A data phase is completed on any clock where both
signals are sampled asserted.

lock_l

Assertion of lock_l indicates an atomic operation that may require multiple
transactions to complete. When lock_l is asserted, nonexclusive transactions
may proceed to an address that is not currently locked.

mem_cs_l

The PCI Local Bus Specification does not preclude product-specific function
/performance enhancements by way of sideband signals. A sideband signal
is loosely defined as any signal that is not part of the PCI specification
and connects two or more PCI nodes and has meaning only to these nodes.
Sideband signals lines must not violate PCI local bus specifications.

Signal mem_cs_l is a sideband signal line. It is used by the PCI-to-EISA
bridge to help manage the EISA memory map and peripheral component
architecture (PCA) compatibility holes (see Section 6.3.4.2).

par_h

The par_h signal is used to create even parity across ad_h<31:0> and
cbe_l<3:0>. Signal par_h is stable and valid one clock cycle after the address

phase. Signal par_h remains valid until one clock cycle after the completion of
the current data phase. The master asserts par_h for address and write data
phases; the target asserts par_h for read data phases.

par64_h

The par64_h signal is used to create even parity across ad_h<63:32> and
cbe_l<7:4>. Signal par64_h is stable and valid one clock cycle after the

address phase. Signal par64_h remains valid until one clock cycle after the
completion of the current data phase. The master asserts par64_h for address
and write data phases; the target asserts par64_h for read data phases.

perr_l

The perr_l signal (parity error) is used to report data parity errors that
occur during all PCI transactions except a special cycle. Signal perr_l is a
tristate signal line that must be asserted by the data-receiving node two cycles
after data with bad parity is detected. Signal perr_l must be asserted for a
minimum of one clock cycle for each phase during which bad data parity is
detected. Signal perr_l, like all sustained tristate signals, must be asserted
high for at least one cycle before being returned from asserted to the tristate
condition.

Preliminary Edition—Subject to Change—September 1995 2–5

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

req_l

Assertion of the req_l signal line (request) indicates to the arbiter that this
node wants to use the PCI bus. Every master node has its own req_l pin.

req64_l

The current bus master asserts req64_l (request 64-bit transfer), indicating
that it wants to transfer data by using 64 bits. Signal req64_l has the same
timing as frame_l. Signal req64_l is asserted low by the system reset signal.
Nodes connected to the 64-bit PCI bus extension will see the line asserted low.
Those nodes not connected to the 64-bit PCI bus extension will see the signal
asserted high by a pull-up device.

rst_l

The rst_l signal line (reset) is used to bring PCI-specific registers, sequencers,
and signals to a consistent state. When rst_l is asserted, all PCI output pins
must be driven to their benign state, usually tristated. Although the signal is
asynchronous, deassertion must be a clean, bounce-free edge.

serr_l

The serr_l pin (system error) is used to report address parity errors, data
parity errors on the special cycles command, or any other system error where
the result will be catastrophic. If a node does not want a nonexistent memory
(NMI) error to be generated, a different reporting mechanism is required.
serr_l is an open-drain signal line and is asserted for a minimum of one clock
cycle by the node reporting the error.

stop_l

The stop_l pin indicates that the current target is requesting that the master
stop the current transaction.

trdy_l

When asserted, the trdy_l (target ready) pin indicates the target node’s
ability to complete the current phase of the transaction. Signal trdy_l is
used in conjunction with irdy_l. A data phase is completed on any clock
assertion where both trdy_l and irdy_l are sampled asserted. During a read
transaction, trdy_l indicates that valid data is present on ad<31:0>. During
a write transaction, trdy_l indicates that the target is ready to accept data.
Wait cycles are inserted until both trdy_l and irdy_l are asserted together.

2–6 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

2.2.3 IOD Bus Signals

This section provides a description of the IOD bus signals.

iod_h<63:0>

The iod_h<63:0> signals carry data between the CIA and DSW on the IOD
bus.

iod_e_h<7:0>

The iod_e_h<7:0> signals carry ECC between the CIA and DSW on the IOD
bus. All ECC generation and detection is performed in the 21164 and CIA.

ioc_h<6:0>

The ioc_h<6:0> signals allow the CIA to control data flow on the IOD bus. The
data transfers are between memory and the PCI bus. CIA control is encoded
as shown in Table 2–2.

Table 2–2 ioc_h<6:0> Control Functions

ioc_h

<6:4>

000 Buffer n x x x Clear valid bits in PCI buffer n.
001xxxxLoad the LW register (Reserved).
010 Buffer n Adr m2 Adr m1 Adr m0 Write PCI buffer n, adr m.
011 Mask3 Mask2 Mask1 Mask0 Write IOR (QW mask).
100 Buffer n Adr m2 Adr m1 Adr m0 Read DMA buffer n, adr m.
101 Buffer n1 Buffer n0 Adr m1 Adr m0 Read IOW buffer n, adr m.
110 Buffer n1

111 Mask3 Mask2 Mask1 Mask0 Start IOW (buffer mask).

ioc_h

<3>

Buffer n

ioc_h

<2>

Buffer n0
Adr m2

ioc_h

<1>

Adr m1 Adr m0 Read buffer (IOW or DMA) low

ioc_h

<0> Function

longword.

Preliminary Edition—Subject to Change—September 1995 2–7

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

cmc_h<8:0>

The cmc_h<8:0> signal lines control flow of data between the 21164 and the
memory arrays. They also start and stop loading of the free-running buffers
(victim, flush, IOW buffers) in the DSW. In Table 2–3, A5 and A4 are address
bits. The Var field encodes the transaction being performed as shown in
Table 2–4, Table 2–5, and Table 2–6.

Table 2–3 cmc_h<8:0> Control Functions

cmc_h

<8:5>

0000 Var 4
0010 x A4

0011 x A4 x Var 1 Var 0 Move IOR buffer data to
0100 A5
0101 A5 A4 Delay Var 1 Var 0 Move memory data to
0110 A5 A4 Delay Stop

0111 A5 A4 Delay Stop

1000 A5 A4 Var 2 Var 1 Var 0 Write victim buffer to
1010 A5 A4 Var 2 Var 1 Var 0 Write DMA0 buffer to
1011 A5 A4 Var 2 Var 1 Var 0 Write DMA1 buffer to

cmc_h

<4>

2

cmc_h

<3>

1

Var 3 Var 2 Var 1 Var 0 Start/stop the buffer.

2

cmc_h

<2>

cmc_h

<1>

cmc_h

<0> Function

Delay Var 1 Var 0 Move fill data from

memory to 21164.

21164.

A4 Delay Var 1 Var 0 Move memory data to

memory buffer 0.
memory buffer 1.

IOWn1

Stop
IOWn0

Move memory data to
memory buffer 0, stop
IOW buffer n.

IOWn1

Stop
IOWn0

Move memory data to
memory buffer 1, stop
IOW buffer n.

memory.
memory.
memory.

1

The variable field encodes the transaction being performed. See Table 2–4, Table 2–5, and Table 2–6.

2

A5 and A4 are address bits.

2–8 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

Table 2–4 Var Encodings for CMC Command 0

Var<4:3> Function

00 None.
01 Start victim.
10 Start flush buffer 0 and clear PCI 0 valid bits.
11 Start flush buffer 1 and clear PCI 0 valid bits.

Table 2–5 Var Encodings for CMC Commands 0, 8, A, and B

Var<2:0> Function

000 None.
001 Stop victim.
010 Stop flush buffer 0.
011 Stop flush buffer 1.
100 Stop IOW 0.
101 Stop IOW 1.
110 Stop IOW 2.
111 Stop IOW 3.

Table 2–6 Var Encodings for CMC Commands 2, 3, 4, 5, 6, and 7

Var<1:0> Function

00 None.
01 Stop victim.
10 Stop flush buffer 0.
11 Stop flush buffer 1.

Preliminary Edition—Subject to Change—September 1995 2–9

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

2.2.4 Memory Control Signals

This section provides a description of the memory control signals.

cas_h<3:0>

The cas_h<3:0> signal lines select the column address in the memory arrays.

mem_ack_l

The mem_ack_l PCI sideband signal line is asserted by the CIA when it has
cleared the transaction path in preparation to receive a transaction from the
PCI-to-EISA bridge. See mem_req_l.

mem_addr_h<12:0>

The mem_addr_h<12:0> signal lines carry the memory array address.

mem_en_h

The mem_en_h signal line enables operation of the memory arrays.

mem_req_l

The mem_req_l signal line is asserted by the PCI-to-EISA bridge to notify
the CIA that it has a transaction pending. The CIA completes all transactions
in progress and then asserts mem_ack_l to the PCI-to-EISA bridge. The
PCI-to-EISA bridge then starts the transaction. See mem_ack_l.

The PCI-to-EISA bridge set can be made using these two chips:

• Intel 82374EB EISA System Component (ESC)

• Intel 82375EB PCI-to-EISA Bridge (PCEB)
The PCEB allows a certain time period for a PCI transaction to complete. The

mem_req_l and mem_ack_l PCI sideband signal lines are used to ensure that
that the CIA performs transactions from the PCI-to-EISA bridge immediately.

mem_we_l<1:0>

The mem_we_l<1:0> signal lines carry the write-enable signal to the memory
arrays.

ras_h<3:0>

The ras_h<3:0> signal lines select the row address in the memory arrays.

set_sel_h<15:0>

The set_sel_h<15:0> signal lines are used to select a memory array.

2–10 Preliminary Edition—Subject to Change—September 1995

2.2.5 Phase-Locked Loop Signals

This section describes the phase-locked loop signals.

pll_agnd_h

Signal pll_agnd_h is the analog ground input to the PLL and is connected to
the system board ground.

pll_clk_h

The pll_clk_h signal is the system clock (or reference signal) input to the
phase-locked loop (PLL) circuit. The pll_clk_h signal line is the source for CIA
timing. It supplies a clock with the same frequency as that supplied to the
PCI.

pll_lp1_h

Signal pll_lp1_h is an output of the PLL (phase detector output).

pll_test_h<3:0>

Signals pll_test_h<3:0> select which internal chip information is presented at
output pins debug_h<1:0>. These signal lines are reserved to Digital.

pll_vss_h

Signal pll_vss_h is the ground input input to the PLL. It is connected to the
system board ground.

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

2.2.6 Miscellaneous Power Signals

This section describes the miscellaneous power signals.

aux_vdd_h

Signal aux_vdd_h is modified (filtered) within the CIA chip before going to the
PLL section of the CIA. Signal aux_vdd_h should be connected to vdd_h on
the module.

aux_vss_h

Signal aux_vss_h is modified (filtered) within the CIA chip before going to the
PLL section of the CIA. Signal aux_vss_h should be connected to vss_h on the
module.

pll_vdd_h

Signal pll_vdd_h is the power input to the PLL. It is connected to the system
board power.

pll_lp2_h

Signal pll_lp2_h is an input to the PLL, driving a VCO input.

Preliminary Edition—Subject to Change—September 1995 2–11

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

2.2.7 Miscellaneous Signals

This section provides a description of the miscellaneous signals.

count_out_h

Signal count_out_h is used during PLL tests.

debug_h<1:0>

Signals debug_h<1:0> present internal CIA information selected by
pll_test_h<3:0>. These signal lines are reserved to Digital.

scan_in_h

Signal scan_in_h is the enable pin for the scan chain.

sys_rst_l

The sys_rst_l signal line is the system reset input signal to the CIA. When
sys_rst_l is asserted, the CIA resets its internal state.

test_mode_h<1:0>

Signals test_mode_h<1:0> define the four operating modes of the CIA as
listed in Table 2–7.

Table 2–7 DSW Operating Modes

test_mode_h<1:0> DSW Operating Mode

00 Tristate mode
01 Normal mode
10 Scan mode
11 PLL test mode

test_or_scan_out_h

Signal test_or_scan_out_h is the TEST_OUT output that is the end of the
parametric NAND tree.

2.2.8 Reserved Signals

This section provides a description of the reserved signals.

gru_ack_h

Signal gru_ack_h is reserved for use by Digital.

gru_sel_h

Signal gru_sel_h is reserved for use by Digital.

2–12 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

2.2.9 DECchip 21171-CA Pin Name List (Alphabetic)

Table 2–8 lists the DECchip 21171-CA (CIA) pins by name in alphabetical
order. The following abbreviations are used in the Type column of the table:

• B = Bidirectional

• I = Input

• P = Power

• O = Output

Table 2–8 DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

ack64_l U5 B — — —

ad_h<0> Y18 B ad_h<1> V15 B
ad_h<2> U14 B ad_h<3> W16 B
ad_h<4> V14 B ad_h<5> W14 B
ad_h<6> U13 B ad_h<7> Y15 B
ad_h<8> V13 B ad_h<9> W12 B
ad_h<10> AA14 B ad_h<11> Y13 B
ad_h<12> AA13 B ad_h<13> AA12 B
ad_h<14> AA11 B ad_h<15> AA10 B
ad_h<16> V10 B ad_h<17> U10 B
ad_h<18> AA8 B ad_h<19> W9 B
ad_h<20> V9 B ad_h<21> U9 B
ad_h<22> W7 B ad_h<23> W8 B
ad_h<24> V8 B ad_h<25> Y5 B
ad_h<26> AA4 B ad_h<27> W5 B
ad_h<28> AA3 B ad_h<29> AA2 B
ad_h<30> U6 B ad_h<31> Y3 B
ad_h<32> W17 B ad_h<33> AA18 B
ad_h<34> Y17 B ad_h<35> AA17 B
ad_h<36> Y16 B ad_h<37> W15 B
ad_h<38> AA16 B ad_h<39> AA15 B
ad_h<40> Y14 B ad_h<41> W13 B
ad_h<42> U12 B ad_h<43> V12 B
ad_h<44> Y12 B ad_h<45> Y11 B
ad_h<46> W10 B ad_h<47> Y10 B
ad_h<48> AA9 B ad_h<49> Y9 B
ad_h<50> Y8 B ad_h<51> AA7 B

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Preliminary Edition—Subject to Change—September 1995 2–13

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–8 (Cont.) DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

ad_h<52> Y7 B ad_h<53> AA6 B
ad_h<54> Y6 B ad_h<55> AA5 B
ad_h<56> W6 B ad_h<57> U8 B
ad_h<58> V7 B ad_h<59> Y4 B
ad_h<60> U7 B ad_h<61> V6 B
ad_h<62> T6 B ad_h<63> Y2 B

addr_h<4> N18 B addr_h<5> R21 B
addr_h<6> R20 B addr_h<7> T21 B
addr_h<8> N17 B addr_h<9> R19 B
addr_h<10> P19 B addr_h<11> T20 B
addr_h<12> P18 B addr_h<13> U21 B
addr_h<14> T19 B addr_h<15> U20 B
addr_h<16> P17 B addr_h<17> V21 B
addr_h<18> R18 B addr_h<19> U19 B
addr_h<20> V20 B addr_h<21> R17 B
addr_h<22> W21 B addr_h<23> T18 B
addr_h<24> V19 B addr_h<25> W20 B
addr_h<26> V26 B addr_h<27> T17 B
addr_h<28> Y20 B addr_h<29> U18 B
addr_h<30> U17 B addr_h<31> E16 B
addr_h<32> B19 B addr_h<33> F15 B
addr_h<34> C18 B addr_h<39> D17 B

addr_bus_req_h D18 B addr_cmd_par_h E15 B
addr_res_h<0> D10 I addr_res_h<1> B11 I

aux_vdd_h C4 P aux_vss_h D5 P

cack_h B21 O — — —

cas_h<0> G19 O cas_h<1> F21 O
cas_h<2> H19 O cas_h<3> G20 O

cbe_l<0> AA19 B cbe_l<1> AA20 B
cbe_l<2> Y21 B cbe_l<3> W18 B
cbe_l<4> W2 B cbe_l<5> T5 B
cbe_l<6> V3 B cbe_l<7> U4 B

2–14 Preliminary Edition—Subject to Change—September 1995

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DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–8 (Cont.) DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

cmc_h<0> D14 O cmc_h<1> B16 O
cmc_h<2> C15 O cmc_h<3> B15 O
cmc_h<4> E13 O cmc_h<5> C14 O
cmc_h<6> F12 O cmc_h<7> D13 O
cmc_h<8> B14 O — — —

cmd_h<0> B18 B cmd_h<1> F14 B
cmd_h<2> C17 B cmd_h<3> D16 B

count_out_h R6 O dack_h F16 O
debug_h<0> T3 I debug_h<1> V5 I
devsel_l V17 B error_h P5 O
fill_error_h M17 O fill_h C19 O
fill_id_h P20 B frame_l V18 B

GND A2 P GND A4 P
GND A5 P GND A6 P
GND A8 P GND A10 P
GND A12 P GND A14 P
GND A16 P GND A17 P
GND A18 P GND A20 P
GND A21 P GND B1 P
GND C22 P GND D1 P
GND D19 P GND E22 P
GND F1 P GND F22 P
GND G1 P GND G22 P
GND J1 P GND J22 P
GND K1 P GND M1 P
GND M22 P GND N22 P
GND P1 P GND R22 P
GND T1 P GND U1 P
GND U22 P GND V1 P
GND W4 P GND W19 P
GND W22 P GND Y1 P
GND AA22 P GND AB2 P
GND AB3 P GND AB5 P
GND AB7 P GND AB9 P
GND AB12 P GND AB13 P
GND AB15 P GND AB17 P

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Preliminary Edition—Subject to Change—September 1995 2–15

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–8 (Cont.) DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

GND AB18 P GND AB19 P
GND AB21 P — — —

gnt_l U3 I — — —
gru_ack_h (Reserved) L6 I gru_sel_h (Reserved) L5 O
idle_bc_h B20 O int_h L17 O

int4_valid_h<0> E14 I int4_valid_h<1> C16 I
int4_valid_h<2> F13 I int4_valid_h<3> D15 I

ioc_h<0> E12 O ioc_h<1> C13 O
ioc_h<2> D12 O ioc_h<3> B13 O
ioc_h<4> C12 O ioc_h<5> B12 O
ioc_h<6> C11 O — — —

iod_h<0> B10 B iod_h<1> C10 B
iod_h<2> E10 B iod_h<3> B9 B
iod_h<4> F10 B iod_h<5> C9 B
iod_h<6> B8 B iod_h<7> C8 B
iod_h<8> D9 B iod_h<9> B7 B
iod_h<10> E9 B iod_h<11> C7 B
iod_h<12> D8 B iod_h<13> B6 B
iod_h<14> D7 B iod_h<15> C6 B
iod_h<16> F9 B iod_h<17> B5 B
iod_h<18> E8 B iod_h<19> D6 B
iod_h<20> C5 B iod_h<21> E7 B
iod_h<22> B4 B iod_h<23> F8 B
iod_h<24> N4 B iod_h<25> P3 B
iod_h<26> P4 B iod_h<27> N6 B
iod_h<28> T2 B iod_h<29> N5 B
iod_h<30> M4 B iod_h<31> F6 B
iod_h<32> D3 B iod_h<33> E4 B
iod_h<34> G5 B iod_h<35> D2 B
iod_h<36> H6 B iod_h<37> E3 B
iod_h<38> F4 B iod_h<39> H5 B
iod_h<40> E2 B iod_h<41> H4 B
iod_h<42> F3 B iod_h<43> G4 B
iod_h<44> F2 B iod_h<45> J6 B
iod_h<46> G3 B iod_h<47> J5 B

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2–16 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–8 (Cont.) DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

iod_h<48> G2 B iod_h<49> J4 B
iod_h<50> H3 B iod_h<51> H2 B
iod_h<52> J3 B iod_h<53> K6 B
iod_h<54> J2 B iod_h<55> K5 B
iod_h<56> K3 B iod_h<57> K2 B
iod_h<58> K4 B iod_h<59> L2 B
iod_h<60> L3 B iod_h<61> M2 B
iod_h<62> M3 B iod_h<63> N2 B

iod_e_h<0> F5 B iod_e_h<1> C3 B
iod_e_h<2> G6 B iod_e_h<3> C2 B
iod_e_h<4> M5 B iod_e_h<5> N3 B
iod_e_h<6> M6 B iod_e_h<7> P2 B

irdy_l V11 B lock_l U15 I
mem_ack_l R4 O — — —
mem_addr_h<0> J20 O mem_addr_h<1> K17 O
mem_addr_h<2> J21 O mem_addr_h<3> K18 O
mem_addr_h<4> K20 O mem_addr_h<5> K21 O
mem_addr_h<6> K19 O mem_addr_h<7> L21 O
mem_addr_h<8> L20 O mem_addr_h<9> M21 O
mem_addr_h<10> M20 O mem_addr_h<11> N21 O
mem_addr_h<12> M19 O — — —

mem_cs_l U2 I mem_en_h H21 O
mem_req_l T4 I mem_we_l<0> N20 O
mem_we_l<1> M18 O par_h R5 B
par64_h V2 B perr_l AA21 B

pll_agnd_h E6 O pll_clk_h F11 I
pll_test_h<0> E18 I pll_test_h<1> L4 I
pll_test_h<2> R2 I pll_test_h<3> R3 I
pll_lp1_h B3 I pll_lp2_h F7 P
pll_vdd_h E5 P pll_vss_h D4 I

PWR5 A3 P PWR5 A7 P
PWR5 A9 P PWR5 A11 P
PWR5 A13 P PWR5 A15 P
PWR5 A19 P PWR5 A22 P

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Preliminary Edition—Subject to Change—September 1995 2–17

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

Table 2–8 (Cont.) DECchip 21171-CA Pin Names (Alphabetic)

Pin Name Pin Type Pin Name Pin Type

PWR5 B2 P PWR5 B22 P
PWR5 C1 P PWR5 D22 P
PWR5 E1 P PWR5 H1 P
PWR5 H22 P PWR5 K22 P
PWR5 L1 P PWR5 L22 P
PWR5 N1 P PWR5 P22 P
PWR5 R1 P PWR5 T22 P
PWR5 V22 P PWR5 W1 P
PWR5 Y22 P PWR5 AA1 P
PWR5 AB1 P PWR5 AB4 P
PWR5 AB6 P PWR5 AB8 P
PWR5 AB10 P PWR5 AB11 P
PWR5 AB14 P PWR5 AB16 P
PWR5 AB20 P PWR5 AB22 P

ras_h<0> J18 O ras_h<1> G21 O
ras_h<2> J19 O ras_h<3> H20 O

req_l P6 O req64_l V4 B
rst_l U16 O scan_in_h L19 I
serr_l W3 B — — —

set_sel_h<0> F17 O set_sel_h<1> G17 O
set_sel_h<2> C20 O set_sel_h<3> F18 O
set_sel_h<4> C21 O set_sel_h<5> D20 O
set_sel_h<6> E19 O set_sel_h<7> H17 O
set_sel_h<8> D21 O set_sel_h<9> G18 O
set_sel_h<10> E20 O set_sel_h<11> F19 O
set_sel_h<12> H18 O set_sel_h<13> E21 O
set_sel_h<14> J17 O set_sel_h<15> F20 O

spare1 U11 I stop_l Y19 B
sys_rst_l L18 I tag_ctl_par_h P21 O
tag_dirty_h N19 O test_mode_h<0> E11 I
test_mode_h<1> D11 I test_or_scan_out_h E17 O
trdy_l W11 B victim_pending_h B17 I

2–18 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

2.2.10 DECchip 21171-CA Pin Assignment List (Alphanumeric)

Table 2–9 lists the DECchip 21171-CA pins in alphanumeric order. The
following abbreviations are used in the Type column of the table:

• B = Bidirectional

• I = Input

• P = Power

• O = Output

Table 2–9 DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

—— — A2GND P
A3 PWR5 PA4GND P
A5 GND PA6GND P
A7 PWR5 PA8GND P
A9 PWR5 P A10 GND P
A11 PWR5 P A12 GND P
A13 PWR5 P A14 GND P
A15 PWR5 P A16 GND P
A17 GND P A18 GND P
A19 PWR5 P A20 GND P
A21 GND P A22 PWR5 P

B1 GND PB2PWR5 P
B3 pll_lp1_h IB4iod_h<22> B
B5 iod_h<17> BB6iod_h<13> B
B7 iod_h<9> BB8iod_h<6> B
B9 iod_h<3> B B10 iod_h<0> B
B11 addr_res_h<1> I B12 ioc_h<5> O
B13 ioc_h<3> O B14 cmc_h<8> O
B15 cmc_h<3> O B16 cmc_h<1> O
B17 victim_pending_h I B18 cmd_h<0> B
B19 addr_h<32> B B20 idle_bc_h O
B21 cack_h O B22 PWR5 P

C1 PWR5 PC2iod_e_h<3> B
C3 iod_e_h<1> BC4aux_vdd P
C5 iod_h<20> BC6iod_h<15> B
C7 iod_h<11> BC8iod_h<7> B

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DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–9 (Cont.) DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

C9 iod_h<5> B C10 iod_h<1> B
C11 ioc_h<6> O C12 ioc_h<4> O
C13 ioc_h<1> O C14 cmc_h<5> O
C15 cmc_h<2> O C16 int4_valid_h<1> I
C17 cmd_h<2> B C18 addr_h<34> B
C19 fill_h O C20 set_sel_h<2> O
C21 set_sel_h<4> O C22 GND P

D1 GND PD2iod_h<35> B
D3 iod_h<32> BD4pll_vss_h I
D5 aux_vss PD6iod_h<19> B
D7 iod_h<14> BD8iod_h<12> B
D9 iod_h<8> B D10 addr_res_h<0> I
D11 test_mode_h<1> I D12 ioc_h<2> O
D13 cmc_h<7> O D14 cmc_h<0> O
D15 int4_valid_h<3> I D16 cmd_h<3> B
D17 addr_h<39> B D18 addr_bus_req B
D19 GND P D20 set_sel_h<5> O
D21 set_sel_h<8> O D22 PWR5 P

E1 PWR5 PE2iod_h<40> B
E3 iod_h<37> BE4iod_h<33> B
E5 pll_vdd PE6pll_agnd_h O
E7 iod_h<21> BE8iod_h<18> B
E9 iod_h<10> B E10 iod_h<2> B
E11 test_mode_h<0> I E12 ioc_h<0> O
E13 cmc_h<4> O E14 int4_valid_h<0> I
E15 addr_cmd_par B E16 addr_h<31> B
E17 test_or_scan_out_h O E18 pll_test_h<0> I
E19 set_sel_h<6> O E20 set_sel_h<10> O
E21 set_sel_h<13> O E22 GND P

F1 GND PF2iod_h<44> B
F3 iod_h<42> BF4iod_h<38> B
F5 iod_e_h<0> BF6iod_h<31> B
F7 pll_lp2_h PF8iod_h<23> B
F9 iod_h<16> B F10 iod_h<4> B
F11 pll_clk_h I F12 cmc_h<6> O
F13 int4_valid_h<2> I F14 cmd_h<1> B

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DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–9 (Cont.) DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

F15 addr_h<33> B F16 dack_h O
F17 set_sel_h<0> O F18 set_sel_h<3> O
F19 set_sel_h<11> O F20 set_sel_h<15> O
F21 cas_h<1> O F22 GND P

G1 GND PG2iod_h<48> B
G3 iod_h<46> BG4iod_h<43> B
G5 iod_h<34> BG6iod_e_h<2> B
G17 set_sel_h<1> O G18 set_sel_h<9> O
G19 cas_h<0> O G20 cas_h<3> O
G21 ras_h<1> O G22 GND P

H1 PWR5 PH2iod_h<51> B
H3 iod_h<50> BH4iod_h<41> B
H5 iod_h<39> BH6iod_h<36> B
H17 set_sel_h<7> O H18 set_sel_h<12> O
H19 cas_h<2> O H20 ras_h<3> O
H21 mem_en_h O H22 PWR5 P

J1 GND PJ2iod_h<54> B
J3 iod_h<52> BJ4iod_h<49> B
J5 iod_h<47> BJ6iod_h<45> B
J17 set_sel_h<14> O J18 ras_h<0> O
J19 ras_h<2> O J20 mem_addr_h<0> O
J21 mem_addr_h<2> O J22 GND P

K1 GND PK2iod_h<57> B
K3 iod_h<56> BK4iod_h<58> B
K5 iod_h<55> BK6iod_h<53> B
K17 mem_addr_h<1> O K18 mem_addr_h<3> O
K19 mem_addr_h<6> O K20 mem_addr_h<4> O
K21 mem_addr_h<5> O K22 PWR5 P

L1 PWR5 PL2iod_h<59> B
L3 iod_h<60> BL4pll_test_h<1> I
L5 gru_sel_h (Reserved) O L6 gru_ack_h (Reserved) I
L17 int_h O L18 sys_rst_l I
L19 scan_in_h I L20 mem_addr_h<8> O
L21 mem_addr_h<7> O L22 PWR5 P

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DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–9 (Cont.) DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

M1 GND PM2iod_h<61> B
M3 iod_h<62> BM4iod_h<30> B
M5 iod_e_h<4> BM6iod_e_h<6> B
M17 fill_error_h O M18 mem_we_l<1> O
M19 mem_addr_h<12> O M20 mem_addr_h<10> O
M21 mem_addr_h<9> O M22 GND P

N1 PWR5 PN2iod_h<63> B
N3 iod_e_h<5> BN4iod_h<24> B
N5 iod_h<29> BN6iod_h<27> B
N17 addr_h<8> B N18 addr_h<4> B
N19 tag_dirty_h O N20 mem_we_l<0> O
N21 mem_addr_h<11> O N22 GND P

P1 GND PP2iod_e_h<7> B
P3 iod_h<25> BP4iod_h<26> B
P5 error_h OP6req_l O
P17 addr_h<16> B P18 addr_h<12> B
P19 addr_h<10> B P20 fill_id_h B
P21 tag_ctl_par_h O P22 PWR5 P

R1 PWR5 PR2pll_test_h<2> I
R3 pll_test_h<3> IR4mem_ack_l O
R5 par_h BR6count_out_h O
R17 addr_h<21> B R18 addr_h<18> B
R19 addr_h<9> B R20 addr_h<6> B
R21 addr_h<5> B R22 GND P

T1 GND PT2iod_h<28> B
T3 debug_h<0> IT4mem_req_l I
T5 cbe_l<5> BT6ad_h<62> B
T17 addr_h<27> B T18 addr_h<23> B
T19 addr_h<14> B T20 addr_h<11> B
T21 addr_h<7> B T22 PWR5 P

U1 GND PU2mem_cs_l I
U3 gnt_l IU4cbe_l<7> B
U5 ack64_l BU6ad_h<30> B

2–22 Preliminary Edition—Subject to Change—September 1995

(continued on next page)

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CASignal Descriptions

Table 2–9 (Cont.) DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

U7 ad_h<60> BU8ad_h<57> B
U9 ad_h<21> B U10 ad_h<17> B
U11 spare1 I U12 ad_h<42> B
U13 ad_h<6> B U14 ad_h<2> B
U15 lock_l I U16 rst_l O
U17 addr_h<30> B U18 addr_h<29> B
U19 addr_h<19> B U20 addr_h<15> B
U21 addr_h<13> B U22 GND P

V1 GND PV2par64 B
V3 cbe_l<6> BV4req64_l B
V5 debug_h<1> IV6ad_h<61> B
V7 ad_h<58> BV8ad_h<24> B
V9 ad_h<20> B V10 ad_h<16> B
V11 irdy_l B V12 ad_h<43> B
V13 ad_h<8> B V14 ad_h<4> B
V15 ad_h<1> B V16 addr_h<26> B
V17 devsel_l B V18 frame_l B
V19 addr_h<24> B V20 addr_h<20> B
V21 addr_h<17> B V22 PWR5 P

W1 PWR5 PW2cbe_l<4> B
W3 serr_l BW4GND P
W5 ad_h<27> BW6ad_h<56> B
W7 ad_h<22> BW8ad_h<23> B
W9 ad_h<19> B W10 ad_h<46> B
W11 trdy_l B W12 ad_h<9> B
W13 ad_h<41> B W14 ad_h<5> B
W15 ad_h<37> B W16 ad_h<3> B
W17 ad_h<32> B W18 cbe_l<3> B
W19 GND P W20 addr_h<25> B
W21 addr_h<22> B W22 GND P

Y1 GND PY2ad_h<63> B
Y3 ad_h<31> BY4ad_h<59> B
Y5 ad_h<25> BY6ad_h<54> B
Y7 ad_h<52> BY8ad_h<50> B
Y9 ad_h<49> B Y10 ad_h<47> B
Y11 ad_h<45> B Y12 ad_h<44> B

(continued on next page)

Preliminary Edition—Subject to Change—September 1995 2–23

DECchip 21171-CA Pin Descriptions

2.2 DECchip 21171-CA Signal Descriptions

Table 2–9 (Cont.) DECchip 21171-CA Pin Assignment (Alphanumeric)

Pin Pin Name Type Pin Pin Name Type

Y13 ad_h<11> B Y14 ad_h<40> B
Y15 ad_h<7> B Y16 ad_h<36> B
Y17 ad_h<34> B Y18 ad_h<0> B
Y19 stop_l B Y20 addr_h<28> B
Y21 cbe_l<2> B Y22 PWR5 P

AA1 PWR5 P AA2 ad_h<29> B
AA3 ad_h<28> B AA4 ad_h<26> B
AA5 ad_h<55> B AA6 ad_h<53> B
AA7 ad_h<51> B AA8 ad_h<18> B
AA9 ad_h<48> B AA10 ad_h<15> B
AA11 ad_h<14> B AA12 ad_h<13> B
AA13 ad_h<12> B AA14 ad_h<10> B
AA15 ad_h<39> B AA16 ad_h<38> B
AA17 ad_h<35> B AA18 ad_h<33> B
AA19 cbe_l<0> B AA20 cbe_l<1> B
AA21 perr_l B AA22 GND P

AB1 PWR5 P AB2 GND P
AB3 GND P AB4 PWR5 P
AB5 GND P AB6 PWR5 P
AB7 GND P AB8 PWR5 P
AB9 GND P AB10 PWR5 P
AB11 PWR5 P AB12 GND P
AB13 GND P AB14 PWR5 P
AB15 GND P AB16 PWR5 P
AB17 GND P AB18 GND P
AB19 GND P AB20 PWR5 P
AB21 GND P AB22 PWR5 P

2.3 DECchip 21171-CA Mechanical Specifications

Figure 2–1 and Table 2–10 indicate the DECchip 21171-CA package
dimensions.

2–24 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Pin Descriptions

2.3 DECchip 21171-CA Mechanical Specifications

Figure 2–1 DECchip 21171-CA Package Dimensions

D
M

D2

E

(Note 3)

-C-

(Note 3)

H

E2

A2

(Note 3)

A1

(Note 2)

M1

AB
AA

Y
W

V
U
T
R
P
N
M

N

L
K
J
H

N1

G
F
E
D
C
B
A

2345678910111213141516171819202122

4X Stand-Off Pin

J

(Note 1)

L1

Q1

D3
D1

(Note 2)

G

E1

(Note 2)E3(Note 4)

A

L

B1

B

Notes for Figure 2–1

The following notes apply to Figure 2–1:

Note 1. Chip capacitors envelope. Commercial grade chip caps; nominal
capacitance 0.082F.
Note 2. Envelope for maximum lid (ceramic, epoxy seal).
Note 3. Envelope for integral heat slug.
Note 4. The drawing/dimensions are for reference only. For board layout,
request an engineering drawing from Digital Semiconductor.

Preliminary Edition—Subject to Change—September 1995 2–25

F

Seating

Plane

LJ-04217.AI

DECchip 21171-CA Pin Descriptions

2.3 DECchip 21171-CA Mechanical Specifications

Table 2–10 DECchip 21171-CA Package Dimensions

Indicator Minimum Maximum

A 1.78 mm (0.070 in) 3.30mm (0.130 in)
A1 NA
A2 NA 1.27 mm (0.050 in)
B 0.40 mm (0.016 in) 0.51 mm (0.020 in)
B1 1.17 mm (0.046 in) 1.37 mm (0.054 in)
D 57.30 mm (2.256 in) 57.51 mm (2.264 in)
D1 NA 24.89 mm (0.980 in)
D2 NA 24.13 mm (0.950 in)
E 57.30 mm (2.256 in) 57.51 mm (2.264 in)
E1 NA 24.89 mm (0.980 in)
E2 NA 24.13 mm (0.950 in)
G 1.78 mm (0.070 in) 2.04 mm (0.080 in)
H NA 3.56 mm (0.140 in)
I NA 4.06 mm (0.160 in)
J NA 1.65 mm (0.064 in)
L 4.06 mm (0.160 in) 4.57 mm (0.180 in)
L1 1.12 mm (0.044 in) 1.42 mm (0.056 in)
Q1 0.23 mm (0.009 in) NA

1

4.19 mm (0.165 in)

Indicator Basic

D3 2.100 in (53.34 mm)
E3 2.100 in (53.34 mm)
F 1.0 in (2.54 mm)
M 2.050 in (52.07 mm)
M1 1.000 in (25.4 mm)
N 2.000 in (50.8 mm)
N1 0.950 in (24.13 mm)

1

NA = Not applicable.

2–26 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

This chapter describes the DECchip 21171-CA (CIA) data paths with functional
units, transactions, and architecture.

3.1 CIA Data Paths with Functional Units Description

This section shows the CIA data path functional units and describes operation
of the functional units.

3.1.1 System Functional Units

The CIA operates as the host bridge on a PCI-based system along with the
21164, four DSWs, Bcache, memory arrays, and support logic. A simplified
description of the system data paths and functional units is presented here to
show where the CIA operates within the system.

The CIA performs control, I/O, and address tasks within the DECchip 21171
Core Logic Chipset as shown in Figure 3–1. The host bridge module is shown
plugged into a 64-bit PCI.

3

Preliminary Edition—Subject to Change—September 1995 3–1

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

Figure 3–1 System Functional Block Diagram

Bcache

21164

PCI-to-(E)ISA

Bridge

(E)ISA

Bus

Data

Switch

CIA ASIC

32-Bit
Slots

Memory

64-Bit PCI Bus

PCI-to-PCI

Bridge

Slot
Slot
Slot
Audio

64-Bit Slots

PCI

Graphics

Internal PCI

SCSI SCSI SCSI

Ethernet

3–2 Preliminary Edition—Subject to Change—September 1995

LJ-04218.AI

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

3.1.2 CIA Functional Units

Figure 3–2 shows the CIA data paths and functional units.

Figure 3–2 CIA Functional Block Diagram

21164 Address
and Command

(IOD Bus)

21164
Instruction
and
Address
Logic

Mem Port I/O Port

21164
Instruction
Queue

Memory
Logic

Memory

RAS

Check

Control

Data_Out

Flush

Address

DMA Read/Write and TLB Miss Address

Out
MUX

ECC Gen

I/O Address Logic

Bypass Path

I/O Address

Queue

Data_In

DMA Write/
Merge Path

I/O Read
Path

DMA Write
Path

DMA Write

Address
Decode

and

Increment

ECC Corr

I/O Read

DMA Read

I/O Write

I/O Write

PCI Data Bypass

I/O Read/Write
Address for PCI

DMA Address
Logic

PA Reg.

Big MUX

PCI Data

PCI
Data-Path
Logic

PCI Address

PCI

Target

Window

Logic

PCI Data/
Address Reg.

Scatter-Gather TLB

Direct Map

TLB Miss Address

PCI Bus

Address/
Command

Hit

Memory Address,

ras, we, Refresh

Current
Address
Register

DMA Read
Prefetch Counter

LJ-04219.AI

Preliminary Edition—Subject to Change—September 1995 3–3

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

The CIA functional units are listed here and are described in Section 3.1.2.1
through Section 3.1.2.5:

• 21164 instruction and address logic

• PCI data path logic

• Memory logic

• I/O address logic

• DMA address logic

3.1.2.1 21164 Instruction and Address Logic

The 21164 instruction and address logic accepts commands from the 21164 and
directs the instruction to the memory port or the I/O port. The DMA read/write
address (or the scatter-gather TLB miss servicing address) also has access to
the memory port through a multiplexer.

The 21164 instruction queue is provided to capture 21164 commands should
the memory or I/O port be busy. The 21164 can issue, at most, two read
miss transactions—with one having a victim. This maximum condition would
require holding three addresses and commands, so a 3-entry buffer is needed.

The flush address register is used during DMA read or write transactions
to the Bcache for the latest data. The Bcache is implemented as a write
invalidate cache and so might have the only valid copy of the required data.

3.1.2.2 PCI Data Path Logic

Because the CIA is the PCI host bridge it generates and decodes PCI addresses
and also supplies and receives data. The data path to and from the PCI goes
through the CIA and the DSW. The ECC generation and check logic is excluded
from the DSW because of the bit slice nature of the DSW and so is performed
by the CIA.

Separate buffers are provided in the CIA for DMA and I/O read/write
transactions. These buffers are either 32 bytes or 64 bytes in size, and are
shown partitioned into 16-byte units, which matches the width of the 21164
data bus.

Later, when the DSW is examined, it will be seen that the DSW also has
buffers for the DMA and I/O paths. Control logic simplification is the reason
for this duplication.

3–4 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

Table 3–1 lists the PCI commands that the CIA responds to and sends.

Table 3–1 PCI Commands Recognized by the CIA

PCI cbe_l<3:0> Command CIA Slave CIA Master

0000 Interrupt acknowledge No Yes
0001 Special cycle No Yes
0010 I/O read No Yes
0011 I/O write No Yes
0100 Reserved — —
0101 Reserved — —
0110 Memory read Yes Yes
0111 Memory write Yes Yes
1000 Reserved — —
1001 Reserved — —
1010 Configuration read No Yes
1011 Configuration write No Yes
1100 Memory read multiple Yes No
1101 Dual address cycle Yes No
1110 Memory read line Yes No
1111 Memory write and invalidate Yes

1

No

1

Accepted as memory write

The CIA has these PCI features:

• Supports 64-bit PCI bus width

• Supports 64-bit PCI addressing (DAC cycles)

• Accepts PCI fast back-to-back cycles

• Issues PCI fast back-to-back cycles in dense address space

Preliminary Edition—Subject to Change—September 1995 3–5

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

3.1.2.3 Memory Logic

Memory logic provides the row and column address for the memory banks
and all the control signals (ras_h, cas_h, mem_we_l<1:0>, and mem_en_h).
The memory logic provides control signals to the DSW to inform it when to
send/strobe the data to/from memory. The CIA also controls memory refresh.

3.1.2.4 I/O Address Logic

The I/O address logic handles the I/O read and write addresses. The address
decode logic extracts the PCI address from the dense/sparse space 21164
address encodings (see Chapter 6 for more details).

This logic also increments the current address of each data cycle for two
reasons:

• In case of a PCI retry, which will require the transaction to be resumed
later, we need to start with the address of the aborted data.

• We need to provide a pointer to the next data item to be loaded/sent from
the I/O read/write buffers.

The CIA can queue up to six I/O write transactions. Two of the I/O write
transactions can be waiting in the 21164 queue and four I/O write transactions
can be sitting in the I/O address queue (a 3-entry I/O address queue is provided
together with a single-entry current address register). This allows six I/O write
transactions to be outstanding (the DSW provides four corresponding I/O write
data buffers). The bypass path is enabled/disabled by CIA_CTRL[CSR_IOA_
BYPASS] (CSR_CTRL<15>) being equal to 0/1 respectively.

3–6 Preliminary Edition—Subject to Change—September 1995

The CIA provides two more buffers that are needed to sustain maximum
bandwidth for memory copy to I/O space. A bypass path is provided for certain
dense-space I/O write transactions, that is, the valid bits for the first 16 bytes
of data are either 1111, 1011, 1010, and 1001—these cases are optimized for a
64-bit PCI with at least two PCI data cycles.

3.1.2.5 DMA Address Logic

The DMA address logic converts PCI addresses to CPU memory addresses.
Two conversion methods are provided:

• A direct path where a base offset is concatenated with the PCI address

• A scatter-gather map, which maps any 8KB PCI page to any 8KB memory

space page

The scatter-gather TLB is eight entries deep with each entry holding four
consecutive PTEs. A TLB miss is handled by hardware but software is required
to invalidate stale entries by writing to the translation buffer invalidate
register (TBIA). See Chapter 6 for more information on address mapping.

The output of the physical address register (PA) has a a counter that generates
the prefetch address for certain DMA read miss transactions. An 8KB detector
prevents prefetching across page boundaries.

DECchip 21171-CA Architecture Overview

3.1 CIA Data Paths with Functional Units Description

3.2 CIA Transactions

The CIA performs the transactions listed here:

• 21164 memory read miss

• 21164 memory read miss with victim

• 21164 I/O read

• 21164 I/O write

• DMA read

• DMA read (prefetch)

• DMA write
These transactions are described in detail in Section 3.2.1 through

Section 3.2.8.

Preliminary Edition—Subject to Change—September 1995 3–7

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

3.2.1 21164 Read Miss Transaction

The 21164 read miss command and address are sent to the CIA. If the CIA
is idle, the command will be stored directly in the memory port register;
otherwise, the command enters the 3-deep CPU instruction queue and remains
there until the memory port is free. The CIA can accept another subsequent
read miss command from the 21164 and store it in the 21164 instruction queue.

The three data paths to the memory port have to arbitrate for use of the
memory port: (1) the direct path and (2) the 21164 instruction queue previously
mentioned and (3) the DMA read/write address path. The DMA read/write
address path is also the path for scatter-gather TLB miss addresses. Upstream
of the multiplexer all instruction ordering from the 21164 is preserved.
Downstream of the multiplexer ordering between I/O write transactions and
21164 memory transactions is lost. This ‘‘post and run’’ I/O write coherency
issue is discussed in Section 3.3.2.

When the 21164 read miss command enters the memory logic, the memory
controller generates ras_h, cas_h, and other address signals for the memory
array. The memory controller then waits for the memory access delay before
instructing the DSW to accept the memory data. The MEMDATA bus width
is 256 bits (32 bytes), and so two memory cycles are required to access the
64-byte block.

The DSW synchronizes the data to the 21164 clock. The fixed 64-byte block
size read data is returned to the 21164 in wrapped-order.

3.2.2 21164 Read Miss with Victim Transaction

The read miss with victim transaction is similar to the read miss transaction
described in Section 3.2.1, except the 21164 will also use a Bcache victim
command to send out the victim block. The victim block is the modified (dirty)
block that is to be replaced in the Bcache by the read miss transaction data.

The read miss command is followed by the Bcache victim command and
address. The read miss command will get to the memory port first and so
the Bcache victim command and address are always written into the 21164
instruction queue. The victim block data is saved in the victim buffer in the
DSW.

3–8 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

The CIA arbiter ensures that a read miss transaction and a victim write
transaction are an atomic operation. The victim data is written to memory
after the read data has been fetched from memory. The row address portion
of the victim address is compared to the row address of the current read miss
transaction. If they match, then no memory ras_h cycle is required; instead,
only a cas_h cycle is needed. The address bits for the memory have been
carefully interspersed to maximize the chance of a victim row address ‘‘hitting’’
the read address—this performance feature is transparent to software. The
memory controller in the CIA generates the memory write pulses and instructs
the DSW to send the victim data to memory.

The DSW victim buffer is invalidated if a DMA write transaction (or DMA
read with lock transaction) ‘‘hits’’ in the victim buffer. Until the 21164 has its
read miss transaction data returned, the victim block is still in the Bcache
and is still ‘‘owned’’ by the 21164. It is possible for the read miss with victim
transaction from the 21164 to be stalled behind a DMA write transaction. The
DMA write transaction could ‘‘hit’’ the victim block—in this case, the DMA
write transaction will cause a flush command to be issued to the 21164, which
will result in the 21164 providing the victim data to the DSW and then the
21164 will invalidate the victim block in Bcache. Thus, the victim data waiting
in the victim buffer is no longer valid and is marked invalid by logic in the
CIA.

3.2.3 21164 Read Transaction to Noncacheable Space

A read transaction by the 21164 to noncacheable space can be to one of four
address spaces:

• PCI memory space

• PCI I/O dense or sparse space

• PCI configuration space

• CIA control and status register (CSR) space

Preliminary Edition—Subject to Change—September 1995 3–9

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

The read command to noncacheable space is accepted by the CIA like the read
miss command, except the instruction goes to the I/O port. All read commands
to noncacheable space go to the I/O address queue. There is no bypass path for
dense space I/O read transactions.

Decode logic is provided on the output of the I/O address queue to extract the
byte address for the PCI from the 21164’s sparse space encoding, and to decode
the address for the correct region (PCI memory, I/O, configuration, or CSR).

A read command to noncacheable space destined for the PCI is described here
because it is the more interesting case. Logic increments the current longword
/quadword address stored in the current address register each data cycle. This
is needed in case of a PCI retry and is also used to index the next data item
in the I/O write/read data buffers. The value in the current address register
corresponds to the address of the data item on the PCI bus (it has the same
canonical time as the PCI data-out register).

The I/O read command address is sent to the PCI after any prior I/O write
transactions have completed (strict ordering is maintained). The PCI returns
the requested data and places it in the I/O read buffer. The contents of this I/O
read buffer are next copied to the I/O read buffer in the DSW and then sent to
the 21164.

Why have the DSW I/O read buffers been replicated in the CIA? The I/O read
buffers in the CIA are provided for the following reasons:

• The path to the DSW might be busy with the end of a prior DMA write
transaction (especially if the data has to be merged with memory data to
build it up to the ECC width).

• At least 64 bits of storage are required for ECC because the PCI can return
32 bits of data at a time.

• It is convenient to handle transaction retries forced by the PCI protocol.
The I/O read buffer in the DSW was provided to build the data up from
64 bits (IOD bus data lines between the CIA and DSW) to the 128 bits
required by the 21164.

I/O read transactions from the 21164 have 8-byte resolution and the CIA
always returns 32 bytes. If smaller resolution is required, sparse space
addressing must be used. Sparse space addressing is described in Chapter 6.

Data is returned in the appropriate byte lanes.

3–10 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

3.2.4 21164 Write Transaction to Noncacheable Space

The 21164 issues write transactions to noncacheable space with longword
resolution. For smaller granularity, sparse space addressing must be used (see
Chapter 6).

Data for I/O write transactions is captured in the I/O write buffer in the DSW.
Four 32-byte buffers are available in the DSW and a further two in the CIA.
This number of entries allows the CIA to sustain maximum bandwidth on a
large copy operation from memory through the 21164-to-I/O space.

The data from these I/O write buffers is sent to the two I/O write buffers in the
CIA: two buffers are provided, allowing one to be emptied to the PCI bus while
the other is being filled. Each 32-byte buffer in the CIA requires a separate
PCI transaction (no merging of the write buffers occurs).

Another benefit of the CIA’s I/O write buffers is simpler data-flow management
when a target PCI device stalls the I/O write transactions.

The address for an I/O write transaction is sent to the CIA I/O port. For a
32-byte aligned dense space write transaction, the I/O write command is either
sent directly to the PCI bus via the bypass path, or queued up in the I/O
address queue. The direct (bypass) path is used if:

• There are no outstanding I/O commands.

• The command is an I/O write command to dense space and the first

16 bytes are mostly valid (like 1111, 1011, 1010, 1001).

This command also goes into the I/O address queue, but only as a convenient
path in the I/O addressing logic section, to get the address into the current
address register.

A total of six I/O write addresses can be queued: the first in the current
address register, two in the 21164 queue, and three in the I/O address queue.
The I/O address queue maintains strict ordering for I/O transactions but does
not maintain strict ordering of I/O write transactions relative to any memory
read or write transactions (see Section 3.3).

Preliminary Edition—Subject to Change—September 1995 3–11

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

3.2.5 DMA Transactions

The PCI address and command are captured in the address/command register
and the data/address register. The address is compared against four address
windows to determine if this PCI command should be accepted or ignored by
the CIA.

Address windows are a requirement of the PCI specification and are software
programmable—they are described in detail in Chapter 6. All PCI commands
destined for memory are accepted by the CIA.

Two registers capture incoming samples from the PCI bus.

• The address register captures the address and command, holding

them for the duration of the transaction.

• The data-in register captures the data, but also captures the

address.

The target window logic is attached to the data-in register. It is located
there to capture a buffer of data (64 bytes) for use with a DMA write
transaction scatter-gather TLB ‘‘miss.’’ The target window logic retries
the master PCI device in case it has more data.

The CIA has released the PCI for further transactions but is busy
servicing the TLB ‘‘miss’’ so must hold the virtual address in the
address register. Should another PCI transaction occur while the CIA
is servicing the TLB ‘‘miss,’’ the CIA will accept that address and
compare it to the target window.

Note

There are three registers associated with each of the four PCI windows:

• Window base register 0–3 (Wn_BASE)—defines the start of the target
window. Wn_BASE[Wn_BASE_SG] determines if the scatter-gather map is
used for the translation.

• Window mask register 0–3 (Wn_MASK)—defines the size of the window.

• Translated base register (Tn_BASE)—holds the base address used to
relocate the PCI address in the 21164’s memory space (for direct mapping)
and is also used to hold the scatter-gather map base address for scatter­gather mapping.

3–12 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

Wn_BASE[Wn_BASE_SG] determines how the PCI address is translated as
follows:

•IfWn_BASE[Wn_BASE_SG] is clear, the address is directly mapped by

concatenating Tn_BASE[CSR_WR_DATA] with the address.

•IfWn_BASE[Wn_BASE_SG] is set, the address is mapped through the

scatter-gather table, allowing any 8KB PCI address to map to any 8KB
memory address.

Figure 3–3 illustrates the mapping. This scatter-gather table is located in
memory, but the CIA provides an 8-entry TLB that caches the most recent
scatter-gather table entries. Each TLB entry holds four consecutive scatter­gather table entries, mapping a contiguous 32KB of virtual PCI addresses to
any four 8KB memory pages.

Figure 3–3 Address Space Overview

21164 CPU
Cached Memory Space (8GB)

8KB
Page

PCI Window

Direct Map

PCI Window

Scatter-Gather

Map

PCI Memory

LJ-04220.AI

Preliminary Edition—Subject to Change—September 1995 3–13

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

3.2.6 DMA Read Transaction

The translated address stored in the PA register is sent to the 21164 through
the flush/read address register and to memory through the memory port. If
the 21164 data cache contains valid modified data, then a copy is sent to the
Bcache-buffer part of one of the two DMA buffers in the DSW and the valid
bit is set. Memory data is always fetched and put in the memory buffer of the
DMA buffer. The PCI-buffer part of the DMA buffer is not used for DMA read
transactions.

When the first valid QW is available in the DSW’s DMA buffer, it is sent to
the DMA read buffer in the CIA through the multiplexers. Any ECC correction
is done in the CIA. From the DMA buffer in the CIA, the data goes from a
register onto the PCI a cycle later. The DMA read data also takes the bypass
path around the multiplexer for as long as the PCI can accept this stream of
data. Once the PCI stalls, then the buffers are used.

3.2.7 DMA Read Transaction (Prefetch)

The PCI supports three types of memory read commands, which are used as
specified in the PCI Local Bus Specification:

• Read—used for small transfers (up to 1/2 a cache line)

• Read line—used for medium transfers (1/2 to 3 cache lines)

• Read multiple—used for large transfers (more than 3 cache lines)

In the PCI environment, most devices assume a processor cache of 32 bytes
(compared to the CIA cache line of 64 bytes). The CIA prefetch strategy is
shown in Table 3–2.

Table 3–2 CIA Prefetch Strategy

PCI Memory Read Command Prefetch Operation

Read None.
Read line Prefetch one block.
Read multiple Prefetch until end of transaction.

3–14 Preliminary Edition—Subject to Change—September 1995

A counter is used to increment the memory block address for prefetching. The
output of this counter goes to the Bcache and memory like a normal DMA read
command address. The returned data is sent to the next free DMA buffer in
the DSW. So as one buffer is being copied down to the CIA, the other is free to
accept DMA prefetched data.

At the end of a transaction all prefetched data in the DMA read buffers is
ignored (that is, no prefetch caching is performed). Prefetching does not
continue over 8KB page boundaries.

The 64-byte DMA read buffer in the CIA acts like two 32-byte halves during
DMA commands—as one half is emptying to the PCI bus, the other half is
being filled.

3.2.8 DMA Write Transaction

The translated address stored in the PA register is sent to the Bcache through
the flush/read address register and also to memory via the memory port. If
the Bcache contains valid (modified) data, the data is sent to the Bcache-buffer
portion of the DMA buffer in the DSW and the Bcache data is invalidated.
Memory data is always fetched and is put in the memory-buffer part of the
DMA buffer.

The DMA write data is taken from the PCI bus and is placed in the DMA write
buffer. If the data is a complete quadword, then ECC is generated and the
data is sent to the PCI-write part of the DMA buffer in the DSW. If the data
is an incomplete quadword, then a merge operation has to be performed. The
valid Bcache or memory quadword is sent to the CIA from the DMA buffer in
the DSW, and the valid bytes of the DMA write data are merged. This merged
quadword then has ECC generated and is sent to the PCI-write buffer portion
of the DMA buffer in the DSW.

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

The DMA buffer in the DSW builds the data up to 64 bytes (the block size)
before sending the data to memory. The memory logic generates the memory
write pulses. The memory address is read from the PA register by way of a
multiplexer.

Note

Should the I/O port be busy with an I/O write/read transaction, the
memory port will be available for DMA write commands.

Preliminary Edition—Subject to Change—September 1995 3–15

DECchip 21171-CA Architecture Overview

3.2 CIA Transactions

One reason for providing a copy of the DMA write buffer in the CIA is that
the data path to the DSW may not be available at the start of a DMA write
transaction It could be busy transferring I/O write transaction data from the
DSW to the I/O write buffers if a 21164 I/O write command had been received
concurrently with a PCI DMA write command.

DMA write transaction data is always written to memory, and is never stored
(cached) in the DMA write buffers across transactions.

3.3 System Data Coherency Issues

The 21164 is the processor in systems using the DECchip 21171 Core Logic
Chipset and the data coherency requirements of the 21164 dominate CIA data
coherency issues. The CIA supports the flush-based data coherency protocol
with a Bcache but with no duplicate tag stores for either the Scache or Bcache.
Therefore the CIA uses the read and flush transactions to probe the 21164
cache.

3.3.1 Basic Properties of the System

The system has these basic properties:

1. The memory arrays do only one thing at a time.

2. A read or write transaction to memory is atomic. No operation of the
memory arrays can occur between the read and write parts of a read­modify-write sequence.

3. The memory array sequence for a 21164 cache ‘‘miss’’ with victim
transaction is atomic in the memory array. A cache miss with victim
transaction causes the 21164 to perform a read miss transaction for the
block required for the cache miss transaction and then a Bcache victim
transaction to write the victim data to memory. No other memory access
can come between the read miss transaction and the Bcache victim
transaction.

4. When ‘‘transaction A’’ gains access to memory it is said to ‘‘own’’ memory.
Once ‘‘transaction A’’ ‘‘owns’’ memory there will be no access for any other
transaction until ‘‘transaction A’’ has completed all of its memory activity.

5. When an I/O TLB ‘‘miss’’ occurs, the CIA issues a read command to the
21164 for the TLB entry and a memory access is also made for this data.
The read command is not issued to the 21164 until memory is owned for
this access.

3–16 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.3 System Data Coherency Issues

6. The CIA processes a PCI device read transaction to memory by issuing

a read command to the 21164 for the data and making a memory access
for the required data. The read command is not issued until memory is
‘‘owned’’ for the memory cycle.

7. A device write transaction to memory causes the CIA to issue a flush

transaction to the 21164 for the data and to start a memory access for the
data. The memory access serves to write data obtained from the 21164
and also serves to write the data from the PCI device to memory. The CIA
does not issue the flush command until memory is ‘‘owned’’ for the memory
write transaction.

8. We can conclude that the 2-step sequences described in 5, 6, and 7 are all

mutually atomic. In each case, the 2-step sequence is a probe of 21164 and
a memory cycle. For any pair of sequences of the types describe in 5, 6,
and 7, both steps of one of the sequences happened entirely before either of
the two steps of the other sequences.

3.3.2 Post and Run I/O Write Data Coherency

The Alpha architecture allows ‘‘posted’’ or ‘‘buffered’’ write transactions to I/O
devices, allowing the CIA to buffer write transactions from the 21164 to a PCI
device. Several read transactions from a PCI device to main memory might
be completed while write transactions to the same PCI device are buffered.
The usual way for a software programmer to ensure that the write data has
reached the device is to read a register on the same device.

The CIA performs the following operations to implement the Alpha architecture
post and run feature.

• Before a read transaction to an I/O location is processed, all preceding

21164 write transactions to devices are flushed out of the buffers.

• Before a read transaction from a PCI device to main memory is processed

all preceding write transactions by the PCI device to main memory are
flushed out of the write buffers.

Preliminary Edition—Subject to Change—September 1995 3–17

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

3.4 CIA Memory ras_h, cas_h, and Address Operation

The technique used by the CIA to eliminate ras_h cycles for victim write
transactions is described here. The method is transparent to software.

3.4.1 Traditional Mapping of 21164 Address to Memory Address

The traditional approach of mapping the 21164 address bit for bit to the
memory address is shown in Figure 3–4.

Figure 3–4 Traditional Mapping to a Memory Address

21164

Block Offset

Tag Index

Cache Address

Physical
Address

Bank Select Row Column

Because a cache is much smaller than available memory, multiple memory
locations will correspond to the same cache location. This correspondence is
shown in the left-hand side of Figure 3–5 where data A1, data B1, and data C1
all map to the same cache location (A1B1C1).

3–18 Preliminary Edition—Subject to Change—September 1995

Memory Address

LJ-04221.AI

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

Figure 3–5 Traditional Victim Cache to Memory Correspondence

Data A1
Data A2
Data A3

A1B1C1

Bcache

Data B1
Data B2
Data B3

Data C1
Data C2
Data C3

Typical Memory

Address Arrangement

LJ-04222.AI

Suppose that data A1 currently resides in the Bcache, but the 21164 wants to
access data C1. A cache miss will occur that will fetch data C1 and overwrite
A1 in the cache. If A1 is the only valid copy of the data (for example, a 21164
write transaction had previously updated A1), then A1 has to be written to
memory before data C1 can be written over data A1. The displaced data A1 is
referred to as a victim.

Look again at Figure 3–5 and notice that in the traditional memory addressing
scheme, data C1 and the potential victim (data A1) are well separated in
memory . They are separated by a multiple of n times the cache size. This
sparse distribution of potential victim locations means a read fill block and its
victim may not reside in the same memory page.

Preliminary Edition—Subject to Change—September 1995 3–19

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

3.4.2 CIA Mapping of 21164 Address to Memory Address

The highest tag bits are used for memory bank selection in both the traditional
and CIA address mapping schemes.

The CIA shuffles the memory address bits so that some of the high-order 21164
address bits (part of the Bcache tag) become the memory column address and
the low-order CPU address bits (part of the cache index) become the memory
row address as shown in Figure 3–6.

Figure 3–6 Modified Mapping to a Memory Address

Block Offset

Tag Index

Cache Address

21164
Physical
Address

Bank Select Row Column

Interchanging the memory row and column address bits, the write transaction
target and the potential victim locations reside in the same SIMMs, even
within the same row within the SIMMs, as shown in Figure 3–7. The chance
of a cache block and its victim residing in the same memory page is greatly
increased. This technique will remove all ras_h cycles from victim write
transactions. In fact, all victims will be able to share an ras_h signal with the
read miss transaction.

3–20 Preliminary Edition—Subject to Change—September 1995

Memory Address

LJ-04223.AI

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

Figure 3–7 CIA Victim Cache to Memory Correspondence

Data A1
Data B1
Data C1

A1B1C1

Bcache

Data A2
Data B2
Data C2

Data A3
Data B3
Data C3

21171 Memory

Address Arrangement

LJ-04224.AI

However, this approach hinders DMA transactions. Consecutive blocks (data
A1, data A2, and data A3), as shown in Figure 3–7, are scattered a page apart
by using this memory addressing scheme. This implies that consecutive DMA
read/write transaction blocks will require a ras_h cycle, reducing possible
bandwidth. The traditional scheme does not suffer this problem.

A compromise between the two schemes, as shown in Figure 3–8, is used by
the CIA. The four low-order bits of the index map straight to the low-order
bits of the column address (just like in a traditional scheme). The remaining
high-order index bits go to the memory row-address. The remainder of the
column address uses the tag portion of the physical address.

Preliminary Edition—Subject to Change—September 1995 3–21

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

Figure 3–8 CIA Mapping to a Memory Address

Block Offset

Tag Index

Cache Address

21164
Physical
Address

Bank Select Row Column

Memory Address

LJ-04225.AI

Using this compromise scheme, a DMA transaction will march through four
64-byte blocks (64 longwords), on average, before requiring a ras_h cycle. This
constitutes a large DMA transfer, minimizing the ras_h penalty.

The logic that determines if a ras_h cycle is required is located in the memory
logic block of Figure 3–2.

3–22 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

Figures 3–9 and 3–10 show the relationship between CPU/DMA address bits
<28:04> and column and row address bits to memory. The memory address
maps for the 128-bit data path and the 256-bit data path are shown in Tables
3–9 and 3–10, respectively. The user specifies row type in MBAn[ROW_TYPE]
(MBAn<2:1>).

Figure 3–9 Memory Address Maps for 128-Bit Data Path

For 128-Bit-Wide Memory:

Row

Type

Row

Type

Note:
CPU tag index requires a minimum cache size of 2MB (CPU/DMA address bits <21:7> required).

DRAM

Size

01

16MB

10 64MB

DRAM

Size

01

16MB

10 64MB

DRAM

Configuration

10R x 10C4MB00
11R x 11C

12R x 10C
12R x 12C

13R x 11C

DRAM

Configuration

10R x 10C4MB00
11R x 11C

12R x 10C
12R x 12C

13R x 11C

28 27 26 25 24 23 22

-

-

-

-

-

C9

C9

R1

R1

R1

-

-

C8

C7

-

-

C8

C7

-

-

C8

C7

R0

-

-

C4

R0

R0

R11

-

C10
R11

-

-

-

-

-

-

-

-

-

-

C5

R3

R3

R3

-

-

C4

-

-

C10

R2

-

-

R2

-

-

R2

-

-

-

-

-

-

-

C3

15 14 13 12 11 10 09
R5

R4

-

-

R5

R4

-

-

R5

R4

-

-

21

20

19

18

17

-

-

-

R9

R8

C6

C5

-

-

-

R10

-

R10

-

07

-

C2

-

C2

-

C2

R9

-

R9

-

06

-

C1

-

C1

-

C1

C6

-

-

C6

08

-

-

C3

-

C3

R12

-

C11

-

R8

-

R8

-

05*

-

C0

-

C0

-

C0

R7

-

R7

-

R7

-

04*

-

C9

-

C5

-

C4

LJ-04399.AI5

16
R6

-

R6

-

R6

-

Preliminary Edition—Subject to Change—September 1995 3–23

DECchip 21171-CA Architecture Overview

3.4 CIA Memory ras_h, cas_h, and Address Operation

Figure 3–10 Memory Address Maps for 256-Bit Data Path

For 256-Bit-Wide Memory:

Row

Type

Row

Type

Note:
CPU tag index requires a minimum cache size of 2MB (CPU/DMA address bits <21:7> required).

DRAM

Size

01

16MB

10 64MB

DRAM

Size

01

16MB

10 64MB

DRAM

Configuration

10R x 10C4MB00
11R x 11C

12R x 10C
12R x 12C

13R x 11C

DRAM

Configuration

10R x 10C4MB00
11R x 11C

12R x 10C
12R x 12C

13R x 11C

28 27 26 25 24 23 22

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

C4

C3

15 14 13 12 11 10 09
R5

R4

-

-

R5

R4

-

-

R5

R4

-

-

C5

C5

R3

R3

R3

-

C4

-

-

C10

R2

-

-

R2

-

-

R2

-

-

C9

C9

C9

R1

R1

R1

-

C8

C7

-

-

C8

C7

-

-

C8

C7

R0

-

-

C4

R0

R0

R11

-

C10
R11

-

-

-

21

20

19

18

17

-

-

-

R9

R8

C6

C5

-

-

-

R10

-

R10

-

07

-

C2

-

C2

-

C2

R9

-

R9

-

06

-

C1

-

C1

-

C1

C6

-

-

C6

08

-

-

C3

-

C3

R12

-

C11

-

R8

-

R8

-

05*

-

C0

-

C0

-

C0

R7

-

R7

-

R7

-

04*

-

-

-

-

-

-

LJ-04400.AI5

16
R6

-

R6

-

R6

-

3–24 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.5 MB and LOCK Instructions

The MB (memory barrier) and LOCK instructions are described in this section.

3.5.1 MB Instruction

The MB instruction may or may not be disabled from leaving the 21164 by
making the BC_CONTROL [EI_CMD_GRP3] bit clear. If BC_CONTROL
[EI_CMD_GRP3] is clear, the CIA should never acknowledge receipt of an MB
instruction.

CACK_EN [MB_ENABLE], in the CIA, enables or disables the CIA from
acknowledging receipt of an MB instruction from the 21164. If CACK_EN
[MB_ENABLE] is clear, the CIA will treat an MB instruction as a NOP. See
Section 3.3.2.

3.5.2 LOCK Instruction

The CIA has to contend with locks originating on either the 21164 or the
PCI. There are two cases that require that the 21164 internal lock state on
a block be cleared (from a system point of view). The first is during a DMA
write transaction to the locked block and the second is when a PCI device has
established a lock.

3.5 MB and LOCK Instructions

The things to consider for system lock behavior are:

• DMA write transaction case—The 21164 maintains its lock flag and

lock address in its bus interface unit (BIU). This lock status is correctly
maintained, even if the locked block is displaced from the Scache, as long
as the system sends all DMA write FLUSH commands to the 21164 (no
duplicate cache tag).

• PCI lock established—A PCI device can only establish a lock on a 16-byte

block of data during a DMA read transaction. Once the lock is established
by the successful DMA read transaction, the PCI device has exclusive
access to that 16-byte block (the PCI target may lock a larger block). This
PCI lock allows the device to do an atomic read-modify-write on a 16-byte
data unit.

The Alpha and PCI architectures have different mechanisms for establishing a
lock:

• For PCI architecture, it is a successful read transaction (with the PCI

LOCK signal asserted) that establishes a lock.

• For Alpha architecture, it is a successful write transaction (STn_C) that

establishes a lock.

Preliminary Edition—Subject to Change—September 1995 3–25

DECchip 21171-CA Architecture Overview

3.5 MB and LOCK Instructions

So, a PCI read transaction with the PCI LOCK signal asserted must be treated
by the 21164 as a write transaction (that is, for the Alpha architecture, it
must have the same effect as a write transaction from some other processor).
Example 3–1 shows an example of the 21164 and PCI competing for a memory
flag.

Example 3–1 21164 and PCI Device Lock Contention

21164 Atomic Update | PCI Device Atomic Update

------------------- | ------------------------

try_again: |

LDQ_L R1, mem_flag |
{ modify memory flag } | READ/LOCK mem_flag
STQ_C R1, mem_flag | { modify mem_flag }

BEQ R,no_store |

------------------ |

------------------ |

no_store: |

{ check for excessive iterations} |
BR try_again |

|

| WRITE/UNLOCK mem_flag

|

Both the 21164 and the PCI device are attempting to perform an atomic read­modify-write operation on a memory flag (a semaphore). The 21164 begins
with a LDQ_L instruction but will not know if the update is successful until
the companion STQ_C instruction completes successfully.

Assume that the PCI device performs a PCI read transaction with the PCI
LOCK signal asserted, and obtains the lock to the memory flag before the
21164 STQ_C instruction is executed. The 21164’s STQ_C instruction must
fail, otherwise, the 21164 and the PCI device will both believe they have
successfully modified the flag.

Before a PCI device establishes the PCI lock, the 21164 must clear its lock
flag. The CIA must perform a flush transaction to the locked block, causing the
21164 to clear its lock flag. Unfortunately, the system must not only perform
a DMA read transaction, but must also write the flushed block to memory.
Once the CIA successfully sends the data to the PCI device, the PCI lock is
established.

3–26 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Architecture Overview

3.5 MB and LOCK Instructions

While the PCI lock is in effect, the 21164 may attempt to refill the flushed
block. This will happen if a loop, as shown in Example 3–1, is repeatedly
executing an LDx_L instruction. The requested block cannot be provided until
the PCI lock has completed because once the block is in the 21164 internal
cache, the CIA loses control of the block.

Initially, the CIA could prevent the 21164 from setting its internal lock flag for
the block by using the 21164 input signal line system_lock_flag_h. The next
time the LDx_L/STn_C loop, the 21164 will have a cache hit on the block and
will be unaware of the system lock state, so the loop will succeed this second
time.

The CIA lock rules are:

• The 21164 system_lock_flag_h input signal line is not connected to the

CIA and is always tied true.

• All DMA write transactions will result in the CIA performing a flush

transaction to the 21164.

• All DMA read transactions with the PCI LOCK signal asserted will result

in the CIA performing a flush transaction to the 21164. The CIA must
write the flushed block to memory. The internal CIA lock address register
will be set with the locking address.

• If the 21164 requests a fill that hits the CIA lock address register, then the

fill is stalled until the PCI lock state is relinquished by the PCI device.

• The 21164 lock transaction will be treated as a NOP for systems with

duplicate tag stores.

• The 21164 write transaction with lock will be treated as a write

transaction.

3.5.3 Locks to Uncached Space

The CIA does not support LDx_L and STn_C to noncacheable space. They are
converted to LDx and STn.

Preliminary Edition—Subject to Change—September 1995 3–27

DECchip 21171-CA Control and Status

This chapter describes the DECchip 21171-CA (CIA) control and status
registers (CSRs). It also provides information about programming memory
timing, configuring memory, and initializing the backup cache (Bcache).

Programmers must write only zeros to register fields defined as
reserved.

4.1 DECchip 21171-CA Registers

The DECchip 21171-CA CSRs are 32 bits wide and are located on NATURALLY
ALIGNED 64-byte addresses. Write transactions to read-only registers
could result in UNPREDICTABLE behavior while read transactions are
nondestructive. Only zeros should be written to reserved bits. The register
descriptions contain the initialized states.

4

Registers

Note

The DECchip 21171-CA CSRs are presented here in seven groups:

• General registers

• Diagnostic registers

• Performance monitor registers

• Error registers

• System configuration registers

• PCI address and scatter-gather registers

• Address translation registers

Preliminary Edition—Subject to Change—September 1995 4–1

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

The Alpha 21164 microprocessor CSRs, which are 64 bits wide, are described
in the Alpha 21164 Microprocessor Hardware Reference Manual. The CSRs of
most interest to uniprocessor system designers are:

• Scache control register (SC_CTL)

• Bcache control register (BC_CONTROL)

• Bcache configuration register (BC_CONFIG)

4.1.1 DECchip 21171-CA General Registers

Table 4–1 lists the DECchip 21171-CA (CIA) general registers and Section 4.2
shows and describes the individual registers.

Table 4–1 DECchip 21171-CA General Registers

Address Mnemonic Name

87.4000.0080 CIA_REV CIA revision register

87.4000.00C0 PCI_LAT PCI latency register

87.4000.0100 CIA_CTRL CIA control register

87.4000.0400 HAE_MEM Hardware address extension memory register

87.4000.0440 HAE_IO Hardware address extension I/O register

87.4000.0480 CFG Configuration register

87.4000.0600 CACK_EN CIA acknowledgment enable register

4.1.2 DECchip 21171-CA Diagnostic Registers

Table 4–2 lists the DECchip 21171-CA (CIA) diagnostic registers and
Section 4.3 shows and describes the individual registers.

Table 4–2 DECchip 21171-CA Diagnostic Registers

Address Mnemonic Name

87.4000.2000 CIA_DIAG CIA diagnostic control register

87.4000.3000 DIAG_CHECK Diagnostic check register

4–2 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

4.1.3 DECchip 21171-CA Performance Monitor Registers

Table 4–3 lists the DECchip 21171-CA (CIA) performance monitor registers
and Section 4.4 shows and describes the individual registers.

Table 4–3 DECchip 21171-CA Performance Monitor Registers

Address Mnemonic Name

87.4000.4000 PERF_MONITOR Performance monitor register

87.4000.4040 PERF_CONTROL Performance control register

4.1.4 DECchip 21171-CA Error Registers

Table 4–4 lists the DECchip 21171-CA (CIA) error registers and Section 4.5
shows and describes the individual registers.

Table 4–4 DECchip 21171-CA Error Registers

Address Mnemonic Name

87.4000.8000 CPU_ERR0 CPU error information register 0

87.4000.8040 CPU_ERR1 CPU error information register 1

87.4000.8200 CIA_ERR CIA error register

87.4000.8240 CIA_STAT CIA status register

87.4000.8280 ERR_MASK CIA error mask register

87.4000.8300 CIA_SYN CIA syndrome register

87.4000.8400 MEM_ERR0 CIA memory port status register 0

87.4000.8440 MEM_ERR1 CIA memory port status register 1

87.4000.8800 PCI_ERR0 PCI error register 0

87.4000.8840 PCI_ERR1 PCI error register 1

87.4000.8880 PCI_ERR2 PCI error register 2

Preliminary Edition—Subject to Change—September 1995 4–3

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

4.1.5 DECchip 21171-CA System Configuration Registers

Table 4–5 lists the DECchip 21171-CA (CIA) system configuration registers and
Section 4.6 shows and describes the individual registers.

Table 4–5 DECchip 21171-CA System Configuration Registers

Address Mnemonic Name

87.5000.0000 MCR Memory configuration register

87.5000.0600 MBA0 Memory base address register 0

87.5000.0680 MBA2 Memory base address register 2

87.5000.0700 MBA4 Memory base address register 4

87.5000.0780 MBA6 Memory base address register 6

87.5000.0800 MBA8 Memory base address register 8

87.5000.0880 MBAA Memory base address register 10

87.5000.0900 MBAC Memory base address register 12

87.5000.0980 MBAE Memory base address register 14

87.5000.0B00 TMG0 Memory timing information register 0

87.5000.0B40 TMG1 Memory timing information register 1

87.5000.0B80 TMG2 Memory timing information register 2

4–4 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

4.1.6 DECchip 21171-CA PCI Address and Scatter-Gather Registers

Table 4–6 lists the DECchip 21171-CA (CIA) PCI address and scatter-gather
registers, and Section 4.7 describes the individual registers.

Table 4–6 DECchip 21171-CA PCI Address and Scatter-Gather Registers

Address Mnemonic Name

87.6000.0100 TBIA Scatter-gather translation buffer invalidate

87.6000.0400 W0_BASE Window base register 0

87.6000.0440 W0_MASK Window mask register 0

87.6000.0480 T0_BASE Translated base register 0

87.6000.0500 W1_BASE Window base register 1

87.6000.0540 W1_MASK Window mask register 1

87.6000.0580 T1_BASE Translated base register 1

87.6000.0600 W2_BASE Window base register 2

87.6000.0640 W2_MASK Window mask register 2

87.6000.0680 T2_BASE Translated base register 2

87.6000.0700 W3_BASE Window base register 3

87.6000.0740 W3_MASK Window mask register 3

87.6000.0780 T3_BASE Translated base register 3

87.6000.07C0 W_DAC Window Base DAC register

register

Preliminary Edition—Subject to Change—September 1995 4–5

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

4.1.7 DECchip 21171-CA Address Translation Registers

Table 4–7 lists the DECchip 21171-CA (CIA) address translation registers and
Section 4.8 describes the individual registers.

Table 4–7 DECchip 21171-CA Address Translation Registers

Address Mnemonic Name

87.6000.0800 LTB_TAG0 Lockable translation buffer Tag 0

87.6000.0840 LTB_TAG1 Lockable translation buffer Tag 1

87.6000.0880 LTB_TAG2 Lockable translation buffer Tag 2

87.6000.08C0 LTB_TAG3 Lockable translation buffer Tag 3

87.6000.0900 TB_TAG0 Translation buffer tag 0

87.6000.0940 TB_TAG1 Translation buffer tag 1

87.6000.0980 TB_TAG2 Translation buffer tag 2

87.6000.09C0 TB_TAG3 Translation buffer tag 3

87.6000.1000 TB0_PAGE0 Translation buffer 0 page 0

87.6000.1040 TB0_PAGE1 Translation buffer 0 page 1

87.6000.1080 TB0_PAGE2 Translation buffer 0 page 2

87.6000.10C0 TB0_PAGE3 Translation buffer 0 page 3

87.6000.1100 TB1_PAGE0 Translation buffer 1 page 0

87.6000.1140 TB1_PAGE1 Translation buffer 1 page 1

87.6000.1180 TB1_PAGE2 Translation buffer 1 page 2

87.6000.11C0 TB1_PAGE3 Translation buffer 1 page 3

87.6000.1200 TB2_PAGE0 Translation buffer 2 page 0

87.6000.1240 TB2_PAGE1 Translation buffer 2 page 1

87.6000.1280 TB2_PAGE2 Translation buffer 2 page 2

87.6000.12C0 TB2_PAGE3 Translation buffer 2 page 3

4–6 Preliminary Edition—Subject to Change—September 1995

(continued on next page)

DECchip 21171-CA Control and Status Registers

4.1 DECchip 21171-CA Registers

Table 4–7 (Cont.) DECchip 21171-CA Address Translation Registers

Address Mnemonic Name

87.6000.1300 TB3_PAGE0 Translation buffer 3 page 0

87.6000.1340 TB3_PAGE1 Translation buffer 3 page 1

87.6000.1380 TB3_PAGE2 Translation buffer 3 page 2

87.6000.13C0 TB3_PAGE3 Translation buffer 3 page 3

87.6000.1400 TB4_PAGE0 Translation buffer 4 page 0

87.6000.1440 TB4_PAGE1 Translation buffer 4 page 1

87.6000.1480 TB4_PAGE2 Translation buffer 4 page 2

87.6000.14C0 TB4_PAGE3 Translation buffer 4 page 3

87.6000.1500 TB5_PAGE0 Translation buffer 5 page 0

87.6000.1540 TB5_PAGE1 Translation buffer 5 page 1

87.6000.1580 TB5_PAGE2 Translation buffer 5 page 2

87.6000.15C0 TB5_PAGE3 Translation buffer 5 page 3

87.6000.1600 TB6_PAGE0 Translation buffer 6 page 0

87.6000.1640 TB6_PAGE1 Translation buffer 6 page 1

87.6000.1680 TB6_PAGE2 Translation buffer 6 page 2

87.6000.16C0 TB6_PAGE3 Translation buffer 6 page 3

87.6000.1700 TB7_PAGE0 Translation buffer 7 page 0

87.6000.1740 TB7_PAGE1 Translation buffer 7 page 1

87.6000.1780 TB7_PAGE2 Translation buffer 7 page 2

87.6000.17C0 TB7_PAGE3 Translation buffer 7 page 3

Preliminary Edition—Subject to Change—September 1995 4–7

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2 DECchip 21171-CA General Registers

This section defines and describes the DECchip 21171-CA general registers.

4.2.1 CIA Revision Register (CIA_REV)

Figure 4–1 CIA Revision Register (87.4000.0080)

31 08 07 00

Reserved
CIA_REV

Table 4–8 CIA Revision Register

Field Name Type Description

LJ-04226.AI

<7:0> CIA_REV RO,CIA Rev CIA revision field.

<31:8> Reserved RO,0 —

0—Pass 1 CIA chip present.
1—Pass 2 CIA chip present.

4–8 Preliminary Edition—Subject to Change—September 1995

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.2 PCI Latency Register (PCI_LAT)

Figure 4–2 PCI Latency Register (87.4000.00C0)

31 08 0716 15 00

Reserved
LATENCY
Reserved

Table 4–9 PCI Latency Register

Field Name Type Description

<7:0> Reserved RO,0 —
<15:8> LATENCY RW,0 PCI master latency timer in PCI clock cycles.
<31:16> Reserved RO,0 —

LJ-04227.AI

Preliminary Edition—Subject to Change—September 1995 4–9

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.3 CIA Control Register (CIA_CTRL)

Figure 4–3 CIA Control Register (87.4000.0100)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN_DMA_RD_PERF
Reserved
RM_TYPE
Reserved
RL_TYPE
Reserved
RD_TYPE
EN_ARB_LINK
ARB_CPU_EN
CPU_FLUSHREQ_EN
IO_FLUSHREQ_EN
CSR_IOA_BYPASS
CON_IDLE_BC
ASSERT_IDLE_BC
ECC_CHK_EN
MCHK_ERR_EN
FILL_ERR_EN
PERR_EN
ADDR_PE_EN
PCI_ACK64_EN
PCI_REQ64_EN
PCI_MEM_EN
PCI_MST_EN
FST_BB_EN
PCI_LOOP_EN
PCI_LOCK_EN
PCI_EN

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DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

Table 4–10 CIA Control Register

Field Name Type Description

<0> PCI_EN RW,0 0—CIA asserts reset to the PCI.

<1> PCI_LOCK_EN RW,0 0—CIA will not lock when the PCI tries to lock it.

<2> PCI_LOOP_EN RW,0 0—CIA will not respond as a target when it is the

<3> FST_BB_EN RW,0 0—CIA will not initiate fast back-to-back PCI

<4> PCI_MST_EN RW,0 0—CIA will not initiate PCI transactions.

<5> PCI_MEM_EN RW,0 0—CIA will not respond to PCI transactions.

<6> PCI_REQ64_EN RW,0 0—CIA will not request 64-bit PCI data transactions.

<7> PCI_ACK64_EN RW,0 0—CIA will not accept 64-bit PCI data transactions.

<8> ADDR_PE_EN RW,0 0—CIA will not check PCI address parity errors.

<9> PERR_EN RW,0 0—CIA will not check PCI data parity errors.

<10> FILL_ERR_EN RW,0 0—CIA will not assert fill_error_h on sysBus.

<11> MCHK_ERR_EN RW,0 0—CIA will not assert error_h on sysBus.

<12> ECC_CHK_EN RW,0 0— CIA will not check IOD data for ECC errors.

<13> ASSERT_IDLE_BC RW,0 0—CIA will not assert idle_bc_h on sysBus when

1—CIA does not assert reset to the PCI.

1—CIA will lock when the PCI tries to lock it.

master.
1—CIA will respond as a target when it is the
master.

transactions.
1—CIA will initiate fast back-to-back PCI
transactions.

1—CIA will initiate PCI transactions.

1—CIA will respond to PCI transactions.

1—CIA will request 64-bit PCI data transactions.

1—CIA will accept 64-bit PCI data transactions.

1—CIA will check PCI address parity errors.

1—CIA will check PCI data parity errors.

1—CIA will assert fill_error_h if an error occurs
during a 21164 read miss transaction.

1—CIA will assert error_h to report system
machine check conditions.

1—CIA will check IOD data for ECC errors.

asserting addr_bus_req_h.
1—CIA will assert idle_bc_h when asserting
addr_bus_req_h.

(continued on next page)

Preliminary Edition—Subject to Change—September 1995 4–11

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

Table 4–10 (Cont.) CIA Control Register

Field Name Type Description

<14> CON_IDLE_BC RW,0 0—CIA may generate a noncontiguous idle_bc_h

<15> CSR_IOA_BYPASS RW,0 0—CIA will not bypass the I/O address queue.

<16> IO_FLUSHREQ_

EN

<17> CPU_FLUSHREQ_ENRW,0 See IO_FLUSHREQ_EN and Table 4–11.

<18> ARB_CPU_EN RW,0 0—Disable the bypass path from the 21164 into the

<19> EN_ARB_LINK RW,0 0—Disable CPU memory read transactions from

<21:20> RD_TYPE RW,0 This field controls the prefetch algorithm used for

<23:22> Reserved RO,0 —
<25:24> RL_TYPE RW,0 This field controls the prefetch algorithm used for

<27:26> Reserved RO,0 —
<29:28> RM_TYPE RW,0 This field controls the prefetch algorithm used

<30> Reserved RO,0 —
<31> EN_DMA_RD_

PERF

RW,0 Used in combination with CPU_FLUSHREQ_EN.

RW,1 0—Disable the DMA read performance logic.

signal.
1—CIA will guarantee that the idle_bc_h signal is
contiguous.

1—CIA will bypass the I/O address queue. See
Table 4–11.

The two bits control the CIA’s response to a PCI
master, causing a flush request to the 21164.

memory and IOA queue.
1—Enable the bypass path from the 21164 into the
memory and IOA queue.

creating an arbitration link (sharing a common ras
cycle).
1—Enable CPU memory read transactions to create
an arbitration link.

PCI memory read commands. See Table 4–12.

PCI memory read line commands. See Table 4–12.

for PCI memory read multiple commands. See
Table 4–12.

1—Enable the DMA read performance logic.

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DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

Table 4–11 CPU and I/O Flush Request

IO_FLUSH_REQ_EN CPU_FLUSH_REQ_EN Response

0 0 Assert mem_ack_l immediately.
0 1 Assert mem_ack_l immediately and do not

1 0 Illegal.
1 1 Wait until IOA queue is empty, then assert

Table 4–12 PCI READ Prefetch Algorithm

RL_TYPE Type Description

allow new CPU commands to proceed.

mem_ack_l but do not allow new CPU
commands to proceed.

0 0 Short Fetch requested longword or quadword and the remainder of

0 1 Medium Prefetch next block and no more. Will not cross 8KB page

1 0 Long Keep prefetching until PCI transaction completes. Will not

1 1 Reserved —

the cache block.

boundary.

cross 8KB page.

Preliminary Edition—Subject to Change—September 1995 4–13

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.4 Hardware Address Extension Memory Register (HAE_MEM)

This hardware address extension register is used to extend a PCI sparse-space
memory address up to the full 32-bit PCI address.

In sparse-addressing mode, the 21164 address provides the low-order PCI
address bits. The high-order PCI address bits <31:26> are obtained from either
the hardware address extension register or the 21164 address, depending on
sparse regions, as shown in Table 4–13.

Figure 4–4 Hardware Address Extension Memory Register (87.4000.0400)

31 29 28 16 15 11 10 08 07 02 01 00

Region 1
Reserved
Region 2
Reserved
Region 3
Reserved

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LJ-04229.AI

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

Table 4–13 HAE_MEM High-Order Sparse-Space Bits

Region

1

1

<31> <30> <29> <28> <27> <26>

1 HAE_MEM HAE_MEM HAE_MEM 21164 21164 21164

<31> <30> <29> <33> <32> <31>

2 HAE_MEM HAE_MEM HAE_MEM HAE_MEM HAE_MEM 21164

<15> <14> <13> <12> <11> <31>

3 HAE_MEM HAE_MEM HAE_MEM HAE_MEM HAE_MEM HAE_MEM

<7> <6> <5> <4> <3> <2>

Region 1 is 80.0000.0000 to 83.FFFF.FFFF.
Region 2 is 84.0000.0000 to 84.FFFF.FFFF.
Region 3 is 85.0000.0000 to 85.7FFF.FFFF.

Table 4–14 lists the address range of each of the three regions.

Table 4–14 Hardware Address Extension Memory Register

Field Name Type 21164 Address Range

PCI Address

<31:29> Region 1 RW,0 80.0000.0000–83.FFFF.FFFF
<28:16> Reserved RW,0 —
<15:11> Region 2 RW,0 84.0000.0000–84.FFFF.FFFF
<10:8> Reserved RW,0 —
<7:2> Region 3 RW,0 85.0000.0000–85.7FFF.FFFF
<1:0> Reserved RW,0 —

Initializing this register to 0000.202816will make all three regions contiguous
starting at PCI address 0.

Preliminary Edition—Subject to Change—September 1995 4–15

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.5 Hardware Address Extension I/O Register (HAE_IO)

Figure 4–5 Hardware Address Extension I/O Register (87.4000.0440)

31 25 24 00

HAE_IO
Reserved

This hardware address extension register is used to extend a PCI sparse-space
I/O address up to the full 32-bit PCI address. In sparse-addressing mode, the
21164 address provides the PCI address <24:0> and HAE_IO provides <31:25>.

At power-up this register is set to zero. In this case, sparse I/O region A and
region B both map to the lower 32MB of sparse I/O space. Setting HAE_IO to
0200 0000 will make regions A and B consecutive in the lower 64MB of PCI
I/O space.

Table 4–15 Hardware Address Extension I/O Register

Field Name Type Description

LJ-04230.AI

<24:0> Reserved RO,0 —
<31:25> HAE_IO RW,0 In sparse-address mode, this field provides

4–16 Preliminary Edition—Subject to Change—September 1995

address bits <31:25>.

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.6 Configuration Register (CFG)

The CFG field bits are used as the low two address bits during an access to
PCI configuration space.

Figure 4–6 Configuration Register (87.4000.0480)

31 02 01 00

Reserved
CFG

Table 4–16 Configuration Register

Field Name Type Description

<1:0> CFG RW,0 PCI configuration space access type:

CFG<1:0> Meaning

0 0 Type 0 configuration cycle
0 1 Type 1 configuration cycle
1 x Reserved

LJ-04231.AI

<31:2> Reserved RO,0 —

Preliminary Edition—Subject to Change—September 1995 4–17

DECchip 21171-CA Control and Status Registers

4.2 DECchip 21171-CA General Registers

4.2.7 CIA Acknowledgment Enable Register (CACK_EN)

The CIA acknowledgment register (CACK_EN) allows software to decide if
the CIA will acknowledge receipt any of four particular commands from the
21164 or to ignore any of these commands (NOP response).

Figure 4–7 CIA Acknowledgment Enable Register (87.4000.0600)

31 04 03 02 01 00

Reserved
BC_VICTIM_EN
SET_DIRTY_EN
MB_EN
LOCK_EN

Table 4–17 CIA Acknowledgment Enable Register

Field Name Type Description

LJ-04232.AI

<0> LOCK_EN RW,1 1—Enables CIA to acknowledge receipt of a

<1> MB_EN RW,1 1—Enables CIA to acknowledge receipt of an MB

<2> SET_DIRTY_EN RW,1 1—Enables CIA to acknowledge receipt of a SET

<3> BC_VICTIM_EN RW,1 1—Enables CIA to acknowledge receipt of

<31:4> Reserved RO,0 —

4–18 Preliminary Edition—Subject to Change—September 1995

LOCK command from the 21164.

command from 21164.

DIRTY command from the 21164.

a BC_VICTIM command from the 21164.