Page 1
DM9000A
APPLICATION NOTES
DM9000A
16 / 8 Bit Ethernet Controller
with General Processor Interface
Application Notes V1.21
Technical Reference Manual
Davicom Semiconductor, Inc
Preliminary 1
Version: DM9000A-AN-V121
November 27, 2007
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DM9000A
APPLICATION NOTES
1 INTRODUCTION.................................................................................................6
1.1 General Description.................................................................................................................. 6
2 GENERAL PROCESSOR BUS DESCRIPTION...............................................7
2.1 Typical Signal Connection with Processor Bus.........................................................................7
2.1.1 Pin Function Table.............................................................................................................8
2.1.2 Processor Parallel Bus 8/ 16-Bit Mode Setting..................................................................8
2.1.3 Command Type...................................................................................................................9
3 SYSTEM HARDWARE DESIGN......................................................................10
3.1 How to Select Chip..................................................................................................................10
3.2 Strap Pins Setting....................................................................................................................10
3.3 Serial EEPROM Operation.....................................................................................................10
3.3.1 EEPROM Format.............................................................................................................11
3.4 GPIO Pins Setting...................................................................................................................15
3.5 Schematic Reference Design...................................................................................................17
3.5.1 Application Schematics for 8-Bit and 16-Bit....................................................................17
4 RESET OPERATION AND PHY POWER-DOWN MODE...........................19
4.1 Power On Reset.......................................................................................................................19
4.2 Software Reset.........................................................................................................................19
4.3 PHY Power Down Mode.........................................................................................................19
4.3.1 GPR PHYPD Setting........................................................................................................20
4.3.2 PHY Register Setting........................................................................................................20
5 HOW TO PROGRAM DM9000A......................................................................21
5.1 How to Read/ Write DM9000A Register .................................................................................21
5.2 Driver Initializing Steps..........................................................................................................22
5.3 How to Read/ Write EEPROM Data.......................................................................................23
5.3.1 HOWTO Read EEP ROM D ata......................................................................................23
5.3.2 HOWTO Write EEPROM Data......................................................................................24
5.4 How to Read/ Write PHY Register ..........................................................................................26
5.4.1 HOWTO Read PHY Register..........................................................................................26
5.4.2 HOWTO Write PHY Register .........................................................................................27
5.5 How to Transmit Packets ........................................................................................................28
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DM9000A
APPLICATION NOTES
5.5.1 Packet Transmission.......................................................................................................28
5.5.2 To Check a Completion Flag..........................................................................................29
5.6 How to Receive Packets..........................................................................................................30
5.6.1 Receive Interrupt Service Routine..................................................................................30
5.6.2 Packet Reception............................................................................................................31
5.6.3 To Check the Packet Status and Length..........................................................................31
5.6.4 Receive the Packet's Data ..............................................................................................32
6 THE OTHERS.....................................................................................................33
6.1 How to transmit and receive more than 2048-byte packets.....................................................33
6.2 The performance of DM9000A................................................................................................33
6.3 WOL (Wake-up on LAN)..........................................................................................................33
6.4 IP/TCP/UDP checksums Offload............................................................................................37
6.5 AUTO-MDIX and Application.................................................................................................38
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DM9000A
APPLICATION NOTES
FIGURE
FIGURE
FIGURE
FIGURE
FIGURE
FIGURE
FIGURE
FIGURE
1.1 DM9000A INTERNAL BLOCK DIAGRAM.................................................................6
2.1 SIGNAL CONNECTION WITH A PROCESSOR INTERFACING ..............................7
2.2 CMD PIN AND PROCESSOR INTERFACE.................................................................9
3.1 SCHEMATIC FOR 8-BIT PROCESSOR.....................................................................17
3.2 SCHEMATIC FOR 16-BIT PROCESSOR...................................................................18
5.1 PACKET TRANSMITTING BUFFER.........................................................................28
5.2 BLOCK DIAGRAM OF THE RECEIVED PACKETS................................................30
6.1 AUTO-MDIX 10BASE-T/100BASE-TX APPLICATION...........................................38
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DM9000A
APPLICATION NOTES
TABLE
TABLE
TABLE
TABLE
TBALE
TABLE
2.1 PIN FUNCTION TABLE FOR PROCESSOR INTERFACE...........................................8
3.1 STRAP PIN CONTROL TABLE....................................................................................10
3.2 EEPROM FORMAT IN 16-BIT MODE .........................................................................11
3.3 EEPROM FORMAT IN 8-BIT MODE...........................................................................13
3.4 GENERAL PURPOSE CONTROL REGISTER (GPCR) TABLE.................................15
3.5 GENERAL PURPOSE REGISTER (GPR) TABLE.......................................................16
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DM9000A
APPLICATION NOTES
1 Introduction
1.1 General Description
The DM9000A is a fully integrated, powerful and cost-effective Fast Ethernet MAC controller
with a general processor interface, an EEPROM interface, a 10/100 PHY and 16K Byte
SRAM (13K Byte for RX FIFO and 3K Byte for TX FIFO). It is designed with low power,
single-voltage and high performance process that supports 3.3V with 5V tolerant I/O. Besides,
the DM9000A supports 8/ 16-bit processor interface to internal memory accesses for many
different processors. It is good integrated 10/100 Mbps transceiver with AUTO-MDIX and
IP/TCP/UDP-Checksum Offload.
The goal of this document is for the embedded design engineers, to implement the DM9000A
LAN chip on any processor's architecture quickly and successfully, with providing the exact
reference information and pertaining to many embedded systems. The software programming
is very simple, so users can port the software drivers to any system easily.
MAC
EEPROM
Interface
Memory
Management
Internal
SRAM
Interface
Processer
TX+/-
RX+/-
Auto
MDIX
100 BaseTX
-
PHYceiver
transceiver
-
Autonegotiation
LED
100 Base-TX
PCS
10 Base T
/
Tx Rx
MII
MII Management
Control
&
MII Register
TX Machine
&Control Status
Registers
RX Machine
Figure 1.1 DM9000A Internal Block Diagram.
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DM9000A
APPLICATION NOTES
2 General Processor Bus Description
This chapter is intended to aid design engineers connecting the DM9000A device to a
micro-processor or micro-controller. The discussion will include the pin functional table, and
the individual control signals of the DM9000A involved in the connection between the device
and an associated micro-processor/ micro-controller in detail.
D0~D7
D8~D15
A2
INT
nRD
nWR
nCS
Power
On
Reset
25Mhz
SD0~SD7 (18~10)
SD8~SD15 (31~22)
CMD (32)
INT (34)
IOR# (35)
EECK (20)
EECS (21)
EEDIO (19)
EEPROM
93C46/ LC46
DM9000A
IOW# (36)
CS# (37)
PWRST# (40)
X1 (44)
X2 (43)
Figure 2.1 Signal Connection with a Processor Interfacing.
TXO+ (7)
TXO- (8)
RXI+ (3)
RXI- (4)
AUOT-MDIX
Transformer
RJ-45
2.1 Signals Connection with Processor Bus
The DM9000A can interface directly with most general processors local bus such as ARM,
MIPS, Intel, TI, Motorola, NEC, and Hitachi... It is designed to suit for the implementation of
Fast Ethernet connectivity solutions to many embedded systems.
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DM9000A
APPLICATION NOTES
2.1.1 Pin Function Table
Note: The pins of processor parallel interface all have a pulled down resistor about 60K Ohm
internally.
Processor
Bus Signal
nRD IOR# 35 I Processor READ Command
nWR IOW# 36 I Processor WRITE Command
nCS /
nAEN
SD0 ~ 7 SD0 ~ 7 18,17,16
SD8 ~ 15 SD8 ~ 15 31,29,28
CMD CMD 32 I Command Type
INT INT 34 O Interrupt Request
DM9000A
Signal
CS# 37 I Chip Select
Pin No. I/O Description
This pin is low active at default; its polarity can be modified by the
EEPROM setting.
This pin is low active at default; its polarity can be changed by the
EEPROM setting.
A low active signal is used to select the DM9000A. Its polarity can be
changed by the EEPROM setting.
I/O DATA Bus 0 ~ 7
14,13,12
,11,10
I/O DATA Bus 8 ~ 15 (in 16-bit mode)
27,26,25
,24,22
When low, the access of this command cycle is INDEX port
When high, the access of this command cy cle is DATA port
This pin is high active and open-collected at default; its polarity and its
output type can be modified by the EEPROM setting.
Table 2.1 Pin Function Table for Processor Interface
2.1.2 8/ 16-Bit Mode Setting
There are two operation modes of DATA bus width, 8-bit or 16-bit, when access to the internal
memory in the DM9000A. These two modes are selected by the strap pin 21 EECS shown the
following table:
EECS (pin 21) DATA width
0 16-bit
1 8-bit
Where, "1" means pull-high with the 10K Ohm resistor, and "0" means floating (default).
The status of DATA width operation mode can be examined from Bit [7] of ISR REG. FEH,
ISR (REG. FEH) IOMODE (DATA width)
Bit [7] Operation
0 16-bit mode
1 8-bit mode
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DM9000A
APPLICATION NOTES
2.1.3 Command Type
In the DM9000A, there are only two registers, named INDEX port and DATA port, which can
be accessed directly. These two ports are distinguished by the CMD pin in the access
command cycle. When CMD is low in command cycle, INDEX port is accessed; otherwise,
when CMD is high, DATA port is accessed.
All of these control and status registers in the DM9000A are accessed indirectly by the
INDEX/ DATA ports. The command sequence to access the specified control/ status register
is: firstly, to write the register’s address into INDEX port, then read/ write their data through
DATA port. The following diagram (Figure 2.2) is an example for the DM9000A CMD pin
connected to an embedded system.
SA2
nCS
CMD
CS
DM9000AProcessor
The DM9000A device INDEX port
= nCS address + 0x0
The DM9000A device DATA port
= nCS address + 0x4
Figure 2.2 CMD Pin and Processor Interface.
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DM9000A
APPLICATION NOTES
3 System Hardware Design
3.1 How to Select Chip
In the command cycle, the DM9000A is accessed by CS pin cooperated with IOR or IOW pins.
These pins are low active at default, while their polarity can be modified by EEPROM setting
to suit for the application of various processor types.
Both of CS pin and IOW/ IOR pin should be active to write/ read the value into INDEX port or
DATA port. So, if the IOW and IOR signals in the system are only used by the DM9000A, the
CS pin can be forced to the active logic level to simplify the system design.
3.2 Strap Pins Setting
The DM9000A provides the following strap pins:
Strap pins control list:
Pin Name Strap Description
20 EECK INT Polarity Type
21 EECS DATA Bus Width
25 GP6 INT Output Type
Table 3.1 Strap Pin Control Table
0: INT active High
1: INT active Low
0: DATA 16-bit mode
1: DATA 8-bit mode
available in 8-bit mod
0: INT Force-Output mode
1: INT Open-Drain mode
e only
Note: "1" means pull-high with the 10K Ohm resistor, and "0" means floating (default).
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APPLICATION NOTES
3.3 Serial EEPROM Operation
The DM9000A supports a serial EEPROM interface. The EEPROM of the DM9000A holds the
following parameters:
1. Ethernet node address.
2. Vendor ID and Product ID auto load.
3. Processor control bus pins polarity setting.
4. Wake-up mode control.
5. PHY ON or PHY OFF while powered up.
6. AUTO-MDIX enable/ disable setting.
7. LED1 & LED2 pins act as IO16 pin and IOWAIT/ WAKE pin in 16-bit mode.
8. LED mode 0 or mode 1 setting.
All of the above mentioned settings are read from the EEPROM upon hardware power-on
reset. The specific target device is IC 93C46, the 1024-bit serial EEPROM. (EEPROM is
93C46/ LC46 such as ATmel, Micro-chip, ATC, and CSI.)
All of accesses to the EEPROM are done in words. All of the EEPROM addresses in the
specification are specified as word addresses.
The default settings of the DM9000A can be changed by the I/O strap pins, or the EEPROM
bits settings with higher priority. The priority for setting the pins polarity is EEPROM > strap
pins > default setting.
3.3.1 EEPROM Format
Name Address
(Word)
Ethernet
Node
Address
Auto Load
Control
0 ~ 2 XX
Programming
Value (Hex)
XX
XX
XX
XX
XX
3 5445 Bit [1:0] = 00: Disable vendor ID and product ID programming.
Description
6-byte Ethernet node address.
*01: Accept ven dor ID and pr oduct ID programming.
Bit [3:2] = 00: Disable setting of Word 6 Bit [8:0].
*01: Accept setting of Word 6 Bit [8:0].
Bit [5:4]: Reserved = 0.
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DM9000A
APPLICATION NOTES
Vendor ID 4 0A46 2-byte vendor ID.
Product ID 5 9000 2-byte product ID.
Pin Control 6 01E7 When Word 3 Bit [3:2] = 01, the se bits can control the CS, IOR, IOW ,
Wake-up
Mode
Control
7 4180 Depend on the setting of Word 3 Bit [15:6] to accept auto load control:
Bit [7:6] = 00: Disable setting of Word 7 Bit [3:0].
*01: Accept setting of Word 7 Bit [3:0].
Bit [9:8]: Reserved = 0.
Bit [11:10] = 00: Disable settin g of Word 7 Bit [7].
*01: Accept setting of Word 7 Bit [7].
Bit [13:12] = 00: Disable settin g of Word 7 Bit [8].
*01: Accept setting of Word 7 Bit [8].
Bit [15:14] = 00: Disable settin g of Word 7 Bit [15:12].
*01: Accept setting of Word 7 Bit [15:12].
Note: The remark * is now programming value.
INT, IOWAIT and IO16 pins polarity:
Bit [0] = 0: Processor CS pin is active high.
*1: Processor CS pin is active low.
Bit [1] = 0: Processor IOR pin is active high.
*1: Processor IOR pin is active low.
Bit [2] = 0: Processor IOW pin is active high.
*1: Processor IOW pin is active low.
Bit [3] = *0: Processor INT pin is active high.
1: Processor INT pin is active low.
Bit [4] = *0: Processor INT pin is force output.
1: Processor INT pin is force open-collected.
Bit [5] = 0: Processor IOWAIT is active high.
*1: Processor IOWAIT is active low .
Bit [6] = 0: Processor IOWAIT is force output.
*1: Processor IOWAIT is force open-co llected.
Bit [7] = 0: Processor IO16 is active high.
*1: Processor IO16 is active low.
Bit [8] = 0: Processor IO16 is force output.
*1: Processor IO16 is force open-collec ted.
Bit [15:9]: Reserved = 0.
Bit [0] = *0: WAKE pin is active high.
1: WAKE pin is active low.
Bit [1] = *0: WAKE pin is in level mode.
1: WAKE pin is in pulse mode.
Bit [2] = *0: Magic packet wake-up event is disabled.
1: Magic packet wake-up event is enabled.
Bit [3] = *0: Link_change wake-up event is disabled.
1: Link_change wake- up event is enabled .
Bit [6:4]: Reserved = 0.
Bit [7] = 0: LED mode 0.
*1: LED mode 1.
Bit [8] = 0: The internal PHY is disabled after power-on.
*1: The internal PHY is enabled after power-on.
The GPR REG. 1FH Bit [0] is modified from this Bit [8].
Bit [13:9]: Reserved = 0.
Bit [14] = 0: AUTO-MDIX OFF, *1: AUTO-MDIX ON.
Bit [15]: Reserved = 0.
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DM9000A
APPLICATION NOTES
Note: The programming value of the EEPROM is only for reference to list 16-bit values,
"XX:XX:XX:XX:XX:XX, 5445, 0A46, 9000, 01E7, 4180".
Name Address
(Word)
Ethernet
Node
Address
Auto Load
Control
Vendor ID 4 0A46 2-byte vendor ID.
Product ID 5 9000 2-byte product ID.
Pin Control 6 01E7 When Word 3 Bit [3:2] = 01, the se bits can control the CS, IOR, IOW ,
0 ~ 2 XX
3 5405 Bit [1:0] = 00: Disable vendor ID and product ID programming.
Table 3.2 EEPROM Format in 8-bit mode
Programming
Value (Hex)
XX
XX
XX
XX
XX
Description
6-byte Ethernet node address.
*01: Accept ven dor ID and produc t ID programming.
Bit [3:2] = 00: Disable setting of Word 6 Bit [8:0].
*01: Accept setting of Word 6 Bit [8:0].
Bit [5:4]: Reserved = 0.
Bit [7:6] = 00: Disable setting of Word 7 Bit [3:0].
*01: Accept setting of Word 7 Bit [3:0 ] and Word 7 Bit [13:12]
= 10 to let LED2 act as WAKE in 16-bit mode only.
Bit [9:8]: Reserved = 0.
Bit [11:10] = 00: Disable settin g of Word 7 Bit [7].
*01: Accept setting of Word 7 Bit [7].
Bit [13:12] = 00: Disable settin g of Word 7 Bit [8].
*01: Accept setting of Word 7 Bit [8].
Bit [15:14] = 00: Disable settin g of Word 7 Bit [15:12].
*01: Accept setting of Word 7 Bit [15:12].
Note: The remark * is now programming value.
INT, IOWAIT and IO16 pins polarity:
Bit [0] = 0: Processor CS pin is active high.
*1: Processor CS pin is active low.
Bit [1] = 0: Processor IOR pin is active high.
*1: Processor IOR pin is active low.
Bit [2] = 0: Processor IOW pin is active high.
*1: Processor IOW pin is active low.
Bit [3] = *0: Processor INT pin is active high.
1: Processor INT pin is active low.
Bit [4] = *0: Processor INT pin is force output.
1: Processor INT pin is force open-collected.
Bit [5] = 0: Processor IOWAIT is active high.
*1: Processor IOWAIT is active low .
Bit [6] = 0: Processor IOWAIT is force output.
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DM9000A
APPLICATION NOTES
Wake-up
Mode
Control
7 4180 Depend on the setting of Word 3 Bit[15:6] to accept auto load control:
*1: Processor IOWAIT is force open-co llected.
Bit [7] = 0: Processor IO16 is active high.
*1: Processor IO16 is active low.
Bit [8] = 0: Processor IO16 is force output.
*1: Processor IO16 is force open-collec ted.
Bit [15:9]: Reserved = 0.
Bit [0] = *0: WAKE pin is active high.
1: WAKE pin is active low.
Bit [1] = *0: WAKE pin is in level mode.
1: WAKE pin is in pulse mode.
Bit [2] = *0: Magic packet wake-up event is disabled.
1: Magic packet wake-up event is enabled.
Bit [3] = *0: Link_change wake-up event is disabled.
1: Link_change wake- up event is enabled .
Bit [6:4]: Reserved = 0.
Bit [7] = 0: LED mode 0.
*1: LED mode 1.
Bit [8] = 0: The internal PHY is disabled after power-on.
*1: The internal PHY is enabled after power-on.
The GPR REG. 1FH Bit [0] is modified from this Bit [8].
Bit [11:9]: Reserved = 0.
Bit [13:12] = *00: LED2 act normal.
01: LED2 act as IOWAIT in 16-bit mode only.
10: LED2 act as WAKE in 16-bit mode on ly.
Bit [14] = 0: AUTO-MDIX OFF,
*1: AUTO -MDIX ON.
Bit [15] = *0: LED1 act normal,
1: LED1 act as IO16 in 16-bit mode only.
Note: List the programming values of the EEPROM in 16-bit mode,
"XX:XX:XX:XX:XX:XX, 5405, 0A46, 9000, 01E7, C180" if LED1 pin 39 act as "IO16".
"XX:XX:XX:XX:XX:XX, 5405, 0A46, 9000, 01E7, 5180" if LED2 pin 38 act as "IOWAIT".
"XX:XX:XX:XX:XX:XX, 5445, 0A46, 9000, 01E7, 6180" if LED2 pin 38 act as "WAKE".
"XX:XX:XX:XX:XX:XX, 5405, 0A46, 9000, 01E7, D180" if LED1 pin 39 act as "IO16" and
LED2 pin 38 act as "IOWAIT" pin used.
"XX:XX:XX:XX:XX:XX, 5445, 0A46, 9000, 01E7, E180" if LED1 pin 39 act as "IO16" and
LED2 pin 38 act as "WAKE" pin used.
Table 3.3 EEPROM Format in 16-bit mode
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DM9000A
APPLICATION NOTES
3.4 GPIO Pins Setting
If the DM9000A operated in 8-bit mode, there are 6 general purpose pins, GP1~GP6, can be
used. Their I/O types are controlled by GPCR REG. 1EH. And their I/O data are presented by
GPR REG. 1FH.
The default values of GPCR Bit [3:1] are all "0"s for the GP3 ~ GP1 pins as the input mode
respectively. But, the GPCR Bit [6:4] GPC64 ar e all forced to "1"s only for the GP6 ~ GP4
pins as the output mode.
GPCR (REG. 1EH) GPIO interface control:
Bit Name Default Description
7 RESERVED 0, RO Reserved.
6:4 GPC64 111, RO
3:1 GPC31 000, RW
0 RESERVED 1, RO Reserved.
Forced to "1"s only as the output ports of GP6 ~ 4
pin 25, 26, 27.
GP3~1 pin 28, 29, 31 set to be the input/ output port:
"1": the output port represented
"0": the input port represented.
Table 3.4 General Purpose Control Register (GPCR) Table
GPR (REG. 1FH) GPIO interface control:
Bit Name Default Description
7 RESERVED 0, RO Reserved.
GP6~4 pin 25, 26, 27 are forced to the output ports
6:4 GPO64 000, RW
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only. Set to "1": the pin output high, set to "0": the pin
output low.
Page 16
DM9000A
APPLICATION NOTES
3 GPIO3 0, RW
2 GPIO2 0, RW
1 GPIO1 0, RW
If GP3 is output port, GPR Bit [3] sets to "1" to
enable the pin 28 output high or sets to "0" to enable
the pin 28 output low.
If GP3 is input port, the value of GPR Bit [3] is "1" to
represent a high signal is received. In contract, the
value of GPR Bit [3] is "0" to represent a low signal
is received.
If GP2 is output port, GPR Bit [2] sets to "1" to
enable the pin 29 output high or sets to "0" to enable
the pin 29 output low.
If GP2 is input port, the value of GPR Bit [2] is "1" to
represent a high signal is received. In contract, the
value of GPR Bit [2] is "0" to represent a low signal
is received.
If GP1 is output port, GPR Bit [1] sets to "1" to
enable the pin 31 output high or sets to "0" to enable
the pin 31 output low.
If GP1 is input port, the value of GPR Bit [1] is "1" to
represent a high signal is received. In contract, the
value of GPR Bit [1] is "0" to represent a low signal
is received.
0 PHYPD 1, RW
Table 3.5 General Purpose Register (GPR) Table
"1": power down the internal PHY
"0": power up the internal PHY.
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DM9000A
APPLICATION NOTES
3.5 Schematic Reference Design
3.5.1 Application Schematics for 8-Bit and 16-Bit
DVDD_33
R2
510
R0603
12
SPEED
LED1
SPEED_LED
JP3
CON312
3
JP4
SPEED_LED
IO16
IOWAIT
FOR MDC/MDIO 16 Bit MODE TEST
JP3 OPEN , JP4 OPEN
DVDD_33
LED1
R1 10K
R0603
1 2
1 2
JP1 JU MPER
JP2 JU MPER
SD5
SD2
SD3
SD6
SD4
SD7
C6
60pF
C0603
C5
60pF
C0603
C4
60pF
C0603
FOR NORMAL SYSTEM
JP3 2-3 SHORT , JP4 2-3 SHORT
FOR X86 ISA SYSTEM 16 Bit MODE TEST
JP3 1-2 SHORT , JP4 2-3 SHORT
JP1 ON : USE 8 Bit MODE
OFF : USE 16 Bit MODE
JP2 ON : USE EEPROM
OFF : NOT USE EEPROM
2.0
JP6
1234567
8
RJ-45
R11
75R
R0603
JP7
1234567
8
CON8
R4
510
R0603
12
LINK/ACT
LED2
LED2
DVDD_33
RJ_45_6
C22
LINK_LED
CON312
3
C21
LINK_LED
C1
0.1UF
C0603
DGND
678
NC
NC
VCC
CSSKDI
DO GND
U1
93LC46/DIP8
123
4 5
R3
10K
R0603
13
14
15
16
17
18
19
20
21
22
23
24
DGND
CHASIS_GROU ND
LED1
RJ_45_1
RJ_45_2
RJ_45_3
LED2
RJ_45_1
RJ_45_2
C24
0.1UF
C0805
0.1UF
C0805
RX+
RJ_45_3
RJ_45_6
C23
0.1UF
C0805
0.1UF
C0805
TX+
TX- RX-
12
SD7
SD6
SD5
SD4
SD3
GND
SD2
SD1
SD0
EEDIO
EEDCK
EEDCS
SD15
VDD
SD14
C?
15PF
C?
15PF
R6
49.9/1%
R5
49.9/1%
C3
0.1UF
AVDD_25
TX-
TX+
RX-
RX+INT
C7
1234567891011
TX-
RX-
TX+
RX+
TXGND
BGRES
RXGND
AVDD25
AVDD25
RJ_45_6
14
16
15
134
NC
MCTNC
TX-/RX-
TX+/RX+
NC
TD-/ RD-
TD+/RD+CTRD-/TD-
U3
1
356
2
For EMI Solution
C0603
C0603
R0603
R0603
C0603
C8
+
0.1UF
AVDD_25
AGND
TX-
TX+
220UF/16V
EC-MR05-2
AGND
C0603
R12
6.8K1%
R0603
DM9000AE/LQFP48
BGGND
48
RXGND
47
SD
46
GND
45
X1
44
X2
43
VDD
42
TEST
41
PWRST#
40
LED1(IO16 f or eeprom )
39
LED2(IOW AIT / W AKEU P for eeprom )
38
CS#
37
DM9000A-8/16bit
SD13
SD12
SD11
SD10
SD9
VDD
SD8
CMD
GND
INT
IOR#
U2
2526272829303132333435
+
DVDD_33
SD14
SD15
SD1
SD0
DGND
DGND
SD12
SD11
SD13
C2
330UF/16V
EC-MR05-2
IOW#
36
IOR#
SD8
CMD
SD9
SD10
IOW#
SD6
SD5
SD0
SD1
642
RP2
7 8
SD7
SD3
SD2
SD4
642
RP4
33
33
135
7 8
135
R10
75R
R0603
RJ_45_1
R9
75R
11
RX-/TX-
RX-
AGND
LED1
NC NC
RD +/ TD + RX+/ TX+
8 9
7 10
For EMI Solution
RX+
C?
15PF
C0603
R140R1006D21N4148
4.7K
R13
D1
1N4148
PH163539
R?
R0603
SMD
R0603
C13
0.01UF/ 2KV
C10
CHASIS_GROUN D
0.1UF
C0603
C12
0.1UF
C0603
AGND
C9
0.1UF
C0603
AGND
C?
15PF
C0603
C?
15PF
C0603
C?
15PF
R8
49.9/1%
R7
49.9/1%
AGND
C0603
C11
0.1UF
C0603
3.3V
R0603
R0603
Q1 REGULATOR
U6A
For EMI Solution
P_IN_5V
DGND
DGND
500
R0603
C?
15PF
C0603
C15
22PF
C0603
Y1
25MHZ/49US
XTAL
C14
22PF
C0603
R?
47K
R0603
DGND
SMD
A C
C20
10UF/16V
EC-MR05-2
+
DGND
A C
RST#
L2
3.3V DVDD_33
4
VOUT
GND
G
VIN VOUT
SOT-223
I O
4
GND
GND
P_IN P_IN
Common Mode Chok e
3
1 2
P_IN
DGND
DGND
DGND
C19
0.1UF
C0603
C18
0.1UF
C0603
DVDD_33
DGNDDGND DGNDDGND
C17
0.1UF
C0603
DVDD_33 DVDD_33
C16
0.1UF
C0603
DVDD_33
AGND
C?
1UF
C0603C?1UF
C?
1UF
C0603
RJ_45_2
RJ_45_3
12
NC
For EMI Solution
CS#
LED2
DVDD_33
of
11Thursday, April 20, 2006
DM9000A-8/16bit TX AUTO-MIDX
DAVICOM Semiconductor Inc.
Custom
Titl e
Size Document Num ber Rev
Date: Sheet
AGND
L1
F.B/120/ S0603
F.B/120/ S0603
DGND
DGND
DGND
Preliminary (for Reference Only)
DGND
C0603
CHASIS_GROUND
CS#
IOR#
RST# LOW ACTIVE (POWER RESET)
CS# LOW ACTIVE (CHIP SELECT)
IOW#
IOR# LOW ACTIVE (IO DATA READ)
IOW# LOW ACTIVE (IO DATA WRITE)
INT HIGH ACTIVE (INTERRUPT ACTIVE)
C4 , C5 , C6 NOISE FILTER
Note:
Filter IOR# , IOW# , CS# Noise
max use 60pF
[ Default OPEN ]
12
SDBUS_0
34
IOW#
IOR#
IO16
IOWAIT
CS#
CMD
INT
JP5 HEADER/16X2
RST#
P_IN_5V
DGND
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
SDBUS_1
SDBUS_2
SDBUS_3
SDBUS_4
SDBUS_5
SDBUS_6
SDBUS_7
SDBUS_8
SDBUS_9
SDBUS_10
SDBUS_11
SDBUS_12
SDBUS_13
SDBUS_14
SDBUS_15
RP3
SDBUS_5
SDBUS_1
SDBUS_4
SDBUS_0
SD9
SD8
642
7 8
SDBUS_9
SDBUS_8
SDBUS_7
SDBUS_6
SDBUS_3
SDBUS_2
SD14
SD10
SD15
SD11
SD12
SD13
642
33
RP1
135
SDBUS_10
SDBUS_11
33
135
7 8
SDBUS_12
SDBUS_14
SDBUS_13
SDBUS_15
SD1
GP2
GP6
SD4
SD2
SD6
SD5
GP3
GP1
SD0
SD1
SD2
SD0
8 Bit Mode16 Bit Mode
SD1
SD2
SD0
DATA BUS CONNE CTOR
SD1
SD2
SD0
GP5
WAKE
SD7
GP4
SD3
SD4
SD3
SD4
SD3
SD4
SD3
LED3
SD9
SD13
SD6
SD5
SD10
SD8
SD12
SD15
SD7
SD11
SD14
SD9
SD13
SD6
SD5
SD10
SD8
SD12
SD15
SD7
SD11
SD14
SD9
SD13
SD6
SD5
SD10
SD8
SD12
SD15
SD7
SD11
SD14
C?
1UF
C0603
For EMI Solution
DGND AGND
Figure 3.1 Schematic for 8-Bit Processor.
Preliminary 17
Version: DM9000A-AN-V121
November 27, 2007
Page 18
DM9000A
APPLICATION NOTES
DVDD
Description
Pulled high, the INT pin is low active;
otherwise the INT pin is high active
This jumper is setting chip select to EEPROM and
is also used as a strap pin to to define the LED
mode is mode 1; otherwise it is mode 0.
Select speed LED(Pin 1 and 2) and IO16(Pin 2
and 3) function for EEPROM setting
Select IOWAIT(Pin 1 and 2) and LINK/ACT
LED(Pin 2 and 3) function for EEPROM setting
JP 4
JP 5
JP 6
JP
Name
C1
0.1UF
DVDD
678
NC
NC
VCC
CSSKDI
DO GND
U1
123
4 5
EECS
EECK
EEDIO
EECK
EECS
EEDIO
JP 7
C5
+
VCC3
C2
100UF/16V
C
1
Q1
LT1117-SOT223
IO
GND
93LC46/PDIP
R1
10K
R0603
3 2
C4
+
DVDD_5
C3
100UF/16V
U2
R2
510
R0603
R3
510
R0603
12
12
LINK/ACT
SPEED
LED1
LED2
LED2
LED1
0.1UF
C0603
CE5MM
AVDD_25
C7
220UF/16V
CE5MM
TX-
TX+
TX+
TX-
TX-
TX+
SD7
VDD25
TXGND
16-bit
+
AGND
0.1UF
C8
RX-
RX+
C10
CE5MM
220UF/16V
+
RX+
RX-
RX-
RX+
RXGND
AGND
0.1UF
C9
R6
6.8K1%
R0603
1
VDD25
BGRES
BGGND
48
RXGND
47
SD
46
GND
45
X1
44
X2
43
VDD
42
TEST
41
PWRST#
40
LED1
39
LED2
38
CS
37
0.1UF
C0603
DGND
CE5MM
12111098765432
SD5
SD6
DM9000AE/LQFP48
SD4
13
SD3
14
GND
15
SD2
16
SD1
17
SD0
18
EEDIO
19
EECK
20
EECS
21
SD15
22
VDD
23
SD14
DM9000A
24
JP3
RJ-45
RJ8-45
1234567
8
R16
75R
R0603
R15
75R
R0603
R14
75R
R0603
11
12
14
16
15
134
NC
NC
MCTNC
TX-/RX-
RX+/TX+
TX+/RX+
TD+/RD+
TD-/RD-CTRD+/TD+
NC
U4
1
356
2
R8
49.9/1%
R0603
R7
R0603
49.9/1%
AGND
C11
0.1UF
C0603
TX+
TX-
DVDD_3
C?
0.1UF
C0603
GND
C?
0.1UF
C0603
VCC1.8
AGND
C13
22PF
C0603
XTAL
Y1
C12
22PF
C0603
25MHZ/49US
PH163539
RD-/TD- RX-/TX-
NC NC
8 9
7 10
AVDD_25
RX+
RX-
SD0
SD2
SD1
SD3
DVDD_3
Y1
VCCY
A1
VCCAA2A3A4A5A6A7A8EN GNDGND
U?
213456789
VCC1.8
GND
R11
0R
GND
R0603
GND
C19
0.01UF/2KV
C0603
C17
C18
0.1UF
C0603
0.1UF
C15
0.1UF
C0603
R13
49.9/1%
R0603
R12
49.9/1%
R0603
SD6
SD4
SD7
SD5
121314151617181920
Y8Y7Y6Y5Y4Y3Y2
C0603
AGND
AGND
C16
C0603
0.1UF
AGND
GND
SD15
SD10
GND
ADG3308
10 1111
VCCY
VCCAA2A3A4A5A6A7A8EN GNDGND
U?
213456789
VCC1.8
DVDDVCC3
121314151617181920
Y8Y7Y6Y5Y4Y3Y2
Y1
A1
ADG3308
10 1111
AGND
GND
SD13
SD8
SD9
SD14
SD11
SD12
DVDD_3
INT
CMD
DVDD_3
Y1
VCCY
A1
VCCAA2A3A4A5A6A7A8EN GNDGND
U?
213456789
VCC1.8
IOW#
CS
IOR#
121314151617181920
Y8Y7Y6Y5Y4Y3Y2
10 1111
Title
GND
ADG3308
1.0
of
11Wednesday , April 20, 2005
DM9000A 16bit demo board
DAVICOM Semiconductor Inc.
C
Size Document N um ber Rev
Date: Sheet
AGNDDGND
IOW#
IOR#
INT
GND
CMD
SD8
VDD
SD9
SD10
SD11
SD12
SD13
25
+
SD13
GND
DVDD
C6
CE5MM
SD1
SD6
SD5
SD4
SD7
SD2
SD3CSSD15
SD7
SD1
SD2
SD3
SD4
SD5
SD6
330UF/16V
SD14
SD0
SD0
SD14
SD15
3635343332313029282726
CMD
SD12
SD11
SD10
SD9
SD8
SD8
SD9
CMD
SD10
SD11
SD12
SD13
IOW#
IOR#
INT
INT
IOR#
IOW#
GND
C14
10UF/16V
CE5MM
4.7K
R0603
R9
+
DVDD
LED1
LED2
LED1
LED2
GND
DVDDDVDD_3
C23
0.1UF
C0603
GND
DVDD
C22
0.1UF
C0603
GND
DVDD
C21
0.1UF
C0603
GNDGND
DVDD
C20
0.1UF
C0603
DVDD
Figure 3.2 Schematic for 16-Bit Processor.
Preliminary 18
Version: DM9000A-AN-V121
November 27, 2007
Page 19
DM9000A
APPLICATION NOTES
4 Reset Operation and PHY Power-down Mode
The DM9000A can be reset by either hardware reset or software reset. A hardware reset can
be accomplished by the power-on reset PWRST# pin 40. A software reset can be
accomplished by setting the network control register (NCR REG. 00) RST Bit [0] = 1.
The internal PHY of the DM9000A can be powered down by writing "1" to PHYPD (the Bit [0]
of the GPR register), or by setting the Power-down Bit [11] = 1 in the PHY basic mode control
register (BMCR PHY REG. 00). In the power-down state, the power consumption is reduced
to a minimum under 21mA/ 3.3V.
4.1 Power On Reset
An active low signal is used to reset the DM9000A LAN chip. The PWRST# pin 40 is asserted
low for at least 20 ms. All of the MAC and PHY registers will be reset to the default values and
the hardware strap pins will also be latched. The DM9000A is ready after 5 us when this pin is
de-asserted and then the data will be downloaded from the EEPROM.
4.2 Software Reset
A software reset can be accomplished by setting RST Bit [0] = 1 in the network control register,
NCR REG. 00. After the reset, some registers will be reset to their default value. And the
DM9000A n eeds only 10 us for a software reset.
4.3 PHY Power Down Mode
In the power-down (power-saving) mode, the DM9000A will disable all the TX&RX functions.
And, it’s almost the same as the PHY SLEEP mode powered down all circuit, except oscillator
and clock generator circuit. But, it’s different to the Power Reduced mode which the TX circuit
still sends out fast link pulse with min. power consumption and wakes up if a valid signal is
detected, automatically.
Preliminary 19
Version: DM9000A-AN-V121
November 27, 2007
Page 20
DM9000A
APPLICATION NOTES
There are two ways to set the power-up/ power-down mode for the internal PHY:
4.3.1 GPR PHYPD Setting
In the MAC registers, the PHYPD bit is used for powering down the internal PHY, and it is
default high "1". If the internal PHY is desired to be activated, the system driver needs to clear
this power-down bit by writing low "0" to PHYPD in the GPR REG. 1FH.
4.3.2 PHY Register Setting
In the PHY registers, the Bit [11] Power-down of the basic mode control register (BMCR REG.
00) can be set high "1" to enable the PHY power-down mode.
Preliminary 20
Version: DM9000A-AN-V121
November 27, 2007
Page 21
DM9000A
APPLICATION NOTES
5 How to Program DM9000A
5.1 How to Read/ Write DM9000A Regi ster
There are only two addressing ports through the access of the host interface. One port is
INDEX port and the other is DATA port. INDEX port is decoded by the pin CMD=0 and DATA
port is decoded by the pin CMD = 1. The content of INDEX port is the address of the register
to access DATA port later. Before accessing the 8-bit data in any register or the 8/ 16-bit data
in the RX/ TX FIFO SRAM (total 16K bytes), the address of the register must be written into
INDEX port. Please refer to the DM9000A datasheet chapter 9.1 about host interface.
Here are the examples to read and write the DM9000A register:
(Where CMD pin is connected to Processor SA2)
UINT16 IOaddr; /* UINT32 IOaddr=0x19000000; for example defined in ARM-base HPI BANK3*/
void iow ( UINT16 reg, UINT8 dataB )
{
outb(reg, IOaddr); /* I/O output a byte to INDEX port, select the register*/
outb(dataB, IOaddr+4); /* I/O output a byte to DATA port, WRITE the register data*/
}
UINT8 ior ( UINT16 reg )
{
outb (reg, IOaddr); /* I/O output a byte to INDEX port, select the register*/
return inb(IOaddr + 4); /*I/O input a byte from DATA port, READ the register data*/
}
Preliminary 21
Version: DM9000A-AN-V121
November 27, 2007
Page 22
DM9000A
APPLICATION NOTES
5.2 Driver Initializing Steps
1. To power on the internal PHY:
iow ( 0x1F, 0x00 ); to set GPR (REG. 1FH) Bit [0]: PHYPD = 0
The PHY is powered down at default. The power-up procedure will be needed to enable it by
writing iow "0" to PHYPD (GP0 = 0). Please refer to the ch.3.4 about setting the GPIO pins.
2. To do a software reset for the DM9000A initial (see chapter 4.2):
i. iow ( 0x00, 0x01 ); to set NCR (REG. 00) RST Bit [0] = 1 for a period time 10 us.
ii. iow ( 0x00, 0x00 ); to clear NCR (REG. 00) RST Bit [0] = 0, or let it auto clear.
3. Program the NCR register. Choose normal mode by setting NCR (REG. 00) LBK Bit [2:1] =
00b. The system designer can choose the network operations such as the internal MAC/ PHY
loop-back mode, forced the external PHY Full/ half duplex mode or to force collisions, and the
wake-up events enable. Please refer to the datasheet chapte r 6.1 about the NCR setting.
4. To set the IMR register (REG. FFH) Bit [7] = 1 to enable the Pointer Auto Return function,
which is the memory read/ write address pointer of the RX/ TX FIFO SRAM.
5. Read the EEPROM data 3 words, for the individual Ethernet node address (if necessa ry).
6. Write 6-byte Ethernet node address into the Physical Address Registers (REG. 10H~15H).
7. Write Hash Table 8 bytes into the Multicast Address Registers (REG. 16H ~ REG. 1 DH).
8. To clear TX & INTR status by R/W1 the NSR REG. 01 and ISR REG. FEH registers. The Bit
[2] TX1END, Bit [3] TX2END, and Bit [5] WAKEST will be cleared automatically by reading it
or writing "1" back. Please refer to the datasheet chapter 6.2 & 6.33 about setting NSR & ISR.
9. To handle the NIC interrupts or polling service routines.
10. Program the IMR register (REG. FFH) Bit [0]/ Bit [1] to enable the RX/ TX interrupt.
11. Program the RCR register to enable RX. The RX function is enabled by setting the RXEN
Bit [0] = 1 in the RX control register, RCR REG. 05. Please refer to the datashe et ch.6.6 RCR.
12. NIC is being activated and ready RX/ TX now.
Preliminary 22
Version: DM9000A-AN-V121
November 27, 2007
Page 23
DM9000A
APPLICATION NOTES
5.3 How to Read/ Write EEPROM Data
The DM9000A supports the serial EEPROM interface and provides a very easy method to
access it. It is only to read/ write the EEPROM&PHY control/ address/ data register (REG.
0BH ~ REG. 0EH), which are used to control and read/ write the EEPROM address or data.
For example, IC 93C46 is a 64-word (1024-bit) EEPROM and the word addresses are
mapped to the EROA Bit [5:0] in the EEPROM&PHY address register, EPAR REG. 0CH.
Besides, EPAR PHY_ADR Bit [7:6] must be set "00"b to enable the word address for the
EEPROM. And, the setting PHY_ADR Bit [7:6] = 01 in EPAR is for the PHY address selected.
Please refer to the datasheet ch.6.12 ~ ch.6.14 about setting the EEPROM&PHY registers.
5.3.1 HOWTO Read EEPROM Data
The following steps are shown to read data from the serial EEPROM (SROM):
Step 1: write the word address into EPAR REG. 0CH.
Step 2: write command = 0x04 into the EEPROM&PHY Control Register (EPCR REG. 0BH)
to start the SROM + READ operation:
i. EPCR (REG. 0BH) EPOS Bit [3] = 0: select SROM mode (this is default: 0).
ii. EPCR (REG. 0BH) ERPRR Bit [2] = 1: issue READ command.
Step 3: read EPCR REG. 0BH and wait until ERRE Bit [0] = 0 ok, or just following Step 4.
Step 4: wait 40 us at least, then write "0" into EPCR REG. 0BH to clear READ command.
Step 5: read the SROM data high byte from EE_PHY_ H REG. 0EH, and the low byte from
EE_PHY_L REG. 0DH in the EEPROM&PHY Data registers.
HOWTO read SROM Word 0x03, Auto Load Control, shown as follows:
1. write word address 0x03 into EPAR REG. 0CH
iow ( 0x0C, 0x03 );
2. write the SROM + READ command = 0x04 into EPCR REG. 0BH
iow ( 0x0B, 0x04 );
3. wait until EPCR REG. 0BH Bit [0] = 0 ok, or just following Step 4
do { udelay ( 10 ); i++; } while ( ( i < 500 ) && ( inb ( IOaddr + 4 ) & 1 ) );
4. delay 40 us at least, then write "0" into EPCR REG. 0BH
Preliminary 23
Version: DM9000A-AN-V121
November 27, 2007
Page 24
DM9000A
APPLICATION NOTES
udelay ( 40 );
iow ( 0x0B, 0 );
5. EE_PHY_H REG. 0EH for the high-byte of the SROM data, and
(UINT8) e2prom[i*2+1] = ior ( 0x0E );
EE_PHY_L REG. 0DH for the low-byte
(UINT8) e2prom[i*2] = ior( 0x0D );
For example, to read the MAC address from the SROM word address 0& 1& 2:
for ( i = 0; i < 3; i++ ) { /* read Ethernet MAC address from SROM */
iow ( 0x0C, i );
iow ( 0x0B, 0x04 );
udelay ( 40 );
iow ( 0x0B, 0 );
/* read the SROM word da ta fro m EPDR to device address */
(UINT8) dev_addr[i*2+1] = ior ( 0x0E );/* the high byte of this 16-bit word */
(UINT8) dev_addr[i*2] = ior ( 0x0D ); /* the low byte of this 16-bit word */
}
5.3.2 HOWTO Write EEPROM Data
The following steps are to write data into the SROM:
Step 1: write the word address into EPAR REG. 0CH.
Step 2: write the data high byte into EE_PHY_H REG. 0EH, and the low byte to EE_PHY_L.
Step 3: write command= 0x12 into EPCR REG. 0BH to start the SROM + WRITE operation:
i. EPCR REG. 0BH WEP Bit [4] = 1: enable SROM WRITE operation.
ii. EPCR REG. 0BH EPOS Bit [3] = 0: select SROM mode (this is default: 0).
iii. EPCR (REG. 0BH) ERPRW Bit [1] = 1: issue WRITE command.
Step 4: read EPCR REG. 0BH and wait until ERRE Bit [0] = 0 ok, or just following Step 5.
Step 5: wait 500 us at least, then, write "0" into EPCR REG. 0BH to clear WRITE command.
HOWTO write 0x1E7 into SROM Word 0x06, Pin Co ntrol, shown as follows:
1. write word address = 0x06 to EPAR REG. 0CH
iow ( 0x0C, 0x06 );
Preliminary 24
Version: DM9000A-AN-V121
November 27, 2007
Page 25
DM9000A
APPLICATION NOTES
2. write the high-byte 0x01 into EE_PHY_H, and the low-byte 0xE7 into EE_PHY_L
iow ( 0x0E, 0x01 );
iow ( 0x0D, 0xE7 );
3. write the SROM + WRITE command = 0x12 into EPCR REG. 0BH
iow ( 0x0B, ( 0x02 | 0x10 ) );
4. wait until EPCR (REG. 0BH) ERRE Bit [0] = 0 ok, or just following Step 5
do { udelay ( 10 ); i++; } while ( ( i < 500 ) && ( inb ( IOaddr + 4 ) & 1 ) );
5. delay 500 us at least, then write "0" into EPCR REG. 0BH
udelay ( 60000 );
iow ( 0x0B, 0 );
For example, to write Ethernet node address 00:E0:63:0E:56:78 into SROM Word 0& 1& 2:
srom_write ( 0x00, 0xE000 ); /* Word 0: low-byte = 00, high-byte = E0 */
srom_write ( 0x01, 0x0E63 ); /* Word 1: low-byte = 63, high-byte = 0E */
srom_write ( 0x02, 0x7856 ); /* Word 2: low-byte = 56, high-byte = 78 */
void srom_write ( int offset, UINT16 dataW )
{
UINT16 i, tmpv;
/* write the SROM word address into EPAR REG. 0CH */
iow ( 0x0C, offset );
/* write the high-byte to EE_PHY_H REG. 0EH, low-byte to EE_PHY_L REG. 0DH */
iow ( 0x0D, dataW & 0xff ); /* the low-b yte of this 16-bit word */
iow ( 0x0E, (dataW >> 8) & 0xff ); /* the high-byte of this 16-bit word */
/* issue the SROM + WRIT E comm and = 0x12 into EPCR REG. 0BH */
iow ( 0x0B, 0x02 | 0x10 );
/* wait >500 us for SROM + WRITE completed then write "0" to clear command */
do { udelay (10); tmpv= inb (IOaddr+4); i++; } while ( (i < 500) && (tmpv & 1) );
udelay ( 60000 );
iow( 0x0B, 0 );
}
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5.4 How to Read/ Write PHY Register
The DM9000A PHY supports only 32 registers, which are mapped to EPAR (REG. 0CH) Bit
[4:0]. The default value of EPAR (REG. 0CH) PHY_ADR Bit [7:6] is "01" to select the PHY
mode. Please refer to the datasheet ch.6.12~6.14 about the EEPROM&PHY registers setting.
5.4.1 HOWTO Read PHY Register
The following steps are shown to read data from the PHY register:
Step 1: write the PHY register offset into EPAR REG. 0CH Bit [4:0], and the PHY address
"01"b into EPAR REG. 0CH Bit [7:6].
Step 2: write command = 0x0C into EPCR REG. 0BH to start the PHY + READ operation:
i. EPCR (REG. 0BH) EPOS Bit [3] = 1: select PHY mode (0: select SROM, see ch.5.3)
ii. EPCR (REG. 0BH) ERPRR Bit [2] = 1: issue READ command.
Step 3: read EPCR RE G. 0BH and wait until ERRE Bit [0] = 0 ok, or just following Step 4.
Step 4: wait 5 us maximum, then write "0x08" into EPCR REG. 0BH to clear READ command.
Step 5: read the PHY data high byte from EE_PHY_H REG. 0EH, and the low byte from
EE_PHY_L REG. 0DH in the EEPROM&PHY Data registers.
For example, to read the PHY register of BMCR at address offset = 0x00:
1. write offset = 0 into EPAR REG. 0CH Bit [4:0], and "01"b into EPAR REG. 0CH Bit[7:6]
iow ( 0x0C, ( 0x00 | 0x40 ) );/* issue PHY address+ 40H (EPAR PHY_ADR = "01"b) */
2. write the PHY + READ command = 0x0C into EPCR REG. 0BH
iow ( 0x0B, ( 0x04 | 0x08 ) );
3. wait until EPCR REG. 0B ERRE Bit [0] = 0 ok, or just following Step 4
do { udelay ( 1 ); i++; } while ( ( i < 50 ) && ( inb ( IOaddr + 4 ) & 1 ) );
4. delay 5 us maximum, then write "0x8" into EPCR REG. 0BH to clear it and keep PHY
udelay ( 5 ); /* wait 1~5 us for the PHY+ READ command completion */
iow ( 0x0B, 0x08 ); /* clear this PHY "READ" command */
5. read the high byte from EE_PHY_H REG. 0EH, and the low byte from EE_PHY_L
(UINT8) phy[offset*2+1] = ior ( 0x0E ); /* the high byte of this 16-bit word */
(UINT8) phy[offset*2] = ior ( 0x0D ); /* the low byte of this 16-bit word */
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5.4.2 HOWTO Write PHY Register
The following steps are to write data into the PHY register:
Step 1: write the PHY register offset into EPAR REG. 0CH Bit [4:0], and the PHY address Bit
[1:0] = "01"b into EPAR REG. 0CH Bit [7:6].
Step 2: write the PHY high byte data to EE_PHY_H REG. 0EH, and low byte to EE_PHY_L.
Step 3: write command = 0x0A into EPCR REG. 0BH to start the PHY + WRITE operation:
i. EPCR (REG. 0B) EPOS Bit [3] = 1: select PHY mode (0: select SROM, see ch.5.3)
ii. EPCR (REG. 0B) ERPRW Bit [1] = 1: issue WRITE command.
Step 4: read EPCR RE G. 0BH and wait until ERRE Bit [0] = 0 ok, or just following Step 5.
Step 5: wait 5 us maximum, then, write "0x8" into EPCR REG. 0BH to clear WRITE command.
For example, to write data = 0x101 into ANAR REG . 04 for the 100M Full-duplex support:
1. write offset= 4 into EPAR REG. 0CH Bit [4:0], and "01" into EPAR REG. 0CH Bit [7:6]
iow ( 0x0C, ( 0x04 | 0x40 ) );/* issue PHY address+ 40H (EPAR PHY_ADR = "01"b) */
2. write the PHY high byte 0x01 into EE_PHY_H, and low byte 0x01 into EE_PHY_L
iow ( 0x0E, 0x01 );
iow ( 0x0D, 0x01 );
3. write the PHY + WRITE command = 0x0A into EPCR REG. 0BH
iow ( 0x0B, ( 0x02 | 0x08 ) );
4. wait until EPCR (REG. 0BH) ERRE Bit [0] = 0 ok, or just following Step 5
do { udelay ( 1 ); i++; } while ( ( i < 50 ) && ( inb ( IOaddr + 4 ) & 1 ) );
5. delay 5 us maximum, then write "8" into EPCR REG. 0BH to clear it and keep PHY
udelay ( 5 ); /* wait 1~5 us for the PHY+WRITE command completion */
iow ( 0x0B, 0x08 ); /* clear this PHY "WRITE" command */
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5.5 How to Transmit Packets
0000
TX Buffer
TX
0BFF
0C00
RX Buffer
RX
3FFF
Figure 5.1 Packet Transmitting Buffer.
Before transmitting a packet, the data of the packet must save into the TX FIFO SRAM, which
is the internal SRAM address 0 ~ 0xBFF in the DM9000A MAC and to write F8H (MWCMD
REG. F8H port latched) into INDEX port firstly. Then, the length of the packet is put in TXPLH
REG. FCH for the high byte and TXPLL REG. FDH for the low byte. The final step is to set the
TXREQ (Transmit Request), Bit [0] in TCR REG. 02, for transmitting this packet.
The DM9000A will generate an interrupt at PTS Bit [1] = 1 in ISR REG. FEH, if setting Bit [1] =
1 in IMR REG. FFH, and also to set a completion flag to either TX1END Bit [2] = 1 or TX2END
Bit[3] = 1 in NSR REG. 01 in toggle to indicate that the packet is transmitted completely.
5.5.1 Packet Transmission
Step 1: check the memory 8/ 16 DATA width,
(u8) io_mode = ior ( 0xFE ) >> 7; /* ISR Bit [7] IOMODE indicating I/O DATA mode */
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Step 2: write the pa cket's data into TX FIFO SRAM,
outb ( IOaddr, 0xF8 ); /* trigger MWCMD REG. F8H with write_ptr++ */
/* u8 TX_data[]: the transmitting data, int TX_length: the length of TX_data[] */
if ( io_mode == DM9000A_BYTE_MODE ) { /* I/O 8-bit Byte mode if ( io_mode = = 1 ) */
for ( i = 0; i < TX_length; i++ ) /* loop to write a Byte data into TX FIFO SRAM */
outb ( TX_data[i], IOaddr + 4 ); }
else if ( io_mode == DM9000A_WORD_MODE ) { /* IO 16-bit Word mode if(io_mode== 0) */
(int) length_tmp = ( TX_length + 1 ) / 2; /* depended on Word mode for loop */
for ( i = 0; i < length_tmp; i++ ) /* loop to write a Word data into TX FIFO SRAM */
outw ( ( (u16 *) TX_data)[i], IOaddr + 4 ); }
Step 3: write the transmitting length into TXPLH REG. FCH and TXPLL REG. FDH,
/* write high byte of the TX data length into TXPLL REG. FDH */
iow ( 0xFD, (TX_length >> 8) & 0xff );
/* write low byte of the TX data length into TXPLH REG. FCH */
Iow ( 0xFC, TX_length & 0xff );
Step 4: start to transmit a packet out,
iow ( 0x02, 1 ); /* set a TX request command, TXREQ, Bit[0] of TCR REG.02 */
5.5.2 To Check a Completion Flag
If the driver is used the polling/ interrupt method, the program segment can be inserted into
the TX routine for detecting a packet transmission completed or even double-check interrupt:
(u8) TX_status = ior ( 0x01 ); /* read NSR REG. 01 status for TX completed */
if ( TX_status & (4 | 8) ) { /* success */ } /* check if TX1END or TX2END=1, TX ok*/
The program segment shown as follows can be inserted into the interrupt handler, if the driver
is used the interrupt driven and setting the IMR PTM Bit [1] = 1 enable:
(u8) INT_status = ior ( 0xFE ); /* got DM900 0A int er rupt status in ISR */
if ( INT_status & 0x02 ) { /* TX success */ /* check if PTS Bit [1] = 1, TX ok */
iow ( 0xFE, 0x02 ); } /* clear PTS Bit [1] latched in ISR */
// if ( INT_status & 0x01 ) { /* RX success */ iow ( 0xFE, 0x01 ); }
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5.6 How to Receive Packets
The received and filtered packet's data save in the RX FIFO, which is the internal SRAM
address 0x0C00 ~ 0x3FFF (13K Byte size) in the DM9000A MAC. There are four bytes for the
MAC header of each packet saving in the RX FIFO SRAM, and using the two registers of
MRCMDX REG. F0H and MRCMD REG. F2H to get the information of the packet incoming.
The first byte is used to check whether a packet is received and filtered in the RX SRAM. If
this byte is "01", it means there is a packet received. If this byte is "00", it means there is no
packet received in the RX SRAM. Before reading the other bytes, make sure the first byte of
the MAC header is "01" or LSB Bit [0] = 1. But, if Bit [1:0] is neither "01"b nor "00"b, the
DM9000A MAC/ PHY must do a software-reset in order to recover from the un-stable states
between the system bus and the DM9000A LAN chip. The second byte saves the "status"
information of the received packet. The format of the status "high byte" is the same as RSR
(REG. 06). Please refer to the datasheet ch.6.7. According to this format, the received packet
can be verified as either a correct packet or an error packet. The third and fourth bytes are the
"length" of the received packet. The others bytes are the received packet's data, or named the
RX payload. The following diagram is shown the format of the received package frame:
4 byte packet status & length Packet data
Length
01 status
low byte
Length
high byte
Data Data
Specify packet data length
4 byte packet status & length Packet data
Length
low byte
Length
high byte
Data Data
status
01
00
No packet
Figure 5.2 Block Diagram of the Received Packets.
5.6.1 Receive Interrupt Service Routine
The following program segment can be inserted to the interrupt handler if the driver is
designed as the interrupt driven or the polling method for waiting packets received ready:
u8 INT_status = ior ( 0xFE ); /* got DM9000A inter rup t statu s in ISR */
if ( INT_status & 0x01 ) { /* doing ch.5.6.2 */ /* check if PRS Bit [0]=1, RX ok */
iow ( 0xFE, 0x01 ); } /* clear PRS latched in ISR Bit [0] (see ch.5.5.2) */
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5.6.2 Packet Reception
The definition of MRCMDX (REG. F0H) is the memory data read command without address
increment register. MRCMDX is only used to read the received packet ready flag "01", or LSB
Bit [0] = 1 and Bit [7:5] & Bit [4:2] indicated the IP/TCP/UDP checksum status and type, from
the RX FIFO SRAM.
Here is an example to get the RX ready message:
(u8) RX_ready = ior ( 0xF0 ); /* dummy READ the packet RX ready flag */
RX_ready = (u8) inb( IOaddr + 4 ); /* got the most updated data */
if ( (RX_ready & 0x01)==1 ) { /* RX ready check: this byte must be "01" or "00" */
/* check the RX status & length (see ch.5.6.3) and income packets (see ch.5.6.4) */
} else if ( (RX_ready & 0x2)!=0 ) { /* stop interface and wait to *reset device */
iow ( 0xFF, 0x80 ); /* stop INT req ues t */
iow ( 0xFE, 0x0F ); /* clear ISR status */
iow ( 0x05, 0x00 ); /* stop RX func tio n */
(u8) device_wait_reset = TRUE; /* raise the MAC/ PHY software-reset flag */
/* iow ( 0x00, 0x01 ); // it’s quick software-reset to replace abov e*
udelay ( 10 );
iow ( 0x00, NCR_set );
iow ( 0xFF, 0x80 );
iow ( 0x05, RCR_set | 1 ); */
/* then, re-new system variables and counters for dropped and queued packets... */
}
5.6.3 To Check the Packet Status and Length
MRCMD (REG. F2H): memory data read command with the increment of the RX read pointer.
The read pointer will be increased after reading the memory read command MRCMD (REG.
F2H). The size, the increment of the RX read pointer, is depended on the system application,
which the I/O bus width is Byte/ Word to increase one or two bytes respectively. MRCMD
(REG. F2H) is only used to read the RX status, length and the packet's data from the RX
SRAM.
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Here is an example to get the RX status and length:
(u8) io_mode = ior ( 0xFE ) >> 7; /* ISR Bit [7] IOMODE indicating DATA I/O mode */
outb ( 0xF2, IOaddr ); /* trigger MRCMD (REG. F2H) with read_ptr++ */
/* int RX_status: the RX packet status, int RX_length: the length of the RX packet*/
if ( io_mode == DM9000A_BYTE_MODE ) { /* I/O 8-bit Byte mode if ( io_mode = = 1 ) */
RX_status = inb ( IOaddr + 4 ) + ( inb ( IOaddr + 4 ) << 8 );
RX_length = inb ( IOaddr + 4 ) + ( inb ( IOaddr + 4 ) << 8 ); }
else if ( io_mode== DM9000A_WORD_MODE ) { /* I/O 16-bit Word mode if(io_mode== 0 ) */
RX_status = inw ( IOaddr+ 4 ); /* the high byte is the status as RSR REG. 06 */
RX_length = inw ( IOaddr + 4 ); }
5.6.4 Receive the Packet's Data
The read pointer will be increased after reading the memory read command MRCMD REG.F2.
According to the length of the received packet, dump out the RX payload and the 4-byte CRC.
Here is an example to get the RX packet's data:
/* u8 RX_data[] : the data of the received packet with the 4-byte CRC checksum */
if ( io_mode == DM9000A_BYTE_MODE ) { /* I/O 8-bit Byte mode if ( io_mode = = 1 ) */
for ( i = 0 ; i < RX_length ; i++ ) /* loop to READ a Byte data from RX FIFO SRAM */
RX_data[ i ] = (u8) inb ( IOaddr + 4 );
}
else
if ( io_mode== DM9000A_WORD_MODE ) { /* I/O 16-bit Word mode if(io_mode== 0) */
(int) tmp_length = ( RX_length + 1 ) / 2; /* Word mode */
for ( i = 0 ; i < tmp_length ; i++ ) /* loop to READ a Word data from RX FIFO SRAM*/
( (u16 *)RX_da ta) [ i ] = inw ( IOa d dr + 4 ); }
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6 The Others
6.1 How to transmit and receive more than 2048-byte pack ets
If a system transmits or receives more than 2048-byte packets, which size is although over
802.3 spec., the TCR (REG. 02) Bit [6] TJDIS and RCR Bit [6] WTDIS should be set to "1".
For example,
#define TCR 0x02
#define RCR 0x05
iow ( TCR , ior ( TCR ) | 0x40 );
iow ( RCR , ior ( RCR ) | 0x40 );
6.2 The performance of DM9000A
The performance of the DM9000A is depended on the capability of MPU/ MCU. If the
MPU/MCU is so fastest to match the timing of the maximum speed for the DM9000A IOR#/
IOW#, the performance will be: 10ns + 10ns = 20ns -> 50Mbps.
Receive or transmit data -> 8 * 50Mbps -> 400 Mbps
8-bit mode
RX & TX data at the same time -> 8 * 50Mbps/ 2 -> 200 Mbps
Receive or transmit data -> 16 * 50Mbps -> 800 Mbps
16-bit mode
RX & TX data at the same time -> 16 * 50Mbps/ 2 -> 400 Mbps
Note: The DM9000A is the 10/100 Mbps Ethernet NIC, so the maximum speed is 100 Mbps.
6.3 WOL (Wake-u p on LAN)
The DM9000A LAN chip also supports the WOL function and the pin 22 WAKE (or the pin 38
LED2, if setting the EEPROM Word 7 Bit [13:12] = 10 in 16-bit mode) output the wake-up
signal to the embedded system. There are three methods to generate WOL signals, which are
the Magic Packet, the Link Change, and the Sample Frame types. This section will discuss
how to implement the WOL function in the DM900 0A MAC.
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(1) Magic Packet
If the DM9000A receives a broadcast packet which content is "FF:FF:FF:FF:FF:FF"+"16 times
of the Node address", then the wake-up pin will be activated. Please note that the Node
address must be the same as the Physical address in the PAR REG. 10H~REG. 15H.
For example:
#define NCR 0x00
#define WCR 0x0F
iow ( WCR , ior ( WCR ) | 0x08 ); /* Magic Packet event enable */
iow ( NCR , ior ( NCR ) | 0x40 ); /* Wake-up remote enable */
/* If a physical address in DM9000A PAR REG. 10H ~ REG. 15H is 00:60:6e:90:00:01 */
/* DM9000A WOL would be active, while received t he Magic packet as follows, */
/* FF FF FF FF FF FF 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 */
/* 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 */
/* 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 */
/* 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 */
/* 00 60 6E 90 00 01 (+ another DM9000A TX auto 4-byte CRC appe nds) */
(2) Link Change
If the link status of the internal PHY has been changed, the wake-up pin will be active.
For example,
#define NCR 0x00
#define WCR 0x0F
iow ( WCR , ior ( WCR ) | 0x20 ); /* Link Change event enable */
iow ( NCR , ior ( NCR ) | 0x40 ); /* Wake-up function enable */
(3) Sample Frame
The Sample Frame would be made up of 6 packets and the maximum size of each packet
can be 2048-byte. The wake-up pin will be active if the DM9000A receives only one set of the
sample frames. The following description will show how to set the Sample Frame in det ail.
z Firstly close the DM9000A receiver function and set the Bit [0] in RCR REG. 05 to "0".
z Stop the self recover function. Set the Bit [7] PAR in IMR REG. FFH to be "0".
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z Save the 6 packets max into the DM9000A FIFO SRAM. The format is shown below,
m-byte3 / packet 3 m-byte2 / packet 2 m-byte1 / packet 1 m-byte0 / packet 0
packet 3-byte 0 packet 2-byte 0 packet 1-byte 0 packet 0-byte 0 0000h
packet 3-byte 1 packet 2-byte 1 packet 1-byte 1 packet 0-byte 1 0004h
： ： ： ：
： ： ： ：
： ： ： ：
： ： ： ： ：
packet 3-byte 2047 packet 2-byte 2047 packet 1-byte 2047 packet 0-byte 2047 1FFCh
m-byte3 / packet 5 m-byte2 / packet 4 m-byte1 / Condition 1 m-byte0 / Condition 0
packet 5-byte 0 packet 4-byte 0 Cond. 1-byte 0 Cond. 0-byte 0 2000h
packet 5-byte 1 packet 4-byte 1 Cond. 1-byte 1 Cond. 0-byte 1 2004h
： ： ： ：
： ： ： ：
： ： ： ：
： ： ： ： ：
packet 5-byte 2047 packet 4-byte 2047 Cond. 1-byte 2047 Cond. 0-byte 2047 3FFCh
DM9000A TX&RX
Memory location
0008h
000Ch
0010h
DM9000A TX&RX
Memory location
2008h
200Ch
2010h
The format of Condition 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
The Condition of packet 1
The Condition of packet 0
The Condition of packet 2
The Condition of packet 3
The format of Condition 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
The Condition of packet 5
The Condition of packet 4
Don’t care.
Don’t care.
If the condition is "00" or "01", don’t care the byte; if "10", check the byte is matched or not;
and if "11", the DM9000A MAC stops checking the sample frame.
z Restart the Sample Frame function by setting the Bit [4] SAMPLEEN in WCR REG. 0FH
to "1" and enable the WOL function by setting the WAKEEN Bit [6]=1 in NCR (REG. 00).
z Restart the DM9000A receiver function by setting the Bit [0] in RCR REG. 05 to be "1".
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For example,
#define NCR 0x00
#define RCR 0x05
#define WCR 0x0F
#define MWRL 0xFA
#define MWRH 0xFB
#define IMR 0xFF
iow ( RCR , ior ( RCR ) & 0xfe );
iow ( IMR , ior ( IMR ) & 0x3f );
/* Here, the Sample Frame put in the DM9000A FIFO SRAM 16KB: 0x0000~ 0x3FFF */
for (i = 0, sample_ptr = 0; i < sample_length; i++, samp le_ptr += 4) {
/* set sample_ptr to MWRL as low byte and to MWRH as high byte in DM9000A SRAM */
iow ( MWRL, sample_p tr & 0xff );
iow ( MWRH, (sample_ ptr >> 8) & 0xff );
outb ( 0xF8, IOaddr ); /* Output port number MWCMD=0xF8 TX WRITE locking */
if (i % 2) outw ( ( ((u16 *) sample _ frame)[(i+1)/2] >> 8), IOaddr + 4 );
else outw ( ((u16 *) sample_frame)[(i+1)/2], IOaddr + 4 ); } /* 16-bit mode */
/* set the condition Byte [0] & Byte [1] of the Sample Frame in 0x2000~ 0x3FFD */
for (i = 0, sample_ptr = 0x2000; i < sample_length; i++, sample_ptr += 4) {
/* set sample_ptr to MWRL as low byte and to MWRH as high byte in DM9000A SRAM */
iow ( MWRL, sample_p tr & 0xff );
iow ( MWRH, (sample_ ptr >> 8) & 0xff );
outb ( 0xF8, IOaddr ); /* Output port number MWCMD=0xF8 TX WRITE locking */
outw( 0x0002, IOaddr + 4 ); } /* Fill Bit [1:0]="10" of condition 0 in pkt 0 */
// iow ( MWRL, (sample_ptr+4) & 0xff); iow ( MWRH, ((sample_ptr+4) >> 8) \
// & 0xff); outw( 0x0003, IOaddr + 4 ); /* Fill Bit [1:0]="11" to stop checking */
iow ( WCR , ior ( WCR ) | 0x10 ); /* Sample Frame enable */
iow ( NCR , ior ( NCR ) | 0x40 ); /* Wake-up remote enable */
iow ( RCR , ior ( RCR ) | 0x01 );
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6.4 IP/TCP/UDP checksums Offload
The DM9000A chip supports the IP/TCP/UDP checksum generations and status checking.
And enable the IP/TCP/UDP checksums offload function in the TCP/IP upper layers of the
embedded OS, while setting the DM9000A IP/TCP/UDP checksum generations and checking.
List powerful function bits in TCSCR & RCSCSR:
TX Check Sum Control Register (TCSCR REG. 31H):
Bit Name Description
2 UDPCSE UDP Check Sum Generation Enable
1 TCPCSE TCP Check Sum Generation Enable
0 IPCSE IP Check Sum Generation Enable
RX Check Sum Control Status Register (RCSCSR REG. 32H):
Bit Name Description
7 UDPS UDP Check Sum Status 0: checksum OK, if UDP packet received.
6 TCPS TCP Check Sum Status 0: checksum OK, if TCP packet received.
5 IPS IP Check Sum Status 0: checksum OK, if IP packet received.
4 UDPP UDP Packet if indicating 1
3 TCPP TCP Packet if indicating 1
2 IPP IP Packet if indicating 1
1 RCSEN Receive Check Sum Enable Checking
When set, the checksum status will be stored in packet first byte of status header.
0 DCSE Discard Check Sum Error Packets
When set, if IP/TCP/UDP checksum field is error , this packet will be discarded.
For example,
#define TCSCR 0x31
#define RCSCSR 0x32
iow ( TCSCR , 0x07 ); /* TX IPCSE + TCPCSE + UDPCSE cs-generation enable */
iow ( RCSCSR , 0x03 ); /* RX checksums checking bad-pkt-dis car d enable */
/* IPS/TCPS/UDPS indicating check-sum status, while RX IP/TCP/UDP (good) packets */
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6.5 AUTO-MDIX and Application circuit
When design AUTO-MDIX circuit of the DM9000A in the embedded system, the following
layout guide must be cared: Traces routed from RXI± and TXO± to the transformer should run
in close pairs directly to the transformer such as YCL-PH163539. The network interface
should be void of any signals other than the TXO± and RXI± pairs between the RJ-45 to the
transformer and the transformer to the DM9000A.
Figure 6.1 AUTO-MDIX 10Base-T/100Base-TX Application.
The DM9000A is default turning on AUTO-MDIX feature, and there are two ways to disable
AUTO-MDIX function:
1. To set the SROM Word 7, Wake-up Mode Control, Bit [14] = 1 then zero to re-load it,
srom_write (0x07, 0x180); /* PHY power-on but disable Auto-MDIX setting into SROM */
iow ( 0x0B, 0x20 ); /* REEP Bit [5] of EPCR REG. 0BH to re-load EEPROM value */
iow ( 0x0B, 0x00 ); /* REEP Bit [5]= 0 normal after 400 us delay for re-load */
2. To write high "1" to the Bit [4] Mdix-down in the PHY REG. 20,
phy_write(20, 0x0010);/* Mdix_down Bit[4]= 1 with Mdix_fix_Value Bit[5]=0 for MDI */
phy_write(20, 0x0030);/* Mdix_down Bit[4]=1 with Mdix_fix_Value Bit[5]=1 for MDIX */
Preliminary 38
Version: DM9000A-AN-V121
November 27, 2007
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