Fig. 7: Simplified schematics of EN_BCK2_LS internal pin configuration................................46
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1Preface
1.1About this manual
This Hardware Manual describes the DIDO CPU modules
family design and functions.
Precise specifications for the Texas Instruments DM814x and
AM387x processors can be found in the CPU datasheets and/or
reference manuals.
1.2Copyrights/Trademarks
Ethernet® is a registered trademark of XEROX Corporation.
All other products and trademarks mentioned in this manual
are property of their respective owners.
All rights reserved. Specifications may change any time without
notification.
1.3Standards
DAVE Embedded Systems Srl is certified to ISO 9001
standards.
1.4Disclaimers
DAVE Embedded Systems does not assume any responsibility
about availability, supplying and support regarding all the
products mentioned in this manual that are not strictly part of
the DIDO CPU module.
DIDO CPU Modules are not designed for use in life support
appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal
injury. DAVE Embedded Systems customers who are using or
selling these products for use in such applications do so at their
own risk and agree to fully indemnify DAVE Embedded Systems for any damage resulting from such improper use or
sale.
1.5Warranty
DIDO is warranted against defects in material and
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workmanship for the warranty period from the date of
shipment. During the warranty period, DAVE Embedded Systems will at its discretion decide to repair or replace
defective products. Within the warranty period, the repair of
products is free of charge as long as warranty conditions are
observed.
The warranty does not apply to defects resulting from improper
or inadequate maintenance or handling by the buyer,
unauthorized modification or misuse, operation outside of the
product’s environmental specifications or improper installation
or maintenance.
DAVE Embedded Systems will not be responsible for any
defects or damages to other products not supplied by DAVE Embedded Systems that are caused by a faulty DIDO module.
1.6Technical Support
We are committed to making our product easy to use and will
help customers use our CPU modules in their systems.
Technical support is delivered through email to our valued
customers. Support requests can be sent to
support-dido@dave.eu.
Software upgrades are available for download in the restricted
access download area of DAVE Embedded Systems web site:
http://www.dave.eu/reserved-area. An account is required to
access this area and is provided to customers who purchase the
development kit (please contact support-dido@dave.eu for
account requests)..
Please refer to our Web site at
http://www.dave.eu/dave-cpu-module-dm814x-dido.html for the
latest product documentation, utilities, drivers, Product
Change Notifications, Board Support Packages, Application
Notes, mechanical drawings and additional tools and software.
Tab. 2: Abbreviations and acronyms used in this manual
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Revision History
VersionDateNotes
0.9.0March 2013First Draft
0.9.1March 2013First Release
0.9.2March 2013First Release with DIDO
development kit
Minor fixes
1.0.0April 2013Released with NELK 4.0.0
Minor fixes
1.0.1May 2013Added information on
EMAC_RMREFCLK signal
Minor fixes
1.0.2December 2013Fixed JTAG_TDO and JTAG_TCK
pinout table entries
1.0.3January 2014Updated pin J2.97 information
Minor fixes
1.0.4April 2014SPI2: removed J2.36 from the
muxable signals
Added HDMI CEC and HPDET
information
1.0.5August 2014Added EMAC_RMREFCLK
termination resistors information
Updated block diagram
Minor fixes
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2Introduction
DIDO is a ready-to-use CPU module/SOM family, based on
Texas Instruments
Cortex-A8 high performance
application processor from
DM814x (“DaVinci”) and
AM387x (“Sitara”) models.
DIDO is is the cutting edge
solution for a high range of
applications, including video
surveillance cameras,
medical video analysis,
smart home controllers,
security systems,
automation and point of
service.
Fig. 1: DIDO CPU module
Fig. 2: DIDO (top-right), NAON
(top-left) and MAYA (bottom)
DIDO is the first
product of DAVE
Embedded Systems
ULTRA Line CPU
modules class, which
includes best-in-class
solutions and
full-featured SOMs.
DIDO shares the same
DM814x processor
with MAYA (LITE Line)
and NAON (ESATTA
Line) and is built with
the same connectors
format (ZFF) as NAON
and LIZARD (ESATTA
Line).
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2.1Product Highlights
●Top class CPU module family based on Texas
Instruments DM814x/AM387x processors models.
●ARM Cortex-A8 architecture @ up to 1 GHz
●Up to 2 GB DDR3 @ 533 MHz SDRAM
●HD Video Encoding/Decoding Capabilities
(High-Definition Video Image Coprocessing – HDVICP v2
engine)
●Multiple video input and output channels
●C674x DSP engine (available on DM8148)
●NEON Multimedia co-processor and PowerVR® SGX
530 Vector/3D Graphics Engine
●On-board flash (NOR and NAND) storage
●Small form factor
●Rich interfaces set including PCI Express, dual CAN,
dual Ethernet, SATA and native 3.3V I/O
●NAON and LIZARD (ESATTA Line) pinout compatible
Fig. 3: DIDO SOM (top view)
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2.2Block DiagramBlock Diagram
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2.3Feature Summary
FeatureSpecificationsOptions
CPU“DaVinci” DM814x
“Sitara” AM387x
ARM v7 architecture
Up to 1 GHz
RAMDDR3 SDRAM @ 533 MHz
Up to 2 GB
StorageFlash NOR SPI
Flash NAND on Local bus
I²C 32 kbit EEPROM
External local
bus
Expansion bus One PCI Express 2.0 Port With Integrated
16 bit GPMC
PHY (5.0 GT/s Endpoint/Root Complex
port)
Tab. 3: CPU, Memories, Busses
FeatureSpecificationsOptions
Graphics
Controller
2D/3D Engines NEON Multimedia SIMD coprocessor
CoprocessorsUp to 750 MHz C674x VLIW DSP
Video capture2x HD Video Input port
HD Video Processing Subsystem
(HDVPSS)
1x up to 24 bit HD Video Output port
1x up to 18 bit HD Video Output port
1x HDMI 1.3 channel + DDC
Analog TV output
TFT/RGB support
PowerVR SGX 530 3D Accelerator
HD Video Coprocessor HDVICP v2
USB2x USB Host 2.0, 480 Mbps, with PHY
UARTs3x UARTs
GPIOUp to 128 lines, shared with other
Input
interfaces
1x USB OTG, 480 Mbps (integrated PHY)
functions (interrupts available)
TSC2003 4-wire resistive touch screen
controller
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FeatureSpecificationsOptions
Available ADC channel
Up to 8x8 keypad controller
Networks1x Fast Ethernet with PHY
1x GRMII 10/100/1000 Mbps interface
High-end Dual CAN controller
StorageSerial ATA 3.0 Gbps with integrated PHY
SD/MMCUp to 3x MMC/SD/SDIO Serial interfaces
(up to 48 MHz)
Serial buses2x I²C, 3x SPI
Audio1x McASP channel
TimersUp to 6 programmable general purpose
timers (PWM function available)
RTCOn board (provided by TPS659113
PMIC), external battery powered
DebugJTAG
EMU port
Tab. 4: Peripherals
FeatureSpecificationsOptions
Supply
Voltage
Active power
consumption
Dimensions68.6 mm x 59.7 mm
Weight<tbd>
MTBF<tbd>
Operation
temperature
Shock<tbd>
Vibration100 G resistance
Connectors2x 140 pin
Connectors
insertion/remo
val
+3.3V
See section 8.3 - Power consumption
0..70 °C
-40..+85 °C
<tbd>
Tab. 5: Electrical, Mechanical and Environmental Specifications
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3Design overview
The heart of DIDO module is composed by the following
components:
●Texas Instruments DM814x/AM387x processor
●Power supply unit
●DDR3 memory banks
●NOR and NAND flash banks
●2x 140 pin connectors with interfaces signals
This chapter shortly describes the main DIDO components.
3.1“DaVinci” DM814x / “Sitara” AM387x CPU
DM814x DaVinci™ and AM387x Sitara™ are highly-integrated,
scalable and programmable CPU families from Texas
Instruments.
DaVinci™ digital media processor solutions are tailored for
digital audio, video, imaging, and vision applications.
Sitara™ ARM microprocessors (MPUs) are designed to
optimize performance and peripheral support for customers in
a variety of markets.
The architecture is designed to provide video, image, graphics
and processing power sufficient to support the following:
● Home and Industrial automation
● Test and measurement
● Digital Signage
● Medical instrumentation
● Remote monitoring
● Motion control
● Point-of-Sale
● Single Board Computers
The following subsystems are part of the device:
● Microprocessor unit (MPU) subsystem based on the ARM®
Cortex™-A8 architecture:
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ARM Cortex-A8 RISC processor, with Neon™
Floating-Point Unit, 32KB L1 Instruction Cache, 32KB L1
Data Cache and 512KB L2 Cache
CoreSight Embedded Trace Module (ETM)
ARM Cortex-A8 Interrupt Controller (AINTC)
Embedded PLL Controller (PLL_ARM)
● PowerVR SGX 530 subsystem for vector/3D graphics
acceleration to support display and gaming effects
● The HDVICP2 is a Video Encoder/Decoder hardware
accelerator supporting a range of encode, decode, and
transcode operations for most major video codec standards.
The main video Codec standards supported in hardware are
MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP,
RV9/10, AVS-1.0, and ON2 VP6.2/VP7.
● The C674x DSP core is the high-performance floating-point
DSP generation in the TMS320C6000™ DSP platform and is
code-compatible with previous generation C64x Fixed-Point
and C67x Floating-Point DSP generation. The C674x
Floating-Point DSP processor uses 32KB of L1 program
memory with EDC and 32KB of L1 data memory. The DSP
has 256KB of L2 RAM with ECC, which can be defined as
SRAM, L2 cache, or a combination of both.
● The high definition video processing subsystem (HDVPSS)
includes video/graphics display and capture processing
using the latest TI developed algorithms, flexible
compositing and blending engine, and a full range of
external video interfaces in order to deliver high quality
video contents to the end devices.
The following table shows a comparison between the devices,
highlighting the differences:
ProcessorDSP3DHDVICPHDVPSS Max clock
speed
DM8148YesYesYesYes1 GHz
DM8147Yesn.a.YesYes1 GHz
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ProcessorDSP3DHDVICPHDVPSS Max clock
speed
AM3874n.a.Yesn.a.Yes1 GHz
AM3872n.a.n.a.n.a.Yes1 GHz
AM3871n.a.n.a.n.a.n.a.1 GHz
Tab. 6: DM814x/AM387x comparison
3.2DDR3 memory bank
DDR3 SDRAM memory bank is composed by 4x 16-bit width
chips resulting in 2x 32-bit combined width banks.
The following table reports the SDRAM specifications:
CPU connectionSDRAM bus
Size min128 MB
Size max2 GB
Width32 bit
Speed533 MHz
Tab. 7: DDR2 specifications
3.3NOR flash bank
NOR flash is a Serial Peripheral Interface (SPI) device. By
default this device is connected to SPI channel 0 and acts as
boot memory.
The following table reports the NOR flash specifications:
CPU connectionSPI channel 0
Size min4 MByte
Size max128 MByte
BootableYes
Tab. 8: NOR flash specifications
3.4NAND flash bank
On board main storage memory is a 8-bit wide NAND flash. By
default it is connected to GPMC_NCS0 chip select. Optionally it
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can be connected to GPMC_NCS7.
CPU connectionGPMC bus
Page size512 byte, 2 kbyte or 4 kbyte
Size min32 MByte
Size max2 GByte
Width8 bit
BootableYes
Tab. 9: NAND flash specifications
3.5Memory Map
The total system memory is divided across various
processors/subsystems. Due to this “multiprocessor” nature,
Memory Mapping for DIDO Module is quite complex, since it
involves the Cortex-A8 core, the two Media Controllers
(Cortex-M3, that take care of the HDVPSS and HDVCIP
subsystems) and the DSP. NELK Memory Map is described in
detail on the dedicated page on the Developer's Wiki:
DIDO, as the other Performance Line CPU modules, embeds all
the elements required for powering the unit, therefore power
sequencing is self-contained and simplified. Nevertheless,
power must be provided from carrier board, and therefore
users should be aware of the ranges power supply can assume
as well as all other parameters. For detailed information,
please refer to Section 5.1.
3.7CPU module connectors
All interface signals DIDO provides are routed through two 140
pin 0.6mm pitch stacking connectors (named J1 and J2). The
host board must mount the mating connectors and connect the
desired peripheral interfaces according to DIDO pinout
specifications.
DIDO modules belongs to the ULTRA Line product class, but
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the basic connectors pinout (called ZFF, Z Form Factor) is
compatible with NAON and LIZARD SOMs. This means that the
interfaces that are in common with the modules of the same
class are routed on the same connector pins: for example, USB
ports (which are implemented on each module) can be found on
the same J1 and J2 pins. On the contrary, specific interfaces
that are available only on one module are replaced with
different interfaces on the other modules. As an example, the
following table reports the three configuration of pin J2.33:
ModuleLIZARDNAONDIDO
PinJ2.33J2.33J2.33
InterfaceLATCHVOUT0-
Pin nameLATCHED_A2VOUT0_FLD/CA
M_PCLK/GPMC_
A12/GP2_02
FunctionLatched
address bit 2
Digital Video
Output Field ID
output
DGND
Ground
Tab. 10: ZFF form factor – example of pinout differences
For mechanical information, please refer to Section 4
(Mechanical specifications). For pinout and peripherals
information, please refer to Sections 6 (Pinout table) and 7
(Peripheral interfaces).
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4Mechanical specifications
This chapter describes the mechanical characteristics of the
DIDO module.
Mechanical drawings are available in DXF format from
the DIDO page on DAVE Embedded Systems website
(http://www.dave.eu/dave-cpu-module-am387x-dm814x-d
ido.html).
4.1Board Layout
The following figure shows the physical dimensions of the DIDO
module:
Fig. 4: Board layout - top view
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● Board height: 59.7 mm
● Board width: 68.6 mm
● Maximum components height is 3.1 mm.
● PCB thickness is 1.8 mm.
The following figure highlights the maximum components'
heights on DIDO module:
Fig. 5: Board layout - size view
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4.2Connectors
The following figure shows the DIDO connectors layout:
Fig. 6: Connectors layout
The following table reports connectors specifications:
Part numberHirose FX8C-140S-SV
Height5.6 mm
Length48.6 mm
Depth3.95 mm
Mating
connectors
Hirose FX8C-140P-SV (5 mm board-to-board height)
Hirose FX8C-140P-SV1 (6 mm board-to-board height)
Hirose FX8C-140P-SV2 (7 mm board-to-board height)
Hirose FX8C-140P-SV4 (9 mm board-to-board height)
Hirose FX8C-140P-SV6 (11 mm board-to-board height)
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5System Logic
5.1Power
Implementing correct power-up sequence for AM387x/DM814x
processor is not a trivial task because several power rails are
involved. DIDO hides this complexity because it embeds most
of the circuitry required.
In typical applications AM387x/DM814x processor interfaces
directly to 3.3V-powered devices that are hosted on carrier
board. In order to be compliant with AM387x/DM814x
power-up requirements, these devices should be turned on at a
specific time during power-up sequence. To achieve this, DIDO
provides EN_BCK2_LS signal. When DIDO is powered, this
signal is low: this means that carrier board 3.3V-powered
devices have to be powered off. During power-up sequence this
signal shall be raised by DIDO circuitry, indicating carrier
board 3.3V-powered devices have to be turned on. After this
rising edge, EN_BCK2_LS shall be kept high.
5.2PMIC
This section will be completed in a future version of this
manual.
5.3Reset
Five different signals are provided by DIDO SOM. Following
sections describes in more detail each one.
5.3.1MRST (J2.102)
This pin is connected to HDRST signal (cold reset) of PMIC
TPS659113. When high, this signals keeps PMIC in off mode
and resets TPS659113 to default settings. MRST has a weak
internal pulldown.
5.3.2PORSTn (J2.109)
PORSTn is a bidirectional open-drain signal. It is connected to:
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● PORn input (Power-on Reset) of DM8148 processor
● output of voltage monitor (see Section 5.4)
● NRESPWRON2 output of PMIC.
Internal pullup is 10kOhm.
5.3.3RSTOUTn (J2.91)
This output signal is asserted by DM8148 processor until it
gets out of reset. It is usually used to reset external memories
and peripherals connected to processor. It is connected to:
● RSTOUT_WD_OUTn pad of DM8148 processor
● 2k2 pull down resistor
● peripherals and memories.
In case it is used to reset devices on carrier board, its driving
capability has to be taken into account.
5.3.4CPU_RESETn (J2.15)
This input signal acts as External Warm Reset. It is connected
to processor's RESETn pad. Internal pullup is 2.2kOhm.
5.3.5JTAG_TRSTn (J2.100)
This input signal acts as Emulation Warm Reset. It is connected
to processor's TRSTn pad. Internal pulldown is 4.7kOhm
5.4Voltage monitor
DIDO SOM is equipped with a multiple-input voltage monitor
whose reset output is connected to PORSTn. Monitored voltage
rails include 3.3V provided by carrier board.
5.5Boot options
Thanks to the versatility of internal BootROM,
DM814x/AM387x processors provide a rich set of boot options
and different configurations selectable via BTMODE[15:0]
bootstrap pins. For a detailed explanation on the boot process
for DM814x/AM387x processors, please refer to the Technical
Reference Manual (available from TI website) at section ROM
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Code Memory and Peripheral Booting. In order to fully
understand how boot work on DIDO platform, please refer to
Section 3.5 (Memory Map).
By default, DIDO provides the following configuration:
SYS_BOOT
pin
BTMODE[15]0GPMC CS0 Wait enableNO
BTMODE[14:13]10GPMC CS0
BTMODE[12]1GPMC CS0 bus widthNO
BTMODE[11]0RSTOUT_WD_OUT
BTMODE[10]0XIP (on GPMC) Boot
BTMODE[9:8]01Ethernet PHY Mode
BTMODE[7:5]000ReservedNO
BTMODE[4:0]10111Boot Mode OrderYES
Default
Value
FunctionConfigurable
NO
Address/Data
multiplexing mode
NO
Configuration
NO
Options
NO
Selection
Bootstrap pins BTMODE[4:0] are routed to main connectors in
order to allow to change bootstrap strategy in user's
application by optional external circuitry.
5.5.1Default boot configuration
With the default configuration, the boot sequence is:
1. MMC
2. SPI
3. UART
4. EMAC
The internal BootROM tries each boot mode in sequence and
stops when it find a valid boot code. For example, assuming
that:
1. default configuration is not changed,
2. no boot MMC card is connected to processor's MMC1
interface,
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3. and there's a valid boot code programmed in SPI memory
the boot sequence performed by ARM core will be:
1. execute bootrom from internal ROM code memory
2. launch 1st stage bootloader
•copied from on-board NOR flash memory connected to
SPI0 port to on-chip SRAM by bootrom
•executed from on-chip SRAM
3. launch 2nd stage bootloader
•copied by 1st stage bootloader from NOR flash memory
connected to SPI0 port to SDRAM
•executed from SDRAM
If no boot code is available in SPI NOR flash (for the bootrom
this means that the first sector read returns 0xFFFFFFFF) the
bootrom tries UART (please see also Section 5.7) and EMAC
peripheral booting.
5.5.2Boot sequence customization
The following reference schematic shows a simple resistor
network that can be implemented on carrier board hosting
DIDO module. For each BTMODE[4:0] pin it is possible to
populate upper or lower side resistor in order to change default
value that is set on module itself. The available boot mode
orders are reported in Table 4-8. “BTMODE[4-0] Configuration
Pins” in Section 4 “ROM Code Memory and Peripheral Booting”
of the DM814x/AM387x Technical Reference Manual.
5.6Clock scheme
This section will be completed in a future version of this
manual.
5.7Recovery
For different reason, starting from image corruption due power
loss during upgrade or unrecoverable bug while developing a
new U-Boot feature, the user will need, sooner or later, to
recover (bare-metal restore) the DIDO SOM without using the
bootloader itself. The following paragraphs introduce the
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available options. For further information, please refer to DAVE
Embedded Systems Developers Wiki or contact the Technical
Support Team.
5.7.1JTAG Recovery
JTAG recovery, though very useful (especially in development
or production environment), requires dedicated hardware and
software tools. DIDO provides the JTAG interface, which,
besides the debug purpose, can be used for programming and
recovery operations. For further information on how to use the
JTAG interface, please contact the Technical Support Team.
5.7.2UART Recovery
UART recovery does not requires any specialized hardware,
apart a PC and a DB9 serial cross cable. The boot sequence
must include the UART option and a way to enable it. Then a
simple procedure allow to load the 1
from the serial line. When the 2nd stage bootloader is running,
reprogramming the flash memory is straightforward.
st
and 2nd stage bootloader
The UART boot uses UART0 interface.
5.7.3SD/MMC Recovery
MMC recovery is a valuable options that requires no special
hardware at all, apart a properly formatted MMC. The boot
sequence must include the SD/MMC option and a way to enable
it. When SD/MMC boot option is selected, bootrom looks for a
valid boot sector on SD/MMC1. Once the board is running after
booting from SD, reprogramming the flash memory is
straightforward.
5.8Multiplexing
DM814x/AM387x pins can have up to seven alternate function
modes. The I/O pins can be internally routed to/from one of
several peripheral modules within the device: this routing is
referred to as Pin Multiplexing. Pin Multiplexing allows
software to choose the subset of internal signals which will be
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mapped to balls of the device for a given application. Pin
multiplexing selects which one of several peripheral pin
functions controls the pin's I/O buffer output data values.
Please note that pin mux configuration is a very critical
step. Wrong configuration may lead to system instability,
side effects or even damage the hardware permanently
Pin multiplexing configuration is quite complex in DIDO but a
tool from TI, the Pin Mux Utility, can help to perform this
operation. Software installation and generic usage
documentation is available on this page of the TI Embedded
Processors Wiki:
The TPS659113 PMIC provides a real-time clock (RTC)
resource with
● Oscillator for 32.768-kHz crystal
● Date, time and calendar
● Alarm capability
● Backup power from external battery
Backup power is provided through the VBAT (J1.9) signal. If not
used, VBAT must be externally connected to GND.
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6Pinout table
This chapter contains the pinout description of the DIDO
module, grouped in four tables (two – odd and even pins – for
each connector) that report the pin mapping of the two 140 pin
DIDO connectors.
Each row in the pinout tables contains the following
information:
PinReference to the connector pin
Pin NamePin (signal) name on the DIDO connectors
Internal
Connections
Ball/pin #Component ball/pin number connected to signal
Supply Group Power Supply Group
TypePin type: I = Input, O = Output, D= Differential, Z =
VoltageI/O voltage
Connections to the DIDO components:
CPU.<x> : pin connected to CPU pad named <x>
KEY.<x>: pin connected to the key switch controller
TSC.<x> : pin connected to the touchscreen
controller
EEPROM.<x> : pin connected to the EEPROM
CAN.<x> : pin connected to the CAN transceiver
PMIC.<x> : pin connected to the Power Manager IC
LAN.<x> : pin connected to the LAN PHY
USB.<x> : pin connected to the USB transceiver
SV.<x>: pin connected to voltage supervisor
MTR: pin connected to voltage monitors
High impedance, S = Supply voltage, G = Ground, A
= Analog signal
The Internal connection column reports the name of the
microprocessor signal, which in turn contains references to all
the peripheral functions that can be associated to that pin. For
example, the following pin name
CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UA
RT4_RXD/GP3[1]
means that the pin can be used as:
● VOUT[1]_B_CB_C[4]: Video output data, port 1, B/CB/C
color bit 4
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● EMAC[1]_MRXD[0]: Ethernet MAC, port 1, [G]MII Receive
Data, bit 0
● VIN[1]A_D[1]: Video input channel 1, port A data input bit 1
● UART[4]_RXD: UART port 4, receive data input
● GP3[1]: General Purpose I/O port 3, channel 1
The following table reports all the function names that can be
found on the Internal connection and the associated
description.
Function
Description
name
VOUT[x]Digital video output. “x” represents the port number (0 or
1).
VIN[x]A/BDigital video input. “x” represents the capture number (0
or 1). Each capture has two ports (A and B)
EMAC[x]Ethernet MAC. “x” represents the port number (0 or 1)
UART[x]UART port. “x” represents the port number (0 to 5)
GPx[y]General Purpose I/O port. “x” represents the port number
(0 to 3)
CAMCamera Interface
SPI[x]SPI channel. “x” represents the channel number (0 to 3)
DCAN[x]Controller Area Network module. “x” represents the
module number (0 to 1)
HDMIHigh-Definition Multimedia Interface
SD[x]MMC/SD/SDIO interfaces. “x” represents the interface
number (0 to 2)
GPMCGeneral Purpose Memory Controller (local bus)
MDManagement Data I/O module
MCA[x]Multi-Channel Audio Serial Port (McASP). “x” represents
the port number (0 to 5)
I2C[x]I2C channel. “x” represents the channel number (0 to 3)
AUDAudio Reference Clock
TIMxGeneral purpose timer. “x” represents the terminal
number (0 to 7)
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6.1Carrier board mating connector J1
J1 – ODD [1 - 139]
PinPin NameInternal ConnectionsBall/
pin #
Supply
Group
TypeVoltageNote
J1.1DGNDDGND-G
J1.3DGNDDGND-G
J1.5USB0_DMCPU.USB0_DMAH11D, I/O
J1.7UART0_RXDCPU.UART0_RXDAH5I
J1.9VBATPMIC.VBACKUPD7SIf not used, VBAT must be externally
SPI1_SCS0N/GP1_16CPU.SPI[1]_SCS[0]n/GP1[16]AD3I/O
J1.89 DGNDDGNDG
J1.91 EMAC_REFCLKCPU.EMAC_RMREFCLK/TIM2_IO/GP1[10]J27I/OAvailable on request (module mount
option). Please refer to section 7.5.1
J1.93 USB0_DRVVBUSCPU.USB0_DRVVBUS/GP0[7]AF11I/O
J1.95 USB1.VBUSCPU.USB1_VBUSINAG14A, I
J1.97 HDMI_DP2CPU.HDMI_DP2AG21O
J1.99 HDMI_DN2CPU.HDMI_DN2AH21O
Some pins can be configured for different functions through mounting options. The rows into
the table appear as the following:
J2.78
MCA2_AFSX/GP0_11CPU.MCA[2]_AFSX/GP0[11]AA5I/O
Module mount option
CVDD_DSPMTR-O
The row content is split in two: the default pin configuration is the upper one (eg
TPS_PWRON); the optional pin configuration is the lower one (eg EMU1).
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6.4Additional notes
6.4.1EN_BCK_LS
J2.97 pin is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a
voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as
depicted below:
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Fig. 7: Simplified schematics of EN_BCK2_LS internal
pin configuration
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7Peripheral interfaces
DIDO modules implement a number of peripheral interfaces
through the J1 and J2 connectors. The following notes apply to
those interfaces:
● Some interfaces/signals are available only with/without
certain configuration options of the DIDO module. Each
signal’s availability is noted in the “Notes” column on the
table of each interface.
The signals for each interface are described in the related
tables. The following notes summarize the column headers for
these tables:
● “Pin name” – The symbolic name of each signal
● “Conn. Pin” – The pin number on the module connectors
● “Function” – Signal description
● “Notes” – This column summarizes configuration
requirements and recommendations for each signal.
7.1Digital Video Output (DVO)
DIDO provides two Digital Video Output interfaces, VOUT0 (up
to 24 bit) and VOUT1 (up to 18 bit), with support to YCbCr/RGB
formats at 1080p@60.
7.1.1VOUT0
The following table describes the interface signals:
Pin nameConn.
Pin
VOUT[0]_VSYNCJ1.69Vertical Sync output
VOUT[0]_CLKJ1.71Clock output
VOUT[0]_AVIDJ1.66Active video outputField ID output
VOUT[0]_HSYNCJ1.68Horizontal Sync
VOUT[0]_B_CB_C[2]J2.74Video Output Data. These signals
VOUT[0]_B_CB_C[3]J2.76
FunctionNotes
output
represent the 8 MSBs of B/CB/C video
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Pin nameConn.
Pin
VOUT[0]_B_CB_C[4]J1.64
VOUT[0]_B_CB_C[5]J1.65
VOUT[0]_B_CB_C[6]J1.62
VOUT[0]_B_CB_C[7]J1.61
VOUT[0]_B_CB_C[8]J1.60
VOUT[0]_B_CB_C[9]J1.59
VOUT[0]_G_Y_YC[2]J2.70
VOUT[0]_G_Y_YC[3]J2.72
VOUT[0]_G_Y_YC[4]J1.58
VOUT[0]_G_Y_YC[5]J1.57
VOUT[0]_G_Y_YC[6]J1.56
VOUT[0]_G_Y_YC[7]J1.55
VOUT[0]_G_Y_YC[8]J1.54
VOUT[0]_G_Y_YC[9]J1.53
VOUT[0]_R_CR[2]J2.62
FunctionNotes
data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb
(Chroma) data bits, for Y/C mode they
are multiplexed Cb/Cr (Chroma) data bits
and for BT.656 mode they are unused.
Video Output Data. These signals
represent the 8 MSBs of G/Y/YC video
data. For RGB mode they are green data
bits, for YUV444 mode they are Y data
bits, for Y/C mode they are Y (Luma) data
bits and for BT.656 mode they are
multiplexed Y/Cb/Cr (Luma and Chroma)
data bits.
VOUT[0]_R_CR[3]J2.64
VOUT[0]_R_CR[4]J1.50
VOUT[0]_R_CR[5]J1.51
VOUT[0]_R_CR[6]J1.48
VOUT[0]_R_CR[7]J1.49
VOUT[0]_R_CR[8]J1.46
VOUT[0]_R_CR[9]J1.47
7.1.2VOUT1
The following table describes the interface signals:
Pin nameConn.
VOUT[1]_CLKJ1.117Clock output
VOUT[1]_AVIDJ1.134Active video
VOUT[1]_VSYNCJ2.119Vertical Sync
Video Output Data. These signals
represent the 8 MSBs of R/CR video data.
For RGB mode they are red data bits, for
YUV444 mode they are Cr (Chroma) data
bits, for Y/C mode and BT.656 modes
they are unused.
FunctionNotes
Pin
output
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Pin nameConn.
FunctionNotes
Pin
VOUT[1]_HSYNCJ2.113Horizontal Sync
output
VOUT[1]_B_CB_C[4]J1.11
VOUT[1]_B_CB_C[5]J1.14
VOUT[1]_B_CB_C[6]J2.125
VOUT[1]_B_CB_C[7]J2.132
VOUT[1]_B_CB_C[8]J2.106
VOUT[1]_B_CB_C[9]J2.108
VOUT[1]_G_Y_YC[4]J2.17
VOUT[1]_G_Y_YC[5]J2.46
VOUT[1]_G_Y_YC[6]J2.49
VOUT[1]_G_Y_YC[7]J2.52
VOUT[1]_G_Y_YC[8]J2.63
VOUT[1]_G_Y_YC[9]J2.69
VOUT[1]_R_CR[4]J2.111
VOUT[1]_R_CR[5]J2.99
VOUT[1]_R_CR[6]J2.87
VOUT[1]_R_CR[7]J2.89
VOUT[1]_R_CR[8]J2.71
VOUT[1]_R_CR[9]J2.68
Video Output Data. These signals
represent the 6 MSBs of B/CB/C video
data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb
(Chroma) data bits, for Y/C mode they
are multiplexed Cb/Cr (Luma) data bits,
and for BT.656 mode they are not used.
Video Output Data. These signals
represent the 6 MSBs of G/Y/YC video
data. For RGB mode they are green data
bits, for YUV444 mode they are Y data
bits, for Y/C mode they are Y (Luma) data
bits and for BT.656 mode they are
multiplexed Y/Cb/Cr (Luma and Chroma)
data bits.
Video Output Data. These signals
represent the 6 MSBs of R/CR video data.
For RGB mode they are red data bits, for
YUV444 mode they are Cr (Chroma) data
bits, for Y/C mode and BT.656 mode they
are not used.
7.2HDMI
DIDO includes an High Definition Multimedia Interface 1.3a
compliant transmitter for digital audio and video, with
integrated HDCP (High-bandwidth Digital Content Protection)
and 1080p60 support. The HDMI interface consists of a digital
HDMI transmitter core with TMDS encoder, a core wrapper
with interface logic and control registers, and a transmit PHY.
HDMI shares the digital video chain with the VOUT1 port, so
when both interfaces are enabled, the same content is
reproduced.
The following table describes the interface signals:
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Pin nameConn.
FunctionNotes
Pin
HDMI_DP2J1.97Transmit data lane
2 – TMDS serial
output 2+
HDMI_DN2J1.99Transmit data lane
2 – TMDS serial
output 2-
HDMI_DP1J1.101Transmit data lane
1 – TMDS serial
output 1+
HDMI_DN1J1.103Transmit data lane
1 – TMDS serial
output 1-
HDMI_DP0J1.105Transmit data lane
0 – TMDS serial
output 0+
HDMI_DN0J1.107Transmit data lane
0 – TMDS serial
output 0-
HDMI_CLKPJ1.109Transmit clock
lane – TMDS clock
output+
HDMI_CLKNJ1.111Transmit clock
HDMI_SDAJ1.138
J2.39
HDMI_SCLJ1.136
J2.34
HDMI_CECJ2.21
J2.47
HDMI_HPDETJ2.44HDMI Hot Plug
7.3Analog SDTV out
DIDO provides a standard definition
Composite/S-video(NTSC/PAL) TV out channel. The signal
meets all requirements defined in ITU-R BT 470.6.
The following table describes the interface signals:
lane – TMDS clock
output-
HDMI I2C Serial
Data I/O
HDMI I2C Serial
Clock output
HDMI Consumer
Electronics Control
I/O
Detect Input
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Pin nameConn.
FunctionNotes
Pin
TV_OUT1J1.131Composite/S-Video
(Luminance)
Amplifier Output
TV_OUT2J1.133S-Video
(Chrominance)
Amplifier Output
7.4Digital Video Input ports
The HD Video Processing Subsystem supports two
independently configurable external video input capture ports
(VIP) up to 165MHz. Each video capture port supports one
scaler capable of both up and down scaling of one
non-multiplexed input stream; each video capture port supports
one programmable color space conversion to convert between
24-bit RGB data and YCbCr data. The VIP supports data
storage in RGB, 422, and 420 formats and each video capture
port channel supports chroma down-sampling (422 to 420) for
any non-multiplexed input data. The chroma down-sampling for
multiplexed streams is done as memory to memory operations
outside of HDVPSS on an individual frame data. Two VIP
instances are not identical from chip level. VIP instance 0 is a
24-bit interface and VIP instance 1 is a 16-bit interface. The
HDVPSS supports two independent pixel clock input domains
for each VIP, called Port A and Port B. Port A supports a single
up to 24 bit data bus at the instance level and Port B supports a
single 8 bit data bus at the instance level. The configuration for
each device input port is described in the following table:
Configured as
“Normal mode”
(internal amplifier
used). This pin drives
the 75- TVΩ
load.
Configured as
“Normal mode”
(internal amplifier
used). This pin drives
the 75- TVΩ
load.
Port APort B
8 bitOff
16 bitOff
24 bitOff
8 bit8 bit
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Port APort B
Off8 bit
7.4.1VIN0
The following table describes the interface signals:
Pin nameConn.
FunctionNotes
Pin
VIN[0]B_CLKJ2.60Input clock for 8-bit
Port B video capture.
VIN[0]A_CLKJ1.26Input clock for 8-bit,
16-bit, or 24-bit Port A
video capture.
VIN[0]B_FLDJ1.38Discrete field
identification signal
for Port B 8-bit YCbCr
capture without
embedded syncs
(“BT.601” modes).
VIN[0]A_FLDJ1.40
J2.122
VIN[0]A_HSYNCJ2.93Discrete horizontal
Discrete field
identification signal
for Port A RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
synchronization signal
for Port A RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
Not used in 16-bit
and 24-bit
capture modes.
Not used in RGB
or 16-bit YCbCr
capture modes.
VIN[0]B_HSYNCJ2.120Discrete horizontal
VIN[0]A_VSYNCJ2.93Discrete vertical
synchronization signal
for Port B RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
synchronization signal
for Port A RGB
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Pin nameConn.
FunctionNotes
Pin
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
VIN[0]B_VSYNCJ2.122Discrete vertical
synchronization signal
for Port B RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
VIN[0]B_DEJ1.42Discrete data valid
signal for Port B RGB
capture mode or
capture without
embedded syncs
(“BT.601” modes).
VIN[0]A_DEJ1.44
J2.120
Discrete data valid
signal for Port A RGB
capture mode or
YcbCr capture without
embedded syncs
("BT.601" modes).
VIN[0]A_D[0]J1.30Data inputs. For 16-bit capture, D[7:0]
VIN[0]A_D[1]J1.32
VIN[0]A_D[2]J1.36
VIN[0]A_D[3]J1.116
VIN[0]A_D[4]J1.120
VIN[0]A_D[5]J1.122
VIN[0]A_D[6]J2.73
VIN[0]A_D[7]J2.75
VIN[0]A_D[8]_BD[0]J2.77
VIN[0]A_D[9]_BD[1]J2.79
VIN[0]A_D[10]_BD[2]J2.81
VIN[0]A_D[11]_BD[3]J1.22
VIN[0]A_D[12]_BD[4]J2.83
VIN[0]A_D[13]_BD[5]J1.18
are Cb/Cr and [15:8] are Y Port A inputs.
For 8-bit capture, D[7:0] are Port A YCbCr
data inputs and D[15:8] are Port B YCbCr
data inputs. For RGB capture, D[23:16]
are R, D[15:8] are G, and BD[7:0] are B
data inputs.
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Pin nameConn.
VIN[0]A_D[14]_BD[6]J1.20
VIN[0]A_D[15]_BD[7]J1.24
VIN[0]A_D[16]J1.23
VIN[0]A_D[17]J1.25
VIN[0]A_D[18]J1.27
VIN[0]A_D[19]J1.29
VIN[0]A_D[20]J1.31
VIN[0]A_D[21]J1.33
VIN[0]A_D[22]J1.92
VIN[0]A_D[23]J1.94
7.4.2VIN1
The following table describes the interface signals:
Pin nameConn.
FunctionNotes
Pin
FunctionNotes
Pin
VIN[1]A_CLKJ1.134Input clock for
8-bit, 16-bit, or
24-bit Port A video
capture.
VIN[1]A_VSYNCJ2.113Discrete vertical
synchronization
signal for Port A
YCbCr capture
modes without
embedded syncs
(“BT.601” modes).
VIN[1]A_HSYNKJ1.117Discrete horizontal
synchronization
signal forPort A
YCbCr capture
modes without
embedded syncs
(“BT.601” modes).
VIN[1]A_DEJ2.119Discrete data valid
signal for Port A
RGB capture mode
Input data is
sampled on the
CLK0 edge.
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Pin nameConn.
FunctionNotes
Pin
or YcbCr capture
without embedded
syncs ("BT.601"
modes).
VIN[1]A_FLDJ2.119Discrete field
identification
signal for Port A
YCbCr capture
modes without
embedded syncs
(“BT.601” modes).
VIN[1]A_D[0]J1.132Video Input 1 Data inputs. For 16-bit
VIN[1]A_D[1]J1.11
VIN[1]A_D[2]J1.14
VIN[1]A_D[3]J2.125
VIN[1]A_D[4]J2.132
VIN[1]A_D[5]J2.106
VIN[1]A_D[6]J2.108
capture, D[7:0] are Cb/Cr and [15:8] are
Y Port A inputs. For 8-bit capture, are
Port A YCbCr data inputs. For RGB
capture, D[23:16] are R, D[15:8] are G,
and D[7:0] are B Port A data inputs.
VIN[1]A_D[7]J2.21
Please note that, in order to use this port
● I2C3 bus must be disabled. As a consequence keypad
controller, EEPROM and touch screen controller are not
available.
● Gigabit Ethernet must be disabled. As a consequence
only FastEthernet Interface is available and Ethernet
Switch is working with only one port.
● HDMI CEC must be disabled. Please note that CEC is
optional on HDMI interface and is currently used only in
consumer devices.
7.5Ethernet ports
The DM814x/AM387x 3PSW (Three Port Switch) Ethernet
Subsystem provides ethernet packet communication and can be
configured as an ethernet switch. It provides the gigabit media
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independent interface (G/MII), reduced gigabit media
independent interface (RGMII), reduced media independent
interface (RMII), the management data input output (MDIO) for
physical layer device (PHY) management. DIDO provides two
ethernet ports, one Fast Ethernet with on-board PHY, and one
Gigabit Ethernet (GRMII only).
7.5.1EMAC_RMREFCLK
EMAC_REFCLK signal is the reference clock for the internal
PHY (SMSC LAN8710) connected to EMAC[0] configured in
RMII mode. This signal is driven by the CPU and can be
optionally routed to J1.91 through a mount option. The
CPU.EMAC_RMREFCLK signal is internally split in two lines,
one connected to the internal PHY and the other routed to the
J1 connector; both lines are terminated with 22 Ω resistors. For
more flexibility on using both EMAC[0] and EMAC[1]
interfaces, this signal has been routed to the J1 connector
providing the following configuration options:
● generated internally (default configuration) and routed
externally for driving an external RMII PHY on the second
MAC (EMAC[1]) at 10/100 Mbit. In this case it is possible to
avoid the cost of an external crystal or oscillator.
● generated by an external PHY mounted on the carrier board
(connected to EMAC[1]) and routed internally to the internal
PHY and CPU. In some cases this configuration could be
preferred.
7.5.2Ethernet 10/100
On-board Ethernet PHY provides interface signals required to
implement the 10/100 Ethernet port. It is connected to
processor EMAC0 controller through RMII interface.
The following table describes the interface signals:
Pin nameConn.
EMAC0_PHY_LED_LINK/ACTJ2.115Link activity LED
Pin
FunctionNotes
This pin is driven
Indication.
active when a valid
link is detected and
blinks when activity
is detected.
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Pin nameConn.
FunctionNotes
Pin
EMAC0_PHY_LED_SPEEDJ2.117Link Speed LED
Indication.
ETH_CTTDJ2.127Tx Center Tap
ETH_CTRDJ2.137Rx Center Tap
ETH_TX-J2.129Transmit Negative
Channel
ETH_TX+J2.131Transmit Positive
Channel
ETH_RX-J2.135Receive Negative
Channel
ETH_RX+J2.133Receive Positive
Channel
EMAC_RMREFCLKJ1.91RMII Reference
Clock
This pin is driven
active when the
operating speed is
100Mbps. It is
inactive when the
operating speed is
10Mbps or during
line isolation.
7.5.3Gigabit EMAC
DIDO provides a Gigabit Ethernet interface connected to
processor EMAC1 controller through GRMII interface. When
required, an external PHY must be mounted on the carrier
board.
The following table describes the interface signals:
Pin nameConn.
EMAC[1]_RGRXCJ1.78RGMII Receive
EMAC[1]_RGRXCTLJ1.108RGMII Receive
EMAC[1]_RGRXD[3]J1.80RGMII Receive Data [3:0]
EMAC[1]_RGRXD[2]J1.86
EMAC[1]_RGRXD[1]J1.88
FunctionNotes
Pin
Clock
Control
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Pin nameConn.
EMAC[1]_RGRXD[0]J1.106
EMAC[1]_RGTXCJ1.87RGMII Transmit
EMAC[1]_RGTXCTLJ1.110RGMII Transmit
EMAC[1]_RGTXD[3]J1.112RGMII Transmit Data [3:0]
EMAC[1]_RGTXD[2]J1.77
EMAC[1]_RGTXD[1]J1.79
EMAC[1]_RGTXD[0]J1.85
EMAC_RMREFCLKJ1.91RMII Reference Clock
7.6CAN ports
DIDO provides two DCAN interfaces (DCAN0 and DCAN1) for
supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the CAN protocol
version 2.0 part A, B and supports bit rates up to 1 Mbit/s.
FunctionNotes
Pin
Clock
Enable
7.6.1DCAN0
DCAN0 port is connected to on-board transceiver which
converts the single-ended CAN signals of the controller to the
differential signals of the physical layer.
The following table describes the interface signals:
Pin nameConn.
CAN_HJ1.96High bus output
CAN_LJ1.98Low bus output
7.6.2DCAN1
When required, DCAN1 must be connected to an external PHY.
The following table describes the interface signals:
FunctionNotes
Pin
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Pin nameConn.
DCAN1_RXJ1.19Receive data pin
DCAN1_TXJ1.21Transmit data pin
7.7UARTs
Three UART ports are routed to DIDO connectors. UART0
provides full Modem Control Signals, while UART3 and UART5
are 4-wire interfaces. Each port can be programmed separately
and can operate in UART, IrDA or CIR modes.
7.7.1UART0
The following table describes the interface signals:
Pin nameConn.
UART0_RXDJ1.7Receive DataFunctions as IrDA
FunctionNotes
Pin
FunctionNote
Pin
receive input in IrDA
modes and CIR
receive input in CIR
mode
UART0_TXDJ1.8Transmit DataFunctions as CIR
transmit in CIR mode
UART0_RTSnJ1.19Request To SendFunctions as transmit
data output in IrDA
modes
UART0_CTSnJ1.21Clear To SendFunctions as SD
transceiver control
output in IrDA and
CIR modes
UART0_DTRnJ2.130Data Terminal
Ready
UART0_DSRnJ2.121Data Set Ready
UART0_DCDnJ2.128Data Carrier
Detect
UART0_RINJ2.123Ring indicator
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7.7.2UART3
The following table describes the interface signals:
Pin nameConn.
FunctionNotes
Pin
UART3_RXDJ2.128Receive DataAlso available as
alternative function
on pin J2.125.
Functions as IrDA
receive input in IrDA
modes and CIR
receive input in CIR
mode.
UART3_TXDJ2.121Transmit DataAlso available as
alternative function
on pin J2.132.
Functions as CIR
transmit in CIR
mode.
UART3_RTSnJ2.123Request To SendAlso available as
alternative function
on pin J1.113.
Functions as transmit
data output in IrDA
modes
UART3_CTSnJ2.130Clear To SendAlso available as
alternative function
on pin J1.119.
Functions as SD
transceiver control
output in IrDA and
CIR modes.
7.7.3UART5
The following table describes the interface signals:
Pin nameConn.
UART5_RXDJ2.122Receive DataAlso available as
FunctionNotes
Pin
alternative function
on pin J2.86.
Functions as IrDA
receive input in IrDA
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Pin nameConn.
Pin
UART5_TXDJ2.120Transmit DataAlso available as
UART5_RTSnJ1.93Request To SendFunctions as transmit
UART5_CTSnJ2.104Clear To SendFunctions as SD
7.8MMC/SD channels
FunctionNotes
modes and CIR
receive input in CIR
mode.
alternative function
on pin J2.88.
Functions as CIR
transmit in CIR
mode.
data output in IrDA
modes
transceiver control
output in IrDA and
CIR modes.
Three standard MMC/SD/SDIO interfaces are available on
DIDO module. The processor includes 3 MMC/SD/SDIO
Controllers which are compliant with MMC V4.3, Secure
Digital Part 1 Physical Layer Specification V2.00 and Secure
Digital Input Output (SDIO) V2.00 specifications. High capacity
SD cards (SDHC) are supported.
7.8.1MMC/SD/SDIO0
MMC/SD0 can be configured as 1-bit or 4-bit mode. When
using this channel, MMC/SD0 can't be configured as 8-bit
mode.
The following table describes the interface signals:
Pin nameConn.
SD0_CLKJ1.124Clock output
SD0_CMDJ1.130Command output
SD0_DAT[0]J1.127Data bit 0Functions as single
FunctionNotes
Pin
data bit for 1-bit SD
mode.
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Pin nameConn.
SD0_DAT[1]J1.129Data bit 1Functions as an IRQ
SD0_DAT[2]J1.102Data bit 2Functions as a Read
SD0_DAT[3]J1.104Data bit 3
7.8.2MMC/SD/SDIO1
MMC/SD1 can be configured as 1-bit, 4-bit or 8-bit mode.
Please note that 8-bit mode can be used only when MMC/SD0
is not enabled.
The following table describes the interface signals:
Pin nameConn.
SD1_CLKJ1.137Clock output
FunctionNotes
Pin
input for 1-bit SD
mode.
Wait input for 1-bit
SD mode.
FunctionNotes
Pin
SD1_CMDJ1.135Command output Also available as
alternative function
on pin J1.130.
SD1_DAT[0]J1.119Data bit 0Functions as single
data bit for 1-bit SD
mode.
SD1_DAT[1]J1.121Data bit 1Functions as an IRQ
input for 1-bit SD
mode.
SD1_DAT[2]J1.123Data bit 2Functions as a Read
Wait input for 1-bit
SD mode.
SD1_DAT[3]J1.125Data bit 3
SD1_DAT[4]J1.127Data bit 4
SD1_DAT[5]J1.129Data bit 5
SD1_DAT[6]J1.102Data bit 6
SD1_DAT[7]J1.104Data bit 7
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7.8.3MMC/SD/SDIO2
The following table describes the interface signals:
Pin nameConn.
SD2_SCLKJ1.128Clock output
SD2_CMDJ2.55Command output
SD2_DAT[0]J2.25Data bit 0Functions as single
SD2_DAT[1]J2.24Data bit 1Functions as an IRQ
SD2_DAT[2]J2.23Data bit 2Functions as a Read
SD2_DAT[3]J2.22Data bit 3
7.9USB ports
DIDO provides three USB 2.0 ports with integrated PHY. USB0
is a OTG 2.0 port, USB1 is a Host/OTG 2.0 port and USB2 is a
2.0 Host port. USB1 can be configured through dedicated
mount options. USB1 and USB2 are the downstreams of a USB
hub connected to the second USB controller provided by the
processor.
FunctionNotes
Pin
data bit for 1-bit SD
mode.
input for 1-bit SD
mode.
Wait input for 1-bit
SD mode.
7.9.1USB0
The following table describes the interface signals:
Pin nameConn.
USB0_DPJ1.6Bidirectional data
USB0_DMJ1.5
USB0_IDJ1.17OTG identification
USB0_VBUSINJ1.165-V VBUS
FunctionNotes
Pin
differential signal
pair (plus/minus)
input.
Senses the level of
comparator input.
the USB VBUS.
Should connect
directly to the USB
VBUS voltage.
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Pin nameConn.
USB0_DRVVBUSJ1.93Used by the USB0
7.9.2USB1
The following table describes the interface signals:
Pin nameConn.
USBP1J2.124Bidirectional data
USBM1J2.126
7.9.3USB2
The following table describes the interface signals:
Pin nameConn.
FunctionNotes
Pin
Controller to
enable the
external VBUS
charge pump.
FunctionNotes
Pin
differential signal
pair (plus/minus)
FunctionNotes
Pin
USBP2J2.134Bidirectional data
USBM2J2.136
7.9.4Other USB signals
The following table describes the interface signals:
Pin nameConn.
USB1_VBUSJ1.955-V VBUS
USB1_DRVVBUSJ1.118Used by the USB1
Pin
differential signal
pair (plus/minus)
FunctionNotes
Senses the level
comparator input.
Controller to enable
the external VBUS
charge pump.
of the USB VBUS.
Should connect
directly to the
USB VBUS
voltage.
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7.10Touchscreen
The touch screen controller is a TSC2003 resistive 4-wire
controller connected to the I2C-3 bus. It also provides an
auxiliary 12-bit A/D converter channel.
Device address is 1001000b.
The following table describes the interface signals:
Connector PinPin
TSC_XPJ1.39X+ Position InputPlease consider
TSC_XMJ1.41X- Position Input
TSC_YPJ1.43Y+ Position Input
TSC_YMJ1.45Y- Position Input
7.11EEPROM
One EEPROM is available to provide additional non-volatile
storage area for user-specific usage. It is connected to the
I2C-3 bus. A1 and A0 bits of address can be configured at
carrier board level
Device address is 10100[A1][A0]b.
The following table describes the interface signals:
Connector PinPin
FunctionNotes
name
the use of ESD
protection
devices on carrier
board when these
pins are
connected to
actual touch
screen.
FunctionNotes
name
EEPROM_A0J1.10I²C Address pinsA1 and A0 bits of
EEPROM_A1J1.12
EEPROM_WPJ2.114Active high
7.12Keypad controller
DIDO provides a 8x8 keypad interface that is implemented in a
dedicated MAX7359ETG+ controller connected to the I2C-3
bus.
Device address is 0111000b.
address can be
configured at
carrier board
level
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The following table describes the interface signals:
Connector PinPin
FunctionNotes
name
KP_ROW0J1.72Keypad row 0
KP_ROW1J1.73Keypad row 1
KP_ROW2J1.74Keypad row 2
KP_ROW3J1.75Keypad row 3
KP_ROW4J1.80Keypad row 4
KP_ROW5J1.78Keypad row 5
KP_ROW6J1.86Keypad row 6
KP_ROW7J1.77Keypad row 7
KP_COL0J1.82Keypad column 0
KP_COL1J1.81Keypad column 1
KP_COL2J1.84Keypad column 2
KP_COL3J1.83Keypad column 3
KP_COL4J1.79Keypad column 4
KP_COL5J1.88Keypad column 5
KP_COL6J1.85Keypad column 6
KP_COL7J1.106Keypad column 7
7.13PCI Express
The device supports connections to PCIe-compliant devices via
the integrated PCIe master/slave bus interface. The PCIe
module is comprised of a dual-mode PCIe core and a SerDes
PHY. The device implements a single one-lane PCIe 2.0 (5.0
GT/s) Endpoint/Root Complex port. Please note that AC
decoupling capacitors are integrated on DIDO, with the
following configuration:
● 100 nF in series with the TX pair lines
● 270 pF in series with the SERDES_CLK pair lines
The following table describes the interface signals:
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Connector PinPin
PCIE_TXP0J2.29
PCIE_TXN0J2.31
PCIE_RXP0J2.28
PCIE_RXN0J2.30
SERDES_CLKPJ2.36
SERDES_CLKNJ2.38
7.14SPI buses
name
FunctionNotes
When the PCIe
PCIE Transmit
Data Lane 0
PCIE Receive
Data Lane 0.
PCIE Serdes
Reference Clock
Inputs and
optional SATA
Reference Clock
Inputs.
SERDES are powered
down, these pins
should be left
unconnected.
When the PCIe
SERDES are powered
down, these pins
should be left
unconnected
When PCI Express
is not used, and
these pins are not
used as optional
SATA
these pins can be
left unconnected
Three SPI channels are available on DIDO. Each port has a
maximum supported frequency of 48 MHz and provides up to 4
chip selects. Communication parameters (frequency, polarity,
phase) are programmable. SPI-0 is connected to the SPI NOR
flash, as described in Section 3.3.
7.14.1SPI1
SPI2 provides 4 chip select signals. The following table
describes the interface signals:
Connector PinPin
SPI[1]_SCLKJ1.34SPI clock
SPI[1]_SCS[3]J1.21
SPI[1]_SCS[2]J1.19
SPI[1]_SCS[1]J2.112
SPI[1]_SCS[0]J1.87
SPI[1]_D[1]J1.90SPI Data I/O. Can be
FunctionNotes
name
SPI chip selects
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Connector PinPin
SPI[1]_D[0]J1.37
7.14.2SPI2
SPI2 provides 3 chip select signals. The following table
describes the interface signals:
Connector PinPin
SPI[2]_SCLKJ1.88
SPI[2]_SCS[2]J2.34SPI chip selects
SPI[2]_SCS[1]J2.45
SPI[2]_SCS[0]J2.50
SPI[2]_D[1]J1.78
SPI[2]_D[0]J1.80
name
name
J2.39
J2.44
J2.47
J2.21
J2.42
FunctionNotes
configured as either
MISO or MOSI.
FunctionNotes
SPI clock
SPI Data I/O. Can be
configured as either
MISO or MOSI.
7.14.3SPI3
SPI3 provides 3 chip select signals. The following table
describes the interface signals:
Connector PinPin
SPI[3]_SCLKJ1.33
SPI[1]_SCS[3]J2.66SPI chip selects
SPI[1]_SCS[1]J2.111
SPI[1]_SCS[0]J1.31
SPI[1]_D[1]J1.92
SPI[1]_D[0]J1.94
FunctionNotes
name
SPI clock
J1.66
J2.99
SPI Data I/O. Can be
J2.87
J2.113
J2.89
configured as either
MISO or MOSI.
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Connector PinPin
7.15I2C buses
Two I2C channels are available on DIDO to provide an interface
to other devices compliant with Philips Semiconductors Inter-IC
bus (I2C-bus™) specification version 2.1. External components
attached to this 2-wire serial bus can transmit/receive 8-bit
data to/from the device through the I2C module. The I2C ports
support standard and fast modes from 10 - 400 Kbps (no
fail-safe I/O buffers).
A third I2C channel (I2C0) is used for the internal connection
between CPU and PMIC (please refer to Section 5.2).
7.15.1I2C2
The following table describes the interface signals:
Connector PinPin
FunctionNotes
name
J2.119
FunctionNotes
name
I2C[2]_SCLJ1.23
I2C[2]_SDAJ2.39
7.15.2I2C3
The following table describes the interface signals:
Connector PinPin
I2C[3]_SCLJ2.106
J2.122
J2.128
J2.66
J2.120
J2.121
name
J1.27
I2C2 ClockFor proper device
operation in I2C
mode, this pin
must be pulled
up via
external resistor.
I2C2 Data I/OFor proper device
operation in I2C
mode, this pin
must be pulled
up via
external resistor.
FunctionNotes
I2C3 ClockJ2.106 line is
internally
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Connector PinPin
I2C[3]_SDAJ2.108
7.16SATA
FunctionNotes
name
J1.98connected to
pull-up resistor;
when using
multiplexed lines
(J1.27, J1.98), the
signal must be
pulled up via
external resistor.
I2C3 Data I/OJ2.106 line is
J1.29
J1.96
internally
connected to
pull-up resistor;
when using
multiplexed lines
(J1.27, J1.98), the
signal must be
pulled up via
external resistor.
DIDO provides a Serial ATA (SATA) 3.0 Gbps controller with
integrated PHY, which supports all SATA power management
features, port multiplier with command-based switching and
activity LEDs. It also provides hardware-assisted native
command queuing (NCQ) for up to 32 entries.
The following table describes the interface signals:
Connector PinPin
name
SATA_TXN0J2.14Serial ATA data
SATA_TXP0J2.12
SATA_RXN0J2.18Serial ATA data
SATA_RXP0J2.16
SATA_ACT0_LEDJ2.19Serial ATA disk 0
7.17Audio interfaces
The multichannel audio serial port (McASP) functions as a
FunctionNotes
transmit
receive
Activity LED output
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general-purpose audio serial port optimized for the needs of
multichannel audio applications. The McASP is useful for
time-division multiplexed (TDM) stream, Inter-Integrated
Sound (I2S) protocols, and inter-component digital audio
interface transmission (DIT). DIDO provides one McASP
interfaces with up to 4 serial data pins.
7.17.1McASP2
The following table describes the interface signals:
Connector PinPin
MCA[2]_ACLKXJ2.80McASP1 Transmit Bit
MCA[2]_AFSXJ2.78McASP1 Transmit
MCA[2]_AXR[0]J2.86McASP1
MCA[2]_AXR[1]J2.88
MCA[2]_AXR[2]J2.90
MCA[2]_AXR[3]J2.92
7.18GPIOs
The GPIO peripheral provides general-purpose pins that can be
configured as either inputs or outputs, for connections to
external devices. In addition, the GPIO peripheral can produce
CPU interrupts in different interrupt generation modes. The
device contains four GPIO modules and each GPIO module is
made up of 32 identical channels.
The device GPIO peripheral supports up to 128 1.8-V/3.3-V
GPIO pins, GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:31].
Each channel must be properly configured, since GPIO signals
are multiplexed with other interfaces signals. For more
information on how to configure and use GPIOs, please refer to
section 5.8.
FunctionNotes
name
Clock I/O
Frame Sync I/O
Transmit/Receive
Data I/Os
7.19Local Bus
The general-purpose memory controller (GPMC) is an unified
memory controller dedicated to interfacing external memory
devices:
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● Asynchronous SRAM-like memories and application-specific
integrated circuit (ASIC) devices
● Asynchronous, synchronous, and page mode (only available
in non-multiplexed mode) burst NOR flash devices
● NAND Flash (with BCH and Hamming Error Code
Detection)
● Pseudo-SRAM devices
● The GPMC includes flexible asynchronous protocol control to
interface to SRAM-like memories and custom logic (FPGA,
CPLD, ASICs, etc.).
● Other supported features include:
● 8/16-bit wide multiplexed address/data bus
● 512 MBytes maximum addressing capability divided among
up to eight chip selects (seven available on DIDO
connectors – GPMC_CS[7] is reserved for on-board NAND
memory).
● Non-multiplexed address/data mode
● Pre-fetch and write posting engine associated with system
DMA to get full performance from NAND device with
minimum impact on NOR/SRAM concurrent access.
DIDO provides up to 8-bit for data and 16 bit for addresses.
Please note that, when enabling the EMAC1 interface (see
7.5.3) the address bus is limited to bits GPMC_A[0] to
GPMC_A[4].
The following table describes the interface signals:
Connector PinPin
FunctionNotes
name
GPMC_CLKJ2.61GPMC Clock
GPMC_CS[6]J2.59GPMC Chip Select #6
GPMC_CS[5]J2.61GPMC Chip Select #5
GPMC_CS[4]J2.53GPMC Chip Select #4
GPMC_CS[3]J2.50GPMC Chip Select #3
GPMC_CS[2]J2.53GPMC Chip Select #2
GPMC_CS[1]J2.48GPMC Chip Select #1
GPMC_CS[0]J2.51GPMC Chip Select #0
GPMC_WEJ2.57GPMC Write Enable
GPMC_OE_REJ2.56GPMC Output Enable
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Connector PinPin
FunctionNotes
name
GPMC_BE[1]J2.85GPMC Upper Byte
Enable
GPMC_BE[0]_CLEJ2.58GPMC Lower Byte
Enable or Command
Latch Enable
GPMC_ADV_ALEJ2.59GPMC Address Valid
or Address Latch
Enable
GPMC_WAIT[1]J2.61GPMC Wait 1
GPMC_A[15]J1.86
GPMC_A[14]J1.112
J2.39
GPMC_A[13]J1.106
J2.34
GPMC_A[12]J1.87
GPMC_A[11]J1.77
GPMC_A[10]J1.85
GPMC_A[9]J1.110
GPMC_A[8]J1.79
GPMC_A[7]J1.80
GPMC_A[6]J1.78
GPMC_A[5]J1.88
GPMC_A[4]J2.25
GPMC_A[3]J2.24
GPMC_A[2]J2.23
GPMC_A[1]J2.22
GPMC_A[0]J1.108
J2.21
GPMC_D[7]J2.10GPMC Multiplexed
GPMC_D[6]J2.11
GPMC_D[5]J2.8
GPMC_D[4]J2.9
GPMC_D[3]J2.6
GPMC_D[2]J2.7
GPMC Address lines
Data/Address I/Os.
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Connector PinPin
name
GPMC_D[1]J2.4
GPMC_D[0]J2.5
FunctionNotes
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8Operational characteristics
8.1Maximum ratings
This section will be completed in a future version of this
manual.
ParameterMinTypMaxUnit
Main power supply voltage3.13.3V
8.2Recommended ratings
This section will be completed in a future version of this
manual.
ParameterMinTypMaxUnit
Main power supply voltage-3.3-V
8.3Power consumption
Providing theoretical maximum power consumption value
would be useless for the majority of system designers building
their application upon DIDO module because, in most cases,
this would lead to an over-sized power supply unit.
Several configurations have been tested in order to provide
figures that are measured on real-world use cases instead.
Please note that DIDO platform is so flexible that it is virtually
impossible to test for all possible configurations and
applications on the market. The use cases here presented
should cover most of real-world scenarios. However actual
customer application might require more power than values
reported here. Generally speaking, application specific
requirements have to be taken into consideration in order to
size power supply unit and to implement thermal management
properly.
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8.3.1Set 1
Measurements have been performed on the following platform:
● NAON SOM (DM8148 model)
● carrier board: NAONEVB-Lite
● System software: NELK 1.0.0
● Power monitor: INA226 (reference U20 of [[NAONEVB-Lite]]
schematics).
● ARM Cortex-A8 frequency: 600 MHz
● SDRAM size: 512 MByte
● SDRAM frequency: 400 MHz
● HDVICP2 frequency: 306 MHz
8.3.2Use cases
CheckpointInput
Voltage
Linux prompt
(M3 unloaded)
Linux prompt
(M3 loaded)
cpuBurnA8 (M3
Loaded)
decode &
display H264
1080p60 on
HDMI
decode &
display H264
1080p60 +
cpuBurnA8
3266 mV8 mV779 mA2550 mW
3261 mV10 mV1040 mA3400 mW
3258 mV12 mV1235 mA3900 mW
3258 mV12 mV1219 mA3975 mW
3255 mV14 mV1352 mA4450 mW
Shunt
Voltage
CurrentPower
Consumpion
Additional notes and reference:
● M3 Unloaded means that the two Cortex-M3 firmware has
not yet been started.
● For decode/display test the sample application included in
the TI EZSDK has been used.
● Cpuburn heavily uses Cortex-A8 and Neon to maximize
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power consumption and heat spreading. See the debian
package information (burnCortexA8.s) for further
information.
● Please note that shunt voltage value is rounded.
● Please note that, although the NAON module has been used
during these tests, usage of the DIDO module would lead to
comparable results.
8.4Heat Dissipation
This section will be completed in a future version of this
manual.
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9Application notes
Please refer to the following documents available on DAVE
Embedded Systems Developers Wiki: