DATEL ADS-B932, ADS-932MM, ADS-932MC Datasheet

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®

INNOV A TION and EX CELLENCE

ADS-932

34 OUTPUT ENABLE

FEA TURES

• 16-bit resolution

• 2MHz sampling rate

• Functionally complete

• No missing codes over full military temperature range

• Edge-triggered

• ±5V supplies, 1.85 Watts

• Small, 40-pin, ceramic TDIP

• 87dB SNR, –88dB THD

• Ideal for both time and frequency-domain applications

GENERAL DESCRIPTION

The low-cost ADS-932 is a 16-bit, 2MHz sampling A/D
converter. This device accurately samples full-scale input
signals up to Nyquist frequencies with no missing codes. The
dynamic performance of the ADS-932 has been optimized to
achieve a signal-to-noise ratio (SNR) of 87dB and a total
harmonic distortion (THD) of –88dB.

Packaged in a 40-pin TDIP, the functionally complete ADS-932
contains a fast-settling sample-hold amplifier, a subranging
(two-pass) A/D converter, an internal reference, timing/control
logic, and error-correction circuitry. Digital input and output
levels are TTL. The ADS-932 only requires the rising edge of
the start convert pulse to operate.

Requiring only ±5V supplies, the ADS-932 dissipates 1.85
Watts. The device is offered with a bipolar (±2.75V) analog
input range or a unipolar (0 to – 5.5V) input range. Models are
available for use in either commercial (0 to +70°C) or military
(–55 to +125°C) operating temperature ranges. A proprietary,
auto-calibrating, error-correcting circuit enables the device to
achieve specified performance over the full military
temperature range. Typical applications include medical
imaging, radar, sonar, communications and instrumentation.

16-Bit, 2MHz

Sampling A/D Converters

INPUT/OUTPUT CONNECTIONS

PIN FUNCTION PIN FUNCTION

1 +3.2V REF. OUT 40 NO CONNECTION
2 UNIPOLAR 39 NO CONNECTION
3 ANALOG INPUT 38 +5V ANALOG SUPPLY
4 ANALOG GROUND 37 –5V SUPPLY
5 OFFSET ADJUST 36 ANALOG GROUND
6 GAIN ADJUST 35 COMP. BITS
7 DIGITAL GROUND 34 OUTPUT ENABLE
8 FIFO/DIR 33 OVERFLOW

9 FIFO READ 32 EOC
10 FST AT1 31 +5V DIGITAL SUPPLY
11 FST AT2 30 DIGITAL GROUND
12 START CONVERT 29 BIT 1 (MSB)
13 BIT 16 (LSB) 28 BIT 1 (MSB)
14 BIT 15 27 BIT 2
15 BIT 14 26 BIT 3
16 BIT 13 25 BIT 4
17 BIT 12 24 BIT 5
18 BIT 11 23 BIT 6
19 BIT 10 22 BIT 7
20 BIT 9 21 BIT 8

DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: [phone] Fax: [phone] • E-mail:[e-mail] • Internet: www.datel.com

POWER and GROUNDING

ANALOG GROUND 4, 36
DIGITAL GROUND 7, 30
+5V DIGITAL SUPPLY 31
–5V SUPPLY 37
+5V ANALOG SUPPLY 38
NO CONNECTION 39, 40

GAIN

GAIN ADJUST 6

+3.2V REF. OUT 1

OFFSET ADJUST 5

ANALOG INPUT 3

START CONVERT 12

EOC 32

COMP. BITS 35

ADJUST

CKT.

+3.2V REFERENCE

OFFSET
ADJUST

CKT.

S/H

CONTROL LOGIC

PRECISION

TIMING AND

Figure 1. ADS-932 Functional Block Diagram

3-STATE

CUSTOM GATE ARRAY

2-PASS ANALOG-TO-DIGITAL CONVERTER

OUTPUT REGISTER

10 FSTAT1
11 FSTAT2

8 FIFO/DIR
9 FIFO/READ

29 BIT 1 (MSB)
28 BIT 1 (MSB)
27 BIT 2
26 BIT 3
25 BIT 4
24 BIT 5
23 BIT 6
22 BIT 7
21 BIT 8
20 BIT 9
19 BIT 10
18 BIT 11
17 BIT 12
16 BIT 13
15 BIT 14
14 BIT 15
13 BIT 16 (LSB)

33 OVERFLOW

ADS-932

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ABSOLUTE MAXIMUM RA TINGS

PARAMETERS LIMITS UNITS

+5V Supply (Pins 31, 38) 0 to +6 Volts
–5V Supply (Pin 37) 0 to –6 Volts
Digital Inputs (Pins 8, 9, 12, 34, 35) –0.3 to +VDD +0.3 Volts
Analog Input (Pin 3) Volts

Bipolar ±5 Volts
Unipolar –10 to +5 Volts

Lead Temperature (10 seconds) +300 °C

PHYSICAL/ENVIRONMENTAL

PARAMETERS MIN. TYP. MAX. UNITS

Operating Temp. Range, Case

ADS-932MC 0 — +70 °C
ADS-932MM –55 — +125 °C

Thermal Impedance

θjc — 4 — °C/Watt
θca — 18 — °C/Watt

Storage Temperature Range –65 — +150 °C
Package Type 40-pin, metal-sealed, ceramic TDIP

Weight 0.56 ounces (16 grams)

FUNCTIONAL SPECIFICA TIONS

(TA = +25°C, ±VCC = ±5V, +VDD = +5V, 2MHz sampling rate, and a minimum 3 minute warm-up ➀ unless otherwise specified.)

+25°C 0 to +70°C –55 to +125°C

ANALOG INPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Input Voltage Ranges

Unipolar — 0 to –5.5 — — 0 to –5.5 — — 0 to –5.5 — Volts
Bipolar — ±2.75 — — ±2.75 — — ±2.75 — Volts

Input Resistance (pin 3) 655 687 — — 685 — — 685 — Ω
Input Resistance (pin 2) 418 426 — — 400 — — 400 — Ω
Input Capacitance — 10 15 — 10 15 — 10 15 pF

DIGITAL INPUTS

Logic Levels

Logic "1" +2.0 — — +2.0 — — +2.0 — — Volts
Logic "0" — — +0.8 — — +0.8 — — +0.8 Volts
Logic Loading "1" — — +20 — — +20 — — +20 µA
Logic Loading "0" ➁ — — –20 — — –20 — — –20 µA

Start Convert Positive Pulse Width ➂ 40 250 — 40 250 — 40 250 — ns

STATIC PERFORMANCE

Resolution — 16 — — 16 — — 16 — Bits
Integral Nonlinearity — ±1 — — ±1.5 — — ±2 — LSB
Differential Nonlinearity (fin = 10kHz) –0.95 ±0.5 +1.0 –0.95 ±0.5 +1.0 –0.95 ±0.5 +1.5 LSB
Full Scale Absolute Accuracy — ±0.1 ±0.3 — ±0.15 ±0.5 — ±0.5 ±0.8 %FSR
Bipolar Zero Error (Tech Note 2) — ±0.1 ±0.2 — ±0.2 ±0.4 — ±0.5 ±0.9 %FSR
Bipolar Offset Error (Tech Note 2) — ±0.1 ±0.3 — ±0.2 ±0.5 — ±0.4 ±0.9 %FSR
Gain Error (Tech Note 2) — ±0.1 ±0.3 — ±0.15 ±0.5 — ±0.5 ±0.9 %
No Missing Codes (fin = 10kHz) 16 — — 16 — — 16 — — Bits

DYNAMIC PERFORMANCE

Peak Harmonics (–0.5dB)

dc to 500kHz — –90 –81 — –90 –81 — –88 –80 dB
500kHz to 1MHz — –90 –81 — –90 –81 — –88 –80 dB

Total Harmonic Distortion (–0.5dB)

dc to 500kHz — –88 –80 — –88 –80 — –85 –78 dB
500kHz to 1MHz — –87 –80 — –87 –80 — –84 –77 dB

Signal-to-Noise Ratio

(w/o distortion, –0.5dB)
dc to 500kHz 83 87 — 83 87 — 80 85 — dB
500kHz to 1MHz 82 86 — 82 86 — 80 84 — dB

Signal-to-Noise Ratio ➃

(& distortion, –0.5dB)
dc to 500kHz 79 84 — 79 84 — 76 82 — dB
500kHz to 1MHz 78 84 — 78 84 — 76 82 — dB

Noise — 83 — — 83 — — 83 — µVrms
Two-Tone Intermodulation

Distortion (fin = 200kHz,

240kHz, fs = 2MHz, –0.5dB) — –89 — — –89 — — –89 — dB

Input Bandwidth (–3dB)

Small Signal (–20dB input) — 7.8 — — 7.8 — — 7.8 — MHz
Large Signal (–0.5dB input) — 7.1 — — 7.1 — — 7.1 — MHz

Feedthrough Rejection

(fin = 1MHz) — 90 — — 90 — — 90 — dB

Slew Rate — ±77 — — ±77 — — ±77 — V/µs
Aperture Delay Time — +8 — — +8 — — +8 — ns
Aperture Uncertainty — 5 — — 5 — — 5 — ps rms
S/H Acquisition Time

( to ±0.001%FSR, 5.5V step) 200 225 — 200 225 — 200 225 — ns

ADS-932

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3

+25°C 0 TO +70°C –55 TO +125°C

DYNAMIC PERFORMANCE (Cont.) MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Overvoltage Recovery Time ➄ — 250 500 — 250 500 — 250 500 ns
A/D Conversion Rate 2 — — 2 — — 2 — — MHz

ANALOG OUTPUT

Internal Reference

Voltage 3.15 +3.2 3.25 3.15 +3.2 3.25 3.15 +3.2 3.25 Volts
Drift — ±30 — — ±30 — — ±30 — ppm/°C

External Current — 5 — — 5 — — 5 — mA

DIGITAL OUTPUTS

Logic Levels

Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts
Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts
Logic Loading "1" — — –4 — — –4 — — –4 mA
Logic Loading "0" — — +4 — — +4 — — +4 mA

Delay, Falling Edge of Enable to
Output Data Valid — — 10 — — 10 — — 10 ns

Output Coding

POWER REQUIREMENTS

Power Supply Ranges ➅

+5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 Volts
–5V Supply –4.75 –5.0 –5.25 –4.75 –5.0 –5.25 –4.9 –5.0 –5.25 Volts

Power Supply Currents

+5V Supply — +225 260 — +225 260 — +225 260 mA
–5V Supply –140 –135 — –140 –135 — –140 –135 — mA

Power Dissipation — 1.85 2.0 — 1.85 2.0 — 1.85 2.0 Watts
Power Supply Rejection — — ±0.07 — — ±0.07 — — ±0.07 %FSR/%V

Footnotes:

➀ All power supplies must be on before applying a start convert pulse. All

supplies and the clock (START CONVERT) must be present during warm-up
periods. The device must be continuously converting during this time. There is
a slight degradation in performance when operating the device in the unipolar
mode.

➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA.
➂ A 1MHz clock with a positive pulse width is used for all production

testing. See Timing Diagram for more details.
40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns

Straight Binary, Complementary Binary, Complementary Offset Binary,
Complementary Two's Complement, Offset Binary, Two's Complement

➃ Effective bits is equal to:

(SNR + Distortion) – 1.76 + 20 log

6.02

➄ This is the time required before the A/D output data is valid once the analog

input is back within the specified range. This time is only guaranteed if the input

does not exceed ±4.75V (bipolar)

or +2 to –7.5V (unipolar).

➅ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for

–55°C operation only. The minimum limits are +4.75V and –4.75V when

operating at +125°C.

Full Scale Amplitude

Actual Input Amplitude

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADS-932
requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital ground systems
are connected to each other internally. For optimal perfor­mance, tie all ground pins (4, 7, 30 and 36) directly to a
large analog ground plane beneath the package.

Bypass all power supplies and the +3.2V reference output to
ground with 4.7µF tantalum capacitors in parallel with 0.1µF
ceramic capacitors. Locate the bypass capacitors as close
to the unit as possible.

2. The ADS-932 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,
always adjust offset before gain. Tie pins 5 and 6 to
ANALOG GROUND (pin 4) if not using offset and gain adjust
circuits.

3. Pin 35 (COMP. BITS) is used to select the digital output
coding format of the ADS-932 (see Tables 2a and 2b).
When this pin has a TTL logic "0" applied, it complements
all of the ADS-932’s digital outputs.

Pin 35 is TTL compatible and can be directly driven with
digital logic in applications requiring dynamic control over its
function. There is an internal pull-up resistor on pin 35
allowing it to be either connected to +5V or left open when a
logic "1" is required.

4. To enable the three-state outputs, connect OUTPUT
ENABLE (pin 34) to a logic "0" (low). To disable, connect pin
34 to a logic "1" (high).

5. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") will initiate a new and probably
inaccurate conversion cycle. Data from both the interrupted
and subsequent conversions will be invalid.

ADS-932

®

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6. Do not enable/disable or complement the output bits or
read from the FIFO during the conversion process (from the
rising edge of EOC to the falling edge of EOC).

7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the
input voltage exceeds that which produces an output of all
1’s or when the input equals or exceeds the voltage that
produces all 0’s. When COMP BITS is activated, the above
conditions are reversed.

8. When configuring the ADS-932 for the unipolar mode, Pin 1
(+3.2V REF.) should be connected to Pin 2 (Unipolar)
through a non-inverting op-amp. For precision DC applica­tions an OP-07 type amplifier is recommended, while AC
applications requiring the lowest level of harmonic distor­tion should consider the AD9631.
When configuring the ADS-932 for the bipolar mode, Pin 2
(Unipolar) should be physically disconnected from the
surrounding circuitry. This will help prevent noise from
coupling into the A/D.

INTERNAL FIFO OPERA TION

The ADS-932 contains an internal, user-initiated, 18-bit, 16­word FIFO memory. Each word in the FIFO contains the 16
data bits as well as the MSB and overflow bits. Pins 8 (FIFO/

When the FIFO is initially empty, digital data from the first
conversion (the "oldest" data) appears at the output of the
FIFO immediately after the first conversion has been
completed and remains there until the FIFO is read.

If the output three-state register has been enabled (logic "0"
applied to pin 34), data from the first conversion will appear at
the output of the ADS-932. Attempting to write a 17th word to
a full FIFO will result in that data, and any subsequent
conversion data, being lost.

Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both
equal to "1"), it can be read by dropping the FIFO READ line
(pin 9) to a logic "0" and then applying a series of 15 rising
edges to the read line. Since the first data word is already
present at the FIFO output, the first read command (the first
rising edge applied to FIFO READ) will bring data from the
second conversion to the output. Each subsequent read
command/rising edge brings the next word to the output lines.
After the 15th rising edge brings the 16th data word to the
FIFO output, the subsequent falling edge on READ will update
the status outputs (after a 20ns maximum delay) to FSTAT1 =
0, FSTAT2 = 1 indicating that the FIFO is empty.

If a read command is issued after the FIFO empties, the last
word (the 16th conversion) will remain present at the outputs.

DIR) and 9 (FIFO READ) control the FIFO's operation. The
FIFO's status can be monitored by reading pins 10 (FSTAT1)
and 11 (FSTAT2).

When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is
inserted into the digital data path. When pin 8 has a logic "0"
applied, the FIFO is transparent and the output data goes
directly to the output three-state register (whose operation is
controlled by pin 34 (ENABLE)). Read and write commands to

FIFO Reset Feature

At any time, the FIFO can be reset to an empty state by putting
the ADS-932 into its "direct" mode (logic "0" applied to pin 8,
FIFO/DIR) and also applying a logic "0" to the FIFO READ line
(pin 9). The empty status of the FIFO will be indicated by
FSTAT1 going to a "0" and FSTAT2 going to a "1". The status

outputs change 40ns after applying the control signals.
the FIFO are ignored when the ADS-932 is operated in the
"direct" mode. It takes a maximum of 20ns to switch the FIFO
in or out of the ADS-932’s digital data path.

FIFO Status, FSTAT1 and FSTAT2

Monitor the status of the data in the FIFO by reading the two

FIFO Write and Read Modes

Once the FIFO has been enabled (pin 8 high), digital data is
automatically written to it, regardless of the status of FIFO
READ (pin 9). Assuming the FIFO is initially empty, it will
accept data (18-bit words) from the next 16 consecutive A/D
conversions. As a precaution, pin 9 (which controls the FIFO's
READ function) should not be low when data is first written to

status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11).

CONTENTS FSTAT1 FSTAT2

Empty (0 words) 0 1
<half full (<8 words) 0 0
half-full or more (≥8 words) 1 0
Full (16 words) 1 1

an empty FIFO.

Table 1. FIFO Delays

DELAY PIN TRANSITION MIN. TYP. MAX. UNITS

Direct mode to FIFO enabled 8 – 10 20 ns
FIFO enabled to direct mode 8 – 10 20 ns
FIFO READ to output data valid 9 – – 40 ns
FIFO READ to status update when changing

from <half full (1 word) to empty
FIFO READ to status update when changing

from ≥half full (8 words) to <half full (7 words)
FIFO READ to status update when changing

from full (16 words) to ≥half full (15 words)
Falling edge of EOC to status update when writing

first word into empty FIFO
Falling edge of EOC to status update when

changing FIFO from <half full (7 words) to 32 – – 110 ns
≥half full (8 words)

Falling edge of EOC to status update when filling
FIFO with 16th word

9 – – 20 ns

9 – – 110 ns

9 – – 190 ns

32 – – 190 ns

32 – – 28 ns

0
1

0
1

0

0
1

1

1

1

0
1

0
1

1

0

0

0

ADS-932

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5

OVERFLOW

CONNECT for UNIPOLAR MODE

CALIBRATION PROCEDURE

Connect the converter per Figure 2. Any offset/gain
calibration procedures should not be implemented until the
device is fully warmed up. To avoid interaction, adjust offset
before gain. The ranges of adjustment for the circuits in
Figure 2 are guaranteed to compensate for the ADS-932’s
initial accuracy errors and may not be able to compensate for
additional system errors.

A/D converters are calibrated by positioning their digital
outputs exactly on the transition point between two adjacent
digital output codes. This is accomplished by connecting
LED's to the digital outputs and performing adjustments until
certain LED's "flicker" equally between on and off. Other
approaches employ digital comparators or microcontrollers to
detect when the outputs change from one code to the next.

For the ADS-932, offset adjusting is normally accomplished
when the analog input is 0 minus ½ LSB (–42µV). See Table
2b for the proper bipolar output coding.

Gain adjusting is accomplished when the analog input is at
nominal full scale minus 1½ LSB's (+2.749874V).

Note: Connect pin 5 to ANALOG GROUND (pin 4) for
operation without zero/offset adjustment. Connect pin 6 to pin
4 for operation without gain adjustment.

Zero/Offset Adjust Procedure

1. Apply a train of pulses to the START CONVERT input (pin

12) so that the converter is continuously converting.

2. For unipolar or bipolar zero/offset adjust, apply –42µV to the
ANALOG INPUT (pin 3).

3. For bipolar inputs, adjust the offset potentiometer until the
code flickers between 1000 0000 0000 0000 and 0111 1111
1111 1111 with pin 35 tied high (complementary offset
binary) or between 0111 1111 1111 1111 and 1000 0000
0000 0000 with pin 35 tied low (offset binary).
For unipolar inputs, adjust the offset potentiometers until all
output bits are 0's and the LSB flickers between 0 and 1 with
Pin 35 tied high (straight binary) or until all bits are 1's and
the LSB flickers between 0 and 1 with pin 35 tied low
(complementary binary).

4. Two's complement coding requires using BIT 1 (MSB) (pin

29). With pin 35 tied low, adjust the trimpot until the output
code flickers between all 0’s and all 1’s.

Gain Adjust Procedure

1. Apply +2.749874V to the ANALOG INPUT (pin 3).

2. For bipolar inputs adjust the gain potentiometer until all
output bits are 0’s and the LSB flickers between a 1 and 0
with pin 35 tied high (complementary offset binary) or until
all output bits are 1’s and the LSB flickers between a 1 and
0 with pin 35 tied low (offset binary).

3. Two's complement coding requires using BIT 1 (MSB)
(pin 29). With pin 35 tied low, adjust the gain trimpot until
the output code flickers equally between 0111 1111 1111
1111 and 0111 1111 1111 1110.

+5V

–5V

+5V

4.7µF

4.7µF

4.7µF

+ +

6.8µF

0.1µF

0.1µF

0.1µF

4.7µF0.1µF

20kΩ

GAIN

ADJUST

+5V

31

DIGITAL

DIGITAL

7, 30

GROUND

38

+5V ANALOG
ANALOG

GROUND

4, 36

37

–5V

34 ENABLE

8 FIFO/DIR

10 FSTAT1

2

UNIPOLAR

FSTAT2

11

+3.2V

1

REF. OUT

6

–5V+5V

ADS-932

20kΩ

–5V+5V

5

OFFSET
ADJUST

ANALOG INPUT

FIFO READ

COMP. BITS

33
32

EOC

29

BIT 1 (MSB)

28

BIT 1 (MSB)

27

BIT2

26

BIT 3

25

BIT 4

24

BIT 5

23

BIT 6

22

BIT 7

21

BIT 8

20

BIT 9

19

BIT 10

18

BIT 11

17

BIT 12

16

BIT 13

15

BIT 14

14

BIT 15

13

BIT 16 (LSB)

3

+5V

9

12START CONVERT

35

Figure 2. Bipolar Connection Diagram

ADS-932

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clock with a 100nsec positive

pulse width is used for all production testing.

0

0 100 200 300 400 500 600 700 800 900 1000

(fs = 2MHz, fin = 975kHz, Vin = –0.5dB, 16,384-point FFT)

THERMAL REQUIREMENTS

All DATEL sampling A/D converters are fully characterized and
specified over operating temperature (case) ranges of 0 to
+70°C and –55 to +125°C. All room-temperature (TA = +25°C)
production testing is performed without the use of heat sinks
or forced-air cooling. Thermal impedance figures for each
device are listed in their respective specification tables.

These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should
be used to ensure devices do not overheat. The ground and
power planes beneath the package, as well as all pcb signal
runs to and from the device, should be as heavy as possible to
help conduct heat away from the package. Electrically
insulating, thermally-conductive "pads" may be installed

underneath the package. Devices should be soldered to
boards rather than "socketed", and of course, minimal air flow
over the surface can greatly help reduce the package
temperature.

In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat sinks.
See Ordering Information for the assigned part number. See
page 1-183 of the DATEL Data Acquisition Components
Catalog for more information on the HS Series. Request
DATEL Application Note AN-8, "Heat Sinks for DIP Data
Converters," or contact DATEL directly, for additional
information.

START

CONVERT

INTERNAL S/H

EOC

OUTPUT

DATA

Notes:

2.

3.

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120

Amplitude Relative to Full Scale (dB)

–130
–140
–150
–160
–170

N N+1

Hold

20ns typ.

Data N-4 Valid Data N-2 Valid

Scale is approximately 50ns per division. fs = 2MHz.1.
This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data

from the first conversion to appear at the output of the A/D.
The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec

(when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse
can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz

N+2

100ns typ.

Acquisition Time

225ns typ.20ns typ.

275ns typ.

75ns typ.

260ns typ.

Conversion Time

Data N-3 Valid

60ns typ.

Invalid

Data

45ns typ.

440ns typ.

Figure 3. ADS-932 Timing Diagram

Invalid

Data

N+3

Data N-1 Valid

Figure 4. FFT Analysis of ADS-932

Frequency (kHz)

ADS-932

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7

+5VF

DGND

1020

C15

12

9

0.1µF

P1

20

B4B5B6

16

5

AB4

AB5

+5VD

30

31

+5VD

DGND

DGNDB10

DGNDB9

171513

181614

18

17

74HCT573

4

3

AB6

29

MSB

DGND

B7

AB7

AB1

28

MSB

COMPLIMB12

ENABLEB11

B8

19

2

AB8

+5VF

AB2

27

B2B3B4

COMPLIM

N.C.
9

11
12

10

B13

11 1

AB3

26

FST1

FIF/DIRB15

READB14

7

5

3

8

6

4

(LSB)
B16

(LSB)

DGND

B16

12

1020

9

AB16

C17

0.1µF
DGND

AB4

AB5

AB6

22

23

24

25

B6B7B8

B5

FST2

START

13

U4

8

AB7

1
2

B15

AB15

21

14

7

AB8

B14

AB14

U6

ENABLE
J2

321

B13

15

6

AB13

32

1

B12

16

5

AB12

74HC86

J3

17

74HCT573

4

COMP

B11

AB11

EOC

U5

231

READ
J4

32

1

18

3

+5VD

B10

AB10

FIFO/DIR
J5

32

1

RD

B9

19

2

AB9

FST2

8

U5

74HC86

10

DGND

FIF

11 1

C8

+5VF

0.1µF

FST1

74HC86

11

7

14

U5

9

13

+5VF

DGND DGND

12

DGND

2.2µF

C21

2.2µF

C12

DGNDB8

DGNDB7

DGNDB6

DGNDB5

DGNDB4

EOCB3

OVRFLWB2

DGNDDGND

AGND AGND AGND AGND

0.1µF

OVRFLW
18

17

74HCT573

4

3

40

UUT

B1B MSBB1(MSB)

33312927252321

34323028262422

0.1µF

1

11

38

+5VA

–5VA

37

-5VA

C16

36

AGND

DGND

1020

0.1µF

35

B1B MSB
19

2

39

NC

+5VF

+5VA

NC

(MSB)
B1

12

U3

987

AB1

COMP

34

COMP

ENABLE

19

B3

B2

15

14

13

6

AB2

AB3

DGND

32

33

OF

EOC

2.2µF

C14

0.1µF

C20

+5VA +5VA

0.1µF

C19

–5VA –5VA

0.1µF

C18

+5VD +5VD

16

15

14

13

U2

8

7

6

5

DGND

C4

2.2µF

C3

0.1µF

–15V

–5VA

+15V

+5VA

C1

7

2

2.2µF

6

AR1

OPTION

AMPLIFIER

SG8

C2

4

3

SG7

R2R1

AGND

+3.2VREF

123

AGND

SG6

2.2µF
AGND

2

B2

ANALOG INPUT

AGND

SG9

AGND

SG5

+5VF

AGND

+5VF

ANA IN

4

C5

14
10

AGND

5

4

0.1µF

12

OFFSET

5

2

9

U1

11

AGND

DGND

74HCT74

FIFO/DIR

DGND

GAIN

6

7

8

FIF

DGND

1

R3

3.3k

6

2

U1

2

1

74HCT74

3

+5VF

8

13
7

DGND

FSTAT2

FSTAT1

READ

9

1011121314151617181920

RD

C10

33pF

1

DGND

C6

2.2µF
DGND

8

14

X1

2MHZ

1

7

B15

LSB

START

AB16

AB15

J1

3 2 1

R6

1

START CONVERT

B1

B12

B13

B14

AB14

AB13

AB12

+5VF

L1

20mH

C7

2.2µF

50

B11

AB11

L2

DGND

+5VD

+5VD

B10

AB10AB10

20mH

–5VA

C9

B9

AB9

2.2µF

–15V

1011121314151617181920212223242526

DGND

74HC86

–5VA

L3

DGND

+15V

6

4

+5VA

123456789

START

CONVERT

U5

5

20mH

C11

2.2µF

P2

SG1

L4

AGND

SG2

+5VA

+5VA

GAIN ADJUST

+5VA

20mH

C13

2.2µF

SG4

SG3

20k

R5

123

20k

R4

123

OFFSET

ADJUST

AGND

DGND

AGND

–5VA

Figure 5. ADS-932 Evaluation Board Schematic.

–5VA

ADS-932 EVALUATION BOARD

ADS-932

®

®

Table 2a. Setting Output Coding Selection (Pin 35)

OUTPUT FORMAT PIN 35 LOGIC LEVEL

Complementary Offset Binary 1
Offset Binary 0
Complementary Two’s Complement 1

(Using MSB, pin 29)
Two’s Complement 0

(Using MSB, pin 29)
Straight Binary 1

Complimentary Binary 0

Table 2b. Output Coding

UNIPOLAR

SCALE

–FS+1 LSB

–FS +1 1/2 LSB

–7/8 FS
–3/4 FS
–1/2 FS

–1/2FS–1/2LSB

–1/4 FS
–1/8 FS

–1 LSB

–1/2 LSB

0

INPUT

RANGE

0 to –5.5V

–5.499916
–5.499874
–4.812500
–4.125000
–2.750000
–2.749958
–1.375000
–0.687500
–0.000084
–0.000042

0.000000

STRAIGHT BINARY

COMP. BINARY

OUTPUT CODING

MSB LSB MSB LSB

1111 1111 1111 1111

LSB "1" to "0"
1110 0000 0000 0000
1100 0000 0000 0000
1000 0000 0000 0000
0111 1111 1111 1111
0100 0000 0000 0000
0010 0000 0000 0000
0000 0000 0000 0001

LSB "0" to "1"
0000 0000 0000 0000

0000 0000 0000 0000

LSB "0" to "1"
0001 1111 1111 1111
0011 1111 1111 1111
0111 1111 1111 1111
1000 000 000 0000
1011 1111 1111 1111
1101 1111 1111 1111
1111 1111 1111 1110

LSB "1" to "0"

1111 1111 1111 1111

COMP. OFF. BIN.OFFSET BINARY TWO'S COMP. COMP. TWO'S COMP.

Table 3. Input Connections

Input Range Input Pin Connect

0 to –5.5V Pin 3 Pin 1 To Pin 2
±2.75V Pin 3 Pin 2 is No Connect

MSB LSB MSB LSB

0111 1111 1111 1111

LSB "1" to "0"
0110 0000 0000 0000
0100 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1100 0000 0000 0000
1010 0000 0000 0000
1000 0000 0000 0001

LSB "0" to "1"
1000 0000 0000 0000

1000 0000 0000 0000

LSB "0" to "1"
1001 1111 1111 1111
1011 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0011 1111 1111 1111
0101 1111 1111 1111
0111 1111 1111 1110

LSB "1" to "0"
0111 1111 1111 1111

INPUT

RANGE

±2.75V

+2.749916
+2.749874
+2.062500
+1.375000

0.000000
–0.000084
–1.375000
–2.062500
–2.749916
–2.749958
–2.750000

BIPOLAR

SCALE

+FS –1 LSB

+FS –1 1/2 LSB

+3/4 FS
+1/2 FS

0

–1 LSB
–1/2 FS
–3/4 FS

–FS +1 LSB

–FS + 1/2 LSB

–FS

®

®

9

0.74

DNL (LSB's)

ADS-932

4410

4000

–0.56

Number of Occurrences

0

0

Digital Output Code

Codes

Figure 6. ADS-932 Histogram and Differential Nonlinearity

65,536

65,536

3000

2000

1000

0

Digital Output Code

Figure 7. ADS-932 Grounded Input Histogram

This histogram represents the typical peak-to-peak noise

(including quantization noise) associated with the ADS-932.

ADS-932

®

®

MECHANICAL DIMENSIONS INCHES (mm)

2.12/2.07

(53.85/52.58)

0.210 MAX.
(5.334)

0.245 MAX.
(6.223)

21 40

1 20

0.100 TYP.
(2.540)

1.900 ±0.008
(48.260)

PIN 1 INDEX
( ON TOP)

0.018 ±0.002
(0.457)

0.045/0.035

(1.143/0.889)

0.110/0.090

(2.794/2.286)

1.11/1.08

(28.20/27.43)

0.200/0.175

(5.080/4.445)

0.035/0.015

(0.889/0.381)

Dimension Tolerances

2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)

Lead Material:
Lead Finish:

over 100 microinches (nominal) nickel plating

SEATING

PLANE

(unless otherwise indicated):

Kovar alloy

50 microinches (minimum) gold plating

0.015/0.009

(0.381/0.229)

0.900 ±0.010
(22.86)

0.110/0.090

(2.794/2.286

ORDERING INFORMATION

MODEL TEMP. RANGE

OPERATING

ADS-932MC 0 to +70°C
ADS-932MM –55 to +125°C

Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead

Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead
Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.

Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.

® ®

ISO 9001

ISO 9001

INNOV A TION and EX CELLENCE

REGISTERED

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: [phone], [phone] Fax: [phone]
Internet: www.datel.com E-mail: [e-mail]
Data sheet fax back: [phone]

DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein

DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein

DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

ACCESSORIES
ADS-B932 Evaluation Board (without ADS-932)

HS-40 Heat Sink for all ADS-932 models

DS-0308A 01/2000

DATEL (UK) LTD. Tadley, England Tel: [phone]

DATEL (UK) LTD. Tadley, England Tel: [phone]

DATEL (UK) LTD. Tadley, England Tel: [phone]
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: [phone]

DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: [phone]

DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: [phone]
DATEL GmbH Munchen, Germany Tel: [phone]

DATEL GmbH Munchen, Germany Tel: [phone]

DATEL GmbH München, Germany Tel: [phone]
DATEL KK Tokyo, Japan Tel: [phone], Osaka Tel: [phone]

DATEL KK Tokyo, Japan Tel: [phone], Osaka Tel: [phone]

DATEL KK Tokyo, Japan Tel: [phone], Osaka Tel: [phone]