DATASHEETS tdf8704 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDF8704

8-bit high-speed analog-to-digital
converter

Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02

Philips Semiconductors

June 1994

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

FEATURES

• 8-bit resolution

• Sampling rate up to 50 MHz

• Extended temperature range (−40 to +85 °C)

• High signal-to-noise ratio over a large analog input

frequency range (7.4 effective bits at 4.43 MHz full-scale
input and at f

= 50 MHz)

clk

• Binary 3-state TTL outputs

• Overflow/underflow 3-state TTL output

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Stable internal reference voltage regulator included

• Power dissipation only 380 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

QUICK REFERENCE DATA

APPLICATIONS

• General purpose high-speed analog-to-digital
conversion for extended temperature applications

• Automotive

• RF, satellite and GPS (Global Positioning System)

• Medical

• General industrial

• Digital video (VCR, TV and satellite).

GENERAL DESCRIPTION

The TDF8704T is an 8-bit high-speed analog-to-digital
converter (ADC) for general industrial applications. It
converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 50 MHz. All
digital inputs and outputs are TTL compatible, although a
low-level AC clock input signal is allowed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 37 46 mA
digital supply current − 23 35 mA

output stages supply current − 16 21 mA
ILE DC integral linear error −±0.4 ±1 LSB
DLE DC differential linearity error −±0.2 ±0.5 LSB
AILE AC integral linearity error note 1 −−±2 LSB
f

clk(max)

P

tot

maximum clock frequency 50 −−MHz

total power dissipation − 380 535 mW

Note

1. Full-scale sine wave (f

= 4.43 MHz; f

i

= 50 MHz).

clk

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

SAMPLING

FREQUENCY

TDF8704T/2 24 SO24L plastic SOT137-1 20 MHz
TDF8704T/4 24 SO24L plastic SOT137-1 40 MHz
TDF8704T/5 24 SO24L plastic SOT137-1 50 MHz

June 1994 2

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

BLOCK DIAGRAM

handbook, full pagewidth

V

RT

V

RB

OGND

V

analog

voltage input

output ground

V

CCA

7

STABILIZER

5DEC

9

I

8

4

20

TDF8704

ANALOG - TO - DIGITAL

CONVERTER

6
AGND

17
DGND

CLK
16

CLOCK DRIVER

LATCHES

OVERFLOW / UNDERFLOW

LATCH

V

CCD

18

TTL OUTPUTS

TTL OUTPUT

CE

22

12
13
14
15
23
24 D2

19
21

11

MSA685

D7
D6
D5
D4
D3

1

D1

2

D0

MSB

data outputs

LSB

V

CCO1

V

CCO2

overflow / underflow

output

analog ground digital ground

Fig.1 Block diagram.

June 1994 3

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
n.c. 3 not connected
V

RB

DEC 5 decoupling input (internal

AGND 6 analog ground
V

CCA

V

I

V

RT

n.c. 10 not connected
O/UF 11 overflow/underflow data output
D7 12 data output; bit 7 (MSB)
D6 13 data output; bit 6
D5 14 data output; bit 5
D4 15 data output; bit 4
CLK 16 clock input
DGND 17 digital ground
V

CCD

V

CCO1

OGND 20 output ground
V

CCO2

CE 22 chip enable input (TTL level input,

D3 23 data output; bit 3
D2 24 data output; bit 2

4 reference voltage BOTTOM

(decoupling)

stabilization loop decoupling)

7 analog supply voltage (+5 V)
8 analog input voltage
9 reference voltage TOP (decoupling)

18 digital supply voltage (+5 V)
19 supply voltage for output stages 1

(+5 V)

21 supply voltage for output stages 2

(+5 V)

active LOW)

handbook, halfpage

1

D1

2

D0

3

n.c.

V

RB

4
5

DEC

AGND

6

V

CCA

V

O/UF

V

RT

n.c.

D7

TDF8704

7
8

I

9
10
11
12

MSA686

Fig.2 Pin configuration.

24

D2
D3

23
22

CE
V

21

CCO2

OGND

20

V

CCO1

19

V

CCD

18
17

DGND

CLK

16

D4

15

D5

14

D6

13

June 1994 4

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V
∆V
∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

CC
CC
CC

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output stages supply voltage −0.3 +7.0 V
supply voltage differences between V
supply voltage differences between V
supply voltage differences between V

CCA
CCO
CCA

and V

and V

and V

CCD

CCD

CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V
AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
junction temperature − +150 °C

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

June 1994 5

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

CHARACTERISTICS (see Tables 1 and 2)

V

= V7 to V6 = 4.75 to 5.25 V; V

CCA

and DGND shorted together; V
V

CCA

to V

= −0.25 to +0.25 V; T

CCD

CCA

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 37 46 mA
digital supply current − 23 35 mA
output stages supply current all outputs LOW − 16 21 mA

Inputs

= V18to V17 = 4.75 to 5.25 V; V

CCD

to V

amb

= −0.25 to +0.25 V; V

CCD

= −40 to +85 °C; typical readings taken at V

CCO

CCO

to V

= V19and V21to V20 = 4.75 to 5.25 V; AGND

= −0.25 to +0.25 V;

CCD

CCA=VCCD

= 5 V and T

amb

=25°C;

LOCK INPUT CLK (REFERENCED TO DGND)

C
V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V

input impedance f
input capacitance f

= 0.4 V −400 −−µA

clk

= 2.7 V −−100 µA

clk

V

clk=VCCD

= 50 MHz − 2 − kΩ

clk

= 50 MHz − 4.5 − pF

clk

−−300 µA

VI(ANALOG INPUT VOLTAGE REFERENCED TO AGDN; SEE FIGS 3 AND 4 AND TABLE 1)
V

V
V
V
V
V
V

I(B)
I(0)
os(B)
I(T)
I(255)
os(T)
I(p-p)

input voltage (BOTTOM) 1.21 1.25 1.29 V
input voltage output code = 0 1.42 1.48 1.51 V
offset voltage (BOTTOM) V

I(0)

to V

I(B)

210 225 240 V
input voltage (TOP) 3.37 3.46 3.58 V
input voltage output code = 255 3.14 3.22 3.30 V
offset voltage (TOP) V
input voltage amplitude

I(T)

to V

I(255)

225 240 255 V

1.69 1.74 1.79 V

(peak-to-peak value)

I

L

I

IL

I

IH

Z

I

C

I

load current on VRT and V

RB

LOW level input current VI = 1.25 V − 0 −µA
HIGH level input current VI = 3.46 V 40 150 400 µA
input impedance fi = 4.43 MHz − 10 − kΩ
input capacitance fi = 4.43 MHz − 14 − pF

−300 − +300 µA

CCD

V

June 1994 6

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

INPUT CE (REFERENCED TO DGND) SEE TABLE 2
V

IL

V

IH

I

IL

I

IH

Reference resistance

R

ref

Outputs

D

IGITAL OUTPUTS D7 TO D0 (REFERENCED TO DGND)

V

OL

V

OH

I

OZ

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V

CCD

V
LOW level input current VIL = 0.4 V −400 −−µA
HIGH level input current VIH = 2.7 V −−20 µA

reference resistance VRT to V

RB

LOW level output voltage IO = 1 mA;

T

= 0 to +85 °C

amb

= 1 mA;

I

O

T

=0to−40 °C

amb

HIGH level output voltage IO = −0.4 mA 2.7 − V
output current in 3-state

0.4 V < VO < V

CCD

− 200 −Ω

0 − 0.4 V

−−0.6 V

CCD

V

−20 − +20 µA

mode

Switching characteristics

C

LOCK INPUT CLK (NOTE 1; SEE FIG.15)

f

clk(max)

maximum clock frequency

TDF8704T/2 20 −−MHz
TDF8704T/4 40 −−MHz
TDF8704T/5 50 −−MHz

t

CPH

t

CPL

clock pulse width HIGH 7 −−ns
clock pulse width LOW 7 −−ns

Analog signal processing

INEARITY

L
ILE DC integral linearity error −±0.4 ±1.0 LSB

DLE DC differential linearity error −±0.2 ±0.5 LSB
AILE AC integral linearity error note 2 −−±2.0 LSB

BANDWIDTH (f
B −0.5 dB analog bandwidth

t

STLH

t

STHL

=40MHZ)

clk

(note 3)
analog input settling time

LOW-to-HIGH
analog input settling time

HIGH-to-LOW

full-scale sine wave − 12 − MHz
75% full-scale sine wave − 16 − MHz
full-scale square wave;

− 2.5 3.5 ns

Fig.8; note 4
full-scale square wave;

− 3.0 4.0 ns

Fig.8; note 4

June 1994 7

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

HARMONICS (f
h

1

=40MHZ)

clk

fundamental harmonics

fi = 4.43 MHz −−0dB

(full scale)

h

all

harmonics (full scale);

fi = 4.43 MHz

all components

second harmonics −−64 −60 dB
third harmonics −−58 −55 dB

THD total harmonic distortion f

= 4.43 MHz −−56 − dB

i

SIGNAL-TO-NOISE RATIO
S/N signal-to-noise ratio without harmonics;

f

= 40 MHz;

clk

fi= 4.43 MHz
EFFECTIVE BITS; NOTE 5; SEE FIGS 9, 10 AND 11
EB effective bits

TDF8704T/2 f

= 20 MHz

clk

= 1.25 MHz − 7.8 − bits

f

i

= 4.43 MHz − 7.6 − bits

f

i

effective bits

TDF8704T/4 f

= 40 MHz

clk

= 4.43 MHz − 7.5 − bits

f

i

= 7.5 MHz − 7.3 − bits

f

i

= 10 MHz − 7.0 − bits

f

i

effective bits

TDF8704T/5 f

= 50 MHz

clk

= 4.43 MHz − 7.4 − bits

f

i

= 7.5 MHz − 7.2 − bits

f

i

= 10 MHz − 6.9 − bits

f

i

TWO-TONE (NOTE 6)
TTIR two-tone intermodulation

= 40 MHz −−56 − dB

f

clk

rejection
BIT ERROR RATE
BER bit error rate f

= 40 MHz;

clk

fi= 4.43 MHz;

VI= ±16 LSB at code 128
DIFFERENTIAL GAIN (NOTE 7)
G

diff

differential gain f

= 20 MHz;

clk

fi= 4.43 MHz
DIFFERENTIAL PHASE (NOTE 7)

ϕ

diff

differential phase f

= 40 MHz;

clk

fi= 4.43 MHz

46 48 − dB

− 10

−11

− times/

samples

− 0.6 − %

− 0.8 − deg

June 1994 8

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing (note 8; see Figs 5 and 7; f

t

ds

t

h

t

d

sampling delay time −−2ns
output hold time 5 −−ns
output delay time − 12 15 ns

= 50 MHz)

clk

3-state output delay times (see Figs 6 and 7)

t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 610ns
enable LOW − 12 16 ns
disable HIGH − 50 54 ns
disable LOW − 10 14 ns

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must be less than 1 ns.

2. Full-scale sine wave (fi = 4.43 MHz; f

= 50 MHz).

clk

3. Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.

4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The
calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

7. Measurement taken using video analyser VM700A.

8. Output data acquisition: the output data is available after the maximum delay time of td.

MBD868

I(B)

o

under

1.29

V

(V)

1.27

1.25

1.23

I (B)

3.49

handbook, halfpage

V

I (T)

(V)

3.47

3.45

3.43
60

Fig.3 Influence of T

0.1 mV/K

V

I (T)

0.05 mV/K

V

I (B)

20 20 60 100

on V

amb

I(T)

T ( C)

amb

and V

5 V supply.

June 1994 9

3.44

ndbook, halfpage

V

I (T)

(V)

3.42

V

I (T)

3.40

3.38

4.25 4.75 5.75

V

I (B)

5.25

Fig.4 Influence of supply voltage on V

V

under T

I(B)

= 25 °C.

amb

17 mV/V

7 mV/V

V (V)

CC

MSA689

I(T)

1.28

V

1.26

1.24

1.22

and

I (B)

(V)

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

Table 1 Output coding and input voltage (typical values; referenced to AGND).

STEP V

I(p-p)

O/UF

D7 D6 D5 D4 D3 D2 D1 D0

Underflow <1.48 1 1 0000000
0 1.48 0 0 0000000
1 − 000000001

. . .. ......

. . .........

254 . 011111110
255 3.46 0 1 1111111
Overflow >3.46 1 1 1111111

Table 2 Mode selection.

CE D7 TO D0 O/UF

1 high impedance high impedance
0 active; binary active

t

BINARY OUTPUT BITS

handbook, full pagewidth

t

CPL

CPH

CLK

V

l

DATA
D0 to D7

DATA

N 2

sample N

t

ds

DATA

N 1

t

d

sample N 1

t

h

DATA

N

Fig.5 Timing diagram for data output.

sample N 2

N

DATA

N 1

1.4 V

2.4 V

1.4 V

0.4 V

MSA688 - 1

June 1994 10

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

V

CE

CCD

50 %

handbook, full pagewidth

fCE= 100kHz.

LOW

V

S1

CCD

t

dZH

t
t
t
t

MLB880

50 %

TEST S1

dLZ
dZL
dHZ
dZH

output
data

output
data

LOW

t

dLZ

10 %

TDF8704

CE

HIGH

t

dHZ

HIGH

t

dZL

50 %

3.3 kΩ

15 pF

90 %

Fig.6 Timing diagram and test conditions of 3-state output delay time.

V

CCD

V

CCD

GND
GND

handbook, halfpage

Fig.7 Load circuit for timing measurement.

June 1994 11

D0 to D7

15 pF

MBB956 - 1

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

handbook, full pagewidth

amplitude

(dB)

0

20

handbook, full pagewidth

t

STLH

code 255

V

50 %

I

code 0

2 ns

CLK

MBD869

50 %

0.5 ns

Fig.8 Analog input settling-time diagram.

2 ns

t

STHL

50 %

50 %

0.5 ns

MBD870

40

60

80

100

120

0 1.25 2.49

Effective bits: 7.89; THD = −61.05dB.
Harmonic levels (dB): 2nd =−84.07; 3rd = −62.50; 4th = −92.01; 5th = −66.56; 6th = −101.15.

Fig.9 Fast Fourier Transform (f

3.74

= 20 MHz; fi= 1.25 MHz).

clk

June 1994 12

8.724.98 6.23 7.47 9.96
f (MHz)

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

handbook, full pagewidth

0

amplitude

(dB)

20

40

60

80

100

120

0 2.48 4.96

Effective bits: 7.61; THD = −57.11 dB.
Harmonic levels (dB): 2nd = −68.53; 3rd = −58.36; 4th = −74.89; 5th = −65.37; 6th = −76.08.

Fig.10 Fast Fourier Transform (f

7.44

= 40 MHz; fi= 4.43 MHz).

clk

MBD871

17.49.93 12.4 14.9 19.9

f (MHz)

handbook, full pagewidth

0

amplitude

(dB)

20

40

60

80

100

120

0 3.12 6.24

Effective bits: 6.91; THD = −46.13 dB.
Harmonic levels (dB): 2nd = −59.66; 3rd = −46.67; 4th = −70.80; 5th = −57.96; 6th = −72.16.

Fig.11 Fast Fourier Transform (f

9.35

= 50 MHz; fi= 10 MHz).

clk

MBD872

21.812.5 15.6 18.7 24.9

f (MHz)

June 1994 13

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

INTERNAL PIN CONFIGURATIONS

V

handbook, halfpage

V

CCO2

CCO1

handbook, halfpage

V

CCA

D7 to D0

O/UF

DGND

MLB036

Fig.12 TTL data and overflow/underflow outputs.

ook, halfpage

V

CCO1

V

AGND

(x 90)

I

MLB037

Fig.13 Analog inputs.

CE

DGND

Fig.14 CE (3-state) input.

June 1994 14

MLB038

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

handbook, full pagewidth

V

CCA

DEC

AGND

Fig.15 V

RB, VRT

and DEC.

MSA687

V

RT

V

RB

V

handbook, full pagewidth

CCD

CLK

30 kΩ 30 kΩ

DGND

Fig.16 CLK input.

June 1994 15

MCD189 - 1

V

ref

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

APPLICATION INFORMATION

handbook, halfpage

47 pF

AGND

AGND

AGND

10 nF

100 nF

1

D1 D2

2

D0

(2)

n.c.

3

(1)

V

4

RB

DEC

5

6

AGND

V

CCA

V

RT

n.c.

O / UF

D7

V

I

(1)

(2)

TDF8704

7

8

9

10

11

12

24

D3

23

CE

22

V

CCO2

21

OGND

20

V

CCO1

19

V

CCD

18

DGND

17

CLK

16

D4

15

D5

14

D6

13

MSA684

The analog and digital supplies should be separated and decoupled.
(1) VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
(2) Pins 3 and 10 should be connected to DGND in order to prevent noise influence.

Fig.17 Application diagram.

June 1994 16

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

PACKAGE OUTLINE

handbook, full pagewidth

S

pin 1

index

112

0.9

0.4

(4x)

15.6

15.2

1.27

0.49

0.36

0.1 S

1324

0.25 M

(24x)

2.45

2.25

0.3

0.1

10.65

10.00

detail A

7.6

7.4

1.1

0.5

1.1

1.0

0.32

0.23

o

0 to 8

MBC235 - 1

A

2.65

2.35

Dimensions in mm.

June 1994 17

Fig.18 Plastic small outline package; 24 leads; large body; SOT137-1.

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

SOLDERING
Plastic small-outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

June 1994 18