DATASHEETS tda8790 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8790

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

Product specification
Supersedes data of 1995 May 08
File under Integrated Circuits, IC02

1996 Feb 21

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

FEATURES

• 8-bit resolution

• Operation between 2.7 and 5.5 V

• Sampling rate up to 40 MHz

• DC sampling allowed

• High signal-to-noise ratio over a large analog input

frequency range (7.3 effective bits at 4.43 MHz
full-scale input at f

• CMOS/TTL compatible digital inputs and outputs

• External reference voltage regulator

• Power dissipation only 30 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• Sleep mode (4 mW)

• No sample-and-hold circuit required.

QUICK REFERENCE DATA

= 40 MHz)

clk

TDA8790

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Camera

• Camcorder

• Radio communication.

GENERAL DESCRIPTION

The TDA8790 is an 8-bit universal analog-to-digital
converter (ADC) for video and general purpose
applications. It converts the analog input signal from

2.7 to 5.5 V into 8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz. All digital inputs and
outputs are CMOS/TTL compatible. A sleep mode allows
reduction of the device power consumption down to 4 mW.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

V

DDO

∆V

DD

I

DDA

I

DDD

I

DDO

analog supply voltage 2.7 3.3 5.5 V
digital supply voltage 2.7 3.3 5.5 V
output stages supply voltage 2.5 3.3 5.5 V
supply voltage difference

V
V

DDA
DDD

− V

− V

DDD
DDO

−0.2 − +0.2 V

−0.2 − +2.25 V

analog supply current − 46mA
digital supply current − 58mA
output stages supply current f

= 40 MHz; CL= 20 pF;

clk

− 12mA

ramp input
INL integral non-linearity f
DNL differential non-linearity f
f

clk(max)

P

tot

maximum clock frequency 40 −−MHz
total power dissipation V

= 40 MHz; ramp input −±0.5 ±0.75 LSB

clk

= 40 MHz; ramp input −±0.25 ±0.5 LSB

clk

DDA=VDDD=VDDO

= 3.3 V − 30 53 mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8790M SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1996 Feb 21 2

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

V

RM

V

DDA

5

CLOCK DRIVER

10

R

LAD

I

9

8

ANALOG -TO - DIGITAL

CONVERTER

CLK

1

LATCHES

V

DDD

3

TDA8790

CMOS

OUTPUTS

2

19

D7

18

D6

17

D5
16 D4
15

D3
14

D2
13 D1
12

D0

TDA8790

SLEEP

MSB

data outputs

LSB

V

RB

7

6

V

analog
ground

SSA

V

output

ground

411

SSOVSSD1

digital

ground

20

MBE502

V

DDO

Fig.1 Block diagram.

1996 Feb 21 3

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input
SLEEP 2 sleep mode input
V

DDD

V

SSD

V

DDA

V

SSA

V

RB

V

RM

V

I

V

RT

V

SSO

D0 12 data output; bit 0 (LSB)
D1 13 data output; bit 1
D2 14 data output; bit 2
D3 15 data output; bit 3
D4 16 data output; bit 4
D5 17 data output; bit 5
D6 18 data output; bit 6
D7 19 data output; bit 7 (MSB)
V

DDO

3 digital supply voltage (2.7 to 5.5 V)
4 digital ground
5 analog supply voltage (2.7 to 5.5 V)
6 analog ground
7 reference voltage BOTTOM input
8 reference voltage MIDDLE

9 analog input voltage
10 reference voltage TOP input
11 digital output ground

20 positive supply voltage for output

stage (2.7 to 5.5 V)

1

CLK

2

SLEEP

V

3

DDD

V

4

SSD

V

5

DDA

V

V

SSA
V

RB

RM

V

RT

TDA8790

6
7
8

V

9

I

10

MBE501

Fig.2 Pin configuration.

TDA8790

V

20

DDO

19

D7

18

D6

17

D5

16

D4

15

D3

14

D2
D1

13

D0

12

V

11

SSO

1996 Feb 21 4

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD

V

DDO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

DD

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

− V

V
V
V

DDA
DDA
DDD

− V

− V

DDD
DDO
DDO

input voltage referenced to V
AC input voltage for switching

referenced to V

SSA
SSD

−1.0 +4.0 V

−1.0 +4.0 V

−1.0 +4.0 V

−0.3 +7.0 V

− V

DDD

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − +150 °C

V

Note

1. The supply voltages V

DDA

, V

DDD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

DDO

voltage ∆VDD remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 120 K/W

1996 Feb 21 5

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

CHARACTERISTICS

V

DDA=V5

V

i(p-p)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

DDA

V

DDD

V

DDO

∆V

I

DDA

I

DDD

I

DDO

Inputs

to V6= 3.3 V; V

= 1.84 V; CL= 20 pF; T

analog supply voltage 2.7 3.3 5.5 V
digital supply voltage 2.7 3.3 5.5 V
output stages supply voltage 2.5 3.3 5.5 V

DD

supply voltage difference

− V

V

DDA

− V

V

DDD

analog supply current − 46 mA
digital supply current − 58 mA
output stages supply current f

DDD=V3

DDD
DDO

to V4= 3.3 V; V

=0to+70°C; typical values measured at T

amb

DDO=V20

= 40 MHz; ramp input;

clk

to V11= 3.3 V; V

CL=20pF

SSA,VSSD

=25°C; unless otherwise specified.

amb

and V

shorted together;

SSO

−0.2 − +0.2 V

−0.2 − +2.25 V

− 12 mA

LOCK INPUT CLK (REFERENCED TO V

C
V

IL

V

IH

I

IL

I

IH

Z

I

C

I

INPUT SLEEP (REFERENCED TO V
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

LOW level input current V
HIGH level input current V
input impedance f
input capacitance f

SSD

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

LOW level input current VIL= 0.3V

HIGH level input current VIH= 0.7V
VI(ANALOG INPUT VOLTAGE REFERENCED TO V
I

IL

I

IH

Z

I

C

I

LOW level input current VI=V

HIGH level input current VI=V

input impedance fi= 1 MHz − 20 − kΩ

input capacitance fi= 1 MHz − 2 − pF

); see note 1

SSD

); see Table 2

SSA

≤ 3.6 V 0.6V

V

DDD

= 0.3V

clk

= 0.7V

clk

= 40 MHz − 4 − kΩ

clk

= 40 MHz − 3 − pF

clk

≤ 3.6 V 0.6V

V

DDD

)

Reference voltages for the resistor ladder; see Table 1
V

RB

V

RT

V

diff

I

ref

reference voltage BOTTOM 1.1 1.2 − V

reference voltage TOP V

TOP

≤ V

differential reference voltage

VRT− V

RB

reference current − 0.95 − mA

RB
RT

DDD

DDD

DDA

DDD
DDD

V

DDD
DDD
DDD

− V

− V

DDD
DDD

V
V

−10+1µA

−−5µA

V

DDD
DDD
DDD

− V

− V

DDD
DDD

V
V

−1 −− µA

−−+1 µA

− 0 −µA

− 9 −µA

2.7 3.3 V

DDA

V

1.5 2.1 2.7 V

1996 Feb 21 6

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

LAD

TC

RLAD

V

osB

V

osT

V

i(p-p)

Outputs

IGITAL OUTPUTS D7 TO D0 (REFERENCED TO V

D
V

OL

V

OH

I

OZ

Switching characteristics

LOCK INPUT CLK; see Fig.4; note 1

C
f

clk(max)

t

CPH

t

CPL

Analog signal processing

resistor ladder − 2.2 − kΩ
temperature coefficient of the

resistor ladder

− 1860 − ppm

− 4092 − mΩ/K

offset voltage BOTTOM note 2 − 170 − mV
offset voltage TOP note 2 − 170 − mV
analog input voltage (peak-to-peak

note 3 1.4 1.76 2.4 V

value)

)

SSD

LOW level output voltage IO= 1 mA 0 − 0.5 V
HIGH level output voltage IO= −1mA V
output current in 3-state mode 0.4V<VO<V

DDO

− 0.5 − V

DDO

DDO

V

−20 − +20 µA

maximum clock frequency 40 −− MHz
clock pulse width HIGH 9 −− ns
clock pulse width LOW 9 −− ns

INEARITY

L
INL integral non-linearity f

= 40 MHz; ramp input;

clk

see Fig.6

DNL differential non-linearity f

= 40 MHz; ramp input;

clk

see Fig.7

BANDWIDTH (f

= 40 MHz)

clk

B analog bandwidth full-scale sine wave;

note 4
75% full-scale sine wave;

note 4
50% full-scale sine wave;

note 4
small signal at mid scale;

= ±10 LSB at

V

i

code 128; note 4
INPUT SET RESPONSE (f
t

STLH

analog input settling time

= 40 MHz; see Fig.8; note 5)

clk

full-scale square wave − 35 ns

LOW-to-HIGH

t

STHL

analog input settling time

full-scale square wave − 35 ns

HIGH-to-LOW
HARMONICS;(f
THD total harmonic distortion f

=40MHZ; see Fig.9; note 6)

clk

= 4.43 MHz −−50 − dB

i

−±0.5 ±0.75 LSB

−±0.25 ±0.5 LSB

− 10 − MHz

− 13 − MHz

− 20 − MHz

− 350 − MHz

1996 Feb 21 7

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S

IGNAL-TO-NOISE RATIO; see Fig.9; note 6

S/N signal-to-noise ratio (full scale) without harmonics;

= 40 MHz;

f

clk

fi= 4.43 MHz
EFFECTIVE BITS; see Fig.9; note 6
EB effective bits f

= 40 MHz

clk

= 300 kHz − 7.8 − bits

f

i

= 4.43 MHz − 7.3 − bits

f

i

DIFFERENTIAL GAIN; see note 7
G

diff

differential gain f

= 40 MHz;

clk

PAL modulated ramp
DIFFERENTIAL PHASE; see note 7

ϕ

diff

differential phase f

= 40 MHz;

clk

PAL modulated ramp

Timing (f

t

ds

t

h

t

d

= 40 MHz; CL= 20 pF); see Fig.4; note 8

clk

sampling delay time −−5ns
output hold time 5 −− ns
output delay time V

= 4.75 V 8 12 15 ns

DDO

= 3.15 V 8 17 20 ns

V

DDO

= 2.7 V 8 18 21 ns

V

DDO

3-state sleep mode delay times; see Fig.5
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 14 18 ns
enable LOW − 16 20 ns
disable HIGH − 16 20 ns
disable LOW − 14 18 ns

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 256:
a) V

b) V

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to 256 at T

amb

amb

=25°C.

=25°C.

− 47 − dB

− 1.5 − %

− 0.25 − deg

1996 Feb 21 8

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

a) The current flowing into the resistor ladder is and the full-scale input range at the converter,

to cover code 0 to code 255, is

b) Since R

----------------------------------------- ­R

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

L

R

L

++

OBRLROT

will be kept reasonably constant from part to part. Consequently variation of the output codes

V

== V

iRLIL

I

L

×

at a given input voltage depends mainly on the difference V
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.

4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal.

5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

7. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC.

8. Output data acquisition: the output data is available after the maximum delay time of t

VRTVRB–

=

----------------------------------------- ­R

++

OBRLROT

R

----------------------------------------- ­R

L

++

OBRLROT

RT

RTVRB

)– 0.838 VRTVRB–(×=()×

− VRB and its variation with temperature and supply

.

d

handbook, halfpage

V

V

V

RT

RM

RB

9

R

OT

code 255

R

7

R

LAD

6

L

I

L

R

OB

MGD284

code 0

Fig.3 Explanation of note 3.

1996 Feb 21 9

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

Table 1 Output coding and input voltage (typical values; referenced to V

STEP

V

I(p-p)

(V)

D7 D6 D5 D4 D3 D2 D1 D0

BINARY OUTPUT BITS

Underflow <1.37 0 0 0 0 0 0 0 0

0 1.37 0 0 0 0 0 0 0 0
1 . 00000001

. . ........

. . ........

254 . 11111110
255 3.13 1 1 1 1 1 1 1 1

Overflow >3.13 1 1 1 1 1 1 1 1

Table 2 Sleep mode selection

SLEEP D7 TO D0 I

1 high impedance 1.2 mA
0 active 9 mA

SSA

)

DDA+IDDD

(typ.)

handbook, full pagewidth

CLK

V

l

DATA
D0 to D7

sample N

DATA

N - 2

t

CPH

t

CPL

50 %

sample N + 1

t

ds

DATA

N - 1

t

d

sample N + 2

t

h

DATA

N

DATA

N + 1

MSA670

V

DDO

50 %
0 V

Fig.4 Timing diagram.

1996 Feb 21 10

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

V

handbook, full pagewidth

DDD

SLEEP

output
data

output
data

LOW

t

dLZ

10 %

TDA8790

SLEEP

HIGH

t

dZL

50 %

20 pF

HIGH

3.3 kΩ

t

90 %

dHZ

LOW

V

S1

DDD

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

DDD

V

DDD

GND
GND

TDA8790

MBE503

f

SLEEP

= 100 kHz.

Fig.5 Timing diagram and test conditions of 3-state output delay time.

1996 Feb 21 11

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

0.291

handbook, full pagewidth

A

(LSB)

0.178

0.065

−0.047

−0.160

−0.272

0 68 102 136 204 23834 170

TDA8790

MBE548

255

codes

0.150

handbook, full pagewidth

A

(LSB)

0.091

0.032

−0.025

−0.84

−0.143

0 68 102 136 204 23834 170

Fig.6 Typical integral non-linearity (INL) performance.

codes

MBE549

255

1996 Feb 21 12

Fig.7 Typical differential non-linearity (DNL) performance.

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

t

handbook, full pagewidth

code 255

code 0

CLK

MBE504

V

I

STLH

50 %

5 ns

50 %

2 ns

5 ns

t

STHL

50 %

50 %

TDA8790

2 ns

Fig.8 Analog input settling-time diagram.

0

A

(dB)

20

40

60

80

100

120

0 5.0 7.5 10.0 15.0 17.52.5 12.5

Effective bits: 7.32; THD = 51.08 dB.
Harmonic levels (dB): 2nd = −68.99; 3rd = −51.62; 4th = −66.05; 5th = −63.23; 6th = −72.79.

MBE550

20

f (MHz)

1996 Feb 21 13

Fig.9 Typical Fast Fourier Transform (f

= 40 MHz; fi= 4.43 MHz).

clk

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

MBE505

V

DDO

D7 to D0

V

SSO

ndbook, halfpage

V

DDA

V

SSA

TDA8790

V

I

MLC857

Fig.10 CMOS data outputs.

V

DDO

SLEEP



V

SSO

MBE506

handbook, halfpage

V

V

V

V

V

DDA

SSA

Fig.11 Analog inputs.

RT
RM
RB

R

LAD

MLC859

Fig.12 SLEEP 3-state input.

1996 Feb 21 14

Fig.13 VRB, VRM and VRT.

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

V

DDD

handbook, halfpage

CLK

V

SSD

Fig.14 CLK input.

1

/2V

MLC860

TDA8790

DDD

APPLICATION INFORMATION

CLK

1

SLEEP

2

V

DDD

3

V

SSD

4

V

DDA

5

I

TDA8790

6
7
8
9
10

V

SSA

(1)

V

RB

(1)

100

nF

V

RM

V

(1)

V

RT

V

SSA

supply through a resistor bridge and a decoupled capacitor.

DDA

100

nF

The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the

reference ladder voltages can be derived from a well regulated V
(1) VRB, VRM and VRT are decoupled to V

V

SSA

SSA

100

nF

V

SSA

.

20
19
18
17
16
15
14
13
12
11

MBE507

V

D7
D6
D5
D4
D3
D2
D1
D0

V

DDO

SSO

1996 Feb 21 15

Fig.15 Application diagram.

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

PACKAGE OUTLINE

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm

20

D

c

y

Z

11

E

H

TDA8790

SOT266-1

A

X

v M

E

A

pin 1 index

110

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

mm

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

1.5

0.1501.4

1.2

0.25

b

3

p

0.32

0.20

p

cD

0.20

6.6

0.13

6.4

0 2.5 5 mm

scale

(1)E(1)

eHELLpQZywv θ

4.5

0.65 1.0 0.2

4.3

6.6

6.2

Q

A

2

A

1

detail X

0.65

0.75

0.45

0.45

(A )

L

p

L

A

3

θ

0.13 0.1

0.48

0.18

(1)

o

10

o

0

OUTLINE

VERSION

SOT266-1

1996 Feb 21 16

REFERENCES

IEC JEDEC EIAJ

EUROPEAN

PROJECTION

ISSUE DATE

90-04-05
95-02-25

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering SSOP

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration:
45 minutes at 45 °C.

Wave soldering SSOP

Wave soldering isnot recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

TDA8790

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320 °C.

1996 Feb 21 17

Philips Semiconductors Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Feb 21 18