DATASHEETS tda8787 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8787

10-bit, 3.0 V analog-to-digital
interface for CCD cameras

Preliminary specification
Supersedes data of 1998 Mar 27
File under Integrated Circuits, IC02

1998 Oct 15

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

FEATURES

• Correlated Double Sampling (CDS), Automatic Gain
Control (AGC), 10-bit Analog-to-Digital Converter (ADC)
and reference regulator included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 18 MHz

• AGC gain range of 36 dB (in steps of 0.1 dB)

• Low power consumption of only 190 mW (typ.)

• Power consumption in standby mode of 4.5 mW (typ.)

• 3.0 V operation and 2.5 to 3.6 V operation for the digital

outputs

• Active control pulses polarity selectable via serial
interface

• 8-bit DAC included for analog settings

• TTL compatible inputs, CMOS compatible outputs.

QUICK REFERENCE DATA

APPLICATIONS

• Low-power, low-voltage CCD camera systems.

GENERAL DESCRIPTION

The TDA8787 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit ADC
together with its reference voltage regulator.

AGC gain is controlled via the serial interface.
The ADC input clamp level is controlled via the serial

interface.
An additional DAC is provided for additional system

controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.

TDA8787

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply voltage 2.5 2.6 3.6 V
analog supply current all clamps active − 55 70 mA
digital supply current − 811mA
digital outputs supply current f

= 18 MHz; CL=20pF;

pix

− 12mA

input ramp response time is 800 µs

ADC

res

V

i(CDS)(p-p)

f

pix(max)

f

pix(min)

DR

AGC

N

tot(rms)

ADC resolution − 10 − bits
maximum CDS input voltage

(peak-to-peak value)

VCC= 2.85 V 650 −−mV
V

≥ 3.0 V 800 −−mV

CC

maximum pixel rate 18 −−MHz
minimum pixel rate 5 −−MHz
AGC dynamic range − 36 − dB
total noise from CDS input to

AGC gain = 0 dB; see Fig.8 − 0.25 − LSB

ADC output

P

tot

total power consumption V

CCA=VCCD=VCCO

=3V − 190 − mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8787HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

1998 Oct 15 2

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1998 Oct 15 3

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BLOCK DIAGRAM

10-bit, 3.0 V analog-to-digital interface for

CCD cameras

Philips Semiconductors Preliminary specification

CPCDS1

CPCDS2

V

CCA3

AGND3

V

CCA1

AGND1

OFDOUT

SHP

47

7

8
42

41

CORRELATED

4

IN

6

5

9

DOUBLE

SAMPLING

OFD DAC

15

14 3

TEST2

TEST1 AGND4

V

CCD3

V

ref

DGND3

1

SHD

48

CDS CLOCK GENERATOR

CLAMP

16

TEST3

2

CLAMP

V

CCA2

18

AGND2

17

AGC

9-BIT

REGISTER

8-BIT

REGISTER

CLPDM

CLPOB

13

45

OAGC OAGCC

40

REGULATOR

OE

37

OUTPUT
BUFFER

20
19
39
38
26

36
35
34
33
32
31
30
29
28
27

25

44

MGM541

DGND1
V

CCD1
DGND2
V

CCD2
OGND

D9
D8

D7
D6
D5
D4
D3
D2
D1
D0

V

CCO

DCLPC

24

PBK

11

PRE-

BLANKING

10

STDBY

AGND5

12

43

COMPARATOR

SHIFTERSHIFT

TDA8787

46

SEN

DAC

23

SCLK

7-BIT

REGISTER

SERIAL

INTERFACE

22

SDATA

10-bit ADC

21

VSYNC

CLK

DATA

FLIP-

FLOP

Fig.1 Block diagram.

TDA8787

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

V

CCD3

DGND3 2 digital ground 3
AGND4 3 analog ground 4
IN 4 input signal from CCD
AGND1 5 analog ground 1
V

CCA1

CPCDS1 7 clamp storage capacitor pin 1
CPCDS2 8 clamp storage capacitor pin 2
OFDOUT 9 analog output of the additional 8-bit control DAC
STDBY 10 standby mode control input (LOW: TDA8787 active; HIGH: TDA8787 standby)
PBK 11 pre-blanking control input
CLPDM 12 clamp pulse input at dummy pixel
CLPOB 13 clamp pulse input at optical black
TEST1 14 test pin input 1 (should be connected to AGND2)
TEST2 15 test pin input 2 (should be connected to AGND1)
TEST3 16 test pin input 3 (should be connected to AGND2)
AGND2 17 analog ground 2
V

CCA2

V

CCD1

DGND1 20 digital ground 1
SDATA 21 serial data input for serial interface control
SCLK 22 serial clock input for serial interface
SEN 23 strobe pin for serial interface
VSYNC 24 vertical sync pulse input
V

CCO

OGND 26 digital output ground
D0 27 ADC digital output 0 (LSB)
D1 28 ADC digital output 1
D2 29 ADC digital output 2
D3 30 ADC digital output 3
D4 31 ADC digital output 4
D5 32 ADC digital output 5
D6 33 ADC digital output 6
D7 34 ADC digital output 7
D8 35 ADC digital output 8
D9 36 ADC digital output 9 (MSB)
OE 37 output enable control input (LOW: outputs active; HIGH: outputs in high impedance)
V

CCD2

DGND2 39 digital ground 2
CLK 40 data clock input

1 digital supply voltage 3

6 analog supply voltage 1

18 analog supply voltage 2
19 digital supply voltage 1

25 output supply voltage

38 digital supply 2

1998 Oct 15 4

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

SYMBOL PIN DESCRIPTION

AGND3 41 analog ground 3
V

CCA3

AGND5 43 analog ground 5
DCLPC 44 regulator decoupling pin
OAGC 45 AGC output (test pin)
OAGCC 46 AGC complementary output (test pin)
SHP 47 preset sample-and-hold pulse input
SHD 48 data sample-and-hold pulse input

42 analog supply 3

SHD

SHP

48

47

OAGC

OAGCC
46

45

DCLPC

AGND5

44

43

CCA3

V

42

AGND3

CLK

41

40

CCD2

DGND2

V

39

38

TDA8787

OE

37

V

CCD3
DGND3
AGND4

AGND1

V

CCA1

CPCDS1
CPCDS2

OFDOUT

STDBY

PBK

CLPDM

24

VSYNC

36
35
34
33
32
31
30
29
28
27
26
25

MGM542

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND

V

CCO

1
2
3
4

IN

5
6
7
8

9
10
11
12

13

14

15

TEST2

TEST1

CLPOB

16

17

TEST3

AGND2

TDA8787

18

19

CCA2

V

V

CCD1

20

21

SDATA

DGND1

22

SCLK

23

SEN

Fig.2 Pin configuration.

1998 Oct 15 5

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

CC

V

i

I

o

T

stg

T

amb

T

j

Note

1. The supply voltages V
voltage difference ∆VCC remains as indicated.

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

between V
between V
between V

CCA
CCA
CCD

and V
and V
and V

CCD
CCO
CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V
data output current −±10 mA
storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − 150 °C

, V

CCA

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

1998 Oct 15 6

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

CHARACTERISTICS

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Digital inputs

I

NPUTS: SHP, SHD, STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE AND PBK

V

IL

V

IH

I

i

Clamps

= 3.0 V; V

CCO

= 2.6 V; f

= 18 MHz; T

pix

=25°C; unless otherwise specified.

amb

analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply

2.5 2.6 3.6 V

voltage
analog supply current all clamps active − 55 70 mA
digital supply current − 811mA
digital outputs supply

current

CL= 20 pF on all data
outputs; input ramp

− 12mA

frequency

LOW-level input voltage 0 − 0.6 V
HIGH-level input voltage 2.2 − V
input current 0 ≤ Vi≤ V

CCD

−2 − +2 µA

CCD

V

G

LOBAL CHARACTERISTICS OF THE CLAMP LOOPS

t

W(clamp)

clamp active pulse width

in number of pixels
INPUT CLAMP (DRIVEN BY CLPDM)
g

m(CDS)

CDS input clamp

transconductance
OPTICAL BLACK CLAMP (DRIVEN BY CLPOB)
G

shift

gain from CPCDS1 and 2

to AGC inputs
I

LSB(cp)

charge pump current for

±1 LSB error at ADC

output
I

push(cp)

available push current of

the charge pump
I

pull(cp)

available pull current of

the charge pump

AGC code = 383 for

18 −−pixels

maximum 4 LSB error

1.5 2.7 3.5 mS

− 0.27 −−

AGC code = 0 −±350 −µA
AGC code = 383 −±10 −µA

− 650 −µA

−−650 −µA

1998 Oct 15 7

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Correlated Double Sampling (CDS)

V

i(CDS)(p-p)

maximum peak-to-peak

CDS input amplitude

(video signal)
V

reset(max)

maximum CDS input reset

pulse amplitude
I

i(IN)

input current into pin IN

(pin 4)
t

CDS(min)

CDS control pulses

minimum active time
t

h(IN-SHP)

CDS input hold time

(pin IN) compared to

control pulse SHP
t

h(IN-SHD)

CDS input hold time

(pin IN) compared to

control pulse SHD

Amplifier

DR
∆G

AGC
AGC

AGC dynamic range − 36 − dB

maximum AGC gain step −0.3 − +0.3 dB

Analog-to-Digital Converter (ADC)

LE
LE

i
d

integral linearity error f

differential linearity error f

Total chain characteristics (CDS + AGC + ADC)

f

pix(max)

t

CLKH

t

CLKL

t

d(SHD-CLK)

maximum pixel frequency 18 −−MHz

CLK pulse width HIGH 15 −−ns

CLK pulse width LOW 15 −−ns

time delay between

SHD and CLK
t

su(PBK-CLK)

set-up time of PBK

compared to CLK
V

i(IN)

video input dynamic signal

for ADC full-scale output
N

tot(rms)

total output noise (RMS

value)

O

CCD(max)

maximum offset between

CCD floating level and

CCD dark pixel level
V

n(i)(eq)(rms)

equivalent input noise

voltage (RMS value)

VCC= 2.85 V 650 −−mV
V

≥ 3.0 V 800 −−mV

CC

500 −−mV

at floating gate level −1 − +1 µA

video input = V

i(CDS)(p-p)

;

11 15 − ns

2 LSB error at ADC output
V

CCA=VCCD

T

=25°C; see Fig.9

amb

V

CCA=VCCD

T

=25°C; see Fig.9

amb

= 18 MHz; ramp input −±1.3 ±2.5 LSB

pix

= 18 MHz; ramp input −±0.5 ±0.9 LSB

pix

=30V;

=30V;

35 7ns

35 7ns

see Fig.9 10 −−ns

10 −−ns

AGC code = 00 800 −−mV
AGC code = 383 12.7 −−mV
see Fig.8

AGC gain=0dB − 0.25 − LSB
AGC gain=9dB − 0.8 − LSB

−70 − +70 mV

− 110 −µV

1998 Oct 15 8

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital-to-analog converter (OFDOUT DAC)

V

OFDOUT(p-p)

additional 8-bit control

DAC (OFD) output voltage

(peak-to-peak value)
V

OFDOUT(0)

DC output voltage for

code 0
V

OFDOUT(255)

DC output voltage for

code 255
TC

DAC

DAC output range

temperature coefficient
Z

OFDOUT

I

OFDOUT

DAC output impedance − 2000 −Ω

OFD output current drive static −− 100 µA

Digital outputs (f

V
V
I

OH
OL

OZ

HIGH-level output voltage IOH= −1mA V

LOW-level output voltage IOL= 1 mA 0 − 0.5 V

output current in 3-state

mode
t
t

C

h(o)
d(o)

L

output hold time see Fig.9 11 −−ns

output delay time CL= 22 pF; V

output load capacitance −− 22 pF

Serial interface

f

SCLK(max)

maximum frequency of

serial interface

= 18 MHz; CL=22pF)

pix

Ri=1MΩ−1.0 − V

− AGND − V

− AGND + 1.0 − V

− 250 − ppm/°C

− 0.5 − V

0.5V<Vo<V

C

= 22 pF; V

L

CCO

CCO

= 3.0 V − 28 tbf ns

CCO

= 2.7 V − 27 tbf ns

CCO

−20 − +20 µA

CCO

5 −−MHz

V

1998 Oct 15 9

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

handbook, full pagewidth

IN

SHP

SHD

CLK

0.6 V

t

h(IN-SHP)

N

0.6 V

t

h(IN-SHD)

2.2 V

N + 1N + 2N + 3

t

CDS(min)

t

CLKH

0.6 V

t

CDS(min)

0.6 V

TDA8787

2.2 V

2.2 V

0.6 V

SDATA

PBK

t

d(SHD-CLK)

t

h(o)

N − 1

t

d(o)

2.2 V

0.6 V

t

su(PBK-CLK)

50%

Fig.3 Pixel frequency timing diagram; all polarities active HIGH.

N

MGM764

1998 Oct 15 10

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

handbook, full pagewidth

IN

SHP

SHD

CLK

2.2 V

t

h(IN-SHP)

N

2.2 V

t

h(IN-SHD)

t

CLKL

0.6 V

N + 1N + 2N + 3

t

CDS(min)

2.2 V 2.2 V

2.2 V

t

CDS(min)

0.6 V

t

d(SHD-CLK)

TDA8787

0.6 V

handbook, full pagewidth

SDATA

PBK

t

N − 1

h(o)

t

d(o)

2.2 V

0.6 V

t

su(PBK-CLK)

50%

Fig.4 Pixel frequency timing diagram; all polarities active LOW.

MGM543

1.0

OFDOUT DAC

voltage

output

(V)

0

0

OFDOUT control DAC input code

255

N

FCE088

Fig.5 DAC voltage output as a function of DAC input code.

1998 Oct 15 11

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

(1)

handbook, full pagewidth

AGCOUT

CLPOB
(active HIGH)

CLPDM
(active HIGH)

PBK
(active HIGH)

VIDEO OPTICAL BLACK

4 pixels

CLPOB

WINDOW

HORIZONTAL FLYBACK DUMMY VIDEO

(2)

PBK window

4 pixels

CLPDM

WINDOW

TDA8787

(1)

MGM544

(1) In case the number of clamp pixels is limited to 18t
(2) When dummy pixels are not available.

Fig.6 Line frequency timing diagram.

42

handbook, halfpage

AGC

gain

36

(dB)

30

24

18

12

6

0

−6
0 64 192 320

; otherwise this timing interval can be smaller.

W(clamp)

128

256 384

AGC input code

FCE057

Fig.7 AGC gain as a function of AGC input code.

1998 Oct 15 12

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

10

handbook, halfpage

N

tot(rms)

(LSB)

8

6

4

2

0

Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account as no signal is inputted.

640 192 320128

256 383

AGC code

FCE098

Fig.8 Total noise performance as a function of AGC gain.

1998 Oct 15 13

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

handbook, full pagewidth

SDATA

SCLK

SEN

OFDOUT DAC

LATCHES

8-bit DAC

D0

D1 D2 D3 D4 D510D6

LSB MSB

8 9 7 6

AGC GAIN

LATCHES

AGC control ADC clamp

ADC CLAMP

LATCHES

control

SHIFT REGISTER

D7 D8 D9 A0 A1

CONTROL PULSE

POLARITY

LATCHES

control pulses

polarity settings

TDA8787

LATCH

SELECTION

MGM546

handbook, full pagewidth

SDATA

SCLK

SEN

Fig.9 Serial interface block diagram.

t

su2

t

MSB LSB

A1 A0 D9 D7 D6 D5 D4 D3

t

su1

D8

hd4

D2 D1 D0

t

hd3

t

su3

MGM547

t

su1=tsu2=tsu3

= 10 ns (min.); t

hd3=thd4

= 10 ns (min.).

Fig.10 Loading sequence of control input data via the serial interface.

1998 Oct 15 14

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

Table 1 Serial interface programming

ADDRESS BITS

A1 A0

0 0 AGC gain control (D8 to D0); bit D9 should be set to logic 0
0 1 DAC OFDOUT output control (D7 to D0); bits D8 and D9 should be set to logic 0
1 0 ADC clamp reference control (D6 to D0); bits D7, D8 and D9 should be set to logic 0
1 1 control pulses (pins SHP, SHD, CLPDM, CLPOB, PBK and CLK) polarity settings

Table 2 Polarity settings

SYMBOL PIN SERIAL CONTROL BIT

SHP and SHD 47 and 48 D0 1 = HIGH; 0 = LOW
CLK 40 D1 1 = rising; 0 = falling
CLPDM 12 D2 1 = HIGH; 0 = LOW
CLPOB 13 D3 1 = HIGH; 0 = LOW
PBK 11 D5 1 = HIGH; 0 = LOW
VSYNC 24 D6 0 = rising; 1 = falling

DATA BITS D9 TO D0

(1)

ACTIVE EDGE OR LEVEL

Note

1. Bit D4 is not used.

Table 3 Standby selection

STDBY ADC DIGITAL OUTPUTS D9 TO D0 I

1 logic state LOW 1 mA
0 active 64 mA

CCA+ICCO+ICCD

(TYP.)

1998 Oct 15 15

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

APPLICATION DIAGRAM

handbook, full pagewidth

(2) (2)

(2)

CCD

1 µF

V

CCD

V

CCA

1 µF

1 µF

1 µF

100

nF

V

CCD3
DGND3
AGND4

AGND1

V

CCA1
CPCDS1
CPCDS2
OFDOUT

STDBY

PBK

CLPDM

SHD

48 47 46 45 44 43 42 41 40 39 38 37
1
2
3

IN

4
5
6
7
8
9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

SHP

OAGC

OAGCC

V

CCA

100

1 µF

CCA3

V

DCLPC

AGND5

TDA8787HL

nF

AGND3

CLK

V

CCD

CCD2

DGND2

V

100

nF

OE

TDA8787

V

CCD

D9

36

D8

35

D7

34

D6

33

D5

32

D4

31

D3

30

D2

29

D1

28

D0

27

OGND

26

V

CCO

25

100

nF

V

CCD

TEST3

CCA2

V

AGND2

100

nF

TEST1

TEST2

V

CCD

(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals t

CLPOB

V

CCA

Fig.11 Application diagram.

1998 Oct 15 16

CCD1

V

h(IN-SHP)

SDATA

DGND1

100

nF

and t

SCLK

serial

interface

V

CCD

h(IN-SHD)

SEN

VSYNC

(1)

MGM548

(see Chapter “Characteristics”).

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

TDA8787

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3b

max.

0.20

1.60

0.05

1.45

1.35

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

p

0.27

0.17

12

Z

D

(1) (1)(1)

cE

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

7.1

6.9

0.5

9.15

8.85

D

E

A

B

9.15

8.85

H

E

LL

E

0.75

0.45

A

p

A

2

A

1

L

detail X

Z

D

0.12 0.10.21.0

0.95

0.55

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OUTLINE
VERSION

SOT313-2

IEC JEDEC EIAJ

REFERENCES

1998 Oct 15 17

EUROPEAN

PROJECTION

ISSUE DATE

94-12-19
97-08-01

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for
CCD cameras

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering

TDA8787

If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

•The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Oct 15 18

Philips Semiconductors Preliminary specification

10-bit, 3.0 V analog-to-digital interface for

TDA8787

CCD cameras

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Oct 15 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/750/02/pp20 Date of release: 1998 Oct 15 Document order number: 9397 75004259