INTEGRATED CIRCUITS
DATA SH EET
TDA8376; TDA8376A
2
I
C-bus controlled PAL/NTSC TV
processors
Objective specification
File under Integrated Circuits, IC02
1996 Jan 26
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Video switches
7.2 Integrated video filters, peaking and black
stretcher
7.3 Synchronization circuit
7.4 Colour decoder
7.5 RGB output circuit and black-current
stabilization
8I
8.1 Start-up procedure
8.2 Inputs
8.2.1 Input control bits
8.2.2 Output control bits
9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 QUALITY SPECIFICATION
11.1 Latch-up
12 CHARACTERISTICS
13 TEST AND APPLICATION INFORMATION
13.1 East-West output stage
13.2 Adjustment of geometry control parameters
14 PACKAGE OUTLINES
15 SOLDERING
15.1 Introduction
15.2 SDIP
15.2.1 Soldering by dipping or by wave
15.2.2 Repairing soldered joints
15.3 QFP
15.3.1 Reflow soldering
15.3.2 Wave soldering
15.3.3 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS
2
C-BUS SPECIFICATION
TDA8376; TDA8376A
1996 Jan 26 2
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
1 FEATURES
• Source selection with 2 CVBS inputs and a Y/C (or extra
CVBS) input
• Output signals of the video switch circuit for the teletext
decoder and a Picture-In-Picture (PIP) processor
• Video identification circuit which is independent of the
synchronization for stable On Screen Display (OSD)
under ‘no-signal’ conditions
• Integrated chrominance trap with pre-shoot
compensation and bandpass filters (automatically
calibrated)
• Integrated luminance delay line
• Asymmetrical peaking in the luminance channel with a
(defeatable) noise coring function
• Black stretcher circuit in the luminance channel
• PAL/NTSC colour decoder with automatic search
system
• Easy interfacing with the TDA8395 (SECAM decoder)
for multistandard applications
• RGB control circuit with black-current stabilization and
white point adjustment; to obtain a good grey scale
tracking the black-current ratio of the 3 guns depends on
the white point adjustment
• Two linear RGB inputs and fast blanking
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
• Vertical count-down circuit
• Geometry correction by modulation of the vertical and
E-W drive
• Vertical and horizontal zoom possibility for 16 : 9
applications (TDA8376A only)
2
C-bus control of various functions
• I
• Low dissipation (700 mW)
• Small amount of peripheral components compared with
competition ICs
• Y, U and V inputs and outputs.
2 GENERAL DESCRIPTION
The TDA8376 and TDA8376A are alignment-free I
controlled video processors which contain a PAL/NTSC
colour decoder, luminance processor, sync processor,
RGB-control and deflection processor. The circuits have
been designed for use with the baseband chrominance
delay line TDA4665 and for DC-coupled vertical and
East-West (E-W) output stages. Both ICs are pin
compatible. The TDA8376A has a flexible horizontal and
vertical zoom possibility for 16 : 9 applications.
The supply voltage for the ICs is 8 V. The ICs are available
in an SDIP package with 52 pins and in a QFP package
with 64 pins (see Chapter 4).
The pin numbers indicated in this document are
referenced to the SDIP52; SOT247-1 package; unless
otherwise indicated.
TDA8376; TDA8376A
2
C-bus
1996 Jan 26 3
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
3 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Supply
V
P
I
P
supply voltage − 8.0 − V
supply current − 75 − mA
Input voltages
V
9,13(p-p)
V
27(p-p)
V
6(p-p)
CVBS input voltage (peak-to-peak value) − 1.0 − V
S-VHS luminance input voltage (peak-to-peak value) − 1.0 − V
S-VHS chrominance input voltage (burst amplitude) (peak-to-peak
− 0.3 − V
value)
V
i(p-p)
RGB input voltage (peak-to-peak value) − 0.7 − V
Output voltages
V
38(p-p)
V
11(p-p)
V
30(p-p)
V
29(p-p)
V
19,20,21(p-p)
TXT output voltage (peak-to-peak value) − 1.0 − V
PIP output voltage (peak-to-peak value) − 1.0 − V
−(R−Y) output voltage (peak-to-peak value) − 525 − mV
−(B−Y) output voltage (peak-to-peak value) − 675 − mV
RGB output signal voltage amplitudes (peak-to-peak value) − 2.0 − V
Output currents
I
40
I
47,48
I
46
horizontal output current 10 −−mA
vertical output current 1 −−mA
E-W drive output current 0.5 −−mA
4 ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
TDA8376 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
TDA8376AH QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);
SOT319-2
body 14 × 20 × 2.8 mm
1996 Jan 26 4
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
5 BLOCK DIAGRAM
ref
VSC
I
(n)
(p)
VDR
VDR
FBI
dbook, full pagewidth
SCO
PH2LF
HOUT
DIG
DEC
BG
DEC
EWD
46
EW
GEOMETRY
OUTPUT
HORIZONTAL
2nd LOOP AND
51837 43 41 39 40
AND
VCO
CONTROL
EHTO
47
49
HORIZONTAL/
ref
SYNC
51250
48
VERTICAL
GEOMETRY
DIVIDER
VERTICAL
SEPARATOR
AND 1st LOOP
BLKIN
BLK
C
18
BLACK
CURRENT
WHITE
BLACK
STRETCHER
SYNC
VERTICAL
SEPARATOR
ROGOBO
BCLIN
22
212019
STABILIZER
BRI CONTR
POINT
ref
RGB MATRIX
DELAY,
AND
PEAKING AND
FILTER
OUTPUT
CORING
TUNING
RGBIN2
141516
RGB INPUT
SAT
G-Y MATRIX
BI2
RI2
GI2
17
AND
SWITCH
AND
SAT CONTROL
PAL/NTSC
DECODER
TDA8376; TDA8376A
MGE078
RGBIN1
RI1 GI1 BI1
LUMIN
LUMOUT
TDA4665
30 29 32 31 28 27 23 24 25 26
RYO BYO BYIRYI
3.6
MHz
4.4
MHz
DET
35 34 33
XTAL2 XTAL1
PH1LF
SDA
(+8 V)
P2
V
SCL
(+8 V)
P1
V
C-BUS
2
I
34 44
TRANSCEIVER
2 x 4 bits
16 x 6 bits
CONTROL DACs
VIDEO
IDENTIFICATION
TDA8376(A)
1996 Jan 26 5
BAND PASSTRAP
SW
HUE
SW
CVBS
FT
DEC
6 7 11 38 12 36
S-VHS SWITCH
913
SWITCH
GND3
454210
GND2
GND1
CVBS/TXT
PIPO
CHROMA
EXT
CVBS
INT
CVBS
ref
SEC
Fig.1 Block diagram (SDIP52; SOT247-1).
CVBS/Y
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
6 PINNING
SYMBOL
SDIP52 QFP64
DEC
DIG
C
BLK
SCL 3 13 I
SDA 4 14 I
DEC
BG
CHROMA 6 17 chrominance input (S-VHS)
CVBS/Y 7 18 external CVBS/Y input
V
P1
CVBS
INT
GND1 10 23 ground 1
PIPO 11 25 picture-in-picture output
DEC
CVBS
FT
EXT
12 26 decoupling filter tuning
13 27 external CVBS input
RGBIN2 14 28 RGB insertion input 2
RI2 15 29 red input 2
GI2 16 30 green input 2
BI2 17 31 blue input 2
BLKIN 18 32 black-current input
BO 19 34 blue output
GO 20 35 green output
RO 21 36 red output
BCLIN 22 37 beam current limiter input
RI1 23 38 red input 1
GI1 24 39 green input 1
BI1 25 40 blue input 1
RGBIN1 26 41 RGB insertion input 1
LUMIN 27 42 luminance input
LUMOUT 28 43 luminance output
BYO 29 44 −(B−Y) signal output
RYO 30 45 −(R−Y) signal output
BYI 31 46 −(B−Y) signal input
RYI 32 47 −(R−Y) signal input
XTAL1 33 49 3.58 MHz crystal connection
XTAL2 34 51 4.43/3.58 MHz crystal connection
DET 35 53 loop filter phase detector
SEC
V
P2
ref
36 54 SECAM reference output
37 55 horizontal oscillator supply voltage (+8 V)
CVBS/TXT 38 56 CVBS/TXT output
PIN
1 11 decoupling digital supply
2 12 black peak hold capacitor
2
C-bus serial clock input
2
C-bus serial data input/output
5 16 band gap decoupling
8 20 main supply voltage (+8 V)
9 22 internal CVBS input
DESCRIPTION
TDA8376; TDA8376A
1996 Jan 26 6
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
SYMBOL
SCO 39 57 sandcastle output
HOUT 40 58 horizontal output
FBI 41 59 flyback input
GND2 42 24 ground 2
PH2LF 43 62 phase-2 filter
PH1LF 44 63 phase-1 filter
GND3 45 60 ground 3
EWD 46 1 east-west drive output
VDR
(p)
VDR
(n)
EHTO 49 5 EHT/overvoltage protection input
VSC 50 7 vertical sawtooth capacitor
I
ref
n.c. 52 2 not connected
n.c. − 6 not connected
n.c. − 9 not connected
n.c. − 10 not connected
n.c. − 15 not connected
n.c. − 19 not connected
n.c. − 33 not connected
n.c. − 48 not connected
n.c. − 50 not connected
n.c. − 52 not connected
V
P3
GND4 − 61 ground 4
GND5 − 64 ground 5
SDIP52 QFP64
47 3 vertical drive 1 positive output
48 4 vertical drive 2 negative output
51 8 reference current input
PIN
DESCRIPTION
− 21 supply voltage 3 (+8 V)
TDA8376; TDA8376A
1996 Jan 26 7
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
handbook, halfpage
CHROMA
CVBS
DEC
C
DEC
CVBS/Y
CVBS
GND1
PIPO
DEC
RGBIN2
BLKIN
BCLIN
RGBIN1
DIG
BLK
SCL
SDA
BG
V
P1
INT
FT
EXT
RI2
GI2
BI2
BO
GO
RO
RI1
GI1
BI1
1
2
3
4
5
6
7
8
9
10
11
12
13
TDA8376(A)
14
15
16
17
18
19
20
21
22
23
24
25
26
MGE076
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
n.c.
I
ref
VSC
EHTO
VDR
(n)
VDR
(p)
EWD
GND3
PH1LF
PH2LF
GND2
FBI
HOUT
SCO
CVBS/TXT
V
P2
SEC
ref
DET
XTAL2
XTAL1
RYI
BYI
RYO
BYO
LUMOUT
LUMIN
TDA8376; TDA8376A
Fig.2 Pin configuration (SDIP52).
1996 Jan 26 8
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
handbook, full pagewidth
PH1LF
EWD
n.c.
VDR
(p)
VDR
(n)
EHTO
n.c.
VSC
I
n.c.
n.c.
DEC
DIG
C
BLK
SCL
SDA
n.c.
DEC
BG
CHROMA
CVBS/Y
n.c.
ref
PH2LF
GND5
64
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GND4
GND3
62
61
60
HOUT
FBI
59
58
TDA8376(A)
SCO
57
P2
CVBS/TXT
V
56
55
TDA8376; TDA8376A
ref
DET
53
n.c.
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XTAL2
n.c.
XTAL1
n.c.
RYI
BYI
RYO
BYO
LUMOUT
LUMIN
RGBIN1
BI1
GI1
RI1
BCLIN
RO
GO
BO
n.c.
SEC
54
1996 Jan 26 9
20
21
22
23
24
25
26
P3
P1
V
INT
V
CVBS
GND1
GND2
PIPO
FT
DEC
Fig.3 Pin configuration (QFP64).
27
EXT
CVBS
28
29
RI2
RGBIN2
30
GI2
31
BI2
32
BLKIN
MGE077
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
7 FUNCTIONAL DESCRIPTION
7.1 Video switches
The circuit has two CVBS inputs and a Super-Video Home
System (S-VHS) input. The input can be chosen by the
2
I
C-bus. The input selector also has a position in which
CVBS
S-VHS input. When the input selector is in this position it
switches to the S-VHS input if the S-VHS detector detects
sync pulses on the S-VHS luminance input. The S-VHS
detector output can be read by the I2C-bus. When the
S-VHS option is not used the luminance input can be used
as a second input for external CVBS signals. The choice is
made via the CVS bit (see Table 1).
The video switch circuit has two outputs which can be
programmed in a different way. The input signal for the
decoder is also available on the TXT output. Therefore this
signal can be used to drive the teletext decoder and the
SECAM add-on decoder. The signal on the PIP output can
be chosen independent of the TXT output. If S-VHS is
selected for one of the outputs the luminance and
chrominance signals are added so that a CVBS signal is
obtained again.
The circuit contains a video identification circuit which
checks whether a video signal is available at the selected
video input. This circuit is independent of the
synchronization circuit. The information of this
identification circuit can also be used to switch the
phase-1 (ϕ1) loop to a low gain when no signal is received
so that a stable OSD display is obtained. The video
identification circuit can be switched on and off via the
I2C-bus.
7.2 Integrated video filters, peaking and black
The circuit contains a chrominance bandpass and trap
circuit. The chrominance trap filter in the luminance path is
designed for a symmetrical step response behaviour. The
filters are realized by gyrator circuits and they are
automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. The luminance
delay line and the delay for the peaking circuit are also
realized by gyrator circuits. During SECAM reception the
centre frequency of the chrominance trap is set to a value
of approximately 4.2 MHz to obtain a better suppression of
the SECAM carrier frequencies.
The peaking function is achieved by two luminance delay
cells each with a delay of 165 ns. The resulting peaking
frequency is 3 MHz. The peaking is asymmetrical so that
the overshoots in the direction of ‘black’ are approximately
two times higher than those in the direction of ‘white’.
is processed, unless there is a signal on the
EXT
stretcher
This provides a better picture impression than a
symmetrical peaking. The circuit contains a coring circuit
to prevent the noise content of the video signal being
amplified by the peaking circuit. This coring circuit can be
switched-off when required.
It is possible to connect a Colour Transient Improvement
(CTI) or Picture Signal Improvement (PSI) IC to the
TDA8376. The luminance signal which has passed the
filter and delay line circuit is available externally. The
output signal of the transient improvement circuit must be
applied to the luminance input circuit. When the CTI
function is not required the two pins must be AC-coupled.
The luminance signal below 50 IRE can be stretched in
accordance with the difference between the peak black
level and the blanking level of the back-porch of the video
signal. The black level stretcher can be switched-off by
connecting pin 2 to the positive supply line.
7.3 Synchronization circuit
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude.
The separated sync pulses are fed to the first phase
detector and to the coincidence detector. This coincidence
detector is only used to detect whether the line oscillator is
synchronized and not for transmitter identification. The first
Phase-Locked Loop (PLL) has a very high-statical
steepness so that the phase of the picture is independent
of the line frequency. To prevent the horizontal
synchronization being disturbed by anti-copy signals such
as Macrovision the phase detector is gated during the
vertical retrace period so that pulses during scan have no
effect on the output voltage. The position of this pulse is
asymmetrical and the width is approximately 22 µs.
The horizontal output signal is generated by an oscillator
which operates at twice the line frequency. Its frequency is
divided-by-two to lock the first control loop to the incoming
signal. The time-constant of the loop can be forced by the
2
I
time-constant depending on the noise content of the
incoming video signal. The free-running frequency of the
oscillator is determined by a digital control circuit which is
locked to the reference signal of the colour decoder. When
the IC is switched on the horizontal output signal is
suppressed and the oscillator is calibrated as soon as all
subaddress bytes have been sent. When the frequency of
the oscillator is correct the horizontal drive signal is
switched on.
TDA8376; TDA8376A
C-bus (fast or slow). If required the IC can select the
1996 Jan 26 10
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
To obtain a smooth switching-on and switching-off
behaviour of the horizontal output stage the horizontal
output frequency is doubled during switch-on and
switch-off (slow start/stop). During that time the duty factor
of the output pulse has such a value that maximum safety
is obtained for the output stage
To protect the horizontal output transistor the horizontal
drive is switched off when a power-on reset is detected.
The drive signal is switched on again when the normal
switch-on procedure is followed, i.e. all sub-address bytes
must be sent and, after calibration, the horizontal drive
signal will be released again via the slow start procedure.
When the coincidence detector indicates an out-of-lock
situation the calibration procedure is repeated.
The circuit has a second control loop to generate the drive
pulses for the horizontal driver stage. To prevent the
horizontal output transistor being switched on during
flyback the horizontal drive output is gated with the flyback
pulse.
The vertical sawtooth generator drives the vertical output
and E-W correction drive circuits. The geometry
processing circuits provide control of horizontal shift, E-W
width, E-W parabola/width ratio, E-W corner/parabola
ratio, trapezium correction, vertical shift, vertical slope,
vertical amplitude, and the S-correction. All these controls
can be set via the I2C-bus. The geometry processor has a
differential current output for the vertical drive signal and a
single-ended output for the E-W drive. Both the vertical
drive and the E-W drive outputs can be modulated for EHT
compensation. The EHT compensation pin is also used for
overvoltage protection.
The TDA8376A geometry processor also offers the
possibility for a flexible vertical and horizontal zoom mode
for 16 : 9 applications. Because of this feature an
additional control can be added on the remote control so
that the viewer can adjust the picture.
In addition the de-interlace of the vertical output can be set
via the I2C-bus.
To avoid damage of the picture tube when the vertical
deflection fails, the guard output current of the TDA8350
can be supplied to the sandcastle output. When a failure is
detected the RGB-outputs are blanked and a bit is set
(NDF) in the status byte of the I2C-bus. When no vertical
deflection output stage is connected this guard circuit will
also blank the output signals. This can be overruled by the
EVG bit of subaddress 0A (see Table 1).
7.4 Colour decoder
The colour decoder contains an alignment-free crystal
oscillator, a killer circuit and the colour difference
demodulators. The 90° phase shift for the reference signal
is made internally. The demodulation angle and gain ratio
for the colour difference signals for PAL and NTSC are
adapted to the standard.
The colour decoder is very flexible. Together with the
SECAM decoder TDA8395 an automatic multistandard
decoder can be designed. In the automatic mode the
SECAM identification is accepted only when the vertical
frequency is 50 Hz. In the forced mode the system can
also identify signals with a vertical frequency of 60 Hz.
Which standard the IC can decode depends on the
external crystals. If a 4.4 MHz and a 3.5 MHz crystal are
used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be
decoded. If two 3.5 MHz crystals are used PAL N and M
can be decoded. If one crystal is connected only
PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The
crystal frequency of the decoder is used to tune the line
oscillator. Therefore the value of the crystal frequency
must be given to the IC via the I
calibration of the horizontal oscillator it is very important
that the crystal indication bits (XA and XB) are not
corrupted (see Table 6). For this reason the crystal bits
(SXA and SXB) can be read in the output bytes so that the
software can check the I2C-bus transmissions
(see Table 38).
7.5 RGB output circuit and black-current
The colour-difference signals are matrixed with the
luminance signal to obtain the RGB-signals. For the
RGB-inputs linear amplifiers have been chosen so that the
circuit is suited for signals coming from the SCART
connector. The RGB2 inputs (pins 14 to 17) have priority
over the RGB1 inputs (pins 23 to 26). Both fast blanking
inputs can be blocked by I
and brightness controls operate on internal and external
signals.
stabilization
TDA8376; TDA8376A
2
C-bus. For a reliable
2
C-bus controls. The contrast
1996 Jan 26 11
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
The output signal has an amplitude of approximately 2 V
black-to-white at nominal input signals and nominal
settings of the controls.
The black current stabilization is realized by feedback from
the video output amplifiers to the RGB control circuit. The
‘black current’ of the 3 guns of the picture tube is internally
measured and stabilized. The black level control is active
during 4 lines at the end of the vertical blanking. During the
first line the leakage current is measured and the following
3 lines the 3 guns are adjusted to the required level. The
maximum acceptable leakage current is ±100 µA.
The nominal value of the ‘black current’ is 10 µA. The ratio
of the currents for the various guns automatically tracks
with the white point adjustment so that the background
colour is the same as the adjusted white point.
The input impedance of the ‘black-current’ measuring pin
is 15 kΩ. Therefore the beam current during scan will
cause the input voltage to exceed the supply voltage. The
internal protection will start conducting so that the
excessive current is bypassed.
When the TV receiver is switched on the black current
stabilization circuit is not active, the RGB outputs are
blanked and beam current limiting input pin is
short-circuited. Only during the measuring lines will the
outputs supply a voltage of 5 V to the video output stage
so that it can be detected if the picture tube is warming up.
These pulses are switched on after a waiting time of
approximately 0.5 s. This ensures that the vertical
deflection is activated so that the measuring pulses are not
visible on the screen. As soon as the current supplied to
the measuring input exceeds a value of 190 µA the
stabilization circuit is activated. After a waiting time of
approximately 0.8 s the blanking and the beam current
limiting input pin are released. The remaining switch-on
behaviour of the picture is determined by the external time
constant of the beam current limiting network.
8I
handbook, halfpage
Valid subaddresses: 00 to 13 (TDA8376) or 00 to 16
(TDA8376A); subaddress FE is reserved for test
purposes. Auto-increment mode is available for
subaddresses.
8.1 Start-up procedure
Read the status bytes until POR = 0 and send all
subaddress bytes. The horizontal output signal is switched
on when the oscillator is calibrated.
Each time before the data in the IC is refreshed, the status
bytes must be read. If POR = 1, the procedure previously
mentioned must be carried out to restart the IC.
When this procedure is not followed the horizontal
frequency may be incorrect after power-up or after a
power dip.
TDA8376; TDA8376A
2
C-BUS SPECIFICATION
A6 A5 A4 A3 A2 A1 A0
10001011/0
Fig.4 Slave address (8A).
R/W
MLA743
1996 Jan 26 12
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
8.2 Inputs
Table 1 Input status bits
FUNCTION
Source select 00 INA INB INC IND FOA FOB XA XB
Decoder mode 01 FORF FORS DL STB POC CM2 CM1 CM0
Hue 02 0 0 A5 A4 A3 A2 A1 A0
Horizontal shift (HS) 03 0 0 A5 A4 A3 A2 A1 A0
E-W width (E-W) 04 0 0 A5 A4 A3 A2 A1 A0
E-W parabola/width (PW) 05 0 0 A5 A4 A3 A2 A1 A0
E-W corner parabola (CP) 06 0 0 A5 A4 A3 A2 A1 A0
E-W trapezium (TC) 07 0 0 A5 A4 A3 A2 A1 A0
Vertical slope (VS) 08 NCIN 0 A5 A4 A3 A2 A1 A0
Vertical amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0
S-correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0
Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0
White point R 0C EXP
White point G 0D 0 CVS A5 A4 A3 A2 A1 A0
White point B 0E MAT 0 A5 A4 A3 A2 A1 A0
Peaking 0F YD3 YD2 YD1 YD0 A3 A2 A1 A0
Brightness 10 RBL COR A5 A4 A3 A2 A1 A0
Saturation 11 IE1 IE2 A5 A4 A3 A2 A1 A0
Contrast 12 0 0 A5 A4 A3 A2 A1 A0
Spare 13 0 0 000000
Spare 14 0 0 000000
Spare 15 0 0 000000
Vertical zoom (VX, 76A) 16 0 0 A5 A4 A3 A2 A1 A0
SUBADDRESS
(HEX)
D7 D6 D5 D4 D3 D2 D1 D0
(1)
CL
(1)
A5 A4 A3 A2 A1 A0
TDA8376; TDA8376A
DATA BYTE
Note
1. The bits EXP and CL in subaddress 0C are only valid for the TDA8376. For the TDA8376A these two bits must be
set to logic 0.
Table 2 Output status bits
FUNCTION
Output status bytes 00 POR FSI STS SL XPR CD2 CD1 CD0
Note
1. X = don’t care.
1996 Jan 26 13
SUBADDRESS
(HEX)
01 NDF IN1 IN2 IFI AFA X
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
(1)
SXA SXB
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
8.2.1 INPUT CONTROL BITS
Table 3 Source select 1
INA INB DECODER AND TXT
0 0 CVBS
0 1 CVBS
INT
EXT
1 0 S-VHS
1 1 S-VHS (CVBS
EXT
)
Table 4 Source select 2
INC IND PIP
0 0 CVBS
0 1 CVBS
INT
EXT
1 0 S-VHS
1 1 S-VHS (CVBS
EXT
)
Table 5 Phase 1 (ϕ1) time constant
FOA FOB MODE
0 0 normal
0 1 slow
(1)
1X
fast
Note
1. X = don’t care.
Table 6 Crystal indication XA and XB
XA XB CRYSTAL
0 0 two 3.6 MHz
0 1 one 3.6 MHz (pin 33)
1 0 one 4.4 MHz (pin 34)
1 1 3.6 MHz (pin 33) and
4.4 MHz (pin 34)
Table 7 Forced field frequency
Note
1. When the forced mode is selected the divider will only
Table 8 Interlace
Table 9 Standby
Table 10 Synchronization mode
Table 11 Colour decoder mode
TDA8376; TDA8376A
FORF FORS FIELD FREQUENCY
0 0 auto (60 Hz when line not
synchronized)
0 1 60 Hz; note 1
1 0 50 Hz; note 1
1 1 auto
(50 Hz when line not synchronized)
switch to that position when the horizontal oscillator is
not synchronized.
DL STATUS
0 interlace
1 de-interlace
STB MODE
0 standby
1 normal
POC MODE
0 active
1 not active
CM2 CM1 CM0 DECODER MODE
0 0 0 not forced, own intelligence
0 0 1 forced NTSC 3.6 MHz
0 1 0 forced PAL 4.4 MHz
0 1 1 forced SECAM
1 0 0 forced NTSC 4.4 MHz
1 0 1 forced PAL 3.6 MHz (pin 33)
1 1 0 forced PAL 3.6 MHz (pin 34)
1 1 1 no function
1996 Jan 26 14
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
Table 12 Vertical divider mode
NCIN VERTICAL DIVIDER MODE
0 normal operation
1 switched to search window
Table 13 Video identification mode
VID VIDEO IDENTIFICATION MODE
0 ϕ
1 not active
Table 14 Long blanking mode
LBM BLANKING MODE
0 adapted to standard (50 or 60 Hz)
1 fixed in accordance with 50 Hz standard
Table 15 EHT tracking mode
HCO TRACKING MODE
0 EHT tracking only on vertical
1 EHT tracking on vertical and E-W
Table 16 Enable vertical guard (RGB blanking)
loop switched on and off
1
Table 20 Condition Y/C input
Table 21 PAL/NTSC matrix
Table 22 Y-delay adjustment; note 1
Note
1. For an equal delay of the luminance and chrominance
TDA8376; TDA8376A
CVS Y-INPUT MODE
0 switched to Y/C mode
1 switched to CVBS mode
MAT MATRIX
0 adapted to standard
1PAL
YD0 to YD3 Y-DELAY
YD3 YD3 × 160 ns +
YD2 YD2 × 80 ns +
YD1 YD1 × 40 ns +
YD0 YD0 × 40 ns
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
EVG VERTICAL GUARD MODE
0 not active
1 active
Table 17 Service blanking
SBL SERVICE BLANKING MODE
0off
1on
Table 18 Overvoltage input mode
PRD OVERVOLTAGE MODE
0 detection mode
1 protection mode
Table 19 Vertical deflection mode (TDA8376 only)
EXP CL VERTICAL DEFLECTION MODE
0 0 normal
0 1 compress
1 0 expand
1 1 expand and lift
Table 23 RGB blanking
RBL RGB BLANKING
0 not active
1 active
Table 24 Noise coring (peaking)
COR NOISE CORING
0off
1on
Table 25 Enable fast blanking RGB1
IE1 FAST BLANKING
0 not active
1 active
Table 26 Enable fast blanking RGB2
IE2 FAST BLANKING
0 not active
1 active
1996 Jan 26 15
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
8.2.2 OUTPUT CONTROL BITS
Table 27 Power-on reset
POR MODE
0 normal
1 power-down
Table 28 Field frequency indication
FSI FREQUENCY
050Hz
160Hz
Table 29 S-VHS status
STS S-VHS INPUT
0 no signal
1 signal
Table 30 Phase 1 (ϕ
SL INDICATION
0 not locked
1 locked
) lock indication
1
Table 33 Output vertical guard
Table 34 Indication RGB1 insertion
Table 35 Indication RGB2 insertion
Table 36 Output video identification
Table 37 IC version indication
TDA8376; TDA8376A
NDF VERTICAL OUTPUT STAGE
0OK
1 failure
IN1 RGB INSERTION
0 no (pin 26 LOW)
1 yes (pin 26 HIGH)
IN2 RGB INSERTION
0 no (pin 14 LOW)
1 yes (pin 14 HIGH)
IFI VIDEO SIGNAL
0 no video signal identified
1 video signal identified
Table 31 X-ray protection
XPR OVERVOLTAGE
0 no overvoltage detected
1 overvoltage detected
Table 32 Colour decoder mode
CD2 CD1 CD0 STANDARD
0 0 0 no colour standard identified
0 0 1 NTSC 3.6 MHz
0 1 0 PAL 4.4 MHz
0 1 1 SECAM
1 0 0 NTSC 4.4 MHz
1 0 1 PAL 3.6 MHz (pin 33)
1 1 0 PAL 3.6 MHz (pin 34)
1 1 1 spare
AFA IC
0 TDA8376
1 TDA8376A
Table 38 Crystal indication SXA and SXB
SXA SXB CRYSTAL
0 0 two 3.6 MHz
0 1 one 3.6 MHz
1 0 one 4.4 MHz
1 1 3.6 and 4.4 MHz
1996 Jan 26 16
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
P
T
stg
T
amb
T
sol
T
j
V
es
supply voltage − 9.0 V
storage temperature −25 +150 °C
operating ambient temperature 0 70 °C
soldering temperature for 5 s − 260 °C
operating junction temperature − 150 °C
electrostatic handling all pins; notes 1 and 2 −2000 +2000 V
all pins; notes 1 and 3 −200 +200 V
Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
3. Machine Model (MM): R = 0 Ω; C = 200 pF.
10 THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air
SDIP52 40 K/W
QFP64 50 K/W
11 QUALITY SPECIFICATION
In accordance with
Handbook”
. The handbook can be ordered using the code 9398 510 63011.
“SNW-FQ-611E”
. The number of the quality specification can be found in the
“Quality Reference
11.1 Latch-up
At T
• I
• I
=70°C all pins meet the following specification.
amb
≥ 100 mA or ≥1.5V
trigger
≤−100 mA or ≤−0.5V
trigger
DD(max)
DD(max)
.
1996 Jan 26 17
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
12 CHARACTERISTICS
V
=8V; T
P
=25°C; unless otherwise specified.
amb
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
M
AIN SUPPLY (PIN 8)
V
P1
I
P1
P
tot
supply voltage 7.2 8.0 8.8 V
supply current − 75 − mA
total power dissipation − 650 − W
HORIZONTAL OSCILLATOR SUPPLY (PIN 37)
V
P2
I
P2
supply voltage 7.2 8.0 8.8 V
supply current − 6 − mA
CVBS and S-VHS input switch
I
NTERNAL AND EXTERNAL CVBS INPUTS (PINS 9 AND 13)
V
9(p-p)
CVBS input voltage
note 1 − 1.0 1.4 V
(peak-to-peak value)
I
9
SS
CVBS
CVBS input current − 4 −µA
suppression of non-selected CVBS
notes 2 and 3 50 −−dB
input signal
S-VHS INPUT (PINS 6 AND 7)
V
7(p-p)
luminance input voltage
− 1.0 1.4 V
(peak-to-peak value)
I
7(p-p)
V
6(p-p)
luminance input current − 4 −µA
chrominance input voltage
note 4 − 0.3 0.45 V
(burst amplitude)
(peak-to-peak value)
Z
i
chrominance input impedance − 50 − kΩ
TXT AND PIP OUTPUT SIGNALS (PINS 38 AND 11)
V
o(p-p)
output signal voltage amplitude
− 1.0 − V
(peak-to-peak value)
Z
o
V
TS
output impedance −− 250 Ω
top sync voltage level − tbf − V
1996 Jan 26 18
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
RGB inputs, colour difference inputs, luminance inputs and outputs
RGB INPUTS (PINS 15 TO 17 AND 23 TO 25); note 5
V
i(p-p)
input signal voltage amplitude for an
note 6 − 0.7 0.8 V
output signal of 2 V (black-to-white)
at nominal controls
(peak-to-peak value)
V
i(p-p)
input signal voltage amplitude
note 2 1.0 −−V
before clipping occurs
(peak-to-peak value)
∆V
o
difference between black level of
−− 20 mV
internal and external signals at the
outputs
I
i
∆t
d
input currents no clamping; note 7 − 0.1 −µA
delay difference for the three
note 2 − 020ns
channels
FAST BLANKING (PINS 14 AND 26)
V
i
input voltage no data insertion −− 0.4 V
data insertion 0.9 −−V
V
14,26(max)
t
d
maximum input pulse data insertion −− 3.0 V
delay time from RGB input to
data insertion; note 5 − 100 − ns
RGB output
∆t
d
delay difference between data
data insertion; note 5 − 50 − ns
insertion to RGB output and
RGB input to RGB output
I
14,26
SS
int
input current −− 0.2 mA
suppression of internal RGB signals notes 1 and 2; data
55 −−dB
insertion; fi= 0 to 5 MHz
SS
ext
suppression of external RGB signals notes 1 and 2; no data
55 −−dB
insertion; fi= 0 to 5 MHz
V
14
input voltage to insert black level at
4 −−V
the RGB outputs to facilitate OSD
signals being applied to the outputs
COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32)
V
32(p-p)
input signal amplitude −(R−Y)
note 7 − 1.05 − V
(peak-to-peak value)
V
31(p-p)
input signal amplitude −(B−Y)
note 7 − 1.35 − V
(peak-to-peak value)
I
31,32
input current for both inputs note 7 − 0.1 1.0 µA
1996 Jan 26 19
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28)
V
28(p-p)
output signal voltage amplitude
top sync to white − 0.45 0.63 V
(peak-to-peak value)
V
TS
Z
o
V
27(p-p)
top sync voltage level − 2.5 − V
output impedance − 250 −Ω
input signal voltage amplitude
− 0.45 − V
(peak-to-peak value)
I
clamp
clamping current during burst key
− 200 −µA
pulse
I
i
input current no clamping −− 0.5 µA
Chrominance filters
C
HROMINANCE TRAP CIRCUIT
f
trap
trap frequency − f
osc
− MHz
during SECAM reception − 4.2 − MHz
QF trap quality factor note 8 − 2 −
SR colour subcarrier rejection 20 −−dB
HROMINANCE BAND-PASS CIRCUIT
C
f
c
centre frequency − f
osc
− MHz
QBP band-pass quality factor − 3 −
Delay line, peaking circuit and black stretcher
DELAY LINE
Y
t
d
t
d1
delay time note 2 − 480 − ns
tuning range delay time 8 steps −160 − +160 ns
B bandwidth of internal delay line note 2 5 −−MHz
EAKING CONTROL; note 9
P
f
t
c(p)
W
peaking centre frequency − 3 − MHz
width of preshoot or overshoot at 50% of pulse; note 2 − 160 − ns
OS overshoot positive − 20 − %
negative − 36 − %
peaking control curve 16 steps see Fig.5
G
W
wave gain − 1.8 −
negative half wave gain
-------------------------------------------------------------positive half wave gain
CORING STAGE
S coring range − 15 − IRE
BLACK LEVEL STRETCHER (PIN 2); note 10
BLS
max
maximum black level shift 15 21 27 IRE
LSH level shift 100% of peak-white −1 0 +1 IRE
50% of peak-white −1 − +3 IRE
15% of peak-white 6 8 10 IRE
1996 Jan 26 20
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Horizontal synchronization circuits
SYNC VIDEO INPUTS(PINS 7, 9 AND 13)
V
SL
SL
7,9,13
HS
VS
sync pulse voltage amplitude note 7 50 300 − mV
slicing level for horizontal sync note 11 − 50 − %
slicing level for vertical sync − 30 − %
HORIZONTAL OSCILLATOR
f
fr
∆f
fr
∆f/∆V
P
free running frequency − 15625 − Hz
spread of free running frequency −− ±2%
frequency variation with respect to
VP=8V±10%; note 2 − 0.2 0.5 %
the supply voltage
∆f
(max)
maximum frequency variation with
T
= 0 to 70 °C; note 2 −− 80 Hz
amb
temperature
FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 44); note 12
f
HR
f
CR
S/N signal-to-noise ratio of the video
frequency holding range PLL −±0.9 ±1.2 kHz
frequency catching range PLL note 2 ±0.6 ±0.9 − kHz
− 20 − dB
input signal at which the time
constant is switched
HYS hysteresis at the switching point − 1 − dB
SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 43)
∆ϕ
t
cr
/∆ϕ
i
o
control sensitivity − 150 −µs/µs
control range from start of horizontal
11 12 −µs
output to flyback at nominal shift
position
t
shift
ϕ
dync
horizontal shift range 63 steps ±2 −−µs
control sensitivity for dynamic
− 5.3 −µs/V
compensation
V
43
voltage to switch on the ‘flash’
note 13 6 −−V
protection
I
43
input current during protection −− 1mA
HORIZONTAL OUTPUT (PIN 40); note 14
V
OL
I
O(max)
V
O(max)
LOW level output voltage IOL=10mA −− 0.3 V
maximum allowed output current 10 −−mA
maximum allowed output voltage −− V
P
V
δ duty factor note 2 − 50 − %
note 2; V
HOUT
= high;
− 75 − %
during switch-on/switch-off
f
switch
frequency during switch-on and
− 2f
HOUT
− Hz
switch-off
t
switch(on)
t
switch(off)
switch-on time − 50 − ms
switch-off time RGB drive maximum − 100 − ms
RGB drive minimum − 50 − ms
1996 Jan 26 21
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
FLYBACK PULSE INPUT (PIN 41)
V
HSW
switching voltage level for horizontal
− 0.4 − V
blanking
V
ϕ2(SW)
V
41(max)
Z
i
switching level for phase-2 loop − 4.0 − V
maximum input voltage note 7 − 8.0 − V
input impedance note 7 − 10 − MΩ
SANDCASTLE PULSE OUTPUT (PIN 39)
V
39
output voltage during burst key 4.8 5.3 5.8 V
during blanking 1.8 2.0 2.2 V
t
W
pulse width burst key pulse 3.3 3.5 3.7 µs
vertical blanking (50 Hz) − 25 − lines
vertical blanking (60 Hz) − 21 − lines
V
clamp
clamping voltage level for vertical
− 2.7 − V
guard detection
I
39(min)
minimum input current to activate
−− 0.5 mA
guard detection
I
39(max)
t
d
maximum allowable input current 2.5 −−mA
delay of start of burst key to start of
− 5.4 −µs
sync
Vertical synchronization and geometry correction
V
ERTICAL OSCILLATOR; note 15
f
f
fr
lock
free running frequency − 50/60 − Hz
locking frequency range 45 − 64.5 Hz
divider value not locked − 625/525 − lines
LR locking range 488 − 722 lines/
frame
ERTICAL RAMP GENERATOR (PIN 50)
V
V
50(p-p)
I
dis
I
charge
sawtooth voltage amplitude
(peak-to-peak value)
VS = 1FH;
C = 100 nF; R = 39 kΩ
− 3.5 − V
discharge current − 1 − mA
charge current set by external
note 16 − 19 −µA
resistor
VS vertical slope control range 63 steps −20 − +20 %
∆I
V
50
50L
charge current increase f = 60 Hz − 20 − %
LOW level voltage of ramp − 2.07 − V
VERTICAL DRIVE OUTPUTS (PINS 47 AND 48)
I
diff(p-p)
differential output current
VA = 1FH − 0.95 − mA
(peak-to-peak value)
I
CM
V
o
common mode output current − 400 −µA
output voltage 0 − 4.0 V
1996 Jan 26 22
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 49); note 13
V
49
input voltage 1.2 − 2.8 V
SMR scan modulation range −5 − +5 %
ϕ
vert
ϕ
EW
I
eq
V
49
vertical sensitivity − 6.3 − %/V
E-W sensitivity when switched-on −−6.3 − %/V
E-W equivalent output current +100 −−100 µA
overvoltage detection level − 3.9 − V
DE-INTERLACE
first field delay − 0.5H −
E-W WIDTH; note 17
CR control range 63 steps
TDA8376 100 − 80 %
TDA8376A 100 − 65 %
I
eq
equivalent output current
TDA8376 0 − 400 µA
TDA8376A 0 − 700 µA
V
o
I
o
E-W output voltage range 1.0 − 8.0 V
E-W output current range
TDA8376 0 − 900 µA
TDA8376A 0 − 1200 µA
PARABOLA/WIDTH
E-W
CR control range 63 steps 0 − 22 %
I
eq
equivalent output current E-W = 3FH; CP = 00H 0 − 440 µA
E-W CORNER/PARABOLA
CR control range 63 steps −43 − 0%
I
eq
equivalent output current PW = 3FH; E-W = 3FH −190 − 0 µA
E-W TRAPEZIUM
CR control range 63 steps −5 − +5 %
I
eq
equivalent output current −100 − +100 µA
VERTICAL AMPLITUDE
CR control range 63 steps 80 − 120 %
I
eqdiff(p-p)
equivalent differential vertical drive
SC = 00H 760 − 1140 µA
output current (peak-to-peak value)
VERTICAL SHIFT
CR control range 63 steps −5 − +5 %
I
eqdiff(p-p)
equivalent differential vertical drive
−50 − +50 µA
output current (peak-to-peak value)
S-CORRECTION
CR control range 63 steps 0 − 30 %
1996 Jan 26 23
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VERTICAL EXPANSION (ZOOM) MODE (TDA8376A ONLY); note 18
Output current variation compared with nominal scan:
VEF vertical expansion factor 0.75 − 1.38 %
output current limiting and RGB
− 1.06 − %
blanking
Colour demodulation part
HROMINANCE AMPLIFIER
C
ACC
cr
∆V variation in amplitude of the output
ACC control range note 19 26 −−dB
−− 2dB
signals over the ACC range
THR
HYS
on
off
threshold colour killer ON −23 −26 −29 dB
hysteresis colour killer OFF strong signal conditions;
− +3 − dB
S/N ≥ 40 dB; note 2
noisy input signals; note 2 − +1 − dB
R
EFERENCE PART
Phase-locked loop;
f
CR
note 20
frequency catching range ±360 ±600 − Hz
∆ϕ phase shift for a ±400 Hz deviation
of the oscillator frequency
Oscillator
TC
osc
temperature coefficient of the
oscillator frequency
∆f
osc
oscillator frequency deviation with
respect to the supply
R
i(min)
C
L(max)
minimum negative input resistance −− 1kΩ
maximum load capacitance −− 15 pF
HUE CONTROL
HUE
cr
∆HUE hue variation for ±10% V
hue control range 63 steps; see Fig.6 ±35 ±40 − deg
P
∆HUE/∆T hue variation with temperature T
note 2 −− 2 deg
note 2 −− tbf Hz/K
note 2; VP=8V±10% −− tbf Hz
note 2 − 0 − deg
= 0 to 70 °C; note 2 − 0 − deg
amb
1996 Jan 26 24
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
DEMODULATORS (PINS 29 AND 30)
V
30(p-p)
−(R−Y) output voltage amplitude
note 21 − 0.525 − V
(peak-to-peak value)
V
29(p-p)
−(B−Y) output voltage amplitude
note 21 − 0.675 − V
(peak-to-peak value)
G gain ratio between both
1.60 1.78 1.96
demodulators G(B−Y) and G(R−Y)
∆V spread of voltage amplitude ratio
note 2 −1 − +1 dB
PAL/NTSC
Z
o
output impedance −(R−Y)/−(B−Y)
note 2 − 500 −Ω
output
B bandwidth of demodulators −3 dB; notes 7 and 21 − 650 − kHz
V
29,30(p-p)
V
30(p-p)
residual carrier output
(peak-to-peak value)
H/2 ripple at −(R−Y) output
f=f
; −(R−Y) output −− 5mV
osc
; −(B−Y) output −− 5mV
f=f
osc
f=2f
f=2f
; −(R−Y) output −− 5mV
osc
; −(B−Y) output −− 5mV
osc
−− 25 mV
(peak-to-peak value)
/∆T variation of output voltage amplitude
∆V
o
note 2 − 0.1 − %/K
with temperature
∆V
o
/∆V
variation of output voltage amplitude
P
note 2 −− ±0.1 dB
with supply voltage
ϕ
e
phase error in the demodulated
−− ±5 deg
signals
COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT
PAL or (SECAM mode with TDA8395);−(R−Y) and−(B−Y) not affected
(G−Y)/(R−Y) ratio of demodulated signals −−0.51
−
±10%
(G−Y)/(B−Y) ratio of demodulated signals −−0.19
−
±25%
NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)
−(B−Y) −(B−Y) signal −(B−Y)
−(R−Y) −(R−Y) signal 1.39(R−Y) − 0.07(B−Y)
−(G−Y) −(G−Y) signal −0.46(R−Y) − 0.15(B−Y)
1996 Jan 26 25
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 36); note 22
f
ref
V
36(p-p)
reference frequency − 4.43 − MHz
output voltage amplitude
0.2 0.25 0.3 V
(peak-to-peak value)
V
o
output voltage level PAL/NTSC identified − 1.5 − V
no PAL/NTSC identified;
− 5.0 − V
SECAM (by TDA8395)
identified
I
36
required current to stop PAL/NTSC
150 −−µA
identification circuit during SECAM
Control part
S
ATURATION CONTROL; note 6
SAT
CR
saturation control range 63 steps; see Fig.7 52 −−dB
CONTRAST CONTROL; note 6
CON
CR
contrast control range 63 steps − 20 − dB
tracking between the three channels
see Fig.8 −− 0.5 dB
over a control range of 10 dB
RIGHTNESS CONTROL
B
BRI
CR
brightness control range 63 steps; see Fig.9 −±0.7 − V
RGB OUTPUT SIGNALS (PINS 19, 20 AND 21)
V
19,20,21(p-p)
output voltage amplitude
(peak-to-peak value)
at nominal luminance input
signal, nominal contrast
tbf 2.0 tbf V
and white-point
adjustment; note 6
at maximum white point
− 3.0 − V
setting
V
BWmax(p-p)
maximum voltage amplitude
(black-to-white)
note 23 − 2.6 − V
at maximum white point
− 3.6 − V
setting
V
RED(p-p)
output voltage amplitude for the ‘red’
channel (peak-to-peak value)
at nominal settings for
contrast and saturation
tbf 2.1 tbf V
control and no luminance
signal to the input (R−Y,
PAL)
V
I
bias
blank
blanking level at the RGB outputs 0.7 0.8 0.9 V
internal bias current of NPN emitter
− 1.5 − mA
follower output transistor
I
o
Z
CR
o
bl
available output current − 5 − mA
output impedance − 150 −Ω
control range of the black-current
stabilization
nominal brightness and
white-point adjustment (with
−− ±1V
respect to the measuring
pulse); V
= 2.5 V
blk
1996 Jan 26 26
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
bl
V
o
black level shift with picture content note 2 −− 20 mV
output voltage of the 4-L pulse after
− 4.2 − V
switch-on
∆bl/∆T variation of black level with
note 2 − 1.0 − mV/K
temperature
∆bl relative variation in black level
note 2
between the three channels during
variations of
supply voltage (±10%) nominal controls −− tbf mV
saturation (50 dB) nominal contrast −− tbf mV
contrast (20 dB) nominal saturation −− tbf mV
brightness (±0.5 V) nominal controls −− tbf mV
temperature (range 40 °C) −− tbf mV
S/N signal-to-noise ratio of the output
signals
V
res(p-p)
residual voltage at the RGB outputs
(peak-to-peak value)
RGB input; note 24 60 −−dB
CVBS input; note 24 50 −−dB
at f
at 2f
osc
plus higher
osc
−− 15 mV
−− 15 mV
harmonics in RGB outputs
B bandwidth of output signals RGB input; at −3dB 8 −−MHz
CVBS input; at −3 dB;
= 3.58 MHz
f
osc
CVBS input; at −3 dB;
= 4.43 MHz
f
osc
− 2.8 − MHz
− 3.5 − MHz
S-VHS input; at −3dB 5 −−MHz
HITE-POINT ADJUSTMENT
W
I2C-bus setting for nominal gain HEX code − 20H −
G
inc(max)
G
dec(max)
maximum increase of the gain HEX code 3FH 40 50 60 %
maximum decrease of the gain HEX code 00H 40 50 60 %
BLACK-CURRENT STABILIZATION (PIN 18); note 25
I
bias
bias current for the picture tube
nominal white point setting − 10 −µA
cathode
I
leak
I
scan(max)
acceptable leakage current − 100 −µA
maximum current during scan − 0.3 − mA
1996 Jan 26 27
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
SYMBOL PARAMETER CONDITIONS MIN. TYP . MAX. UNIT
B
EAM CURRENT LIMITING (PIN 22); note 23
V
V
CR
diffCR
contrast reduction starting voltage − 3.5 − V
voltage difference for full contrast
− 2.0 − V
reduction
V
V
BR
diffBR
brightness reduction starting voltage − 2.5 − V
voltage difference for full brightness
− 1.0 − V
reduction
V
bias
I
ch(int)
I
disch
internal bias voltage − 4.5 − V
internal charge current − 25 −µA
discharge current due to ‘peak-white
− 200 −µA
limiting’
Notes
1. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
3. This parameter is measured at nominal settings of the various controls.
4. Indicated is a signal for a colour bar with 75% saturation (chrominance : burst ratio = 2.2 : 1).
5. The RGB1 inputs (pins 14 to 17) have priority over the RGB2 inputs (pins 23 to 25).
6. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. In the nominal
brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses.
7. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
8. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:
1
f
3dB–
f
=
1
osc
–
-------2Q
9. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
10. For video signals with a black level which deviates from the back-porch blanking level the signal is ‘stretched’ to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.10). The black level is
detected by the capacitor connected to pin 2. The black level stretcher can be made inoperative by connecting pin 2
to the positive supply line. The values given are valid only when the luminance input signal (pins 7, 9 and 13) has a
value of 1 V (p-p).
11. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch).
1996 Jan 26 28
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a
noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be
automatically or overruled by the I2C-bus.
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification
circuit with the first loop can be defeated via the I2C-bus.
To prevent that the horizontal synchronization being disturbed by anti-copy guard signals like Macrovision the phase
detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage.
The width of the gate pulse is approximately 22 µs, the phase position around the sync pulse is asymmetrical. During
weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of
the gate pulse is reduced to 5.7 µs so that the effect of the noise is reduced to a minimum.
The output current of the phase detector in the various conditions are shown in Table 39.
13. The ICs have two protection inputs. The protection on pin 43 is intended to be used as ‘flash’ protection. When this
protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow
start procedure. The protection on pin 49 is intended for overvoltage (X-ray) protection. When this protection is
activated the horizontal drive can be switched-off (via the slow stop procedure). It is also possible to continue the
horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the two
modes of operation is made via the PRD bit.
14. During switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (V
After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak
currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double
value and the RGB drive is set to maximum so that the EHT capacitor is discharged. After approximately 100 ms the
RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off.
15. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This
divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per
frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode
the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).
b) Standard mode ‘narrow window’.
This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator
is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch
back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in
accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the
standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync
pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider requires some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 08.
TDA8376; TDA8376A
= high).
HOUT
1996 Jan 26 29
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
16. Conditions: frequency is 50 Hz; normal mode; VS = 1FH.
17. The E-W output current range of the TDA8376A is higher than that of the TDA8376 because of the horizontal zoom
function of the TDA8376A. The output range percentages mentioned for E-W control parameters are based on the
assumption that 400 µA variation in E-W output current is equivalent to 20% variation in picture width.
18. The TDA8376A has a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra
DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 75 to 138%
of the nominal scan. At an amplitude of 106% of the nominal scan the output current is limited and the blanking of
he RGB outputs is activated. This is illustrated in Fig.21. In addition to the variation of the vertical amplitude the
vertical slope control range is also increased. This allows variation of the position of the bottom part of the picture
independent of the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical ‘zoom’
DAC.
19. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.
20. All frequency variations are referenced to a 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are
measured with the Philips crystal series 9922 520 with a series capacitance of 18 pF. The oscillator circuit is rather
insensitive to the spurious responses of the crystal. Provided the resonance resistance of the third overtone is higher
than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal
parameters for the crystals are:
a) load resonance frequency f
b) motional capacitance C
c) parallel capacitance C
(CL= 20 pF) = 4.433619 or 3.579545 MHz
0
= 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal)
M
= 5 pF for both crystals.
0
The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures
given in are therefore valid for the specified crystal series. In this, tolerances of the crystal with respect to nominal
frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic
addition. Whenever different typical crystal parameters are used the following equation might be helpful for
calculating the impact on the detuning capabilities:
C
Detuning range:
M
--------------------------
1
2
C
0
+
------ C
L
The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the
crystal. The actual series capacitance in the application should be C
= 18 pF to account for parasitic capacitances
L
on and off chip. For 3-normal applications with two crystals connected to one pin the maximum parasitic capacitance
of the crystal pin should not exceed 15 pF.
21. The −(R−Y) and −(B−Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain
ratio . The matrixing to the required signals is achieved in the control part.
BY–()–
----------------------- RY–()–
1.78=
22. The subcarrier output signal can be supplied to the TDA8395 but it can also be used as drive signal for external comb
filters. For this reason the signal is continuously available at the output. Only when SECAM has been identified the
subcarrier signal is available only during the vertical retrace time. This is to avoid cross-talk between the SECAM
input signal and the subcarrier signal. An external DC load on this pin is not allowed because this current will disturb
the reliability of the communication between the TDA8376/TDA8376A and the TDA8395.
23. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the
contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input.
24. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
25. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain
(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a
result the ‘black-current’ of each gun is adapted to the white point setting so that the background colour will follow
the white point adjustment.
1996 Jan 26 30
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
Table 39 Output current of the phase detector in the various conditions
I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE
VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE
− 0 0 0 yes yes yes 30 30 yes
(1)
− 0 0 0 yes no no 180 270 no auto
− 0 0 1 yes yes yes 30 30 yes slow
− 0 0 1 yes yes no 180 270 yes fast
− 01−yes −−180 270 no fast
00−−no −−6 6 no OSD
− 1 −−−−−−−−off
Note
1. Only during vertical retrace, pulse width 22 µs. In other conditions the pulse width is 5.7 µs and the gating is
continuous.
(%)
50
MLA738 - 1
50
(deg)
MLA739 - 1
auto
30
10
10
30
50
048C10
Overshoot in direction ‘black’.
DAC (HEX)
Fig.5 Peaking control curve.
F
30
10
10
30
50
010203040
DAC (HEX)
Fig.6 Hue control curve.
1996 Jan 26 31
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
MLA740 - 1
250
(%)
225
200
175
150
125
100
75
50
25
0
010203040
DAC (HEX)
100
(%)
TDA8376; TDA8376A
MLA741 - 1
90
80
70
60
50
40
30
20
10
010203040
DAC (HEX)
Fig.7 Saturation control curve. Fig.8 Contrast control curve.
0.7
(V)
0.35
0
0.35
0.7
0
010203040
Relative variation with respect to the measuring pulse.
DAC (HEX)
MLA742 - 1
100
handbook, halfpage
80
output
(IRE)
60
40
20
−20
(1) Maximum black level shift.
(2) Level shift at 15% of peak white.
B
(2)
B
0
A
(1)
A
200 100
MGE079
40 60 80
input (IRE)
Fig.9 Brightness control curve.
1996 Jan 26 32
Fig.10 I/O relationship of the black level stretcher.
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
13 TEST AND APPLICATION INFORMATION
SDA
handbook, full pagewidth
CVBS
INT
CVBS
EXT
CVBS/Y
CHROMA
PIPO
9
13
7
6
11
34 33 38
XTAL2
4.4
MHz
SCL RI2 GI2 BI2 RGBIN2 RI1 GI1 BI1
4 3 15 16 17 14 23 24 25 26
TDA8376(A)
36 30 29 32 31 39
XTAL1
3.6
MHz
TXT
SEC
ref
RYO RYICVBS/
BYO
TDA8376; TDA8376A
RGBIN1
21
RO
20
GO
19
BO
18
BLKIN
22
BCLIN
46
EWD
47
VDR
(p)
48
VDR
(n)
40
HOUT
41
BYI SCO
FBI
to text decoder
TDA8395
Fig.11 Application diagram.
13.1 East-West output stage
In order to obtain correct tracking of the vertical and
horizontal EHT-correction, the E-W output stage should be
dimensioned as illustrated in Fig.12.
Resistor REW determines the gain of the E-W output stage.
Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor.
1996 Jan 26 33
TDA4665
The preferred value of R
is 39 kΩ which results in a
c
reference current of 100 µA (V
The value of R
EW
R
c
R
Example: With V
EW
V
×=
---------------------- 18 V
must be:
scan
×
ref
= 3.9 V Rc=39kΩand V
ref
then REW= 68 kΩ.
= 3.9 V
ref
MGE080
scan
= 120 V
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
handbook, full pagewidth
R
EW
TDA8376(A)
46
EWD
EW OUTPUT
STAGE
R
39 kΩ
(2%)
5051
V
ref
c
I
ref
C
saw
100 nF
(5%)
V
DD
HORIZONTAL
DEFLECTION
STAGE
DIODE
MODULATOR
MGE081
TDA8376; TDA8376A
V
scan
V
EW
600
handbook, halfpage
400
I
vert
(µA)
200
0
−200
−400
−600
0
1/2 t
Fig.12 East-West output stage.
MGE082
handbook, halfpage
I
(µA)
time
t
vert
900
700
500
300
100
−100
−300
−500
−700
0t
1/2 t
MGE083
time
VA = 0, 31H and 63H; VSH = 31H; SC = 0.
Fig.13 Control range of vertical amplitude.
1996 Jan 26 34
VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.
Fig.14 Control range of vertical slope.
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
time
MGE084
handbook, halfpage
I
vert
(µA)
t
SC = 0, 31H and 63H; VA = 31H; VHS = 31H.
Picture height does not change with setting of S-correction for
nominal vertical amplitude (VA = 31H).
600
handbook, halfpage
400
I
vert
(µA)
200
0
−200
−400
−600
0
VSH = 0, 31H and 63H; VA = 31H; SC = 0.
1/2 t
600
400
200
-200
-400
-600
TDA8376; TDA8376A
MGE085
0
0
1/2 t
time
t
Fig.15 Control range of vertical shift.
1200
handbook, halfpage
1000
IEW
(µA)
800
600
400
200
0
0
1/2 t
time
MGE086
Fig.16 Control range of S-correction.
time
MGE087
t
900
handbook, halfpage
800
IEW
(µA)
700
600
500
400
t
300
0
1/2 t
EW = 0, 31H and 63H; PW = 31H; CP = 31H.
Fig.17 Control range of E-W width.
1996 Jan 26 35
PW = 0, 31H and 63H; EW = 31H; CP = 31H.
Fig.18 Control range of E-W parabola/width ratio.
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
time
MGE088
handbook, halfpage
IEW
(µA)
t
TC = 0, 31H and 63H; EW = 31H; PW = 31H.
Fig.20 Control range of E-W trapezium correction.
900
handbook, halfpage
800
I
EW
(µA)
700
600
500
400
300
0
CP = 0, 31H and 63H; EW = 31H; PW = 63H.
1/2 t
Fig.19 Control range of E-W corner/parabola ratio.
650
600
550
500
450
400
350
TDA8376; TDA8376A
MGE089
0
1/2 t
time
t
handbook, full pagewidth
TDA8376A only.
vertical
position
(%)
−10
−20
−30
−40
−50
−60
70
60
50
40
30
20
10
0
TOP
PICTURE
138%
100%
75%
BOTTOM
PICTURE
blanking for expansion 138%
1/2 t
time
t
MGE090
1996 Jan 26 36
Fig.21 Sawtooth waveform and blanking pulse.
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
13.2 Adjustment of geometry control parameters
The deflection processor of the TDA8376/TDA8376A
offers nine control parameters for picture alignment:
• Vertical picture alignment
– S-correction
– vertical amplitude
– vertical slope
– vertical shift
• Horizontal picture alignment
– horizontal shift
– E-W width
– E-W parabola/width
– E-W corner/parabola
– E-W trapezium correction.
It is important to notice that the TDA8376/ TDA8376A is
designed for use with a DC-coupled vertical deflection
stage. This is the reason why a vertical linearity alignment
is not necessary (and therefore not available).
For a particular combination of picture tube type, vertical
output stage and E-W output stage it is determined which
are the required values for the settings of S-correction,
E-W parabola/width ratio and E-W corner/parabola ratio.
These parameters can be preset via the I
not need any additional adjustment. The remainder of the
parameters are preset with the mid-value of their control
range (i.e. 1FH), or with the values obtained by previous
TV-set adjustments.
The vertical shift control is intended for compensation of
off-sets in the external vertical output stage or in the
picture tube. It can be shown that without compensation
these off-sets will result in a certain linearity error,
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation
proportional to the value of the off-set, and to the square of
the S-correction required. The necessity to use the vertical
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction, and on the demands upon vertical linearity.
2
C-bus, and do
For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
mode can be entered by setting the SB-bit HIGH. In this
mode the RGB-outputs are blanked during the second half
of the picture. There are two different methods for
alignment of the picture in vertical direction. Both methods
make use of the service blanking mode.
The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment the vertical shift should not be changed. The
top of the picture is placed by adjustment of the vertical
amplitude, and the bottom by adjustment of the vertical
slope.
The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method a video signal is required in which the middle of the
picture is indicated (e.g. the white line in the circle test
pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
symmetrical with respect to the middle of the screen by
adjustment of the vertical amplitude and vertical shift.
After this adjustment the vertical shift has the correct
setting and should not be changed.
If the vertical shift alignment is not required VSH should be
set to its mid-value (i.e. VSH = 1FH). Then the top of the
picture is placed by adjustment of the vertical amplitude
and the bottom by adjustment of the vertical slope. After
the vertical picture alignment the picture is positioned in
the horizontal direction by adjustment of the E-W width and
the horizontal shift. Finally (if necessary) the left and
right-hand sides of the picture are aligned in parallel by
adjusting the E-W trapezium control.
To obtain the full range of the vertical zoom function of the
TDA8376A the adjustment of the vertical geometry should
be carried out at a nominal setting of the zoom DAC at
position 19H.
TDA8376; TDA8376A
1996 Jan 26 37
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
14 PACKAGE OUTLINES
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
D
seating plane
L
Z
52
e
b
TDA8376; TDA8376A
SOT247-1
M
E
A
2
A
A
1
w M
b
1
27
c
(e )
M
1
H
pin 1 index
1
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
A
UNIT b
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
mm
5.08 0.51 4.0
OUTLINE
VERSION
SOT247-1
12
min.
max.
IEC JEDEC EIAJ
1.3
0.8
b
1
0.53
0.40
REFERENCES
cEe M
0.32
0.23
(1) (1)
D
47.9
47.1
14.0
13.7
E
26
(1)
Z
1
L
M
E
3.2
15.80
2.8
15.24
EUROPEAN
PROJECTION
17.15
15.90
e
w
H
0.181.778 15.24
ISSUE DATE
90-01-22
95-03-11
max.
1.73
1996 Jan 26 38
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
c
y
X
51 33
52
32
Z
e
A
E
A
H
E
E
2
A
A
1
SOT319-2
Q
(A )
3
pin 1 index
64
1
w M
b
e
DIMENSIONS (mm are the original dimensions)
mm
OUTLINE
VERSION
SOT319-2
A
max.
3.20
0.25
0.05
2.90
0.25
2.65
IEC JEDEC EIAJ
UNIT A1A2A3b
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
p
D
H
D
cE
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REFERENCES
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PROJECTION
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ISSUE DATE
92-11-17
95-02-04
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1996 Jan 26 39
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
15 SOLDERING
15.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
15.2 SDIP
15.2.1 S
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
15.2.2 R
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
15.3 QFP
15.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
OLDERING BY DIPPING OR BY WA VE
EPAIRING SOLDERED JOINTS
Reference Handbook”
(order code 9398 652 90011).
). If the
stg max
“Quality
(order code 9397 750 00192).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
15.3.2 WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
• The footprint must be at an angle of 45° to the board
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.3.3 R
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
TDA8376; TDA8376A
pressure followed by a smooth laminar wave)
soldering technique should be used.
direction and must incorporate solder thieves
downstream and at the side corners.
EPAIRING SOLDERED JOINTS
1996 Jan 26 40
Philips Semiconductors Objective specification
I2C-bus controlled PAL/NTSC TV processors
16 DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
TDA8376; TDA8376A
18 PURCHASE OF PHILIPS I
Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
1996 Jan 26 41
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