DATASHEETS tda8083 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8083

Satellite Demodulator and Decoder
(SDD3)

Product specification
File under Integrated Circuits, IC02

1999 Jul 28

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

FEATURES

• One chip Digital Video Broadcasting (DVB)
(ETS300421)compliantdemodulatorand concatenated
Viterbi and Reed-Solomon decoder with de-interleaver
and de-randomizer

• 3.3 V supply voltage

• Relevant outputs are 5 V tolerant to ease interface to

5 V environment

• Few external components for full application

• On-chip crystal oscillator (4 MHz) and Phase-Locked

Loop (PLL) for internal clock generation

• Power-on reset module

• QPSK/BPSK demodulator:

– Different modulation schemes: Quadrature Phase

Shift Keying (QPSK) and Binary Phase Shift Keying
(BPSK)

– Interpolator and internal anti-aliasing filter to handle

variable symbol rates
– Tuner Automatic Gain Control (AGC) control
– Two on-chip matched 7-bit Analog-to-Digital

Converters (ADCs)
– Square-root raised-cosine Nyquist
– Maximum symbol frequency of 30 Msymbols/s
– Can be used at low channel Signal-to-Noise Ratio

(S/R)
– Internal full digital carrier recovery, clock recovery

and AGC loops with programmable loop filters
– Two carrier recovery loops enabling optimum phase

noise suppression
– S/R estimation.

• Viterbi decoder:
– Rate1⁄2convolutional code based
– Constraint length K = 7 with G1= 171

G2= 133

– Supported puncturing code rates:1⁄2,2⁄3,3⁄4,4⁄5,5⁄6,

6

⁄7,7⁄8and8⁄

– 4-bit ‘soft decision’ inputs for both I and Q
– Truncation length of 144
– Automatic synchronization to detect puncturing rate

and spectral inversion

– Channel Bit Error Rate (BER) estimation from

10−2to 10

– Differential decoding optional.

oct

9

−8

oct

and

TDA8083

• Reed-Solomon (RS) decoder:
– (204, 188, T = 8) Reed-Solomon code
– Automatic synchronization of bytes, transport

packets and frames

– Internal convolutional de-interleaving (I = 12; using

internal memory)

– De-randomizer based on Pseudo Random Binary

Sequence (PRBS)

– External indication of uncorrectable error (transport

error indicator is set)
– Indication of the number of lost blocks
– Indication of the number of corrected blocks.

• Interface:
–I2C-bus interface initializes and monitors the

demodulator and Forward Error Correction (FEC)
decoder; a default mode is defined

– 6-bit I/O expander for flexibleaccess to and from the

I2C-bus
–I2C-bus configurable interrupt input
– Switchable I2C-busloop-through tosuppress I2C-bus

crosstalk in the tuner
– Digital Satellite Equipment Control (DiSEqC) 1.X,

tone burst generation and tone mode with a

22 or 44 kHz carrier
– Parallel or serial output mode for MPEG transport

stream (3-state mode also possible)
– Standby mode for reduced power consumption.

• Package: QFP100

• Boundary scan test.

APPLICATIONS

• Digital satellite TV: demodulation and FEC.

1999 Jul 28 2

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

GENERAL DESCRIPTION

This document specifies a DVB compliant demodulator
and forward error correction decoder IC for reception of
QPSK or BPSK modulated signals for satellite
applications. The Satellite Demodulator and Decoder
(SSD) can handle variable symbol rates without adapting
the analog filters within the tuner. Typical applications for
this device are:

• MCPC (Multi-Channel Per Carrier): one QPSK or
BPSK modulated signal in a single satellite channel
(transponder)

• Simul-cast: QPSK or BPSK modulated signal together
with a Frequency Modulated (FM) signal in a single
satellite channel (transponder).

The TDA8083 can handle variable symbol rates in the
range of 12 to 30 Msymbols/s with a minimum number of
low cost and non-critical external components.

TheTDA8083 hasminimal interfaceswith thetuner. Itonly
requires the demodulated analog I and Q baseband input
signals and provides a tuner AGC control signal.
Analog-to-digital conversion is done internally by two
matched 7-bit ADCs.

TDA8083

The TDA8083 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely
internally, thereby minimizing I2C-bus communication.
The output of the TDA8083allows different outputmodes
(parallel or serial) to interface to a demultiplexer,
descrambler or MPEG-2 decoder including a 3-state
mode. For evaluation of the TDA8083, demodulator and
Viterbi decoder outputs can be made available externally.

The SDDcan be controlled andmonitored by the I2C-bus.
A 5-bit bidirectional I/O expanderand an interrupt line are
available. By sending an interrupt signal, the SDD can
inform the microcontroller of its internal status. Separate
resets are available for logic only, logic plus the I2C-bus
andcarrier loops.A switchableI2C-busloop-through tothe
tuner is implemented to switch off the I2C-bus connection
to thetuner. This reducesphase noise in thetuner in case
of I2C-bus crosstalk.

Furthermore, for dish control applications hardware
supports DiSEqC 1.X and tone burst generation via
I2C-buscontrol. A 22 or a 44 kHzcarrier canbegenerated
(tone mode).

The TDA8083 runs on a low frequency crystal which is
upconverted to a clock frequency bymeans of an internal
PLL. Furthermore, the TDA8083has an internal anti-alias
filter, which can cover the range of symbol frequencies
without the need to switch external (SAW) filters.

1999 Jul 28 3

Philips Semiconductors Product specification

Satellite Demodulator and Decoder

TDA8083

(SDD3)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DD(tot)

f

clk(int)

r

s

α

ro

IL implementation loss note 2 − 0.3 − dB
S/R signal-to-noise ratio locking the SDD in

P

tot

T

stg

T

amb

T

j

Notes

1. Typical value is specified fora symbol rate of 27.5 Msymbols/s, a puncture rate of3⁄4and a supply voltage of3.3 V.

Maximum value isspecified for a symbolrate of 30 Msymbols/s, a puncturerate of7⁄8, a supplyvoltage of 3.6 V and
using a 4 MHz crystal.

2. Implementationloss atthe demodulatoroutput andminimumSNR tolock theTDA8083 aremeasured includingtuner

in a laboratory environment at a symbol rate of 27.5 MS/s.

analog supply voltage 3.0 3.3 3.6 V
digital supply voltage 3.0 3.3 3.6 V
total supply current note 1 − 270 340 mA
internal clock frequency −−64 MHz
symbol rate 12 − 30 Msymbols/s
Nyquist roll-off − 35 − %

2 −−dB

QPSK mode; note 2

total power dissipation T

=70°C; note 1 − 890 1220 mW

amb

storage temperature −55 − +150 °C
ambient temperature 0 − 70 °C
junction temperature T

=70°C −−125 °C

amb

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8083H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm); body

14 × 20 × 2.8 mm

SOT317-2

1999 Jul 28 4

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1999 Jul 28 5

BLOCK DIAGRAM

Philips Semiconductors Product specification

Satellite Demodulator and Decoder

(SDD3)

I0 to I6

AGC

QA

Q0 to Q6

IA

99, 100, 1, 2,
6, 7, 8

80

94

78

9, 11, 12, 13,
14, 16, 17

SDA SCL

53

I2C-BUS

CONTROL

ADC

COARSE

AGC

ADC

INTERRUPT

CONTROL

A0

52

55

MUX

MUX

54

SCLT TDI

SDAT

65

2

C-BUS

I
TUNER
SWITCH

DIGITAL

PHASE

ROTATOR

DTO

CONTROL

GENERAL PURPOSE

P0 to P5

64 71

DATA I/O

EXPANDER

SQUARE-ROOT RAISED-COSINE

SQUARE-ROOT RAISED-COSINE

Σ∆ CONVERTER

98

TDO

24, 23, 22,
21, 27, 26

BOUNDARY SCAN TEST

TDA8083

ANTI-ALIASING FILTERING

INTERPOLATION

CLOCK

RECOVERY

ANTI-ALIASING FILTERING

INTERPOLATION

CARRIER RECOVERY

(AFC LOOP)

POWER-ON

RESET

39

TCK63TMS69TRST

70

DISEQC AND

TONE BURST

FINE
AGC

91

62

FINE AGC
CONTROL

DIGITAL

PHASE

ROTATOR

DTO

CONTROL

XTALO

XTALI

86

85

OSCILLATOR

AND PLL

CARRIER RECOVERY

(PHASE LOOP)

LOCK

DETECTORS

SYNCHRONIZATION

DE-INTERLEAVER

VITERBI DECODER

REED-SOLOMON DECODER

58

DLOCK

57

VLOCK

56

RSLOCK

28

PDOCLK

50

48
49

61

20

4

PDOSYNC

PDO0
to PDO7

PDOERR
PDOVAL

TEST
TPLL

PRESET

FCE353

29, 30,
31, 33,
34, 35,

38, 45

ENERGY DISPERSAL REMOVAL

INT

OUTSD

POR

DISCTRL

Fig.1 Block diagram.

handbook, full pagewidth

TDA8083

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

PINNING

SYMBOL PIN I/O DESCRIPTION

I2 1 I digital I-input bit 2 (ADC bypass); note 1
I3 2 I digital I-input bit 3 (ADC bypass); note 1
V

SSD1

TPLL 4 I test pin (normally connected to ground)
V

SSD2

I4 6 I digital I-input bit 4 (ADC bypass); note 1
I5 7 I digital I-input bit 5 (ADC bypass); note 1
I6 8 I digital I-input bit 6 (ADC bypass; MSB); note 1
Q0 9 I digital Q-input bit 0 (ADC bypass; LSB); note 1
V

DDD1

Q1 11 I digital Q-input bit 1 (ADC bypass); note 1
Q2 12 I digital Q-input bit 2 (ADC bypass); note 1
Q3 13 I digital Q-input bit 3 (ADC bypass); note 1
Q4 14 I digital Q-input bit 4 (ADC bypass); note 1
V

SSD3

Q5 16 I digital Q-input bit 5 (ADC bypass); note 1
Q6 17 I digital Q-input bit 6 (ADC bypass; MSB); note 1
V

SSD4

V

DDD2

PRESET 20 I input for default mode setting
P3 21 I/O quasi-bidirectional I/O port (bit 3)
P2 22 I/O quasi-bidirectional I/O port (bit 2)
P1 23 I/O quasi-bidirectional I/O port (bit 1)
P0 24 I/O quasi-bidirectional I/O port (bit 0)
V

DDD3

P5 26 I/O quasi-bidirectional I/O port (bit 5)
P4 27 I/O quasi-bidirectional I/O port (bit 4)
PDOCLK 28 O clock output for transport stream bytes
PDO0 29 O parallel data output (bit 0) or serial data output
PDO1 30 O parallel data output (bit 1)
PDO2 31 O parallel data output (bit 2)
V

SSD5

PDO3 33 O parallel data output (bit 3)
PDO4 34 O parallel data output (bit 4)
PDO5 35 O parallel data output (bit 5)
V

SSD6

V

SSD7

PDO6 38 O parallel data output (bit 6)
POR 39 O Power-on reset output
V

DDD4

3 − digital ground 1 (core and input periphery)

5 − digital ground 2 (core and input periphery)

10 − digital supply voltage 1 (core and input periphery)

15 − digital ground 3 (core and input periphery)

18 − digital ground 4 (output periphery)
19 − digital supply voltage 2 (core and input periphery)

25 − digital supply voltage 3 (output periphery)

32 − digital ground 5 (output periphery)

36 − digital ground 6 (core and input periphery)
37 − digital ground 7 (core and input periphery)

40 − digital supply voltage 4 (output periphery)

TDA8083

1999 Jul 28 6

Philips Semiconductors Product specification

Satellite Demodulator and Decoder

TDA8083

(SDD3)

SYMBOL PIN I/O DESCRIPTION

V

DDD5

V

SSD8

V

DDD6

V

DDD7

PDO7 45 O parallel data output (bit 7)
n.c. 46 − not connected
V

SSD9

PDOERR 48 O transport error indicator output
PDOVAL 49 O data valid indicator output
PDOSYNC 50 O transport packet synchronization pulse output
V

SSD10

SCL 52 I serial clock of I
SDA 53 I/O serial data of I
INT 54 O interrupt output (active LOW); note 1
A0 55 I I
RSLOCK 56 O Reed-Solomon lock indicator output
VLOCK 57 O Viterbi lock indicator output
DLOCK 58 O demodulator lock indicator output
V

DDD8

V

DDD9

TEST 61 I test pin (normally connected to ground)
TRST 62 I BST optional asynchronous reset input (normally connected to ground)
TCK 63 I BST dedicated test clock input (normally connected to ground)
SCLT 64 O serial clock of I
SDAT 65 I/O serial data of I
V

DDD10

V

SSD11

V

SSD12

TMS 69 I BST control signal input (normally connected to ground)
TDO 70 O BST serial test data output
TDI 71 I BST serial test data input (normally connected to ground)
V

DDD11

V

SSD13

V

SSD(AD)

V

DDD(AD)

V

ref(B)

V

SSA1

QA 78 I analog input Q
V

ref(Q)

IA 80 I analog input I
V

SSA2

41 − digital supply voltage 5 (core and input periphery)
42 − digital ground 8 (core and input periphery)
43 − digital supply voltage 6 (core and input periphery)
44 − digital supply voltage 7 (output periphery)

47 − digital ground 9 (core and input periphery)

51 − digital ground 10 (output periphery)

2

C-bus input; note 1

2

C-bus input or output; note 1

2

C-bus hardware address input

59 − digital supply voltage 8 (core and input periphery)
60 − digital supply voltage 9 (core and input periphery)

2

C-bus loop-through output; note 1

2

C-bus loop-through input or output; note 1
66 − digital supply voltage 10 (core and input periphery)
67 − digital ground 11 (output periphery)
68 − digital ground 12 (core and input periphery)

72 − digital supply voltage 11 (core and input periphery)
73 − digital ground 13 (core and input periphery)
74 − digital ground ADC
75 − digital supply ADC
76 O bottom reference voltage output for ADC
77 − analog ground 1

79 O AGC decoupling output (Q path)

81 − analog ground 2

1999 Jul 28 7

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

SYMBOL PIN I/O DESCRIPTION

V

ref(I)

V

DDA

V

DD(XTAL)

XTALI 85 I crystal oscillator input
XTALO 86 O crystal oscillator output
V

SS(XTAL)

V

DDD12

V

DDD13

V

SSD14

DISCTRL 91 O 22 or 44 kHz output for dish control applications
V

SSD15

V

SSD16

AGC 94 O tuner AGC output; note 1
n.c. 95 − not connected
V

DDD14

V

DDD15

OUTSD 98 O sigma delta output; note 1
I0 99 I digital I-input bit 0 (ADC bypass; LSB); note 1
I1 100 I digital I-input bit 1 (ADC bypass); note 1

82 O AGC decoupling output (I path)
83 − analog supply voltage
84 − supply voltage for crystal oscillator

87 − ground for crystal oscillator
88 − digital supply voltage 12 (core and input periphery)
89 − digital supply voltage 13 (core and input periphery)
90 − digital ground 14 (core and input periphery)

92 − digital ground 15 (output periphery)
93 − digital ground 16 (core and input periphery)

96 − digital supply voltage 14 (output periphery)
97 − digital supply voltage 15 (core and input periphery)

TDA8083

Note

1. This pin is 5 V tolerant.

1999 Jul 28 8

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

handbook, full pagewidth

V

SSD1
TPLL

V

SSD2

Q0

V

DDD1

Q1
Q2
Q3
Q4

V

SSD3

Q5
Q6

V

SSD4

V

DDD2

PRESET

P3
P2
P1
P0

V

DDD3

P5
P4

PDOCLK

PDO0
PDO1

I1I0OUTSD

99989796959493929190898887868584838281

100

1

I2

2

I3

3
4
5
6

I4

7

I5

8

I6

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

DDD15

V

V

DDD14

n.c

AGC

SSD15

SSD16

DISCTRL

V

V

TDA8083H

SSD14

V

V

DDD12

DDD13

V

V

SS(XTAL)

XTALO

XTALI

TDA8083

SSA2

ref(I)

DDAVDD(XTAL)

V

V

V

IA

80

V

79

ref(Q)

78

QA
V

77

SSA1

V

76

ref(B)

V

75

DDD(AD)

V

74

SSD(AD)

V

73

SSD13

V

72

DDD11

71

TDI
TDO

70

TMS

69

V

68

SSD12

V

67

SSD11

V

66

DDD10

SDAT

65

SCLT

64
63

TCK
TRST

62

TEST

61

V

60

DDD9

V

59

DDD8

DLOCK

58

VLOCK

57

RSLOCK

56
55

A0

54

INT
SDA

53

SCL

52

V

5130

SSD10

31323334353637383940414243444546474849

PDO2

V

SSD5

PDO3

PDO4

PDO5

V

SSD6VSSD7

PDO6

POR

DDD4VDDD5

V

Fig.2 Pin configuration.

1999 Jul 28 9

SSD8

V

DDD6VDDD7

V

PDO7

n.c.

SSD9

V

PDOVAL

PDOERR

50

FCE352

PDOSYNC

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

APPLICATION INFORMATION

handbook, full pagewidth

FRONT
PANEL

CONTROL

4 MHz clock

I

TUNER

ZERO IF

telco i/f

card(s)

Q

smart

TDA8083

(SDD3)

2

I

C-bus

SAA7214

(T-MIPS)

VXX

MODEM

TDA8004

FLASH

AV PES

SAA7215

(DIVA3)

16-Mbit

SDRAM

DRAM

OPTIONAL

16-Mbit

SDRAM

RGB
CVBS/YC

LR

ADAC

1394

L + PHY

BUFFERS

SWITCHING

TDA8083

IEEE 1394

IEEE 1284
RS232

SCART1

SCART2

SCART3

FCE354

Fig.3 Satellite set-top box concept.

1999 Jul 28 10

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

80 51

81

50

Z

A

E

TDA8083

SOT317-2

pin 1 index

100

1

w M

b

0.40

0.25

p

D

H

D

0 5 10 mm

(1)

(1) (1)(1)

D

0.25

0.14

20.1

19.9

14.1

13.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

30

Z

D

scale

eH

H

24.2

0.65

23.6

31

D

e

w M

b

p

B

E

18.2

17.6

E

v M

A

v M

B

LL

p

1.0

0.6

A

H

E

2

A

A

1

detail X

Zywv θ

Z

E

D

0.8

0.15 0.10.21.95

0.4

1.0

0.6

(A )

3

θ

L

p

L

o

7

o

0

OUTLINE

VERSION

SOT317-2

IEC JEDEC EIAJ

REFERENCES

1999 Jul 28 11

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

SOLDERING
Introduction to soldering surface mount packages

Thistext givesa verybriefinsight toa complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount ICpackages. Wavesoldering isnot alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times(preheating, solderingand cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurface mountdevices (SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TDA8083

If wave soldering isused the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wavewith high upward pressurefollowed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages withleads onfoursides, thefootprintmust
be placedat a 45° angleto the transport direction ofthe
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placementand beforesoldering, the packagemust
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads.Use a low voltage(24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jul 28 12

Philips Semiconductors Product specification

Satellite Demodulator and Decoder

TDA8083

(SDD3)

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages arenot suitable for wave soldering asa solder joint between the printed-circuitboard and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is onlysuitable for LQFP, TQFP and QFP packages witha pitch (e) equal to or larger than0.8 mm;

5. Wave solderingis only suitablefor SSOP andTSSOP packages witha pitch (e)equal to orlarger than 0.65 mm;it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporizationof the moisture in them (the so called popcorn effect). For details,refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

1999 Jul 28 13

Philips Semiconductors Product specification

Satellite Demodulator and Decoder

TDA8083

(SDD3)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in suchapplications do so at their ownrisk and agree to fullyindemnify Philips for any damagesresulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components inthe I2C systemprovided the system conformsto the I2C specificationdefined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1999 Jul 28 14

Philips Semiconductors Product specification

Satellite Demodulator and Decoder
(SDD3)

TDA8083

NOTES

1999 Jul 28 15

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS,Via Casati, 23 - 20052 MONZA(MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document doesnot formpart of any quotation or contract, isbelieved to be accurate and reliable and may bechanged
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

67

SCA

Printed in The Netherlands 545004/01/pp16 Date of release:1999 Jul 28 Document order number: 9397 75005355