DATASHEETS tda2579c DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA2579C

Synchronization circuit with
synchronized vertical divider
system for 60 Hz

Preliminary specification
File under Integrated Circuits, IC02

Philips Semiconductors

January 1994

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

FEATURES
Synchronization and horizontal part

• Horizontal sync separator and noise inverter

• Horizontal oscillator

• Horizontal output stage

• Horizontal phase detector (sync to oscillator)

• Triple current source in the phase detector with

automatic selection

• Normal phase detector time constant is increased to fast
during the vertical blanking period (external switching for
VTR conditions not necessary)

• Slow phase detector time constant and gated sync pulse
operation are automatically switched on by an internal
sync pulse noise level detection circuit

• Fast phase detector time is switched on for locking

• Time constant externally switchable

• Inhibit of horizontal phase detector and video transmitter

identification circuit during equalizing pulses and vertical
sync pulse

• Inhibit of horizontal phase detector during separated
vertical sync pulse

• Second phase detector for storage compensation of the
line output stage

• 3-level sandcastle pulse generator

• Automatic adaption of the burst key pulse width

• Video transmitter identification circuit

• Stabilizer and supply circuit for starting the horizontal

oscillator and output stage directly from the mains
rectifier

• Horizontal output current with constant duty factor value
of 55%

• Duty factor of the horizontal output pulse is 55% when
the horizontal flyback pulse is absent.

Vertical part

• fV = 60 Hz (M) system

• Vertical synchronization pulse separator without

external components and two integration times

• Zener diode reference voltage source for the vertical
sawtooth generator and vertical comparator

• Divider system with three different reset enable windows

• Synchronization is set to 528 divider ratio when no

vertical sync pulse and no video transmitter is identified

• Divider window is forced to wide window when a vertical
sync pulse is detected within the window provided by
reset divider and end of vertical blanking period, on
condition that the voltage on pin 18 is ≤1.2 V

• Divider ratio is 528 (f

• Linear negative-going sawtooth generated via the

divider system (no frequency adjustment)

• Comparator with low DC level feedback signal

• Output stage driver

• fV = 60 Hz identification output combined with mute

function

• Start of vertical blanking is shifted to the start of the
pre-equalizing pulses when the divider ratio is between
522 and 528 lines per picture

• Guard circuit which generates the vertical blanking
pulse level on the sandcastle output pin 17 when the
feedback level at pin 2 is not within the specified limits.

GENERAL DESCRIPTION

The TDA2579C is an integrated circuit generating all
requirements for synchronization of its horizontal oscillator
and output stage plus those of the vertical part which
comprises a divider system, sawtooth generator,
comparator and output stage.
The TDA2579C is almost identical to the TDA2579B.
It is optimized for the M (60 Hz) TV system.

TDA2579C

= 60 Hz) for DC signal on pin 5

V

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

TDA2579C 18 DIL plastic SOT102

January 1994 2

PINS PIN POSITION MATERIAL CODE

PACKAGE

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

I

16

minimum required current for starting
horizontal oscillator and output stage

V

10

I

10

main supply voltage − 12 − V
supply current − 70 − mA

Input signals

V

5-9

I

12

V

2

sync pulse input amplitude 0.05 − 1V
horizontal flyback pulse input current 0.2 1 − mA
vertical comparator input voltage

AC (peak-to-peak value) − 0.8 − V
DC − 1 − V

Output signals

V

11

horizontal output voltage
(open collector)

V

1

vertical output stage driver
(emitter follower)

V

17

sandcastle output voltage levels

burst key 9.8 −−V
horizontal blanking − 4.5 − V
vertical blanking − 2.5 − V

IDEO TRANSMITTER IDENTIFICATION OUTPUT; note 1

V
V

13

I

13

V

13

output voltage no sync pulse present −−0.32 V
output current no sync pulse present −−5mA
output voltage sync pulse present;

I11 = 25 mA −−0.5 V

I1 = 1.5 mA 5 −−V

divider ratio <576

6.2 −−mA

− 7.6 − V

Note

1. Open collector loaded with external resistor to positive supply.

January 1994 3

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

horizontal

drive

11

HORIZONTAL

2

ϕ

12 V

1

nF

22

I 6.2 mA

µF

2.7 nF

Ω33 k

Ω4.7 k

9

101615

SWITCH

SUPPLY

START

CIRCUIT

STABILIZER

OSCILLATOR

HORIZONTAL

Ω6.8 k

OUTPUT

TOO LOW

FLYBACK

REFERENCE

to pin 16

CURRENT

PROTECTION

PULSE

PROTECTION

2

ϕ

PHASE

DETECTOR

WIDTH

PULSE

MODULATOR

TDA2579C

MGA791

TDA2579C

12

input

flyback pulse

14

100 nF

47 nF

KEY

BURST

VERTICAL

BLANKING

DIVIDER

VIDEO

TRANSMITTER

13

mute

60 Hz

OUTPUT

SANDCASTLE

GUARD

CIRCUIT

VERTICAL

ZENER

VERTICAL

REFERENCE

IDENTIFICATION

Ω15 k

VERTICAL/

12 V

OUTPUT

VERTICAL

VERTICAL

COMPARATOR

43 2 1 17

SAWTOOTH

OSCILLATOR

GENERATOR

4.7 nF

150 nF

Ω150 k

NOISE

DETECTOR

DETECTOR

SYNC PULSE

NOISE LEVEL

Ω1.2 k

6.8 µF

68 nF

150 pF

video

signal

Ω1 k

input

85

SYNC

VERTICAL/

SEPARATOR

HORIZONTAL

6

Ω5.6 k

2.2µF
R =

PHASE

S

ANTITOP

1

ϕ

REFERENCE

1

ϕ

DETECTOR

NOISE

INVERTER

7

Ω22

F

22

µ

GATING

DETECTOR

COINCIDENCE

18

output

sandcastle

drive

vertical

vertical

feedback

to vertical deflection

current measuring resistor

Ω220 k

Fig.1 Block diagram.

January 1994 4

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

PINNING

SYMBOL PIN DESCRIPTION

V

OUT

FB 2 vertical feedback input
SAW 3 vertical sawtooth generator
VDC 4 vertical deflection current output
VID 5 video signal input
CSL 6 slicing level storage capacitor
RSL 7 slicing level resistor

ϕ

1

GND 9 ground (0 V)
V

P

H

OUT

FLYB 12 horizontal flyback pulse input
MUTE 13 mute output
H

SHIFT

H

OSC

STAB 16 start circuit stabilizer input
SC 17 sandcastle output
DET 18 coincidence detector output

1 vertical driver output

8 phase detector ϕ

1

10 main supply voltage (+12 V)
11 horizontal driver output

14 horizontal picture shift capacitor
15 horizontal oscillator frequency

setting

V

1

OUT

FB

2

SAW

3

VDC

4

VID

5

TDA2579C

CSL

6

RSL

7

ϕ

8

1

GND

9

MGA790

Fig.2 Pin configuration.

TDA2579C

DET

18

SC

17

STAB

16

H

15

OSC

H

14

SHIFT

MUTE

13

FLYB

12

H

11

OUT

V

10

P

FUNCTIONAL DESCRIPTION

The TDA2579C generates both horizontal and vertical
drive signals, a 3-level sandcastle output pulse, a
transmitter identification signal and 60 Hz window
information.

The horizontal oscillator and horizontal output stage
functions are started via the supply current into pin 16.
The required current has a typical value of 5 mA which can
be taken directly from the mains rectifier. The horizontal
output transistor at pin 11 is not conducting until the supply
current at pin 16 has reached its typical value. The starting
circuit has a hysteresis of approximately 1 mA. The
horizontal output current of pin 11 starts at a duty cycle of
60%. All other IC functions are enabled via the main supply
voltage on pin 10.

The pin 16 supply system enables slaved synchronized
switch mode systems in which the horizontal output signal
of the TDA2579C is used as master signal. In such a
system the 12 V supply (main supply at pin 10) can be
generated by the line output stage.

An internal Zener diode reference voltage is used for the
vertical processing part. The IC embodies a synchronized

divider system for generating the vertical sawtooth at
pin 3. Thus no vertical frequency adjustment is required.

The circuit operation is restricted to the M (f

= 60 Hz)

V

system.

Vertical part (pins 1, 2, 3 and 4)

The IC embodies a synchronized divider system for
generating the vertical sawtooth at pin 3. The divider
system has an internal frequency doubling circuit, thus the
horizontal oscillator is operating at its nominal line
frequency and one line period equals 2 clock pulses.
No vertical frequency adjustment is required due to the
divider system. The divider system operates with
3 different reset windows for maximum
interference/disturbance protection.

The windows are activated via an up/down counter.
The counter increases its value by 1 each time the
separated vertical sync pulse is within the window being
searched. The count is reduced by 1 when the vertical
sync pulse is not present.

The reset of the counter system (clock pulse 0) is at half a
line period after the start of the vertical pulse at pin 5.

January 1994 5

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

In accordance with the convention for the M system, field
one line 1 number 1 starts at the first equalizing pulse, the
reset of the divider system is at the start of line 4 for the first
field and in the middle of line 265 for the second field.

Divider system

ODE A: LARGE (SEARCH) WINDOW

M
Divider ratio between 488 and 576.
This mode is valid for the following five conditions:

1. Divider is locking to a new transmitter.

2. Divider ratio found, not being within the narrow window
limits.

3. Up/down counter value of the divider system operating
in the narrow window mode decreases below count 1.

4. External forced setting. This can be achieved by
loading pin 18 with a 220 Ω resistor to earth or by
connecting a 3.6 V stabistor diode between pin 18 and
ground.

5. A vertical sync pulse was detected within the interval
provided by reset divider (at 528) and the end of the
vertical blanking while the voltage at pin 18 is ≤1.2 V.

ODE B: NARROW WINDOW

M
Divider ratio between 522 and 528.
The divider system switches over to this mode when the

up/down counter has reached its maximum value of
12 approved vertical sync pulses in the large window
mode. When count 12 is reached the vertical sync pulse is
tested for the standard TV-norm being the divider ratio

525. When this value is valid for the 12th vertical pulse, the

up/down counter is reset to 0 and the up/down counter
tests for a valid 525 divider ratio. When at the 12th vertical
pulse the divider ratio is not equal to n = 525 then the
divider system remains in the narrow window mode and
remains testing for the standard TV-norm. When the
divider operates in this mode and a vertical sync pulse is
missing within the window the divider is reset at the end of
the window and the counter value is decreased by 1. At a
counter value below count 1 the divider system switches
over to the large window mode.

ODE C: STANDARD TV-NORM

M
Divider ratio 525; fV = 60 Hz.
When the up/down counter has reached its maximum

value of 12 in the narrow window mode and the divider
ratio equals n = 525 the information applied to the up/down
counter is changed such that now the standard divider
ratio value is tested and the up/down counter is reset to 0.

TDA2579C

When the up/down counter reaches the value of
14 approved M TV-norm pulses the divider system is
changed over to the standard divider ratio mode.
In this mode the divider is always reset at the standard
value even if the vertical sync pulse is missing. A missed
vertical sync pulse decreases the counter value by 1.
When the counter reaches the value of 10 the divider
system is switched over to the large window mode. The
standard TV-norm condition provides maximum protection
for video recorders playing tapes with anti-copy guards.

M

ODE D: NO TV TRANSMITTER FOUND

At pin 18 the voltage level is less than 1.2 V.
In this condition, only noise is present and no vertical sync

pulse is detected, the divider is reset to count 528. In this
way a stable picture display at normal height is achieved.

ODE E: VIDEO TAPE RECORDERS IN FEATURE MODE

M

NTSC (M system) 3-speed video tape recorders

It should be noted that some VTRs operating in the picture
search mode, generate such distorted pictures that the no
TV transmitter detection circuit can be activated as the
voltage on pin 18 drops below 1.2 V. This would imply a
rolling picture (Mode D). In general VTRs do use a
re-inserted vertical pulse in the feature mode. Therefore
the divider system has been designed such that the divider
is forced to the wide window mode when V18 is below 1.2 V
and a vertical sync pulse is detected within the window
provided by the reset divider at 528 and the end of the
vertical blanking period.

General

The divider system also generates the anti-top-flutter
pulse which inhibits the Phase 1 detector during the
vertical sync pulse. The width of this pulse depends on the
divider mode. For the divider mode A the start is generated
at the reset of the divider. In modes B and C the
anti-top-flutter pulse starts at the beginning of the first
equalizing pulse sequence. The anti-top-flutter ends after
the second equalizing pulse sequence.

The vertical blanking pulse is also generated via the
divider system. The start is at the reset of the divider while
the blanking pulse ends at count 34, the middle of line 21
of field 1 and at the end of line 283 of field 2.

The vertical blanking pulse generated at the sandcastle
output pin 17 is made by adding the anti-top-flutter pulse
and the blanking pulse. In this way the vertical blanking
pulse starts at the beginning of the first equalizing pulse
when the divider operates in the B or C mode.

January 1994 6

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

Vertical sawtooth

To generate a vertical linear sawtooth voltage a capacitor
should be connected to pin 3. The recommended value is
150 nF to 330 nF. The capacitor is charged via an internal
current source starting at the reset of the divider system.
The voltage on the capacitor is monitored by a comparator
which is also activated at reset. When the capacitor has
reached a voltage value of 5.0 V the voltage is kept
constant until the charging period ends. The charging
period width is 26 clock pulses. At clock pulse 26 the
comparator is switched off and the capacitor is discharged
by an npn transistor current source the value of which can
be set by an external resistor connected between pin 4
and ground (pin 9). Pin 4 is connected to a pnp transistor
current source which determines the current of the npn
current source at pin 3. The pnp current source on pin 4 is
connected to an internal Zener diode reference voltage
which has a typical voltage of 7.5 V. The recommended
operating current range is 10 to 75 µA. The resistor at
pin 4 should be 100 to 770 kΩ. By using a double current
mirror concept the vertical sawtooth pre-correction voltage
can be set to the required value by external components
connected between pins 3 and 4 or by superimposing a
correction voltage in series with the earth connection of the
resistor connected to pin 4.
The vertical amplitude is set by the current of pin 4.

Vertical feedback

The vertical feedback voltage of the output stage has to be
applied to pin 2. For the normal amplitude adjustment the
values are DC = 1 V and AC = 0.8 V (p-p).
The low DC voltage value improves the picture bounce
behaviour as less parabola compensation is required.
Even a DC-coupled feedback circuit is possible.

Vertical guard

The IC also contains a vertical guard circuit. This circuit
monitors the vertical feedback signal on pin 2. When the
level on pin 2 is below 0.35 V or higher than 1.85 V the
guard circuit inserts a continuous voltage level of 2.5 V in
the sandcastle output signal of pin 17. This results in
blanking of the picture displayed, thus preventing a
burnt-in horizontal line.

Vertical driver output

The driver output is at pin 1, it can deliver a drive current
of 1.5 mA at 5 V output. The internal impedance is
approximately 170 Ω. The output pin is also connected to
an internal current source with a sink current of 0.25 mA.

TDA2579C

Integration time of the vertical synchronization pulse separator

The vertical sync separator has two integration times:

• long time; typical 19 µs, valid for 1.8 ≤ V
(no noise detected)

• short time; typical 12 µs, valid for noise detected and
V18≥ 1.2 V.

When V18 drops below 1.2 V, the integration time is forced
back to 19 µs to prevent switching of the divider system to
the wide window mode for noise only conditions.

Sync separator, phase detector and TV-station
identification (pins 5, 6, 7 and 18)

SYNC SEPARATOR

The video input signal is connected to pin 5. The sync
separator is designed such that the slicing level is
independent of the amplitude of the sync pulse. The black
level is measured and stored in the capacitor at pin 7. The
slicing level is stored in the capacitor at pin 6. The slicing
level value can be chosen by the value of the external
resistor connected between pins 6 and 7. The value is
given by the formula:

R

S

p

--------------------- -

5.3 RS×

Where RS is the resistor connected between pins 6 and 7
and the top sync levels equals 100%. The recommended
resistor value is 5.6 kΩ.

BLACK LEVEL DETECTOR

A gating signal is used for the black level detector. This
signal is composed of an internal horizontal reference
pulse with a duty factor of 50% and the flyback pulse at
pin 12. In this way the TV transmitter identification
operates also for all DC conditions at input pin 5 (no video
modulation, plain carrier only).
During the vertical blanking interval the slicing detector is
inhibited by a signal which starts with the anti-top-flutter
pulse and ends with the reset of the vertical divider circuit.
In this way shift of the slicing level due to the vertical sync
signal is reduced and separation of the vertical sync pulse
is improved.
An internal noise inverter is activated when the video level
at pin 5 decreases below 0.7 V.

100 R

value in kΩ().×=

S

18

≤ 7.8 V

January 1994 7

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

NOISE LEVEL DETECTOR

The IC also embodies a built-in sync pulse noise level
detection circuit. This circuit is directly connected to pin 5
and measures the noise level at the middle of the
horizontal sync pulse. When a signal-to-noise level (S/N)
of ≤19 dB is detected a counter circuit is activated.

S/N

= 20 log

A video input signal is processed as "acceptable noise
free" when 12 out of 15 sync pulses have a noise level
below 19 dB for successive field periods. The sync pulses
are processed during a 15 line width gating period
generated by the divider system. The measuring circuit
has a built-in noise level hysteresis of approximately 3 dB.
The use of a filter of 1 kΩ and 150 pF in front of pin 5
reduces the noise content of the CVBS signal by
approximately 6 dB.
When the "acceptable noise free" condition is found the
phase detector of pin 8 is switched to not gated and normal
time constant. When a higher sync pulse noise level is
found the phase detector is switched over to slow time
constant and gated sync pulse detection. At the same time
the integration time of the vertical sync pulse separator is
reduced providing V

PHASE DETECTOR (SEE FIG.3)

The phase detector circuit is connected to pin 8. This
circuit consists of 3 separate phase detectors which are
activated depending on the voltage of pin 18 and the state
of the sync pulse noise detection circuit. For normal and
fast time constants all three phase detectors are activated
during the vertical blanking period, this with the exception
of the anti-top-flutter pulse period, and the separated
vertical sync pulse time. As a result, phase jumps in the
video signal related to the video head, take over of video
recorders are quickly restored within the vertical blanking
period. At the end of the blanking period the phase
detector time constant is increased by a factor of 1.4.
In this way there is no requirement for external VTR time
constant switching, and thus all station numbers are
suitable for signals from VTR, video games or home
computers.

Video voltage (black-to-white signal)

----------------------------------------------------------------------------------------------- ­Noise (RMS)

> 1.2 V.

18

TDA2579C

For quick locking of a new TV station starting from a noise
only signal condition (normal time constant) a special
circuit is incorporated. A new TV station which is not
locked to the horizontal oscillator will result in a voltage
decrease below 0.1 V at pin 18. This will activate a field
period counter which switches the phase detector to fast
for 3 field periods during the vertical scan period.
The horizontal oscillator will now lock to the new TV station
and as a result, the voltage on pin 18 will increase to
approximately 6.5 V. When pin 18 reaches a level of 1.8 V
the mute output transistor of pin 13 is switched off and the
divider is set to the large window. In general the mute
signal is switched off within 5 ms (C
reception of a new TV signal. When the voltage on pin 18
reaches a level of 5 V, usually within 15 ms, the field
counter is switched off and the time constant is switched
from fast to normal during the vertical scan period.

If the new TV station is weak, the sync noise detector is
activated. This will result in a change over of pin 18 voltage
from 6.5 V to approximately 10 V. When pin 18 exceeds
the level of 7.8 V the phase detector is switched to slow
time constant and gated sync pulse condition.
The phase detector output current during the blanking
period is now reduced from 2 mA to 1.35 mA.
When desired, most conditions of the phase detector can
also be set by external means in the following way:

• fast time constant, TV transmitter identification circuit
not active, connect pin 18 to ground (pin 9)

• fast time constant, TV transmitter identification circuit
active, connect a 220 kΩ resistor between pin 18 and
ground; this condition can also be set by using a 3.6 V
stabistor diode instead of a resistor

• slow time constant (with the exception of the vertical
blanking period), connect pin 18 via a 10 kΩ resistor to
+12 V (pin 10); in this condition the transmitter
identification circuit is not active

• no switching to slow time constant required (transmitter
identification circuit active), connect a 6.8 V Zener diode
between pin 18 and ground.

= 47 nF) after

18

January 1994 8

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

mute

(pin 13)

gating

ϕ

detector

1

ϕ

detector

1

I80.35 mA

ϕ

detector

2

I81.0 mA

not gated

ϕ

detector

3

I80.65 mA

not gated

ABCDEFG

voltage

(pin 18)

0.1 V 1.2 V 1.8 V 3.5 V 5 V 7.8 V

TDA2579C

1
0

1
0

1
0

1

0

1

0

MGA792

Fig.3 Operation of the three phase detector circuits.

Explanation of areas A to G shown in Fig.3

A switching over to new TV station activates 3 field

period counter
B noise only condition
C TV transmitter identification hysteresis range
D fast time constant
C-E fast time constant hysteresis range
F normal time constant
G sync pulse noise level detection circuit forces

pin 18 to >7.8 V while signal-to-noise level

<19 dB; slow time constant and gated sync pulse

operation.

Supply (pins 9, 10 and 16)

The IC has been designed such that the horizontal
oscillator and output stage operate a very low supply
current into pin 16. The horizontal oscillator starts at a
supply current of approximately 4 mA (V16 approximately
6 V). The horizontal output stage is forced into the
non-conducting stage until the supply current has reached
a typical value of 5 mA.
The circuit has been designed such that after starting the
horizontal output function, a current drop of approximately
1 mA is allowed.
The starting circuit has the ability to derive the main supply
(pin 10) from the horizontal output stage. The horizontal
output signal can also be used as oscillator signal for
synchronized switched-mode power supplies.

January 1994 9

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

The maximum allowed starting current is 9.7 mA
(T

=25°C).

amb

The main supply should be connected to pin 10 and pin 9
should be used for ground. When the voltage on pin 10
increases from zero to its final value (typ. 12 V) a part of
the supply current of the starting circuit is taken from pin 10
via internal diodes and the voltage on pin 16 will stabilize
on a typical value of 9.3 V. In stabilized conditions
(V10> 10 V) the minimum required supply current into
pin 16 is approximately 2.5 mA.
All other IC functions are switched on via the main supply
voltage on pin 10. When this voltage reaches a value of
approximately 7 V the horizontal phase detector is
activated and the vertical ramp on pin 3 is started. The
second phase detector circuit and burst pulse circuit are
started when the voltage on pin 10 reaches the stabilized
voltage value of pin 16 typical 9.3 V.

To close the second phase detector loop a flyback pulse
must be applied to pin 12. When no flyback pulse is
detected the duty factor of the horizontal output stage
is 50%.
For remote switch-off pin 16 can be connected to ground
(via a npn transistor with a collector series resistor of
approximately 500 Ω) which decreases pin 16 voltage to
≤5 V and switches off the horizontal output pulse.

Horizontal oscillator, horizontal output transistor and second phase detector

The horizontal oscillator is connected to pin 15. The
frequency is set by an external RC combination between
pin 15 and ground (pin 9). The open collector horizontal
output stage is connected to pin 11. An internal Zener
diode configuration limits the open voltage of pin 11 to
approximately 14.5 V. The horizontal output transistor at
pin 11 is blocked until the current into pin 16 reaches a
value of approximately 5 mA.
A higher current results in a horizontal output signal at
pin 11, which starts with a duty factor of approximately
40% HIGH.
The duty factor is set by an internal current-source-loaded
npn emitter follower stage connected to pin 14 during
starting. When pin 16 changes over to voltage stabilization
the npn emitter follower and current source load at pin 14
are switched off and the second phase detector is
activated, provided a horizontal flyback pulse is present at
pin 12. When no flyback pulse is detected at pin 12 the
duty factor of the horizontal output stage is set to 50%. The
phase detector circuit at pin 14 compensates for storage
time in the horizontal deflection output state.

TDA2579C

The horizontal output pulse duration is 29 µs HIGH for
storage times between 1 µs and 17 µs (flyback pulse of
12 to 29 µs). A higher storage time increases the
HIGH time.
Horizontal picture shift is possible by forcing an external
charge or discharge current into the capacitor at pin 14.

Mute output and 60 Hz identification (pin 13)

The collector of an npn transistor is connected to pin 13.
When the voltage on pin 18 drops below 1.2 V (no TV
transmitter) the npn transistor is switched on. When the
voltage on pin 18 increases to a level of approximately

1.8 V (new TV transmitter found) the npn transistor is
switched off.
This function is available when pin 13 is connected to
pin 10 (+12 V) via an external pull-up resistor of 10 to
20 kΩ. When no TV transmitter is identified the voltage on
pin 13 will be LOW (<0.5 V).
When an M-system TV transmitter with a divider ratio<576
(60 Hz) is found an internal pnp transistor with its emitter
connected to pin 13 will force the output voltage down to
approximately 7.6 V.

Sandcastle output (pin 17)

The sandcastle output pulse generated at pin 17 has three
different voltage levels. The highest level (10.4 V) can be
used for burst gating and black level clamping. The second
level (4.5 V) is obtained from the horizontal flyback pulse
at pin 12 and is used for horizontal blanking. The third level
(2.5 V) is used for vertical blanking and is derived via the
vertical divider system. For 60 Hz the blanking pulse
duration is 34 clock pulses started from the reset of the
vertical divider system.

For TV signals which have a divider ratio between 522 and
528 the vertical blanking pulse is started at the first
equalizing pulse.

January 1994 10

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

LIMITING VALUES

In accordance with Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

I

16

V

P

P

tot

T

stg

T

amb

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

R

th j-a

CHARACTERISTICS

V

= V10 = 12 V; I16 = 6.2 mA; T

P

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

start current V10 = 0 V − 9.7 mA
supply voltage − 13.2 V
total power dissipation − 1.2 W
storage temperature −55 +150 °C
operating ambient temperature −25 +70 °C

from junction to ambient in free air 50 K/W

= 25 °C; unless otherwise specified.

amb

Supply

V

P

I

16

V

16

I

10

supply voltage (pin 10) 10 12 13.2 V
supply current (pin 16) note 1

= 0 V 6.2 − 9.7 mA

V

10

= 1 to 10 V;

V

10

T

≤ 70 °C

amb

> 10 V 2.5 − 9.7 mA

V

10

6.2 − 8.7 mA

stabilized voltage (pin 16) 8.8 9.3 9.7 V
current consumption (pin 10) − 70 85 mA

Video input (pin 5)

V
V

5
5(p-p)

top sync level 1.5 3.1 3.75 V

sync pulse amplitude (peak-to-peak value) note 2 0.05 0.6 1 V
SL slicing level note 3 35 50 65 %
t

d

delay between video input and detector

see Fig.5 0.2 0.3 0.55 µs

output
S/N signal-to-noise ratio with sync pulse noise

level detector circuit active

CVBS = 1 V without
filter at pin 5; note 4

− 19 − dB

Sync pulse

HYS noise level detector circuit hysteresis − 3 − dB

Noise gate (pin 5)

V

5

switching level − 0.7 1 V

January 1994 11

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

First control loop (pin 8) horizontal oscillator to synchronization signal

∆f holding range ±700 ±800 − Hz
∆f catching range ±700 ±800 ±1100 Hz
α

CS

ϕ

10

ϕ

16

Second control loop (pin 14) horizontal flyback to horizontal oscillator

/∆t

∆t

d

t

d

t

d

control sensitivity video with respect to burst

key and flyback pulse:

slow time constant note 5 − 2 − kHz/µs
normal time constant note 6 − 5 − kHz/µs
fast time constant note 6 − 3 − kHz/µs

phase modulation due to hum on the supply

note 7 − 0.2 −µs/V

line (peak-to-peak value)

phase modulation due to hum on the input

note 8 − 0.08 −µs/V

current (peak-to-peak value)

control sensitivity td = 10 µs 200 300 600 µs/µs

o

control range 1 − 45 µs

control range for constant duty factor

129−tFB−µs

horizontal output

control edge of horizontal output signal

− positive −

(pin 11)

Phase adjustment (pin 14) via second control loop

α

CS

I

14

Horizontal oscillator (pin 15) C

f

H

∆f

H

control sensitivity td = 10 µs − 25 −µA/µs

maximum allowed control current −−±60 µA

= 2.7 nF; R

osc

= 34.2 kΩ

osc

frequency (no sync) − 15625 − Hz

spread (fixed external components,

−−±4%

no sync)
∆f

H

frequency deviation between starting point

− +5 +8 %

output signal and stabilized condition
TC temperature coefficient −−1.10

Horizontal output (pin 11) open collector

V

11H

V

11

HIGH level output voltage −−13.2 V

start voltage protection

13 − 15.8 V

(internal Zener diode)
I

16L

LOW level input current protection output

− 5.0 6.2 mA

enabled
V

11L

δ duty factor output current during starting I
V

11L

δ duty factor output current without flyback

LOW level output voltage start condition I11 = 10 mA − 0.1 0.5 V

= 6.2 mA 50 60 70 %

16

LOW level output voltage normal condition I11 = 25 mA − 0.3 0.5 V

45 50 55 %

pulse pin 12

-4

− K

January 1994 12

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

OH

TC temperature coefficient −−4.10
∆H

W/Hd

Sandcastle output signal (pin 17)

V

17

V

17

t

P

V

12

t

d1

t

d2

duration of output pulse HIGH storage time

27 29 31 µs
horizontal deflection
stage = 10 µs

-2

− K

influence of delay time on pulse width of

− 0.16 −µs/µs

horizontal output signal
controlled edge − positive −

output voltage during:

burst key 9.8 10.4 − V
horizontal blanking I
vertical blanking I

zero level output voltage I

= 1 mA 4.1 4.5 4.9 V

load

= 0.3 mA 2.1 2.5 2.9 V

load

= 0.5 mA − 0.7 − V

sink

burst key pulse width 60 Hz 3.4 3.65 4 µs
horizontal blanking level − 1 − V
vertical blanking note 9
phase position burst key time between

2.3 2.7 3.1 µs
middle sync pulse at pin 5 and start burst
key pulse at pin 17

phase position burst key time between start

60 Hz −−9.1 µs
sync pulse at pin 5 and end of burst key
pulse at pin 17

Coincidence detector, video transmitter identification circuit and time constant switching levels (see Fig.1)

I

18

V

18

V

18

V

18

V

18

detector output current − 0.25 − mA
voltage level for in sync condition ϕ1 normal 5.8 6.4 7 V
voltage level for noisy sync pulse ϕ1 slow and gated 9 10.1 − V
voltage level for noise only note 10 − 0.3 − V
switching level:

normal to fast <3.2 3.5 3.8 V
mute output active and fast to normal <1.0 1.2 1.4 V
field period counter 3 periods fast <0.08 0.12 0.16 V
normal to fast mute output inactive locking >1.5 1.75 2 V
fast to normal locking >4.7 5 5.3 V
normal to slow gated sync pulse >7.4 7.8 8.2 V

Video transmitter identification output (pin 13)

V

13

I

13

I

13

60 Hz identification (pin 13) R

V

13

output voltage active no sync; I13 = 2 mA − 0.15 0.32 V
sink current active no sync; V13 = 1 V −−5mA
output current inactive sync 60 Hz −− 1µA

positive supply 15 kΩ

13

pnp emitter follower voltage note 11 7.2 7.65 8.1 V

January 1994 13

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Flyback input pulse (pin 12)

V

12

I

12

V

12(p-p)

R

12

t

d

Vertical ramp generator (pin 3)

t

c

I

3

V

3

V

3(p-p)

switching voltage level − 0.9 − V
input current 0.2 − 3mA
input pulse (peak-to-peak value) −−12 V
input resistance − 3.5 − kΩ
phase position without shift; time between

2.1 2.5 2.9 µs
the middle of the sync pulse at pin 5 and the
middle of the horizontal blanking pulse at
pin 17

charge current pulse width − 26t

clk

−

charge current − 3 − mA
top level ramp signal voltage divider in

note 12 4.55 4.85 5.25 V

60 Hz mode
ramp amplitude (peak-to-peak value);

C3 = 150 nF; note 12 − 2.5 − V

R4 = 330 kΩ; fV = 60 Hz

Current source (pin 4)

V

4

I

4

output voltage I4 = 20 µA 7 7.5 7.9 V
allowed current range T

TC temperature coefficient output voltage I

Current source (pin 3)

I

3/4

TC temperature coefficient I

current ratio pin 3/pin 4 I4= 35 µA; V3 = 2 V − 1.05 −

3

Comparator (pin 2)

V

V

I

2

2

2(p-p)

input voltage DC level R4 = 330 kΩ;

input voltage AC level (peak-to-peak value) R4 = 330 kΩ;

input current V2 = 0 V −−1µA

Vertical output stage (pin 1) npn emitter follower

V

1

R

S

I

sink

maximum output voltage I1 = +1.5 mA; note 12 5 5.5 6.3 V
sync separator resistor − 170 −Ω
continuous sink current − 0.25 − mA

Vertical guard circuit (pin 2)

V

2H

V

2L

active switching level HIGH V17 = 2.5 V; note 12 >1.7 1.85 2.0 V
active switching level LOW V17 = 2.5 V; note 12 <0.25 0.35 0.45 V

= 25 to 70 °C10 − 75 µA

amb

= 40 µA − 50 − 10-6/K

4

I4 = 40 µA; R4 fixed − 100 − 10-6/K

0.98 1.075 1.17 V

C3 = 150 nF

− 0.8 − V

C3 = 150 nF

January 1994 14

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Internal vertical sync pulse separator

t

d1

delay between video signal at pin 5 and
internally separated vertical sync pulse;
normal signal condition

t

d2

delay between video signal at pin 5 and

V18≥ 1.2 V −− −17 µs
internally separated vertical sync pulse;
noisy signal condition

Notes to the characteristics

1. Value inclusive R

pin 11 to pin 16 = 6.8 kΩ.

L

2. Up to 1 V peak-to-peak the slicing level is constant, at amplitudes exceeding 1 V peak-to-peak the slicing level will
increase.

3. The slicing level is fixed by the formula:

R

p

s

-------------------- -

5.3 Rs×

100%.×=

Where RS is the resistor between pins 6 and in kΩ; top sync = 100%.

12 19 25 µs

4. S/N

= 20 log

Video voltage (black-to-white signal)

----------------------------------------------------------------------------------------------- ­Noise (RMS)

A low-pass filter of 1 kΩ and 150 pF decreases the noise content of the CVBS signal by 6 dB.

5. Undercompensated.

6. Overcompensated.

7. Measured between pin 5 and sandcastle output pin 17.

8. Measured with 3.3 µF feedback capacitor between pin 16 and 6.8 µF capacitor in PLL filter pin 8.

9. Maximum divider ratio (60 Hz):

×

2f

H

n

-------------­f

576 (2 clock pulses per video line).==

V

Start vertical blanking:

− search (large) window mode (60 Hz)

− reset divider = start vertical sync pulse plus 1 clock pulse

− small/standard window mode (60 Hz)

− clock pulse 517.

Stop vertical blanking:

− all window modes (60 Hz)

− clock pulse 34.

10. Depends on DC level of pin 5, value given is valid for V
2f

×

H

11. Valid for

--------------

f

V

576.<

≈ 5V.

5

12. Value related to internal Zener diode reference voltage. Spread includes complete spread of reference voltage.

January 1994 15

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

0

10

26
34

130

160

vertical sawtooth charge pulse

start

blocking pulse phase detector 1
vertical blanking

end of blocking pulse (60 Hz)

end of vertical sawtooth charge pulse
end of vertical blanking (60 Hz)

noise detector window

TDA2579C

search mode

488
517

search

window

One video line equals two counter pulses.
Reset counter 32 µs after start of vertical sync pulse at pin 5.
Reset counter = counter state 0.

60 Hz

identification

525

528

576

MGA793

blocking pulse phase detector 1 (60 Hz)

start

vertical blanking (60 Hz)

normal reset

reset divider when mute is active; no vertical sync found

Fig.4 Counter system.

normal and narrow window

January 1994 16

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

video input

signal V

separated
horizontal

sync pulse

ϕ detector

1

reference

ϕ detector

1
output I

horizontal

oscillator
sawtooth

horizontal

flyback

pulse

internal

gating

pulse

coincidence

detector

output I

ϕ detector

2

reference

external

horizontal

flyback

pulse V

12-9

ϕ detector

2

output I

5-9

18

14

8

0.3 s

storage time

horizontal

deflection stage

µ

3.75 s

2.5 s

µ

1/2 t

4.7 s

µ

7.5 s

FB

µ

3.75 s

µ

t

FB

TDA2579C

ϕ reference level

1

ϕ reference level

2

µ

switching level

0V

1/2 t

FB

horizontal

output

signal V

sandcastle

output

signal V

11-9

17-9

29 s

µ

µ

6 s

divider in search window mode

60 Hz: 34 clock pulses

other divider modes

60 Hz: 42 clock pulses

Two counter pulses equals one video line.

Fig.5 Timing diagram.

January 1994 17

12 sµ

t

P

0.2 s

µ

10.4 V

4.5 V

2.5 V

0.7 V

MGA794

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

12 V

16

10

detector

2

ϕ

FLYBACK HORIZONTAL OUTPUT

HORIZONTAL

DETECTORϕ

2

pin 16

Ω

k

6.8

3.0 mA

100 nF

0.2 mA

pin 16pin 10

11121415876

Ω

k

5.6

G

Ω

11

pin 10

pin 16

k

G

Ω

Ω

3.9 kΩ2.2 k

2.2 k

F

G

I

start up

H

H

II

2

ϕ

I

stabilizer

TDA2579C

9

0.8 mA

1.4 mA

MGA796

Ω

k
15

12 V

Ω

1 k

Ω

Ω

160

Ω

11

1.8 k

k

2.7Ωk

SUPPLY

1.4 mA

60 Hz

identification

Ω

Ω

6

12 k

k

TRANSMITTER IDENTIFICATION SANDCASTLE

Ω

Ω

12

k

k

1.2

Ω

E

EFD

Ω

33 kΩ4.7 k

2.7 nF

F6.8

Ω

µ

1.2 k

68 nF

F22

µ

Ω

22

Ω

k

5.6

F2.2

µ

36 k

9.5Ωk

stabilizer

Ω

6.2Ωk

5.6

D

18Ωk

Ω

560Ω880

Ω

560Ω880

Ω

560Ω880

Ω

4

k

Ω

360

Ω

k

A

ref
V

2.8 V

2.4Ωk

C

4.7Ωk

C

8.4Ωk

C

A

4.3Ωk

9

Ω

220

2 V reference

Ω

k

C

start up

6.2Ωk

TDA2579C

HORIZONTAL OSCILLATOR

2.4Ωk

0 V

DETECTORϕ

1

A

Ω

11

k

B

A

Ω

k

10.5

SYNC SEPARATOR

noise

detector

3.5Ωk

Ω

2

k

Ω

1

k

Ω

Ω

10 k

6

k

Ω

2 k

5

VERTICAL DRIVER COINCIDENCE DETECTOR

VERTICAL COMPARATOR

stabilizer

V

B

INPUT

VIDEO

VERTICAL SAWTOOTH GENERATOR

1 k

Ω

5.1 k

A250

A250

µ

µ

Ω

2

k

Ω

160Ω150

K

K

Ω

k

2.15

Ω

2 k

I

Ω

1.5 k

Ω

1.5 k

Ω

k

1.3

7.7Ωk

Ω

200

stab

V

100 nF

4.3Ωk

4.3Ωk

3.6Ωk

F4.7

µ

Ω

k
43

I

150 nF

Ω

k

150

4 3 2 1 18 13 17

Ω

k
220

Fig.6 Internal circuitry

January 1994 18

Ω

1 k

150 pF

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

98 576 4321

220

Ω4.7

µF

26 V

DEFLECTION

VERTICAL DEFLECTION CIRCUIT

100µF

COIL

1000

µF

TDA3654

BAX12

Ω560

Ω270

Ω1 k

TDA2579C

(1)

1 nF 10 nF

(1)

470 pF

Ω4.3 k Ω4.3 k

Ω43 k

horizontal

drive

100

µF

68 nF

9

12 V

video

input

6.8

22

µF

µF

Ω1.2 k

85

2.2µF150
pF

Ω22

Ω5.6 k

76

220

Ωk

1

Ωk

150

Ωk

4321

0.5

Ω

Ω3.6 k

4.7 µF

150 nF

TDA2579C

11

1210 1615

Ω12 k

Ω39 k

horizontal

flyback

0.2 to

3.0 mA

13 14

Ω6.8 k

100

nF

47

Ωk

horizontal

shift

100Ωk33

4.7

f adj.

o

10

2.7
nF

Ωk

Ωk

nF

6.2 mA to 9.7 mA

start

voltage

4.7
nF

Ω1 k

17

22
µF

18

MGA795

100 nF

sandcastle
transmission

identification
60 Hz
identification

(1) Dependent on printed-circuit board layout.

Fig.7 TDA2579C and TDA3654 combination 110° Flat Square picture tube.

January 1994 19

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

PACKAGE OUTLINE

22.00

21.35

seating plane

3.9

3.4

0.85
max

18

1

2.54
(8x)

1.4 max

0.53
max

10

9

0.51
min

0.254 M

6.48

6.14

3.7

max

4.7

max

0.32 max

TDA2579C

8.25

7.80

7.62

9.5

8.3

MSA259

Dimensions in mm.

Fig.8 18-lead dual in-line; plastic (SOT102).

SOLDERING
Plastic dual in-line packages

Y DIP OR WAVE

B
The maximum permissible temperature of the solder is

260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply the soldering iron below the seating plane (or not
more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.

January 1994 20

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

January 1994 21

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

NOTES

TDA2579C

January 1994 22

Philips Semiconductors Preliminary specification

Synchronization circuit with synchronized
vertical divider system for 60 Hz

NOTES

TDA2579C

January 1994 23

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
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Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

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KWAI CHUNG, Tel. [phone], Fax. [phone]

India: PEICO ELECTRONICS & ELECTRICALS Ltd.,

Components Dept., Shivsagar Estate, Block 'A',
Dr. Annie Besant Rd., Worli, BOMBAY 400 018,
Tel. [phone], Fax. [phone]

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P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

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Metro MANILA, Tel. [phone], Fax. [phone]

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Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978,

TAIPEI 10446, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

60/14 MOO 11, Bangna - Trad Road Km. 3
Prakanong, BANGKOK 10260,
Tel. [phone] to 9, (2)398-2083, Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD27 © Philips Electronics N.V. 1993

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other industrial or intellectual property rights.

Printed in The Netherlands 9397 725 20011

Philips Semiconductors