DATASHEETS tda10045 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA10045

Single Chip DVB-T Channel
Receiver

Preliminary specification
File under Integrated Circuits, IC02

2000 March 15

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

FEATURES

• 2K and 8K COFDM demodulator (Fully DVB-T compliant : ETS 300-744).

• All modes supported including hierarchical modes.

• Fully automatic transmission parameters detection.

• DSP based synchronization (upgradability).

• No extra-host software required.

• On chip 10-bit ADC.

nd

or 1st IF variable analog input.

• 2

• Only fundamental Crystal oscillator needed.

• Frequency offset estimator to speed up the scan.

• RF Tuner input power measurement

• Parallel or serial transport stream interface.

• On chip FEC decoder.

• BER measurement (before and after Viterbi decoder)

• SNR estimation

• TPS bits I2C readable (including spare ones)

• Channel frequency response output.

• Controllable dedicated I2C tuner bus (5V tolerant).

• 2 low frequency spare DAC. (∆Σ

• Spare I/O.

• CMOS 0.2

m technology.

µ

)

APPLICATIONS

• DVB-T fully compatible.

• Digital data transmission using COFDM modulations.

DESCRIPTION

The TDA10045 is a single chip channel receiver for 2K and 8K COFDM modulated signals based on the ETSI
specification (ETSI 300 744). The device interfaces directly to an IF signal, which could be either first or second
IF and integrates a 10-bit AD converter, a NCO and a PLL, simplifying external logic r equirements and limiting
system costs.

The TDA10045 performs all the COFDM demodulation tasks from IF signal to the MPEG2 tr ansport stream. An
internal DSP core manages the synchronization and the control of the demodulation process, and implements
specialy developed software for robustness against co and adjacent channel interferers, to deal with SFN echoes
situations, and to help for a very fast scan of the bandwidth.
After base band conversion and FFT demodulation, the channel frequency response is estimated based on the
scattered pilots, filtered in both time and frequency domains. This estimation is used as a correction on the
signal, carrier by carrier. A common phase error and estimator is used to deal with the tuner phase noise.
The FEC decoder is automatically synchronized thanks to the frame synchronization algorithm that uses the TPS
information included in the modulation.

This device is controlled via an I2C bus (called master). The chip provides 2 switchable I2C bus derived from the
master. A tuner I2C bus to be disconnected from the I2C master when not necessary and an Eeprom I2C bus.
The DSP software code can be fed to the chip via the master I2C bus or via the dedicated Eeprom I2C bus.

Designed in 0.2 µm CMOS technology and housed in a 100-pin MQFP package, the TDA10045 operates over
the commercial temperature range.

2000 March 15 2

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

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VAGC

Digital IF

FI(9:0)

Analog IF
(VIM,VIP)

SACLK

XIN

SP-IN(1:0)

CTRL_VCXO

DS_SPARE(1:0)

SCL_EEP

SDA_EEP

SCL
SDA

10

Fsamp

2Fsamp

PLL

A
D
C

spare inputs

3 spare

optional

I2C

Interface

AGC

∆Σ

AND OFDM

DEMODULATION

DIGITAL FRONT-END

10

Base
Band

Conversion

NCO

Carrier

Recovery

FFT

Coarse

Time

Estimator

OAK+ DSP CORE

∆Σ

3 * 10

SYNCHRONISATION

CHANNEL ESTIMATION

AND CORRECTION

OFDM

Spectrum

CPE

Calculation

Partial

Channel

Estimation

Time

Interpolation

Frequency

Interpolation

Frequency, Timing, Frame Recovery

FFT Window positioning

TPS decoding

Confidence
Calculation

Channel

Correction

SCL_TUN
SDA_TUN

DO

OCLK

DEN

PSYNC

UNCOR

MPEG2

Output

Interface

Descrambler

RS

decoder

CHANNEL DECODER

2000 March 15 3

Outer

Forney

Deinterleaver

Confidence

Frequency

response

Viterbi

Decoder

VBER CBERCPT_UNCOR

Bit

Deinterleaver

(I,Q)

Constellation

Inner

Frequency

Deinterleaver

& Demapper

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

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SYMBOL PIN NUMBER TYPE DESCRIPTION

CLOCK AND RESET SIGNALS

CLR# 14 I Asynchronous reset signal, active low

XIN

XOUT 79 O Crystal oscillator output pin.

SACLK

CTRL_VCXO

80

33

(3.3V)

3O

(3.3V)

DEMODULATOR SIGNALS

FI[9:0] 34-35-36-37-38-

41-42-43-44-45

30

FFT_WIN

VAGC 4 O

FEL

IT

49 0D
48

IO TRI Input data fr om an external ADC, FI must be tied to ground when not

IO TRI

(3.3V)

(5V)

(5V)

Crystal oscillator input pin. Typically a fundamental XTAL oscillator is

I

connected between XIN and XOUT.

Sampling frequency output. This output clock can be fed to an external

O

(10-bit) ADC as sampling clock. Depending on “Sel_Saclk” (Reg
CONFADC), SACLK could also provide twice the sampling clock.
If not in NCO mode, control of an external sampling VCXO (after low­pass filtering)

used, positive notation (from 0 to 1023) or two's complement notation
(from -512 to 511). In internal ADC mode, these outputs can be used
to monitor extra demodulator output signal (constellation, frequency
response).
Output or input signal indicating the start of the active data; equals 1
during complex sample 0 of the active FFT block. Can be used to
synchronize 2 chips.
output value from the Delta-Sigma Modulator, used to control a log­scaled amplifier (after analog filtering )
front end lock. FEL is an output drain output and therefore requires an
external pull up resistor.
Interrupt line. This output interrupt line can be configured by the I2C

OD

interface. See registers Itsel and Itstat. IT is an open drain output and
therefore requires an external pull up resistor.

FEC OUTPUTS

DO[7:0] 67-68-69-72-73-

74-75-76

OCLK 66 O

DEN 65 O

PSYNC 64 O

UNCOR 63 O

2000 March 15 4

O

(3.3V)

(3.3V)

(3.3V)

(3.3V)

(3.3V)

output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default. When
the serial mode is selected, the output data is delivered by DO[0].
Output CLock. OCLK is the output clock for the parallel DO[7:0]
outputs. (may be inverted, see POCLK and DISABLE_TS I2C
registers)
output data validation signal active high during the valid and regular
data bytes (may be inverted, see PDEN and DISABLE_TS I2C
registers).
Pulse Synchro. This output signal goes high on a rising edge of OCLK
when a synchro byte is provided, then goes low until the next synchro
byte (may be inverted, see PPSYNC and DISABLE_TS I2C registers).
RS error flag, active high on one RS packet if the RS decoder fails in
correcting the errors (may be inverted, see PUNCOR and
DISABLE_TS I2C registers).

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

ON-CHIP ADC SIGNALS

92

VIM

91

VIP

VREFP

VREFM

VD1
VS1 99 I Ground return for the digital switching circuitry.
VD2
VS2 97 I Ground return for the analog clock drivers.
VD3
VS3 96-89 I Ground return for analog circuits.

94
93

100

98

95-90

Negative input to the A/D converter. This pin is DC biased to half
supply through an internal resistor divider (2x20K resistors). In order

I

to remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between -0.5 and 0.5 volts (See SW I2C
register).
Positive input to the A/D converter. This pin is DC biased to half supply
through an internal resistor divider (2x20K resistors). In order to

I

remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between –0.5 and 0.5 volts.

Positive voltage reference for the A/D converter. See SW I2C register

O

for the output level.
Negative voltage reference for the A/D converter. See SW I2C register

O

for the output level.
Power supply input for the digital switching circuitry sensitive to the

I

supply noise. The DC voltage should be 1,8V.

Power supply input for the analog clock drivers. The DC voltage should

I

be 3.3V.

Power supply input for the analog circuits. The DC voltage should be

I

3.3V.

I2C INTERFACES

SCL 11 I I2C master serial clock. Up to 700 kbit/s.

SDA 12 I/O I2C master serial data inout, open drain I/O pad.

16-17

SADDR[1:0]

9

SCL_TUN

10

SDA_TUN
SCL_EEP 5 O Extra I2C clock to download DSP code from an external EEPROM.

SDA_EEP 8 I/O Extra I2C data bus to download DSP code from an external

15

EEPADDR

SADDR[1:0] are the 2 LSBs of the I2C address of the TDA10045. The

I

MSBs are internally set to 00010. Therefore the complete I2C address
of the TDA10045 is (MSB to LSB): 0,0,0,1,0,SADDR[1], SADDR[0]
Tuner I2C serial clock signal.This signal derived from the master SCL

OD

can be set to high impedance when no tuner acces needed. (See
BP_I2C_TUN register) (open drain)
Tuner I2C serial data signal.This signal derived from the master SDA

I/O

can be set to high impedance when no tuner acces needed. (See
BP_I2C_TUN register) (open drain)

(Optional mode). Can be connected to the master I2C Bus. (open
drain)

EEPROM. (Optional mode). Can be connected to the master I2C Bus.
(open drain)
EEPRAD is the LSB of the I2C address of the EEPROM. The MSBs

I

are internally set to 101000. Therefore the complete I2C address of
the EEPROM is (MSB to LSB): 1,0,1,0,0,0, EEPADDR

2000 March 15 5

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

DSP SIGNALS

DOWNLOAD 27 I Processor control, Boot Mode

If 0 the DSP downloads the software from an external eeprom on the
dedicated I2C BUS (SDA_EEP, SCL_EEP).
If 1 the software is downloaded in the I2C register CODE_IN from the
host. In this case no need of external eeprom.

SP_IN[1:0] 28-29 I Spare inputs

DS_SPARE_1 60 O

(3.3V)

DS_SPARE_2 59 O

(3.3V)

PLL SIGNALS

PLLVCC 88 I Power supply input for the analog circuits of the PLL module. (typ
PLLGND 87 I Ground return for the analog circuits of the PLL module.

DGND 85 I Ground return for the digital circuits of the PLL module.
DVCC 84 I Power supply input for the digital circuits of the PLL module. (typ

Spare delta-sigma output. Managed by the DSP to handle a low
frequency DAC. ( automatic first stage tuner AGC measurement for
example).
Spare delta-sigma output. Managed by the DSP or by an I2C register
to generate an analog level. (after a RC low-pass filter)

3.3V)

1.8V)

BOUNDARY SCAN

TCK 55 I clock signal for boundary-scan. Wired to GND (if not used)

TDI 54 I Input port for boundary-scan. Wired to GND (if not used)

TMS 53 I Mode programming signal for boundary-scan. Wired to GND (if not

used)

TRST 52 I Asynchronous reset signal for boundary-scan. Wired to GND (if not

used)

TDO 56 O

(3.3V)

Output port for boundary-scan. NC (if not used)

POWER SUPPLIES

VSS 2-7-19-26-32-40-

47-58-62-71-78-

82

VDD50 25-46 VCC5VPositive Power Supply 5 V typical. If no need of 5V tolerant IO can be
VDD33 1-6-31-61-77 VDD
VDD18 18-39-57-70-81 VDD

GND

0V Ground level 0 V

set to 3.3V (with caution).

3.3V

1.8V

Positive Power Supply 3.3V typical
Positive Power Supply 1.8V typical

2000 March 15 6

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

FIGURE 2 : EXTERNAL BLOCK DIAGRAM

VDD50 GNDVDD18VDD33

Xin Xout Power Supplies

VAGC
SDA_TUN
SCL_TUN
IT
FEL
PSYNC
UNCOR
DEN
OCLK
DO(7:0)

8

FI(9:0)

CLR#

VIP

VIM

10

Inputs Outputs

TDA10045

JTAGDSP InterfaceInterface

SADDR(1:0) TDOTDI

SCL SDA

SCL
EEP

SDA
EEPDSSPARE

2000 March 15 7

SP_IN

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

FIGURE 3 : TYPICAL APPLICATION : DVB-T FRONT END RECEIVER

I2C

RF

TUNER

RF_AGC

SCL

SDA

IF1

IF_AGC

IF

Interface

optional IF2 down
conversion reference
frequency

RC

IF1
or
IF2

RC

VAGC

VIP
VIM

SACLK

SDA_TUN
SCL_TUN

Xin

10

A
D
C

TDA10045

Xout

EEPROM

Optional

SDA_EEP
SCL_EEP

PSYNC

UNCOR
DEN
OCLK
DO(7:0)

8

RC

Optional ADC

DS_SPARE_1

SP_IN(0)

SCL, SDA

I2C Bus

TUNER

• A RF tracking filter tracks the RF wanted frequency and suppresses the image.

• A first local AGC could be done at RF level, the AGC level information could be provided externaly and the chip

offers facilities to measure this level thanks to the optional ADC (Rem: this measure is automaticaly made by the
DSP, the host has just to read the result).

• A mixer oscillator and a PLL down-convert the RF signal to Intermediate Frequency IF1 typicaly 36.125 MHz

• SAW filters reject the adjacent analog channels power at IF1

IF INTERFACE

• It is either an analog IF amplifier when IF1 is sampled (digital down-conversion concept)

• Or an analog IF amplifier followed by a down-conversion from IF1 to IF2 at few MHz (ex :4.57 MHz)

• When this second solution is used, the ADC sampling clock could be used (after low-pass filtering) as reference

clock for down-conversion (rem : twice the ADC sampling clock could also be provided – see reg CONFADC).

• The IF amplifier is controlled by the digital AGC of the chip. A simple RC circuitry will filter the single-bit (∆Σ
modulated) AGC control (VAGC)

• The sampling clock could also be used to control an external ADC, then the input of the chip are digital (FI[9 :0])

TDA10045

• The chip is controlled by an I2C Bus and driven by an external low-cost crystal oscillator

• The software of the embedded DSP could be downloaded from the main I2C bus or from a dedicated I2C Bus

connected to an external slave I2C Eeprom.

• An internal bidirectional switch allows to program the tuner through the chip and then switch off this link in order
to avoid phase noise distortions due to I2C Bus traffic

2000 March 15 8

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

FIGURE 4 : PIN DIAGRAM

VD1

VS1

VD2

VS2

VS3

VD3

VREFP

VREFM

VIM

VIP

VD3

VS3

PLLVCC

PLLGND

DGND

DVCC

VSS

VDD18

VDD33

VSS

CTRLVCXO

VAGC

SCL_EEP

VDD33

VSS

SDA_EEP

SCL_TUN

SDA_TUN

SCL

SDA

CLB#

EEPADDR

SADDR[1]
SADDR[0]

VDD18

VSS
TM[3]
TM[2]
TM[1]
TM[0]

SCAN_EN

VDD50

VSS

DWNLOAD

SP_IN[1]
SP_IN[0]

FFT_WIN

100 99 98 97 96 95 94 93 92 9190 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 4041 42 43 44 45 46 47 48 49 50

TDA10045

100 MQFP

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

XOUT
XIN
VSS
VDD33
DO[0]
DO[1]
DO[2]
DO[3]
DO[4]
VSS
VDD18
DO[5]
DO[6]
DO[7]
OCLK
DEN
PSYNC
UNCOR
VSS
VDD33
DS_SPARE1
DS_SPARE2
VSS
VDD18
TDO
TCK
TDI
TMS
TRSTN

VSS

FI[9]

FI[8]

FI[7]

FI[6]

FI[5]

VDD33

SACLK

2000 March 15 9

VDD18

VSS

FI[4]

FI[3]

FI[2]

FI[1]

FI[0]

IT

VSS

VDD50

FEL

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

TABLE 1 : PIN DESCRIPTION

Pin Pin Name Direction

1 VDD33 ­2 VSS ­3CTRLVCXO I
4 VAGC O
5 SCL_EEP O
6 VDD33 ­7 VSS ­8 SDA_EEP IOD

9 SCL_TUN OD
10 SDA_TUN IOD
11 SCL I
12 SDA IOD
13 - ­14 CLB# I
15 EEPADDR I
16 SADDR[1] I
17 SADDR[0] I
18 VDD18 ­19 VSS ­20 VSS I
21 VSS I
22 VSS I
23 VSS I
24 VSS I

3
3
3
3
3

25 VDD50 ­26 VSS ­27 DWNLOAD I
28 SP_IN[1] I
29 SP_IN[0] I
30 FFT_WIN IO
31 VDD33 ­32 VSS ­33 SACLK O
34 FI[9] IO

35 FI[8] IO
36 FI[7] IO
37 FI[6] IO
38 FI[5] IO
39 VDD18 ­40 VSS ­41 FI[4] IO
42 FI[3] IO
43 FI[2] IO
44 FI[1] IO
45 FI[0] IO
46 VDD50 ­47 VSS ­48 IT OD
49 FEL OD
50 - ­51 - ­52 TRSTN I
53 TMS I
54 TDI I
55 TCK I
56 TDO O
57 VDD18 ­58 VSS ­59 DS_SPARE2 O
60 DS_SPARE1 O
61 VDD33 ­62 VSS ­63 UNCOR O
64 PSYNC O
65 DEN O
66 OCLK O
67 DO[7] O
68 DO[6] O
69 DO[5] O
70 VDD18 -

71 VSS ­72 DO[4] O
73 DO[3] O
74 DO[2] O
75 DO[1] O
76 DO[0] O
77 VDD33 ­78 VSS ­79 XIN I
80 XOUT O
81 VDD18 ­82 VSS ­83 - ­84 DVCC ­85 DGND ­86 - ­87 PPLGND ­88 PLLVCC ­89 VS3 ­90 VD3 ­91 VIP ­92 VIM ­93 VREFM ­94 VREFP ­95 VD3 ­96 VS3 ­97 VS2 ­98 VD2 ­99 VS1 -

100 VD1 -

Notes :

1.All inputs (I) are TTL, 5V tolerant inputs. (If VDD50 set to 5V).

2.OD are Open Drain 5V outputs, so they must be connected to a pull-up resistor to either VDD33 or VDD50

3. Foundry test IO, inputs must be connected to GND.

2000 March 15 10

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

PACKAGE INFORMATION

NOTE : Dimensions are in millimeters

2000 March 15 11

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

DATA SHEET STATUS

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification Development This data sheet contains the design target or goal specifications for

product development. Specification may change in any manner without
notice.

Preliminary specification Qualification This datasheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification Production This data sheet contains final specifications. Philips Semiconductors

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values givenare in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any other conditionsabovethosegiven in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythat such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingthese products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofany of these products, conveys no licenceortitle
under any patent, copyright, or mask work right to these
products,and makes no representations orwarrantiesthat
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2

PURCHASE OF PHILIPS I

C COMPONENTS

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2000 March 15 12

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

NOTES

2000 March 15 13

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

NOTES

2000 March 15 14

Philips Semiconductors Preliminary specification

Single Chip DVB-T Channel Receiver TDA10045

NOTES

2000 March 15 15

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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753504/03/pp16 Date of release: 2000 March 15 Document order number: 9397 750 07144