DATASHEETS saa7219 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7219

MPEG2 Transport RISC processor

Product specification
Supersedes data of 1999 Sep 20
File under Integrated Circuits, IC02

2000 Jun 14

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

CONTENTS

1 FEATURES

1.1 External interfaces

1.2 CPU related features

1.3 MPEG2 systems features

2.1 SAA7219 overview

2.2 SAA7219 in a DVB system
3 ORDERING INFORMATION
5 PINNING
6 APPLICATION INFORMATION

6.1 Memory configurations
7 PACKAGE OUTLINE

8.1 Introduction to soldering surface mount
packages

8.2 Reflow soldering

8.3 Wave soldering

8.4 Manual soldering

8.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

9 DATA SHEET STATUS
10 DEFINITIONS
11 DISCLAIMERS

2000 Jun 14 2

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

1 FEATURES

• Conditional access descrambling Digital Video

Broadcasting (DVB) compliant and MULTI2 compliant

• Stream demultiplexing: Transport Stream (TS),

Packetized Elementary Stream (PES), program and
proprietary streams

• Internal 32-bit MIPS RISC based Central Processing

Unit (CPU) supporting MIPS16 instruction set and
running at 81 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool

support

• Package: SQFP208.

1.1 External interfaces

• Versatile compressed stream input at 108 Mbits/s

• A 32-bit microcontroller extension bus supporting

DRAM, SDRAM,Flash, (E)PROM andexternal memory
mapped I/O devices. It also supports a synchronous
interface to communicate with the integrated MPEG
Audio Video Graphics Decoder (AVGD) SAA7215 at

40.5 Mbytes.

• An IEEE 1284 interface(Centronics) supporting master

and slave modes. Usable as a general purpose port.

• An interface to IEEE 1394 devices (such as Philips

PDI 1394 chip-set)

• Two UART (RS232) data ports with Direct Memory

Access (DMA) capabilities (187.5 kbits/s) including
hardware flow control signals RXD, TXD, RTS and CTS
for modem support

• A Synchronous Serial Interface (SSI) to connect an

off-chip modem analog front-end

• An elementary UART with DMA capabilities, dedicated

to front panel devices for instance

• Two dedicated smart-card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers with DMA

capabilities, supporting the standard (100 kbit/s) and
fast (400 kbits/s) I2C-bus modes

• 32 general purpose, bidirectional I/O interface pins, 8 of

which may also be used as interrupt inputs

• One Pulse Width Modulated (PWM) output with 8-bit

resolution

• A General Purpose/High-Speed (GP/HS) interface
supporting stream recording through IEEE 1394
interface IC

• An extended JTAG interface for board test support.

1.2 CPU related features

The SAA7219 contains an embedded RISC CPU, which
incorporates the following features:

• A 32-bit PR3930 core running at 81 MHz

• 8-kbyte, 2-way set associative instruction cache

• 4-kbyte, 4-way set associative data cache

• A programmable low-power mode, including wake-up

on interrupt

• A memory management unit with 32 odd/even entries
and variable page sizes

• Multiply/accumulate/divide unit with fast
multiply/accumulate for 16-bit and 32-bit operands

• Two fully independent 24-bit timers and one 24-bit timer
including watchdog facilities

• A real-time clock unit (active in Sleep mode)

• Built-in software debug support unit as part of Extended

Enhanced JTAG debug interface

• On-chip SRAM of 4 kbytesfor storing code whichneeds
fast execution.

1.3 MPEG2 systems features

• Hardware based parsing of Transport Stream (TS),
Philips Semiconductors program and proprietary
software data streams. Maximum input rate is
108 Mbits/s.

• A real-time descrambler consisting of 3 modules:
– A control word bank containing 14 pairs (odd, even)

of control words and a default control word

– The DVB descrambler core implementing the stream

decipher and block decipher algorithms

– The MULTI2 descrambler algorithm implementing

the CBC and OFB mode descrambling functions.

2000 Jun 14 3

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

• Hardware section filtering based on 32 different Packet
Identifiers (PIDs) with a flexible number of filter
conditions (8 or 4-byte condition plus 8 or 4-byte mask)
per PID and a total filter capacity of 40 (8-byte condition
checks) or up to 80 (4-byte condition checks) filter
conditions:

– 4 TS/PES filters for retrieval for data at TS or PES

level for applications such as subtitling, TXT or
retrieval of private data

– Flexible DMA based storage of the 32 section

substreams and 4 TS/PES data substreams in the
external memory.

• System time base management with a double counter
mechanism for clock control and discontinuity handling,
2 Presentation Time Stamp (PTS)/Decoding Time
Stamp (DTS) timers

• A GP/HS filter which can serve as an alternate input
from for example IEEE 1394 devices. The IEEE 1394
GP/HS mode supports packet insertion and has an
internal SRAM for storing 2 packets. It can also output
either scrambled or descrambled TS to IEEE 1394
devices.

2 GENERAL DESCRIPTION

2.1 SAA7219 overview

The device is part of a comprehensive source decoding kit
which contains all the hardware and software required to
receive and decode MPEG2 transport streams, including
descrambling, demultiplexing. In addition, it includes a
PR3930 core which is a 32-bit MIPS RISC-based CPU
core supporting the MIPS 16 instruction set to reduce
memory requirements and several peripheral interfaces
such as UARTs, I2C-bus units, an IEC 1883, and an
IEEE 1284 (Centronics) interface. The SAA7219 is
therefore capable of performing all controller tasks in
digital television receiver applications such as set-top
boxes. Furthermore, the SAA7219 is compliant to DVB
and MULTI2 standards.

The SAA7219 receives transport streams through a
versatile stream input interface capable of handling both
byte-parallel and bit-serial streams in various formats,
supporting data streams up to and including 13.5 Mbyte/s
(108 Mbits/s).Thestreamdataisfirstappliedtoanon-chip
descrambler incorporating a DVB descramblingalgorithm,
on the basis of 14 control word pairs stored in on-chip
RAM. Demultiplexing is subsequently applied to the
stream, to separate up to 32 individual data streams.

The demultiplexer section includes clock recovery and
timebase management. Program Specific Information
(PSI), Service Information (SI), Conditional Access (CA)
messages and private data are selected and stored in
external memory, for subsequent off-line processing by
the internal PR3930 CPU core.

To support advanced board testing facilities the SAA7219
includes boundary scan test hardware, according to the
EJTAG standard. The device features a low-power sleep
mode, which is capable of sustaining set-top box standby
functionality, thus eliminating the need for a separate front
panel controller. The SAA7219 requires a supply voltage
of 3.3 V and most devices input and output interfaces are
5 V tolerant except the extension bus which is 3.3 V only.
The SAA7219 is mounted in a SQFP208 package.

2.2 SAA7219 in a DVB system

The SAA7219 has been designed to offer optimum
performance when used with the SAA7215 for MPEG2
AVG decoding.

• Synchronous bus interface transfer at 40.5 MHz on
16 bits

• SAA7215 has one dedicated SDRAM for MPEG2 audio
video handling and one for graphics and CPU data. The
second memory offers high bandwidth and low latency
tothe SAA7219 when accessing it to downloadgraphics
or executing some applications. This enables a high
level of performance together with a low system cost by
having one SDRAM for graphics and CPU data.

3 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA7219HS/C2 SQFP208 plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body

28 × 28 × 3.4 mm; high stand-off height

2000 Jun 14 4

SOT316-1

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2000 Jun 14 5

input

stream

output

stream

CPU section

MIPS

PR3930

CORE

DATA CACHE

INSTRUCTION CACHE

TIMER 1

INPUT

INTERFACE

GP/HS

INTERFACE

1394 GATEWAY

pagewidth

PWM

PID

FILTER

PCR

PROCESSING

DESCRAMBLER

DVB AND MULTI2
MPEG system-bus

TS/PES

FILTERS

demultiplexer descrambler section

AV

FILTER

SECTION

FILTERS

AUDIO AND

VIDEO

INTERFACE

AVD

interface

4 BLOCK DIAGRAM

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

TIMER 2

TIMER 3 (WATCHDOG)

DSU

EJTAG

SS MM

PI-BUS

CTRL

JTAG

JTAG interface

M = master peripheral with embedded DMA channel
S = slave peripheral

EXTENSION BUS

MMU

CONTROLLER

bus interface

CARD READER UART

smart card

interface

PI-bus

2

1

UART and SSI

connections

01

MPEG SYSTEM

GATEWAY

M

SSI

PIO

INTERFACE

SS

I2C

010

SCL and

SDA lines

FILTER DMA

CONTROLLER

M

M

1284

32 kHz

1284 bus32-bit PIOexternal

MPEG SYSTEM

INT.HANDLER

SS S

RTC

INTERRUPT

CONTROLLER

peripheral section

4-KBYTE

SRAM

FCE374

Reset

Clock

Fig.1 Block diagram.

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2000 Jun 14 6

5 PINNING Table 1 SQFP208 package: 179 functional pins and 29 power supply pins

SYMBOL PIN I/O BUFFER TYPE VOLT

PIO interface (32 pins)

PIO0 to PIO7 105 to 112 I/O bidirectional, 3 mA output drive 5 V usable as interrupt inputs and/or I/O lines
PIO8/BOOTIS32 113 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap. At power-on, it indicates the

PIO9/BOOTIS16 114 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap. At power-on, if BOOTIS32 is

PIO10 to PIO15 116 to 121 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap
PIO(31:16)/D(31:16) 2, 4 to 9, 11 to 16,

18 to 20

Extension bus (58 pins)

D15 to D0 21, 22, 24, 25,

28 to 30, 33 to 36,
38 to 41

A0 to A21 63 to 65, 67 to 71,

73 to 77, 81 to 85,

87 to 90
RAS0N 49 O 8 mA output drive 3.3 V row access strobe for DRAM and SDRAM Bank 0
RAS1N/DCS1N 48 O 8 mA output drive 3.3 V row access strobe for DRAM and SDRAM Bank 1
LCASN 46 O 8 mA output drive 3.3 V column access strobe lower byte
MLCASN 43 O 8mA output drive 3.3 V column access strobe mid lower byte
MUCASN 44 O 8 mA output drive 3.3 V column access strobe mid upper byte
UCASN 42 O 8 mA output drive 3.3 V column access strobe upper byte
WEN 62 O 8 mA output drive 3.3 V write enable
DCS0N 47 O 8mA output drive 3.3 V chip select for SDRAM Bank 0
CS6N to CS0N 50 to 56 O 8 mA output drive 3.3 V chip select
OEN 58 O 8 mA output drive 3.3 V output enable
DTACKN 59 I TTL input 5 V Data termination acknowledge. Asserted LOW by

CS_SDN 60 O 2 mA output drive 3.3 V selects the graphics SDRAM memory space of the

I/O bidirectional, 6 mA output drive 5 V I/O lines or upper 16-bit data bus. The data bus

I/O bidirectional, 8 mA output drive 3.3 V lower 16-bit data bus

O 8 mA output drive 3.3 V address bus

(1)

data bus size of the booting device.

LOW, it indicates if the system should reboot from a
16-bit or 8-bit device.

width of the booting device is automatically
configured at power-on.

the peripheral when the data bus is valid.

SAA7215

DESCRIPTION

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

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2000 Jun 14 7

SYMBOL PIN I/O BUFFER TYPE VOLT

(1)

DESCRIPTION

CS_RGN 61 O 2mA output drive 3.3 V selects the control registers of the SAA7215
CLK 91 O 8 mA output drive 3.3 V 40.5 MHz clock

UART 0 interface (4 pins)

RXD0 141 I TTL input 5 V UART0 receive data line or receive serial data
TXD0 142 O 2 mA output drive 3.3 V UART 0 transmit data line or transmit serial data
RTSN0 143 O 2 mA output drive 3.3 V UART 0 request to send
CTSN0 144 I TTL input 5 V UART 0 clear to send

UART 1 and SSI interfaces (5 pins)

RXD1/V34_RXD 137 I TTL input 5 V UART 1 receive data line or receive serial data of

the SSI interface

TXD1/V34_TXD 138 O 2 mA output drive 3.3 V UART 1 transmit data line or transmit serial data of

the SSI interface

RTSN1/V34_FS 139 I/O bidirectional, 3 mA output drive 5 V UART 1 request to send (output) or frame

synchronization reference of the SSI interface
(input)

CTSN1/V34_CLK 140 I TTL input 5 V UART1 clear to send or serial input interface clock

of the SSI interface (up to 3.375 MHz)

MCLK 146 O 2 mA output drive 3.3 V master clock for the SSI interface (36.684 MHz)

UART 2 interface (2 pins)

RXD2 135 I TTL input 5 V UART2 receive data line
TXD2 136 O 2 mA output drive 3.3 V UART 2 transmit data line

2

I

C-bus 0 interface (2 pins)

2

SCL0 149 I/O bidirectional with open-drain

5V I

C-bus 0 clock line

8 mA output drive

SDA0 150 I/O bidirectional with open-drain

5V I

2

C-bus 0 data line

8 mA output drive

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

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2000 Jun 14 8

SYMBOL PIN I/O BUFFER TYPE VOLT

2

C-bus 1 interface (2 pins)

I

SCL1 147 I/O bidirectional with open-drain

(1)

5V I

2

C-bus 1 clock line

DESCRIPTION

8 mA output drive

SDA1 148 I/O bidirectional with open-drain

5V I

2

C-bus 1 data line

8 mA output drive

Smart card 0 interface (5 pins)

CLK_CARD0 128 O 2 mA output drive 3.3 V ISO UART 0 card clock
CMDVCCN0 129 O 2 mA output drive 3.3 V ISO UART 0 command of the VCC
RSTIN0 132 O 2mA output drive 3.3 V ISO UART 0 reset of the card
OFFN0 133 I TTL input 5 V ISO UART 0 card presence
SC_I/O0 134 I/O bidirectional with open-drain

5 V ISO UART0 I/O line

8 mA output drive

Smart card 1 interface (5 pins)

CLK_CARD1 122 O 2 mA output drive 3.3 V ISO UART 1 card clock
CMDVCCN1 123 O 2 mA output drive 3.3 V ISO UART 1 command of the VCC
RSTIN1 124 O 2mA output drive 3.3 V ISO UART 1 reset of the card
OFFN1 125 I TTL input 5 V ISO UART 1 card presence
SC_I/O1 126 I/O bidirectional with open-drain

5 V ISO UART1 I/O line

8 mA output drive

Input Stream interface (11 pins)

PKTSTROBE 154 I TTL input 5 V byte strobe or bit strobe
PKTSYNC 155 I TTL input 5 V packet synchronization
PKTVALID 156 I TTL input 5 V data valid, or bit stream word select
PKTDATA7 to PKTDATA0 157 to 164 I TTL input 5 V 8-bit primary TS data input

GP/HS interface (11 pins)

GPDATA7 to GPDATA0 166 to 169,

I/O bidirectional, 3 mA output drive 5 V GP/HS data bus

171 to 174
GPVALID 175 I/O bidirectional, 3 mA output drive 5 V GP/HS control lines
GPSYNC 176 I/O bidirectional, 3 mA output drive 5 V GP/HS control lines
GPSTROBE 177 I/O bidirectional, 3 mA output drive 5 V GP/HS control lines

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

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2000 Jun 14 9

SYMBOL PIN I/O BUFFER TYPE VOLT

SAA7215 MPEG interface (11 pins)

V_STROBE 93 O 2 mA output drive 3.3 V HIGH-to-LOW transition strobes the video data in

A_STROBE 94 O 2 mA output drive 3.3 V HIGH-to-LOW transition strobes the audio data in

AV_ERROR 95 O 2 mA output drive 3.3 V flag for bit stream error (active HIGH)
AV_DATA7 to AV_DATA0 96 to 103 O 2 mA output drive 3.3 V MPEG audio/video stream output port

IEEE 1284 interface (18 pins)

GPD0 to GPD7 190 to 197 I/O bidirectional, 3 mA output drive 5 V parallel data bus
NSELECTIN 199 I/O bidirectional, 3 mA output drive 5 V host to peripheral select line
NINIT 200 I/O bidirectional, 3 mA output drive 5 V host to peripheral control line
NSTROBE 201 I/O bidirectional, 3 mA output drive 5 V host to peripheral strobe line
NACK 202 I/O bidirectional, 3 mA output drive 5 V peripheral acknowledge line
BUSY 203 I/O bidirectional, 3 mA output drive 5 V peripheral busy line
PERROR 204 I/O bidirectional, 3 mA output drive 5 V peripheral error line
SELECT 205 I/O bidirectional, 3 mA output drive 5 V peripheral on-line
NAUTOF 206 I/O bidirectional, 3 mA output drive 5 V host to peripheral control line
NFAULT 207 I/O bidirectional, 3 mA output drive 5 V peripheral error line
DIR1284 208 O 2 mA output drive 3.3 V direction control of the external buffers

PWM interface (1 pin)

PWM0 165 O open-drain 8 mA output drive 5 V open-drain 5 V tolerant for VCXO control

System interface (3 pins)

RESETN 1 I/O bidirectional with open-drain

8 mA output drive and Schmitt
trigger input with high

hysteresis
XTAL1 153 I 3.3 V 13.5 MHz crystal input
XTAL2 152 O 3.3 V 13.5 MHz crystal output

(1)

the AV_DATA stream

the AV_DATA stream

3.3 V General system reset; active LOW. The pad is
bidirectional with an open-drain which is asserted
LOW when the internal watchdog time out is
detected.

DESCRIPTION

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

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2000 Jun 14 10

SYMBOL PIN I/O BUFFER TYPE VOLT

JTAG and Test interface (5 pins)

TDO 178 O 3-state, 2 mA output drive 3.3 V Test data output/Target PC output.

TDI 179 I TTL input 5 V Test data input/Debug interrupt.

TMS 180 I TTL input 5 V Testmode select. This input is decoded by the TAP

TRST 181 I TTL input 5 V Testreset. Active LOW level for asynchronous reset

TCK 184 I TTL input 5 V Test clock. Input clock used to shift data into or out

EJTAG extension reserved for PR3930 (4 pins)

DSU_CLK 185 O 2 mA output drive 3.3 V DSU clock is equivalent to the processor clock.

PCST0 to PCST2 186, 188 and 189 O 2 mA output drive 3.3 V CPUstatus: debug mode, pipeline stall, occurrence

(1)

Real-time trace mode off. Serial output data is
shifted from JTAG instruction register to the TDO
pin on the falling edge of the TCK clock. When no
data is shifted out, TDO is 3-stated.

Real-time trace mode on. TDO provides
non-sequential program counter output at the
processor clock speed.

Real-time trace mode off. Serial input data (TDI) is
shifted into the JTAG instruction register or data
register on the rising edge of the TCK clock,
depending of the TAP controller state.

Real-time trace mode on. An active LOW level at
this input sampled by TCK positive edge, is used as
interrupt to switch the real-time trace mode off
(standard JTAG).

controller to control test operation. Sampled on the
rising edge of TCK.

of the EJTAG module, independent of the processor
logic.

from the JTAG instruction or data register.

Captures address and data from pin TDO when PC
trace mode is on. Is 3-stated when bit 0 or 15 of the
JTAG control register is logic 0.

of exception

DESCRIPTION

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

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2000 Jun 14 11

SYMBOL PIN I/O BUFFER TYPE VOLT

(1)

DESCRIPTION

Supplies (29 pins)

V

DD(P)

3, 17, 31, 43, 66,

−− − pad supply voltage
80, 92, 115, 145
and 187

V

SS(P)

10, 23, 37, 57, 72,

−− − ground supply
86, 104, 127, 170
and 198

V

DD(C)

27, 79, 130

−− − core supply voltage
and 182

V

SS(C)

26, 78, 131

−− − ground supply
and 183

V

DD(PLL)

151 −− − analog supply for the on-chip PLLs

Note

1. 5 V tolerant inputs can receive signals swinging between V

and 3.3 V or VSS and 5 V. 5 V tolerant bidirectional I/O pins can receive signals

SS

swinging between VSS and 3.3 V or VSS and 5 V when they are inputs and swing between VSS and VDD when they are outputs.

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

handbook, halfpage

208

1

SAA7219

52

53

Fig.2 Pin configuration

157

104

156

105

FCE380

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

6 APPLICATION INFORMATION

handbook, full pagewidth

Telecommunication i/f

FRONT
PANEL

CONTROL

VXX

MODEM

TDA8004Smart cards

16-MBIT

SDRAM

16-MBIT

SDRAM

(OPTIONAL)

LR

A DAC

SWITCHING

RF in

TDA8060
TDA5056

TUNER

SAA8044

(SDD)

SAA7219

SAA7215

2

MPEG TSI2C-bus

AV PES

CVBS/YC

RGB

BUFFERS

IEEE 1394

L + PHY

IEEE 1384
RS232

IEEE 1394

FLASH

DRAM

(OPTIONAL)

FCE375

SCART1 SCART2 SCART3

Fig.3 Set-top box example.

2000 Jun 14 12

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

6.1 Memory configurations
Table 2 Low-end and high-end memory configurations

CONFIGURATION SDRAM DRAM PROM FLASH PERIPHERALS

Low-end 1M × 16 256K × 16 512K × 8 −
High-end up to 2 banks of 64 Mbits up to 2 banks of 4 Mbytes up to 4 Mbytes 2 to 7 banks of up to

4 Mbytes

SAA7219

16

16

DRAM/

SDRAM

SAA7215

8

16

PROM

SDRAM
(MPEG)

FLASH RESERVED

Fig.4 Typical low-end memory configuration.

32

DRAM

PROM

FLASH 1 FLASH 2

FCE376

SAA7219

16

SAA7215

16

16

Fig.5 Typical high-end unified memory configuration.

2000 Jun 14 13

SDRAM
(MPEG)

SDRAM

GRAPHICS

FCE377

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

7 PACKAGE OUTLINE

SQFP208: plastic shrink quad flat package;
208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height

c

y

X

A

SOT316-1

157

208

156

105

104

Z

E

e

H

E

E

w

M

b

p

A

2

A

A

1

(A )

3

θ

L

p

L

pin 1 index

1

w

b

e

p

M

Z

D

H

D

53

52

v

M

D

A

B

v

M

B

detail X

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

4.10

0.50

0.25

3.6

3.2

0.25

UNIT A1A2A3b

cE

p

0.27

0.20

0.17

0.09

(1)

(1) (1)(1)

D

28.1

27.9

eH

H

28.1

27.9

0.5

30.9

30.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT316-1 MS-029

2000 Jun 14 14

D

E

30.9

30.3

LL

p

0.75

0.45

0.080.21.3 0.08

EUROPEAN

PROJECTION

Z

D

1.39

1.11

Zywv θ

E

1.39

1.11

o

8

o

0

ISSUE DATE

99-12-27
00-01-25

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

8 SOLDERING

8.1 Introduction to soldering surface mount packages

Thistextgivesavery brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

8.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

8.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

2000 Jun 14 15

8.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

8.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Jun 14 16

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

9 DATA SHEET STATUS

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification Development This data sheet contains the design target or goal specifications for

product development. Specification may change in any manner without
notice.

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification Production This data sheet contains final specifications. Philips Semiconductors

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

10 DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.

11 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury.Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyoftheseproducts,conveysnolicenceortitle
under any patent, copyright, or mask work right to these
products,andmakes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2

12 PURCHASE OF PHILIPS I

Purchase of Philips I

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2000 Jun 14 17

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

NOTES

2000 Jun 14 18

Philips Semiconductors Product specification

MPEG2 Transport RISC processor SAA7219

NOTES

2000 Jun 14 19

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

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Indonesia: PT Philips DevelopmentCorporation, Semiconductors Division,
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
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Italy: PHILIPS SEMICONDUCTORS, ViaCasati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
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Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753504/02/pp20 Date of release: 2000 Jun 14 Document order number: 9397 750 06809