DATASHEETS saa7197 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7197

Clock Generator Circuit for desktop
video systems (CGC)

Product specification
File under Integrated Circuits, IC22

August 1996

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

FEATURES

• Suitable for Desktop Video systems

• Two different sync sources selectable

• PLL frequency multiplier to generate 4 times of input

frequency

GENERAL DESCRIPTION

The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family. The
circuit operates in either the phase-locked loop mode
(PLL) or voltage controlled oscillator mode (VCO).

• Dividers to generate clocks LLCA, LLCB, LLC2A and
LLC2B (2nd and 4th multiples of input frequency)

• PLL mode or VCO mode selectable

• Reset control and power fail detection

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

LFCO

f

i

V

I

V

O

T

amb

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V
analog supply current 3 − 9mA
digital supply current 10 − 60 mA
LFCO input voltage (peak-to-peak value) 1 − V

DDA

input frequency range 5.5 − 8.0 MHz
input voltage LOW 0 − 0.8 V
input voltage HIGH 2.0 − V

DDD

output voltage LOW 0 − 0.6 V
output voltage HIGH 2.6 − V

DDD

operating ambient temperature range 0 − 70 °C

V

V

V

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

SAA7197P 20 DIP plastic SOT146-1
SAA7197T 20 SO plastic SOT163-1

August 1996 2

PACKAGE

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

BLOCK DIAGRAM

handbook, full pagewidth

MS 1

LFCO

CE

11

19LFCO2
2

LFCOSEL

LOOP

FILTER

PHASE

DETECTOR

PRE-FILTER

AND

PULSE

SHAPER

MS = LOW

V

V

VCO

FREQUENCY

DIVIDER

16

DDD1

DDA

5178

1 : 2

POWER-ON

RESET

PORD

V

DDD2

FREQUENCY

DIVIDER

1 : 2

DELAY

4

V

SSA

SAA7197

6, 9, 13, 183

V

SSD

7

LLCA

10

LLCB

14

LLC2A

20

LLC2B

15

CREF

12

RESN

MEH461

Fig.1 Block diagram.

FUNCTION DESCRIPTION

The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder, square pixel
(DMSD-SQP), digital video colour space converter
(DCSC) and optional extensions. The SAA7197 completes
a system for Desktop Video applications in conjunction
with memory controllers.

The input signal LFCO is a digital-to-analog converted
signal provided by the DMDS-SQPs horizontal PLL. It is
the multiple of the line frequency:

7.38 MHz = 472 × f

in 50 Hz systems

H

6.14 MHz = 360 × fHin 60 Hz systems

LFCO2 (TTL-compatible signal from an external reference
source) can be applied to pin 19 (LFCOSEL = HIGH).

August 1996 3

The input signal LFCO or LFCO2 is multiplied by factors 2
or 4 in the PLL (including phase detector, loop filter, VCO
and frequency divider) and output on LLCA (pin7), LLCB
(pin 10), LLC2A (pin 14) and LLC2B (pin 20). The
rectangular output signals have 50% duty factor. Outputs
with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available the PLL has locked-on.

Mode select MS

The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

Source select LFCOSEL

Line frequency control signal LFCO (pin 11) is selected by
LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2
input signal (pin 19). This function is not tested.

Power-on reset

Power-on reset is activated at power-on, when the supply
voltage decreases below 3.5 V (Fig.4) or when chip enable
is done. The indicator output RESN is LOW for a time
determined by capacitor on pin 3. The RESN signal can be

Chip enable CE

The buffer outputs are enabled and RESN set HIGH by
CE = HIGH (Fig.4). CE = LOW sets the clock outputs

applied to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied
before RESN becomes HIGH.

HIGH and RESN output LOW.

CREF output

2 f

output to control the clock dividers of the

LFCO

DMSD-SQP chip family.

PINNING

SYMBOL PIN DESCRIPTION

MS 1 mode select input (LOW = PLL mode)

(1)

CE 2 chip enable /reset (HIGH = outputs enabled)
PORD 3 power-on reset delay, dependent on external

capacitor

V

SSA

V

DDA

V

SSD1

LLCA 7 line-locked clock output signal (4 times f
V

DDD1

V

SSD2

LLCB 10 line-locked clock output signal (4 times f

4 analog ground (0 V)
5 analog supply voltage (+5 V)
6 digital ground 1 (0 V)

LFCO

8 digital supply voltage 1 (+5 V)
9 digital ground 2 (0 V)

LFCO

LFCO 11 line-locked frequency control input signal 1
RESN 12 reset output (active-LOW, Fig.4)
V

SSD3

13 digital ground 3 (0 V)
LLC2A 14 line-locked clock output signal 2A (2 times f
CREF 15 clock reference output, qualifier signal

(2 times f

LFCO

)
LFCOSEL 16 LFCO source select (LOW = LFCO selected)
V
V

DDD2
SSD4

17 digital supply voltage 2 (+5 V)

18 digital ground 4 (0 V)
LFCO2 19 line-locked frequency control input signal 2
LLC2B 20 line-locked clock output signal 2B (2 times f

)

)

LFCO

(1)

LFCO

(1)

PIN CONFIGURATION

halfpage

PORD

V

SSA

V

DDA

V

SSD1

LLCA

V

DDD1

V

SSD2

)

LLCB

)

MS

CE

1
2
3
4
5
6
7
8
9

10

SAA7197

20
19
18
17
16
15
14
13
12
11

MGL505

Fig.2 Pin configuration.

LLC2B
LFCO2

V

SSD4

V

DDD2

LFCOSEL
CREF
LLC2A

V

SSD3
RESIN
LFCO

Note

1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of
horizontal frequency.

August 1996 4

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134);
ground pins as well as supply pins together connected.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDA

V

DDD

V

diff GND

V

O

P

tot

T

stg

T

amb

V

ESD

Note

1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to

analog supply voltage (pin 5) −0.5 7.0 V
digital supply voltage (pins 8 and 17) −0.5 7.0 V
difference voltage V
output voltage (IOM= 20 mA) −0.5 V

DDA

− V

DDD

−±100 mV

DDD

V
total power dissipation (DIL20) 0 1.1 W
storage temperature range −65 150 °C
operating ambient temperature range 0 70 °C
electrostatic handling

(1)

for all pins − tbf V

“Handling MOS devices”

.

CHARACTERISTICS

V

DDA=VDDD

= 4.5 to 5.5 V; f

= 5.5 to 8.0 MHz and T

LFCO

= 0 to 70 °C unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

reset

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8 and 17) 4.5 5.0 5.5 V
analog supply current (pin 5) 3 − 9mA
digital supply current (I8+ I17) note 1 10 − 60 mA

power-on reset threshold voltage Fig.4 − 3.5 - V
Input LFCO (pin 11)
V

11

V

i

f

LFCO

C

11

DC input voltage 0 − V

input signal (peak-to-peak value) 1 − V

DDA
DDA

input frequency range 5.5 − 8.0 MHz

input capacitance −−10 pF
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3
V

IL

V

IH

f

LFCO2

I

LI

input voltage LOW 0 − 0.8 V

input voltage HIGH 2.0 − V

DDD

input frequency range for LFCO2 5.5 − 8.0 MHz

input leakage current LFCOSEL 50 − 150 µA

others −− 10 µA

C

I

input capacitance −−5pF
Output RESN (pin 12)
V

OL

V

OH

t

d

output voltage LOW IOL= 2 mA 0 − 0.4 V

output voltage HIGH IOH= −0.5 mA 2.4 − V

DDD

RESN delay time C3= 0.1 µF; Fig.4 20 − 200 ms

V
V

V

V

August 1996 5

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output CREF (pin 15)

V

OL

V

OH

f

CREF

C

L

t

SU

t

HD

Output signals LLCA, LLCB, LLC2A and LLC2B (pins 7, 10, 14, and 20); note 3
V

OL

V

OH

t

comp

f

LL

t

, t

r

f

t

LL

output voltage LOW IOL= 2 mA 0 − 0.6 V

output voltage HIGH IOH= −0.5 mA 2.4 − V

output frequency CREF Fig.3 − 2 f

LFCO(2)

DDD

V

MHz
output load capacitance 15 − 40 pF
set-up time Fig.3; note 1 12 −−ns
hold time Fig.3; note 1 4 −−ns

output voltage LOW IOL= 2 mA 0 − 0.6 V
output voltage HIGH IOH= −0.5 mA 2.6 − V

DDD

V
composite rise time Fig.3; notes 1 and 2 −−8ns
output frequency LLCA Fig.3 − 4 f
output frequency LLCB − 4 f
output frequency LLC2A − 2 f
output frequency LLC2B − 2 f

LFCO(2)
LFCO(2)
LFCO(2)
LFCO(2)

MHz

MHz

MHz

MHz
rise and fall times Fig.3 −− 5ns
duty factor LLCA, LLCB, LLC2A

and LLC2B (mean values)

note 1; Fig.3;
at 1.5 V level 40 50 60 %

Notes

1. f

2. t

= 7.0 MHz and output load 40 pF (Fig.3). V

LFCO

is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter

comp

SSA

and V

short connected together.

SSD

components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than ±2 ns if output loads are matched within 20%.

3. MS and LFCO2 functions not tested.

August 1996 6

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

handbook, full pagewidth

CREF

LLCA
LLCB

LLC2A
LLC2B

t

comp

t

HD

t

LLC H

t

LLC2 H

2.4 V

0.6 V

t

t

SU

t

LLC

t

LLC L

t

f

t

LLC2

t

f

HD

2.6 V

1.5 V

0.6 V

t

r

t

LLC2 L

2.6 V

1.5 V

0.6 V

t

r

MEH466

Fig.3 Output timing.

August 1996 7

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

handbook, full pagewidth

V

DDA

V

DDD

+3.5 V

0 V

LFCO

RESN

LLCA
LLCB
LLC2A
LLC2B

power-on

t

d

clock HIGH

during

internal reset

reset

time

oscillation

normal

operation

PLL lock-on

Fig.4 Reset procedure.

oscillation disturbed

t

d

power failure

starts a new

reset procedure

normal

operation

MEH467

handbook, full pagewidth

1
2

V

DDD

16

MS

19

CE
LFCOSEL
LFCO2

V

SSD

11

LFCO

Fig.5 Internal circuit.

August 1996 8

V

V

V

V

DDD

SSD

DDD

SSD

7
10
14
15

LLCA

20

LLCB
LLC2A
LLC2B
CREF

12

RESN

MEH469

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

PACKAGE OUTLINES

DIP20: plastic dual in-line package; 20 leads (300 mil)

D

seating plane

L

Z

20

pin 1 index

e

b

SOT146-1

M

E

A

2

A

A

1

w M

b

1

11

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT146-1

1 2

min.

max.

1.73

1.30

0.068

0.051

IEC JEDEC EIAJ

b

b

1

0.53

0.38

0.021

0.015

0.36

0.23

0.014

0.009

REFERENCES

cD E e M

(1) (1)

26.92

26.54

1.060

1.045

SC603

August 1996 9

6.40

6.22

0.25

0.24

10

(1)

M

e

L

1

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

H

E

10.0

0.2542.54 7.62

8.3

0.39

0.33

0.010.10 0.30

ISSUE DATE

w

92-11-17
95-05-24

Z

max.

2.04.2 0.51 3.2

0.0780.17 0.020 0.13

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

SO20: plastic small outline package; 20 leads; body width 7.5 mm

D

c

y

Z

20

pin 1 index

1

e

11

A

2

10

w M

b

p

SOT163-1

E

H

E

Q

A

1

L

p

L

detail X

(A )

A

X

v M

A

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT163-1

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

IEC JEDEC EIAJ

075E04 MS-013AC

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

13.0

7.6

7.4

0.30

0.29

1.27

0.050

12.6

0.51

0.49

REFERENCES

August 1996 10

eHELLpQ

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

PROJECTION

0.25

0.25 0.1

0.01

0.01

EUROPEAN

ywv θ

Z

0.9

0.4

8

0.004

ISSUE DATE

0.035

0.016

95-01-24
97-05-22

0

o
o

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video
systems (CGC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

DIP

SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

(order code 9398 652 90011).

). If the

stg max

SAA7197

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

August 1996 11

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video

SAA7197

systems (CGC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

August 1996 12

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

NOTES

August 1996 13

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

NOTES

August 1996 14

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

NOTES

August 1996 15

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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 657027/00/01/pp16 Date of release: August 1996 Document order number: 9397 750 02438