Product specification
Supersedes data of January 1994
File under Integrated Circuits, IC01
1997 Feb 24
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
FEATURES
• Anti-aliasing filter (2nd order)
• Integrated 57 kHz band-pass filter (8th order)
• Reconstruction filter (2nd order)
• Clocked comparator with automatic offset compensation
• 57 kHz carrier regeneration
• Synchronous demodulator for 57 kHz modulated RDS
signals
GENERAL DESCRIPTION
The integrated CMOS circuit SAA6579 is an RDS
demodulator. It recovers the additional inaudible RDS
information which is transmitted by FM radio broadcasting.
The data signal RDDA and the clock signal RDCL are
provided as outputs for further processing by a suitable
decoder (microcomputer).
The operational functions of the device are in accordance
with the
“CENELEC EN 50067”
.
• Selectable 4.332/8.664 MHz crystal oscillator with
variable dividers
• Clock regeneration with lock on biphase data rate
• Biphase symbol decoder with integrate and dump
functions
• Differential decoder
• Signal quality detector
• Subcarrier output.
QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
DDA
V
DDD
I
tot
V
i(rms)
V
OH
V
OL
T
amb
analog supply voltage (pin 5)3.65.05.5V
digital supply voltage (pin 12)3.65.05.5V
total supply current−6−mA
RDS input amplitude (RMS value; pin 4)1−−mV
HIGH level output voltage for signals RDDA, RDCL, QUAL and T574.4−−V
LOW level output voltage for signals RDDA, RDCL, QUAL and T57−−0.4V
operating ambient temperature−40−+85°C
ORDERING INFORMATION
TYPE
NUMBER
NAMEDESCRIPTIONVERSION
PACKAGE
SAA6579DIP16plastic dual in-line package; 16 leads (300 mil); long bodySOT38-1
SAA6579TSO16plastic small outline package; 16 leads; body width 7.5 mmSOT162-1
1997 Feb 242
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
BLOCK DIAGRAM
handbook, full pagewidth
47 pF
4.332/8.664 MHz
82 pF
2.2 k
+5 V
Ω
0.1 µF
MPX
signal
+5 V
2.2 µF
330 pF
SCOUT
560 pF
V
0.1 µF
MUX
CIN
DDA
V
ref
4
ALIASING
FILTER
8
7
CLOCKED
COMPARATOR
5
3
REFERENCE
VOLTAGE
ANTI-
OSCOOSCI
57 kHz
BANDPASS
(8th ORDER)
COSTAS LOOP
VARIABLE AND
FIXED DIVIDER
RECONSTRUCTION
FILTER
13
OSCILLATOR
DIVIDER
BIPHASE
SYMBOL
DECODER
14
AND
SAA6579
V
P1
CLOCK
REGENERATION
AND SYNC
6
V
SSA
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
9
MODETEST
10
V
DDD
12
QUALITY BIT
GENERATOR
DIFFERENTIAL
DECODER
11
V
SSD
QUAL
1
RDDA
2
RDCL
16
T57
15
MEH162
Via pin MODE two different crystal frequencies can be used.
MODECRYSTAL CLOCK
LOW4.332 MHz
HIGH8.664 MHz
Fig.1 Block diagram and application circuit.
1997 Feb 243
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
PINNING
SYMBOLPINDESCRIPTION
QUAL1quality indication output
RDDA2RDS data output
V
ref
3reference voltage output (0.5V
MUX4multiplex signal input
V
V
DDA
SSA
5+5 V supply voltage for analog part
6ground for analog part (0 V)
CIN7subcarrier input to comparator
SCOUT8subcarrier output of reconstruction filter
MODE9oscillator mode/test control input
TEST10test enable input
V
V
SSD
DDD
11ground for digital part (0 V)
12+5 V supply voltage for digital part
OSCI13oscillator input
OSCO14oscillator output
T571557 kHz clock signal output
RDCL16RDS clock output
DDA
)
handbook, halfpage
QUAL
RDDA
V
ref
MUX
V
DDA
V
SSA
CIN
SCOUT
1
2
3
4
5
6
7
8
SAA6579
MGD684
16
15
14
13
12
11
10
9
RDCL
T57
OSCO
OSCI
V
DDD
V
SSD
TEST
MODE
Fig.2 Pin configuration.Fig.3 Pin configuration.
1997 Feb 244
handbook, halfpage
QUAL
RDDA
V
ref
MUX
V
DDA
V
SSA
CIN
SCOUT
1
2
3
4
SAA6579T
5
6
7
8
MGD685
16
15
14
13
12
11
10
9
RDCL
T57
OSCO
OSCI
V
DDD
V
SSD
TEST
MODE
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
DDA
V
DDD
V
n
T
stg
T
amb
V
es
Notes
1. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
analog supply voltage (pin 5)06V
digital supply voltage (pin 12)06V
voltage on all pins; grounds excluded−0.5V
+ 0.5V
DDX
storage temperature−40+150°C
operating ambient temperature−40+85°C
electrostatic handling for all pins except
pins 9 and 10
note 1±300−V
note 2+1500−3000V
FUNCTIONAL DESCRIPTION
The SAA6579 is a demodulator circuit for RDS
applications. It contains a 57 kHz bandpass filter and a
digital demodulator to regenerate the RDS data stream out
of the multiplex signal (MPX).
Filter part
The MUX signal is band-limited by a second-order
anti-aliasing-filter and fed through a 57 kHz band-pass
filter (8th order band-pass filter with 3 kHz bandwidth) to
separate the RDS signals. This filter uses switched
capacitor technique and is clocked by a clock frequency of
541.5 kHz derived from the 4.332/8.664 MHz crystal
oscillator. Then the signal is fed to the reconstruction filter
to smooth the sampled and filtered RDS signal before it is
output on pin 8. The signal is AC-coupled to the
comparator (pin 7). The comparator is clocked with a
frequency of 228 kHz (synchronized by the 57 kHz of the
demodulator).
Digital part
The synchronous demodulator (Costas loop circuit) with
carrier regeneration demodulates the internal coupled,
digitized signal. The suppressed carrier is recovered from
the two sidebands (Costas loop). The demodulated signal
is low-pass-filtered in such a way that the overall pulse
shape (transmitter and receiver) approaches a
cosinusoidal form in conjunction with the following
Integrate and dump circuit.
The data-spectrum shaping is split into two equal parts and
handled in the transmitter and in the receiver. Ideally, the
data filtering should be equal in both of these parts.
The overall data-channel-spectrum shaping of the
transmitter and the receiver is approximately 100% roll-off.
The Integrate and dump circuit performs an integration
over a clock period. This results in a demodulated and
valid RDS signal in form of biphase symbols being output
from the integrate and dump circuit. The final stages of
RDS data processing are the biphase symbol decoding
and the differential decoding. After synchronization by
data clock RDCL (pin 16) data appears on the RDDA
output (pin 2). The output of the biphase symbol decoder
is evaluated by a special circuit to provide an indication of
good data (QUAL = HIGH) or corrupt data (QUAL = LOW).
Timing
Fixed and variable dividers are applied to the
4.332/8.664 MHz crystal oscillator to generate the
1.1875 kHz RDS clock RDCL, which is synchronized by
the incoming data. Which ever clock edge is considered
(positive or negative going edge) the data will remain valid
for 399 µs after the clock transition. The timing of data
change is 4 µs before a clock change. Which clock
transition (positive or negative going clock) the data
change occurs in, depends on the lock conditions and is
arbitrary (bit slip).
During poor reception it is possible that faults in phase
occur, then the clock signal stays uninterrupted, and data
is constant for 1.5 clock periods. Normally, faults in phase
do not occur on a cyclic basis. If however, faults in phase
occur in this way, the minimum spacing between two
possible faults in phase depends on the data being
transmitted. The minimum spacing cannot be less than
16 clock periods. The quality bit changes only at the time
of a data change.
1997 Feb 245
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
CHARACTERISTICS
V
DDA=VDDD
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
DDA
V
DDD
I
tot
V
ref
MPX input (signal before the capacitor on pin 4)
V
i MPX(rms)
V
i MPX(p-p)
R
4-6
G
8-4
57 kHz band-pass filter
f
c
B−3 dB bandwidth2.53.03.5kHz
Gstop band gain∆f=±7 kHz31−−dB
R
o(8)
Comparator input (pin 7)
V
i(rms)
R
i
Oscillator input (pin 13)
V
IH
V
IL
I
I
=5V; T
=25°C and measurements taken in Fig.1; unless otherwise specified.
amb
analog supply voltage (pin 5)3.65.05.5V
digital supply voltage (pin 12)3.65.05.5V
total supply currentI5+I
reference voltage (pin 3)V
12
=5V−2.5−V
DDA
RDS amplitude (RMS value)∆f=±1.2 kHz RDS;
−6−mA
1−−mV
∆f=±3.5 kHz ARI; see Fig.5
maximum input signal capability
(peak-to-peak value)
f=57±2 kHz200−−mV
f < 50 kHz1.4−−V
f < 15 kHz2.8−−V
f > 70 kHz3.5−−V
input resistancef = 0 to 100 kHz40−−kΩ
signal gainf = 57 kHz172023dB
HIGH level input voltageV
LOW level input voltageV
input currentV
= 5.0 V4.0−−V
DDD
= 5.0 V−−1.0V
DDD
= 5.5 V−−±1µA
DDD
1997 Feb 246
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Digital demodulator and outputs QUAL, RDDA, T57, OSCO and RDCL (pins 1, 2, 14, 15 and 16)
V
OH
V
OL
f
RDCL
∆t
RDCL
f
T57
I
O
HIGH level output voltageIQ= −20 µA; V
LOW level output voltageIQ= 3.2 mA; V
nominal clock frequency RDCL−1187.5 −Hz
jitter of RDCL−− 18µs
nominal subcarrier frequency T57note 1−57.0−kHz
output current OSCO (pin 14)V
output current QUAL, RDDA, T57,
RDCL (pins 1, 2, 15 and 16)
= 4.5 V; V14= 0.4 V1.5−−mA
DDD
= 4.5 V; V14= 4.1 V−1.6−−mA
V
DDD
V
= 4.5 V; V14= 0.4 V5.9−−mA
DDD
= 4.5 V; V14= 4.1 V−5.3−−mA
V
DDD
4.332 MHz crystal parameters
f
∆f
∆f
C
R
0
max
o
L
xtal
XTAL frequency−4.332−MHz
maximum permitted tolerance−±50−10
adjustment tolerance of f
0
T
=25°C−−±2010
amb
T
= −40 to +85 °C−− ±2510
amb
load capacitance−30−pF
resonance resistance−− 60Ω
8.664 MHz crystal parameters
f
∆f
∆f
C
R
0
max
o
L
xtal
XTAL frequency−8.664−MHz
maximum permitted tolerance−±50−10
adjustment tolerance of f
0
T
=25°C−−±3010
amb
T
= −40 to +85 °C−− ±3010
amb
load capacitance−30−pF
resonance resistance−− 60Ω
Note
1. The signal T57 has a phase lead of 123° (±180°) relative to the ARI carrier at output SCOUT.
= 4.5 V4.4−−V
DDD
= 5.5 V−− 0.4V
DDD
−6
−6
−6
−6
−6
−6
1997 Feb 247
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
handbook, full pagewidth
RDCL
RDDA,
QUAL
100
handbook, full pagewidth
correct
blocks
(%)
75
50
25
(1)(2)
4 µs4 µs
842 µs421 µs
Fig.4 RDS timing diagram including a phase jump.
MEH163
MGD683
0
−1
10
(1) RDS + ARI (BK).
(2) RDS only.
Fig.5 Typical RDS sensitivity.
1997 Feb 248
1
Vi (RDS signal, RMS value)
(mV)
10
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
D
seating plane
L
Z
16
pin 1 index
e
b
b
1
9
A
w M
SOT38-1
M
E
A
2
A
1
c
(e )
1
M
H
E
1
0510 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A
max.
4.70.513.7
OUTLINE
VERSION
SOT38-1
min.
A
12
max.
0.15
IEC JEDEC EIAJ
050G09MO-001AE
b
1.40
1.14
0.055
0.045
b
0.53
0.38
0.021
0.015
1
cEeM
0.32
0.23
0.013
0.009
REFERENCES
(1)(1)
D
21.8
21.4
0.86
0.84
1997 Feb 249
8
6.48
6.20
0.26
0.24
e
0.30
1
M
L
3.9
3.4
0.15
0.13
E
8.25
7.80
0.32
0.31
EUROPEAN
PROJECTION
H
9.5
0.2542.547.62
8.3
0.37
0.010.100.0200.19
0.33
ISSUE DATE
w
92-10-02
95-01-19
Z
max.
2.2
0.087
(1)
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
SO16: plastic small outline package; 16 leads; body width 7.5 mm
D
c
y
Z
16
pin 1 index
1
e
9
A
2
A
1
8
w
b
p
M
E
H
E
detail X
SOT162-1
A
X
v
M
A
Q
(A )
L
p
L
A
3
θ
0510 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
A
max.
2.65
0.10
A
0.30
0.10
0.012
0.004
1
A2A
2.45
2.25
0.096
0.089
0.25
0.01
b
3
p
0.49
0.32
0.36
0.23
0.019
0.013
0.014
0.009
(1)E(1)(1)
cD
10.5
7.6
7.4
0.30
0.29
1.27
0.050
10.1
0.41
0.40
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT162-1
IEC JEDEC EIAJ
075E03 MS-013AA
REFERENCES
1997 Feb 2410
eHELLpQ
10.65
10.00
0.42
0.39
1.4
0.055
1.1
0.4
0.043
0.016
1.1
1.0
0.043
0.039
PROJECTION
0.25
0.250.1
0.01
0.01
EUROPEAN
ywvθ
Z
0.9
0.4
8
0.004
0.035
0.016
0
ISSUE DATE
92-11-17
95-01-24
o
o
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
DIP
OLDERING BY DIPPING OR BY WA VE
S
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
EPAIRING SOLDERED JOINTS
R
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
AVE SOLDERING
W
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
EPAIRING SOLDERED JOINTS
R
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Feb 2411
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Feb 2412
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
NOTES
1997 Feb 2413
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
NOTES
1997 Feb 2414
Philips SemiconductorsProduct specification
Radio Data System (RDS) demodulatorSAA6579
NOTES
1997 Feb 2415
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands547027/1200/02/pp16 Date of release: 1997 Feb 24Document order number: 9397 750 00913
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