DATASHEETS saa5233 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA5233

Dual standard PDC decoder

Objective specification
File under Integrated Circuits, IC02

Philips Semiconductors

June 1994

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

FEATURES

• Digital data slicer

• Acquisition and decoding of VPS data

(EBU PDC System A)

• Acquisition and decoding of Teletext packet 8/30/2 data
(EBU PDC System B)

• Separate storage of VPS data and packet 8/30/2
allowing dual standard PDC decoders

• I2C-bus interface with automatic word address
increment

• Programmable interrupt for data received

• Programmable error level detection

• Single +5 V power supply.

GENERAL DESCRIPTION

The SAA5233 is a dual standard Program Delivery Control
(PDC) decoder, allowing the reception and decoding of
both VPS data (EBU PDC System A) and Teletext packet
8/30/2 data (EBU PDC System B). It is intended for use in
European video recorders which are manually
programmed, so that they receive broadcast real time
switching signals for accurate timing of program recording.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

f

clk

V

sync

V

vid(p-p)

supply voltage 4.5 5.0 5.5 V
supply current − 30 45 mA
crystal input frequency − 27 − MHz
CVBS sync voltage amplitude 0.1 0.3 0.6 V
CVBS video voltage amplitude

0.7 1.0 1.4 V

(peak-to-peak value)

T

amb

T

stg

operating ambient temperature −20 − +70 °C
storage temperature −55 − +125 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

SAA5233P 16 DIP16 plastic SOT38-1
SAA5233T 20 SO20L plastic SOT163-1

June 1994 2

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

BLOCK DIAGRAM

SCL SDA

handbook, full pagewidth

V

V
V
V
V

INT

V

SS1

SS2
SS3
SS4
SS5

AD

DD

14

15

4

5

9
10
11
16

27 MHz

POWER

ON RESET

13.5 MHz

1.125 MHz

27 MHz
OSCILLATOR
AND DIVIDER

12 13

2

I C BUS

INTERFACE

INTERRUPT

CONTROL

TELETEXT

AND VPS

CONTROL

DATA SLICER

AND CLOCK

REGENERATOR

ANALOGUE
TO DIGITAL

CONVERTER

MEMORY

INTERFACE

AND RAM

SAA5233

8/30/2

ACQUISITION

AND

DECODING

VPS

ACQUISITION

AND

DECODING

PLL AND

TIMING

INPUT

CLAMP

AND SYNC

SEPARATOR

OSCOUT OSCIN OSCGND CVBS BLACK IREF

Fig.1 Block diagram; pin numbers for DIP16.

June 1994 3

321876

MLB725

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

PINNING

SYMBOL

DESCRIPTION

DIP16 SO20L

CVBS 1 1 composite video input
BLACK 2 2 video black level storage pin
n.c. − 3 not connected
IREF 3 4 reference current input

PIN

V

DD

V

SS1

4 5 +5 V supply

5 6 0 V ground 1 (main ground pin)
OSCOUT 6 7 27 MHz crystal oscillator output
n.c. − 8 not connected
OSCIN 7 9 27 MHz crystal oscillator input
OSCGND 8 10 27 MHz crystal oscillator ground
V

SS2

V

SS3

9 11 0 V ground 2; connect to V

10 12 0 V ground 3; connect to V

SS1
SS1

n.c. − 13 not connected
V

SS4

SCL 12 15 serial clock open-drain input for I
SDA 13 16 serial data open-drain input/output for I

11 14 connect to V

in normal operation

SS1

2

C-bus

2

C-bus
i.c. − 17 internally connected; do not connect in normal operation
AD 14 18 programmable I2C-bus address bit input
INT 15 19 interrupt open-drain output
V

SS5

16 20 connect to V

in normal operation

SS1

handbook, halfpage

CVBS

BLACK

IREF

V

DD

V

SS1

OSCOUT

OSCIN

OSCGND

1
2
3
4

SAA5233

5
6
7
8

MLB726

V

16

SS5

15

INT

14

AD

13

SDA

12

SCL
V

11

SS4

V

10

SS3

V

9

SS2

Fig.2 Pin configuration; DIP16.

June 1994 4

handbook, halfpage

OSCOUT

OSCGND

1

CVBS

BLACK

OSCIN

2
3

n.c.

4

V

5

DD

V

SS1

n.c. n.c.

SAA5233

6
7
8
9

10

MLB727

20
19
18
17
16
15
14
13
12
11

V

SS5
INT
AD
i.c.IREF
SDA

SCL
V

SS4

V

SS3
V

SS2

Fig.3 Pin configuration; SO20L.

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

Imax

V

Omax

I

IOmax

I

Omax

T

amb

T

stg

supply voltage −0.3 +6.5 V
maximum input voltage (any input) −0.3 VDD+ 0.3 V
maximum output voltage (any output) −0.3 VDD+ 0.3 V
maximum DC input or output diode current −±20 mA
maximum output current (any output) −±10 mA
operating ambient temperature −20 +70 °C
storage temperature −55 +125 °C

June 1994 5

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

QUALITY AND RELIABILITY

This device will meet the requirements of the
accordance with

“Quality Reference Pocketbook (order number 9398 510 34011)”

“Philips Semiconductors General Quality Specification SNW-FQ-611E”

. The principal requirements are as

shown in Tables 1 to 4.

Group A
Table 1 Acceptance tests per lot.

TEST REQUIREMENTS

(1)

Mechanical cumulative target: <100 ppm
Electrical cumulative target: <100 ppm

Group B
Table 2 Processability tests (by package family).

TEST REQUIREMENTS

(1)

Solderability <7% LTPD
Mechanical <15% LTPD
Solder heat resistance <15% LTPD

Group C
Table 3 Reliability tests (by process family).

TEST CONDITIONS REQUIREMENTS

(1)

Operational life 168 hours at Tj= 150 °C <1500 FPM; equivalent to <100 FITS

at Tj=70°C

Humidity life temperature, humidity, bias

<2000 FPM
(1000 hours, 85 °C, 85% RH or
equivalent test)

Temperature cycling performance T

stg(min)

to T

stg(max)

<2000 FPM

in

Table 4 Reliability tests (by device type).

TEST CONDITIONS REQUIREMENTS

ESD and latch-up ESD Human body model

2000 V; 100 pF; 1.5 kΩ
ESD Machine model

200 V; 200 pF; 0 Ω
latch-up 100 mA; 1.5 × V

DD

(absolute maximum)

Note to Tables 1 to 4.

1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.

June 1994 6

(1)

<15% LTPD

<15% LTPD

<15% LTPD

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

CHARACTERISTICS

V

= 4.5 to 5.5 V; VSS=0V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

I

DD

supply voltage 4.5 5.0 5.5 V
supply current − 30 45 mA

Inputs

CVBS
V

sync

V

vid(p-p)

sync voltage amplitude 0.1 0.3 0.6 V
video voltage amplitude

(peak-to-peak value)

V

dat(text)

Teletext data voltage
amplitude

V

dat(vps)

Z

source

Z

I

C

I

VPS data voltage amplitude 0.30 0.50 0.70 V
source impedance −−250 Ω
input impedance 2.5 5.0 − kΩ

input capacitance −−10 pF
IREF
R

V

gnd

IREF

resistor to ground − 27 − kΩ

input reference voltage − 0.5V
AD
V

IL

V

IH

I

LI

C

I

LOW level input voltage −0.3 − +0.3V

HIGH level input voltage 0.7V

input leakage current VI=0toV

input capacitance −−10 pF
SCL
V

IL

V

IH

I

LI

C

I

f

clk

t

r

t

f

LOW level input voltage −0.3 − +0.3V

HIGH level input voltage 0.7V

input leakage current VI=0toV

input capacitance −−10 pF

clock frequency 0 − 100 kHz

input rise time 0.3VDDto 0.7V

input fall time 0.7VDDto 0.3V

= −20 to +70 °C; unless otherwise specified.

amb

0.7 1.0 1.4 V

0.30 0.46 0.70 V

DD

DD

DD
DD

−10 − +10 µA

−10 − +10 µA

−−1000 ns

−−300 ns

DD

DD

DD

− V

DD

− VDD+ 0.3 V

DD

− VDD+ 0.3 V

V

V

June 1994 7

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Outputs

INT (OPEN-DRAIN OUTPUT)
V

PU

V

OL

I

OL

C

L

t

f

Inputs/Outputs

BLACK
C

black

I

LI

SDA (OPEN-DRAIN OUTPUT)
V

IL

V

IH

I

LI

C

I

C

L

t

r

t

f

V

OL

t

f

CRYSTAL OSCILLATOR (OSCIN; OSCOUT)

V

osc

G

v

C

I

C

fb

pull-up voltage at pin −−V

DD

LOW level output voltage IOL= 3 mA 0 − 0.4 V

LOW level output current −−4.0 mA

load capacitance −−400 pF

output fall time CL= 100 pF;

0.7VDDto 0.3V

DD

−−100 ns

storage capacitor to ground − 100 − nF

input leakage current VI=0toV

DD

LOW level input voltage −0.3 − +0.3V

HIGH level input voltage 0.7V

input leakage current VI=0toV

DD

−10 − +10 µA

V

DD

DD

− VDD+ 0.3 V

−10 − +10 µA

input capacitance −−10 pF

load capacitance −−400 pF

input rise time 0.3VDDto 0.7V

input fall time 0.7VDDto 0.3V

DD
DD

−−1000 ns

−−300 ns

LOW level output voltage IOL= 3 mA 0 − 0.4 V

output fall time CL= 400 pF;

0.7VDDto 0.3V

oscillator voltage amplitude

DD

−−200 ns

− 1.0 − V

(peak-to-peak value)

small signal voltage gain − 1.0 −

input capacitance −−10 pF

feedback capacitance − 1 − pF

June 1994 8

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2

C-bus timing (see Fig.4)

I

f

clk

t

BUF

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

t

HD;DAT

t

SU;DAT

t

r

t

f

t

SU;STO

Note

1. After this time the first clock pulse is generated.

SCL clock frequency 0 − 100 kHz

bus free time between a

4.7 −−µs

STOP and START

repeated START hold time note 1 4.0 −−µs

SCL clock LOW time 4.7 −−µs

SCL clock HIGH time 4.0 −−µs

set-up time for a repeated

4.7 −−µs

START

data hold time 0 −−ns

data set-up time 250 −−ns

SDA, SCL input rise time 0.3VDDto 0.7V

SDA, SCL input fall time 0.7VDDto 0.3V

DD
DD

−−1000 ns

−−300 ns

set-up time for STOP 4.0 −−µs

ndbook, full pagewidth

SDA

SCL

SDA

MBC764

t

BUF

t

HD;STA

t

LOW

t

r

t

HD;DAT

t

SU;STA

Fig.4 I2C-bus timing diagram.

t

HIGH

t

f

t

SU;DAT

t

SU;STO

June 1994 9

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

FUNCTIONAL DESCRIPTION
Control of device

The function of the device is controlled via the I

2

C-bus.

Pin AD provides a choice of two alternative addresses.
The PDC acquisition section requires little software control

apart from enabling the interrupts which occur when data
is found. Interrupts can be enabled for either Teletext
packet 8/30/2 or VPS and both can be enabled to allow for
the presence of both standards being transmitted on the
same TV channel. The interrupt register is accessed as
address 01 WRITE, see Section “Register 01: Interrupt
(reset state X00X XXXX)”.

When an interrupt is signalled, a bit is set in the status
register to indicate its source. Information about the
received PDC data is given in the status register D5 and
D6. The microcontroller must service the ‘data received’
interrupts within 40 ms (VPS) or 200 ms
(Teletext packet 8/30/2), since new data may be written
after this period. The status register is accessed as
address 00 READ; see Section
“Register 00:Control/Status (reset state XXX0 XX00)”.
When the status register has been read the data received
flags and interrupt signal are reset.

Data of both types is constantly received and stored, but
can be selectively acquired by setting bits D1 and D0 of the
control register. This allows acquisition of only Teletext
packet 8/30/2 on every VBI line or only VPS data on every
VBI line. The control register is accessed as address
00 WRITE, see Section “Register 00:Control/Status (reset
state XXX0 XX00)”.

Storage of PDC data

The PDC data memory is accessed at address 02 (HEX)
to 31 (HEX). The exact addresses of Teletext packet
8/30/2 and VPS data is shown in Table 5.

T

ELETEXT DATA

The Teletext packet 8/30/2 data is stored after hardware
Hamming correction. There are 4 data bits stored in the
lower nibble of each byte in address 11 (HEX)
to 1D (HEX); see Table 13, in the order shown in Table 5.
The status message, which is odd parity coded, is stored
as a byte which represents a Teletext character in address
1E (HEX) to 31 (HEX); see Table 14.

VPS

DATA

The VPS data from Line 16 is stored in register address
02 (HEX) to 0F (HEX) in the order shown in Table 5. VPS

data is biphase decoded and stored with 4 data bits stored
in the lower nibble of each byte, in the same way as
Teletext packet 8/30/2 data; see Tables 11 and 12. In
addition to the VCR data, Word 4
(Program Source Identification, ASCII sequential) is
stored, which may be useful for future applications.

2

The stored data is read via the I

C-bus in the normal way.
Multiple reception/majority error correction of the data is
the responsibility of the control software, the device simply
stores the data as transmitted after Hamming or biphase
decoding. As both VPS and Teletext packet 8/30/2 signals
are stored separately, it is possible to deal with future
situations where both EBU PDC System A and EBU PDC
System B transmissions may be present on the same TV
channel, the defaults and level of service being chosen by
the software control.

Error indication

Indication of errors in the received data is given in two
ways and is programmable by setting bit D4 in the control
register.

The first is a flag to indicate Hamming or biphase errors
and is stored with the related data in bit 0 of the upper
nibble of the data byte.

The second is no interrupt which is sent to the
microcontroller but the data signal quality bit (D7) is set.

The level of interrupt is controlled by the Interrupt
Error Level bit which is D4 of the control register. If this bit
is not set then an interrupt only occurs if an error free line
of either Teletext packet 8/30/2 or VPS data is received
and stored in RAM. If this bit is set then an interrupt occurs
if the correct framing code and Teletext packet header
8/30/2 is found, or the correct start code for VPS data is
found. The data is then stored in the RAM with any errors
indicated in the upper nibble. This may be used by more
sophisticated software, which could decide the importance
of an error in a particular nibble.

2

I

C-bus interface

EATURES

F

• Standard I2C-bus slave transceiver

• Operates from 0 to 100 kHz

• Acknowledge function is performed

• Auto-increment between registers and direct addressing

• Selectable I2C-bus slave address dependent on

address pin AD.

June 1994 10

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

Register map

The data received when address locations 00 (HEX) to 31 (HEX) are read or written is shown in Table 5.

Table 5 Register map.

ADDRESS (HEX) DATA

00 control/status direct
01 interrupt direct
02 VPS B5 direct/auto-increments to 03
03 VPS B5 direct/auto-increments to 04
04 VPS B11 direct/auto-increments to 05
05 VPS B11 direct/auto-increments to 06
06 VPS B12 direct/auto-increments to 07
07 VPS B12 direct/auto-increments to 08
08 VPS B13 direct/auto-increments to 09
09 VPS B13 direct/auto-increments to 0A
0A VPS B14 direct/auto-increments to 0B
0B VPS B14 direct/auto-increments to 0C
0C VPS B15 direct/auto-increments to 0D
0D VPS B15 direct/auto-increments to 0E
0E VPS B4 direct/auto-increments to 0F
0F VPS B4 stop value
10 − direct

11 8/30/2 B13 direct/auto-increments to 12
12 8/30/2 B14 direct/auto-increments to 13
13 8/30/2 B15 direct/auto-increments to 14
14 8/30/2 B16 direct/auto-increments to 15
15 8/30/2 B17 direct/auto-increments to 16
16 8/30/2 B18 direct/auto-increments to 17
17 8/30/2 B19 direct/auto-increments to 18
18 8/30/2 B20 direct/auto-increments to 19
19 8/30/2 B21 direct/auto-increments to 1A
1A 8/30/2 B22 direct/auto-increments to 1B
1B 8/30/2 B23 direct/auto-increments to 1C
1C 8/30/2 B24 direct/auto-increments to 1D
1D 8/30/2 B25 direct/auto-increments to 1E
1E status message direct/auto-increments to 1F

: : direct/auto-increments

31 status message stop value

(1)

ADDRESSING

Note

1. For the address range 02H to 0FH, even addresses hold the least significant nibble and odd addresses hold the most
significant nibble. BXX refers to byte definitions, EBU specification of the domestic video PDC system.

June 1994 11

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

Register 00:Control/Status (reset state XXX0 XX00)

Register 00 is split into two parts. The control part (WRITE only) consisting of bits D4, D1 and D0 and status part (READ
only) consisting of bits D7 to D5.

Table 6 Register 00.

D7 D6 D5 D4 D3 D2 D1 D0

−−−IEL −−ACQ 8/30/2 ACQ VPS

DSQ 8/30/2 RF VPS RF −−−−−

Table 7 Register 00 bit description.

SYMBOL BIT FUNCTION

IEL D4 Interrupt Error Level.

When logic 0, signal only completely valid data lines from Teletext packet 8/30/2
received and VPS received flags.
When logic 1, signal valid framing code and Teletext packet header 8/30/2 received or
valid start codeword for VPS received.

ACQ 8/30/2
ACQ VPS

DSQ D7 Data Signal Quality.

8/30/2 RF D6 8/30/2 Received Flag.

VPS RF D5 VPS Received Flag.

D1
D0

Acquire 8/30/2.
Acquire VPS.
Allows selective decoding of either Teletext packet 8/30/2 data or VPS data. If both are
set to the same value the system automatically selects the format being transmitted
(see Table 8).

When logic 1, good Teletext or VPS data signal is being received.
When logic 0, no Teletext or VPS data signal is being received.

When logic 1, and IEL (D4) = logic 0 an error-free Teletext packet 8/30/2 has been
received, Hamming decoded and stored in the RAM. When logic 1, and IEL(D4) =
logic 1 a Teletext packet with a valid framing code and 8/30/2 header has been
received, Hamming decoded and stored in RAM.
When logic 0 no Teletext packet 8/30/2 data received.

When logic 1, and IEL(D4) = logic 0, an error-free VPS data line has been received,
biphase decoded and stored in the RAM. When logic 1, and IEL(D4) = logic 1 a VPS
data line with valid start code has been received, biphase decoded and stored in RAM.
When logic 0 no VPS data received.

Table 8 Selection of Teletext packet 8/30/2 data or VPS data.

ACQ 8/30/2 ACQ VPS FUNCTION

0 0 use automatic selection algorithm for line 16
0 1 acquire only VPS data on every VBI line
1 0 acquire only 8/30/2 data on every line 16
1 1 use automatic selection algorithm for line 16

June 1994 12

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

Register 01: Interrupt (reset state X00X XXXX)

Register R01 is WRITE only.

Table 9 Register 01.

D7 D6 D5 D4 D3 D2 D1 D0

− 8/30/2 IE VPS IE −−−−−

Table 10Register 01 bit description.

SYMBOL BIT FUNCTION

8/30/2 IE D6 8/30/2 Interrupt Enable.

This allows the reception of Teletext packet 8/30/2 data to be signalled on the INT pin.
When logic 0 reception of Teletext packet 8/30/2 data is not signalled on INT pin.
When logic 1 reception of Teletext packet 8/30/2 data is signalled on INT pin.

VPS IE D5 VPS Interrupt Enable.

This allows the reception of VPS data to be signalled on the INT pin.
When logic 0 reception of VPS data is not signalled on INT pin.
When logic 1 reception of VPS data is signalled on INT pin.

Register 02 to 0F (HEX): VPS data bytes

A single VPS data bytes is stored as two memory bytes, the least significant nibble of both memory bytes is the data
making up the single VPS data byte. The most significant nibble of each memory byte is used to indicate a biphase error
in the least significant nibble. This is indicated by the least significant bit being set, the top three bits are not used and
are fixed to logic 0 (see Table 11).

Table 11VPS data bytes.

ADDRESS (HEX) REGISTER DATA

02 VPS B5 least significant nibble 0000 1100
03 VPS B5 most significant nibble 0000 0101

Note

1. Equivalent to VPS B5 0101 1100 (MSB to LSB).

Table 12Register 02.

D7 D6 D5 D4 D3 D2 D1 D0

−−−BIPHASE
ERROR BIT

Register 11 to 1D (HEX): Teletext packet 8/30/2 data bytes

Data is stored as single bytes. The four least significant bits represent the data. The fifth bit if set indicates a Hamming
error in the stored data. The top three bits of the byte are not used and are fixed to logic 0.

DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0

(1)
(1)

Table 13Register 11.

D7 D6 D5 D4 D3 D2 D1 D0

−−−HAMMING
ERROR BIT

June 1994 13

DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

Register 1E to 31D (HEX): Status display message

Data is stored as bytes which represent a Teletext character. The data is odd parity checked, if a parity error occurs this
causes the byte not to be written to the RAM. The MSB is not used and is fixed to logic 0.

Table 14Register 11.

D7 D6 D5 D4 D3 D2 D1 D0

− DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0

I2C-bus slave address

The slave address for the device can take one of two
values dependent on the state of the input pin AD.

Table 15Device address.

AD SLAVE ADDRESS

0 0010 001X
1 0010 000X

(1)
(1)

Note

1. Where X is the R/

2

C-bus increment

I

W bit.

The I2C-bus will also increment between registers as listed
in Table 16

Table 16Increment between registers.

ADDRESS CONTENTS

02 to 0F (HEX) VPS data bytes
11 to 31 (HEX) Teletext packet 8/30/2 data bytes and

Status display message

Addressing any register in either of these ranges will
initialize an increment until the final stop value provided
each byte is acknowledged by the receiver.

Initialization during power-up

The device has an internal power-on reset unit which is
used to reset the I

2

C-bus interface to be a slave
transceiver. It also initializes the device to receive only
completely valid Teletext packet 8/30/2 and VPS data. The
interrupt signals for both Teletext packet 8/30/2 and VPS
are disabled.

June 1994 14

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

APPLICATION INFORMATION

handbook, full pagewidth

3.3
kΩ

video

input

15 pF

4.7 µH

27 MHz 3rd

overtone

5 V

100

nF

100 nF

27 kΩ

33
µF

10

pF

100 nF

100

nF

1

2

3

4

5

6

7

8

CVBS

BLACK

IREF

V

DD

SAA5233

V

SS1

OSCOUT

OSCIN

OSCGND

V

SS5

INT

AD

SDA

SCL

V

SS4

V

SS3

V

SS2

MLB728

16

220 Ω

15

14

13

(1)

12

11

10

9

5 V

4.7
kΩ

INT to
microcontroller

2

I C bus
to microcontroller

(1) I2C-bus address 0010 001R/W.

Fig.5 Application diagram; DIL16.

Table 17Crystal characteristics.

SYMBOL PARAMETER TYP. MAX. UNIT

Crystal (27 MHz, 3rd overtone)

C1 series capacitance 1.7 − pF
C0 parallel capacitance 5.2 − pF
C

L

R

r

load capacitance 20 − pF

resonance resistance − 50 Ω
R1 series resistance 20 −Ω
X

a

X

j

X

d

ageing −±5×10

adjustment tolerance −±25 × 10

drift −±25 × 10

−6

−6

−6

year

−1

June 1994 15

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

PACKAGE OUTLINES

handbook, full pagewidth

seating plane

3.9

3.4

2.2

max

22.00

21.35

3.7

4.7

max

max

0.51
min

2.54
(7x)

1.4 max

16

1

0.53
max

0.254 M

9

6.48

6.14

8

0.32 max

8.25

7.80

7.62

9.5

8.3

MSA254

Dimensions in mm.

Fig.6 Plastic dual in-line package; 16 leads (300 mil); DIP16, SOT38-1.

June 1994 16

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

handbook, full pagewidth

S

pin 1

index

13.0

12.6

0.1 S

0.9

(4x)

0.4

1120

2.45

0.3

2.25

0.1

110

detail A

1.27

0.49

0.36

0.25 M

(20x)

7.6

7.4

10.65

10.00

1.1

0.5

1.1

1.0

0.32

0.23

0 to 8

MBC234 - 1

A

2.65

2.35

o

Dimensions in mm.

Fig.7 Plastic small outline package; 20 leads; large body; SO20L, SOT163-1.

June 1994 17

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

SOLDERING
Plastic dual in-line packages

Y DIP OR WAVE

B
The maximum permissible temperature of the solder is

260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low-voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.

Plastic small-outline packages

BYWAVE
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

R

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

June 1994 18

Philips Semiconductors Objective specification

Dual standard PDC decoder SAA5233

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

PURCHASE OF PHILIPS I

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

June 1994 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: INTEGRATED CIRCUITS:

Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. [phone] ext. 2336, Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,

P.O. Box 10 63 23, 20043 HAMBURG,
Tel. [phone], Fax. [phone].

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,

6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. [phone], Fax. [phone]

India: Philips INDIA Ltd, Components Dept,

Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS COMPONENTS S.r.l.,

Viale F. Testi, 327, 20162 MILANO,
Tel. [phone], Fax. [phone].

Japan: Philips Bldg 13-37 , Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD32 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

533061/01/1500/pp20 Date of release: June 1994
Document order number: 9397 736 20011

Philips Semiconductors