DATASHEETS saa4960 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA4960

Integrated PAL comb filter

Preliminary specification
File under Integrated Circuits, IC02

1996 Oct 15

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

FEATURES

• One chip adaptive PAL comb filter

• Time discrete but continuous amplitude signal

processing with analog interfaces

GENERAL DESCRIPTION

The SAA4960 is an adaptive alignment-free one chip
comb filter compatible with PAL systems and provides
high performance in Y/C separation.

• Internal delay lines, filters, clock processing and signal
switches

• Alignment-free

• No hanging dots or residual cross colour on vertical

transients

• Few external components.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CCA

V

DDD

V

CCO

V

CCPLL

I

CCO

I

DDD

I

CCA

I

CCPLL

V

17(p-p)

V

10(p-p)

V

1(p-p)

V

14(p-p)

V

12(p-p)

V

15(p-p)

analog supply voltage 4.75 5 5.5 V
digital supply voltage 4.75 5 5.5 V
analog supply voltage output buffer 4.75 5 5.5 V
analog supply voltage PLL 4.75 5 5.5 V
analog supply current output buffer − 70 90 mA
digital supply current − 10 20 mA
analog supply current − 35 40 mA
analog supply current PLL − 1.5 3.0 mA
CVBS and Y input signal (peak-to-peak value) 0.7 1 1.4 V
chrominance input signal (peak-to-peak value) − 0.7 1 V
subcarrier input signal (peak-to-peak value) 100 200 400 mV
luminance output signal (peak-to-peak value) 0.6 1 1.54 V
chrominance output signal (peak-to-peak value) − 0.7 1.1 V
CVBS and Y output signal (peak-to-peak value) 0.6 1 1.54 V

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA4960 DIP28 plastic dual in-line package; 28 leads (600 mil) SOT117-1

1996 Oct 15 2

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

BLOCK DIAGRAM

A

A

+5 V

100 µF

D

+5 V

100 µF

A

handbook, full pagewidth

+5 V

100 µF

A

+5 V

100 nF

100 nF

100 nF

100 nF

100 nF

524

REFBP REFDL

47 Ω

DDD

V

21 22

DGND

CCO

V

OGND

11 8

CCA

V

AGND

97

CCPLL

V

VOLTAGE

REFERENCE

CURRENT

REFERENCE

CONT1

CONT2

LPF

CONTROL

LPFO1

CL3

CVBSO
15

LPFO1

DELAY

S2A

CVBSDL

COMPENSATION

CONT1

CL3

STOPS

CCOMB

CONT1

CL3

−1

CL3

O

C

12

LPFO2

BPF

COMB

FILTER

BPF

S2C

CONT1

CL3

CL3

BPF

SAA4960

CL3

CL3

MHA366

28

4162

i.c. i.c. i.c. i.c.

O

Y
14

S2B

YCOMB

LPFO1

BPF

Fig.1 Block diagram.

CL3

LINES

DELAY

SYSPAL

HSEL

100 nF

100 µF

A

A

D

26 27

PLLGND

DET

V

DET

H

1

FSC

HSEL

3

BYP

CL3

SYSP AL

CLOCK

CONTROL

61325

SSYN

STOPS

FSCSW

COMBENA

H

1996 Oct 15 3

DET

SYNC

19

CSY
A

DET

V

SEPARATOR

100 nF

CLAMP

17

/CVBS

ext

Y

100 nF

S1

LPFI

+5 V

CONT2

18

LPFION

23

n.c.

20

n.c.

BIAS

ext 10

C

100 nF

Remark: all switches in LOW position.

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

PINNING

SYMBOL PIN DESCRIPTION

FSC 1 subcarrier frequency input
i.c. 2 internally connected
BYP 3 bypass mode forcing input
i.c. 4 internally connected
REFBP

SSYN 6 bypass definition input
V

CCA

V

CCO

AGND 9 analog ground (signal reference)
C

ext

OGND 11 analog ground output buffer
C

O

FSCSW 13 f
Y

O

CVBSO 15 uncombed CVBS output signal
i.c. 16 internally connected

/CVBS 17 CVBS (VBS) input signal

Y

ext

LPFION 18 disable alias-filter
CSY 19 storage capacitor
n.c. 20 not connected
DGND 21 digital ground
V

DDD

n.c. 23 not connected
REFDL 24 decoupling capacitor for delay lines
COMBENA 25 COMB-mode output signal
PLLGND 26 analog ground PLL
V

CCPLL

i.c. 28 internally connected

decoupling capacitor for band-pass

5

filter reference

7 analog supply voltage
8 analog supply voltage output buffer

10 external chrominance input signal

12 chrominance output signal

reference selection input

sc

14 luminance output signal

22 digital supply voltage

27 analog supply voltage PLL

handbook, halfpage

FSC

1

i.c.

2

BYP

3

i.c.

4

REFBP

FSCSW

SSYN
V

CCA

V

CCO

AGND

C

ext

OGND

C

Y

5
6
7

SAA4960

8

9
10
11
12

O

13

O

MHA365

Fig.2 Pin configuration.

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

i.c.
V

CCPLL

PLLGND
COMBENA
REFDL
n.c.
V

DDD

DGND
n.c.
CSY
LPFION
Y

/CVBS

ext

i.c.
CVBSO

1996 Oct 15 4

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

FUNCTIONAL DESCRIPTION
Functional requirements

The PAL comb filter processes the video standards PAL B,
G and H. PAL D and I signals can also be processed but
with the drawback of a slightly reduced bandwidth.

For SECAM and SVHS signals, the input signals can be
bypassed to the output without processing by selecting the
BYPASS-mode.

A sync separation circuit is incorporated to generate
control signals for the internal clock processing. With a
sync compression of up to 12 dB the sync separator works
properly (see Fig.4).

The IC is controlled via four pins:

1. BYP forces the IC into the BYPASS-mode (comb filter
function off)

2. SSYN defines whether the COMB-mode is entered
synchronously or not and defines the polarity of the
BYP pin

3. FSCSW selects the reference frequency f

or 2 × f

sc

sc

4. LPFION enables the internal pre-filter.

It is possible to select the following modes of operation:

COMB-mode: Luminance and chrominance comb filter
function active if BYPASS-mode not active.

BYPASS-mode: Signal processing not active, all clocks
inactive, C
Y

/CVBS (pin 17) is bypassed to YO (pin 14) and

ext

(pin 10) is bypassed to CO (pin 12) and

ext

CVBSO (pin 15). This mode is forced via BYP (pin 3).

If the stimulus of the mode is changed, the IC is following
the new mode after the stabilization time given in Table 1.

Table 1 Stabilization time after mode change

MAXIMUM

MODE CHANGE

STABILIZATION

TIME

COMB-mode to BYP ASS-mode 1 line
BYP ASS-mode to COMB-mode 1 field

The mode change from BYPASS to COMB depends on
SSYN (pin 6) and can be asynchronous or synchronous
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.

Pin description

FSC (

PIN 1)

Input for the reference frequency fsc (see note 2 of Chapter
“Characteristics”) or 2 × fsc. For SECAM standard signals
the best signal performance in BYPASS-mode is achieved
by switching the FSC input signal off externally.

BYP (

PIN 3)

Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
frequencies. Thus applications are supported where the
operation mode (COMB or BYPASS) is controlled by the
DC-level of the FSC input signal at pin 1. For those
applications the BYP input can be externally connected to
FSC (pin 1).

Depending on SSYN (pin 6) the function of BYP can be
adapted to a certain application with respect to the polarity
of the logic level and with respect to the behaviour when
entering the COMB-mode.

Dependent on SSYN the BYP input can be either inverted
or non-inverted with the function as shown in Table 2:

Table 2 Bypass function

SSYN BYP SELECTED MODE

LOW LOW COMB-mode
LOW HIGH BYPASS-mode
HIGH LOW BYPASS-mode
HIGH HIGH COMB-mode

Dependent on SSYN the behaviour when entering the
COMB-mode is different for the both selectable logic
polarities while the BYPASS-mode is always entered
asynchronously (immediately).

Table 3 Behaviour when entering the COMB-mode

SSYN ENTERING COMB-MODE

LOW immediately if BYP = LOW
HIGH synchronized by vertical pulse if BYP = HIGH

The PLL and the clock processing are always stopped if
the selected level for BYPASS is applied to BYP
(independent of the vertical pulse).

1996 Oct 15 5

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

REFBP (PIN 5)
Decoupling capacitor for the band-pass filter reference

voltage.

SSYN (

PIN 6)

Input signal that controls the function of BYP (pin 3).

V

CCA,VCCO,VDDD

AND V

(PINS 7, 8, 22 AND 27)

CCPLL

Supply voltages.

AGND, OGND, DGND

AND 26)

21

AND PLLGND (PINS 9, 11,

Ground connection. AGND is used as signal reference for
all analog input and output signals.

(PIN 10)

C

ext

Input for an external chrominance signal which is
correlated to the external VBS signal.

(PIN 12)

C

O

Chrominance output signal. This output can be switched
between the comb filtered chrominance from the CVBS
signal and the external chrominance signal from the input
C

if the IC is forced into BYPASS-mode.

ext

Table 4 C

MODE C

output signal

O

OUTPUT SIGNAL

O

COMB comb filtered chrominance signal
BYPASS external chrominance signal of C

ext

input

Table 6 YO output signal

MODE Y

OUTPUT SIGNAL

O

COMB comb filtered luminance signal
BYPASS external CVBS signal of Y

CVBSO (

PIN 15)

/CVBS input

ext

CVBS output signal directly from the input in
BYPASS-mode or delayed by the signal processing time
of 2 lines and an additional processing delay.

Table 7 CVBSO output signal

MODE CVBSO OUTPUT SIGNAL

COMB delay compensated CVBS signal
BYPASS external CVBS signal of Y

/CVBS (PIN 17)

Y

ext

/CVBS input

ext

Input for the CVBS signal or for an external VBS signal.

LPFION (

PIN 18)

Input signal to disable the internal pre-filter LPFI.

Table 8 Pre-filter mode

LPFION SELECTED MODE

LOW LPFI inactive
HIGH LPFI active
Floating LPFI active

CSY (

PIN 19)

FSCSW (

PIN 13)

Input signal to select between fsc or 2 × fsc as reference at
the FSC input pin.

Table 5 Reference frequency selection

FSCSW SELECTED REFERENCE

HIGH 2 × f
LOW f

(PIN 14)

Y

O

sc

sc

VBS output signal. This output can be switched between
the comb filtered luminance signal (including
synchronization) and the external (C)VBS signal from the
input Y

/CVBS. In COMB-mode the output signal is

ext

delayed by 2 lines and by an additional processing delay.

1996 Oct 15 6

Sync top capacitor for the sync separator.

REFDL (

PIN 24)

Decoupling capacitor for the delay line reference voltage.

COMBENA (

PIN 25)

Output signal that indicates the current mode of operation.
This output is forced to LOW if the comb filter is in
BYPASS-mode.

Table 9 Mode of operation

COMBENA SELECTED MODE

LOW BYP ASS-mode; PLL and clock processing

stopped

HIGH COMB-mode

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

Internal functional description

S

WITCHED CAPACITOR DELAY LINE

Delays the CVBS input signal by 2 lines and 4 lines. Input
signals for the delay lines are the CVBS signal, the clock
CL3 (3 × fsc), the control signal HSEL and the standard
selection signal SYSPAL.

Output signals are the non-delayed, the 2-line delayed and
the 4-line delayed CVBS signal.

WITCHED CAPACITOR BAND-PASS FILTERS (BPF)

S
The comb filter input BPFs attenuate the low frequencies

to guarantee a correct signal processing within the logical
comb filter.

The comb filter output BPF reduces the alias components
that are the result of the non-linear signal processing within
the logical comb filter.

OGICAL COMB FILTER

L
Separates the chrominance from the band-pass filtered

CVBS signal.

OMPENSATION DELAY

C
Compensates the internal processing time of the

band-pass filters and the logical comb filter section.

DDER

A
The comb filtered luminance output signal is obtained by

adding the delayed CVBS signal and the inverted comb
filtered chrominance signal.

OW-PASS FILTER INPUT (LPFI)

L
Analog input low-pass filter to reduce the outband

frequencies of EMC. The input low-pass filter is included in
the signal path but it can be switched off via the input
signal LPFION.

OW-PASS FILTER OUTPUT (LPFO1 AND LPFO2)

L
Two different types of output low-pass filters (LPFO1 and

LPFO2) are necessary to get equal signal delays within the
luminance path and the chrominance path (important for
good transient behaviour). The low-pass output filter type
LPFO1 is used for the luminance output while LPFO2 is
used for the chrominance output. The filters are analog 3
order elliptic low-pass filters that convert the output signals
from the time discrete to the time continuous domain
(reconstruction filter).

LPF

CONTROL

Automatic tuning of the low-pass filters is achieved by
adjusting the filter delays. The control information for all
filters (CONT1 and CONT2) is derived from a built-in
reference filter (LPFO1-type) that is part of a control loop.
The control loop tunes the reference filter delay and thus
all other filter delays to a time constant derived from the
system clock CL3.

C

ONTROL AND CLOCK PROCESSING (CLOCK CONTROL)

The control and clock processing block (see Fig.7)
consists of the sub-blocks PLL, the clock processing and
the mode control. The PLL and the clock processing are
released for operation if the input level at BYP selects the
COMB-mode.

Main tasks of the control and clock processing are:

• Clock generation of system clock CL3

• Delay line start control

• Mode control.

The signal processing is based on a 3 × fsc system clock
(CL3), that is generated by the clock processing from the
fscsignal at FSC (pin 1) via a PLL. Because the subcarrier
frequency divided by the line frequency results not in an
integer value a clock phase correction of 180° is necessary
every second line for PAL standards. The clock phase
correction is controlled by the input signals horizontal
sync. Additionally the delay line start is synchronized once
a field to the input signals horizontal sync. The 25 Hz PAL
offset is corrected in this way.

The PLL provides a master clock MCK of 6 × fsc, which is
locked to the subcarrier frequency at FSC (pin 1).

The system clock CL3 (3 × fsc) is obtained from MCK by a
divide-by-two circuit. The 180° phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle.

The generated clock is a pseudo-line-locked clock that is
referenced to fsc. The sync separator generates the
necessary signals H

DET

and V

indicating the line (H)

DET

and the field (V) sync periods.
The current mode of operation (BYPASS or COMB) is

external readable via COMBENA (pin 25).

rd

1996 Oct 15 7

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

The input signals of the control and clock processing
(CLOCK CONTROL) are:

H

: analog horizontal pulse from sync separator

DET

V

: analog vertical pulse from sync separator

DET

FSC: subcarrier frequency (fsc or 2 × fsc)
FSCSW: reference frequency selection
BYP: BYPASS control signal
SSYN: vertical synchronous mode selection for BYP

and polarity selection of BYP.

The output signals are:

CL3: system clock (3 × fsc)
HSEL’s: line start signals for the delay lines
STOPS: forces the comb filter via the switches S2A,

S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or
asynchronous with V

; depending on SSYN)

INT

COMBENA: HIGH during COMB-mode; otherwise
LOW.

Table 10 Function of STOPS signal

STOPS-STATE SELECTED MODE

LOW COMB
HIGH BYPASS

Table 11 Function of signal switch S1

LPFION-STATE DELAY LINE INPUT

LOW non-pre-filtered input signal

/CVBS

Y

ext

HIGH pre-filtered input signal Y
Floating pre-filtered input signal Y

IGNAL SWITCH S2A

S

/CVBS

ext

/CVBS

ext

For the CVBSO output two signals can be selected via the
signal switch S2A.

Table 12 CVBSO output signal

STOPS-STATE

CVBSO OUTPUT

SIGNAL

MODE

LOW delayed input CVBSDL COMB
HIGH non-delayed input

/CVBS

Y

ext

BYPASS

SIGNAL SWITCHES S2B AND S2C
Two switches are included to bypass the comb filter signal

processing. The input video signal C

for the switch S2C

ext

is internally biased.
For the YO output two signals can be selected via S2B.

H

ORIZONTAL AND VERTICAL SYNC SEPARATOR

A build-in sync separator circuit generates the H
V

signals from the Y

DET

/CVBS input signal. This circuit

ext

DET

and

is still working properly at input signals with a 12 dB
attenuated sync in a normal 700 mV black-to-white video
signal (see Fig.4).

LAMP

C
The black level clamping of the video input signal is

performed by the sync separator stage. The clamping level
is nearly adequate to the voltage at REFDL (pin 24).

IGNAL SWITCH S1

S
The switch is included to bypass the low-pass input filter.
For the CVBS input of the delay line block two signals can

be selected via the slow signal switch S1.

Table 13 Y

STOPS-STATE Y

output signal

O

OUTPUT SIGNAL MODE

O

LOW YCOMB

(combed luminance)

HIGH input Y

For the C

Table 14 C

STOPS-STATE C

output two signals can be selected via S2C.

O

output signal

O

OUTPUT SIGNAL MODE

O

LOW CCOMB

(combed chrominance)

HIGH input C

COMB

/CVBS BYPASS

ext

COMB

ext

BYPASS

1996 Oct 15 8

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V input voltage protection threshold except pin 1 −0.3 V
I

CC

I

O

supply voltage − 6.5 V

+ 0.3 V

CC

total supply current − 155 mA
output current (CO, YO and CVBSO) −±15 mA
output current (COMBENA) − 10 mA

P

tot

T

amb

T

stg

V

es

total power dissipation − 900 mW
operating ambient temperature 0 70 °C
storage temperature −25 +150 °C
electrostatic handling note 1

Note

1. Human Body Model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; charge device model: C = 200 pF; R = 0 Ω; V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 31 K/W

1996 Oct 15 9

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

CHARACTERISTICS

V

DDD=VCCA=VCCO=VCCPLL

C = 0.7 V (p-p) (0 dB); input signal FSC = 200 mV (p-p), sine wave, DC level = 2 V; input signal LPFION = 5 V; test
signal: EBU colour bar 100/0/75/0
source impedance for FSC = 75 Ω; load impedance for CVBSO, Y
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply voltage

V
V

CCA
CCO

analog supply voltage (pin 7) note1 4.75 5 5.5 V
analog supply voltage output buffer

(pin 8)

V

DDD

V

CCPLL

digital supply voltage (pin 22) note 1 4.75 5 5.5 V
analog supply voltage PLL (pin 27) note 1 4.75 5 5.5 V

FSC (pin 1)

V

1(p-p)

input AC voltage (peak-to-peak value) 100 200 400 mV
input AC voltage is valid for

sine wave −−−−
square wave 0.4 0.5 0.6 duty

V
C
I
Z

1

1

leak

1

input DC level 0 − 5.3 V
input capacitance −−10 pF
input leakage current −−10 µA
source impedance −−800 Ω

BYP (pin 3)

V
V
I
C

IH
IL

leak

3

HIGH level input voltage 2.4 − V
LOW level input voltage 0 0.85 1.5 V
input leakage current −−10 µA
input capacitance −−10 pF

REFBP (pin 5)

V

5

DC voltage 1.1 1.25 1.4 V

SSYN (pin 6)

V
V
I

leak

C

V

I

CCA

V

I

CCO

IH
IL

6

CCA

CCO

(pin 7)

(pin 8)

HIGH level input voltage 2.4 − V
LOW level input voltage 0 0.85 1.5 V
input leakage current −−10 µA
input capacitance −−10 pF

analog supply current − 35 40 mA

supply current − 70 90 mA

=5V; T

“CCIR471-1”

=25°C; input signal Y

amb

; source impedance for Y

/CVBS=1V(p-p) (0 dB); input signal

ext

/CVBS, C

ext

, CO=1kΩ and 20 pF in parallel; unless otherwise

O

=75Ω decoupled with 100 nF;

ext

note 1 4.75 5 5.5 V

CC

CC

cycle

V

V

1996 Oct 15 10

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C

(pin 10)

ext

V

10

R

10

C

10

Z

10

C

(pin 12)

O

V

10/V12

COMB-mode: transfer function C-path see Fig.8
V

12

 DC jump when forcing into

∆V

12

R

12

R

L

C

L

V

17/V12

FPN fixed pattern noise for divided clock

α

cr

S/N signal-to-noise ratio (0.7 V/V

α

cr

V

12(p-p)

G

d

FSCSW (pin 13)

V

IH

V

IL

C

13

I

leak

input voltage (AC coupled) − 03dB
input resistance 1.25 V 500 700 1000 kΩ
input capacitance −−10 pF
source impedance −−1kΩ

BYPASS-mode: CO/C

ext

fsc±0.3fsc; note 2 −1 0 +1 dB

DC offset voltage related to input −400 0 +400 mV

− 100 450 mV

BYPASS-mode
output resistance − 10 100 Ω
load resistance (to ground) 0.3 −−kΩ
load capacitance (to ground) −−25 pF
suppression (comb depth) see Fig.5 and

note 3

26 30 − dB
20 24 − dB

H

20 24 − dB

H

−−−30 dB

−−−50 dB

−−−37 dB

−−−30 dB

frequencies referenced to 0.7 V (p-p)

crosstalk suppression at vertical

283 × f

H

(283 − 43) × f
(283 + 35) × f

0.75f

sc

f

sc

1.5f

sc

2f

sc

see Fig.3 26 30 − dB

transients no-colour ↔ colour

noise) unweighted;

eff

56 72 − dB

fsc±0.3fsc; note 2
crosstalk between different inputs 0 to 5 MHz −−60 −40 dB
FSC residue in BYPASS-mode related

−−−60 dB

to 700 mV (p-p)
differential gain 0.95 −−

HIGH level input voltage 2 − V

CC

V
LOW level input voltage 0 − 0.8 V
input capacitance −−10 pF
input leakage current −−10 µA

1996 Oct 15 11

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

YO (pin 14)

V

14/V17

BYPASS-mode: CO/C

ext

COMB-mode: transfer function Y-path see Fig.9
V

14

 DC jump when forcing into

∆V

14

DC offset voltage related to input −400 0 +400 mV

BYPASS-mode

R

14

R

L

C

L

V

17/V14

output resistance − 10 100 Ω
load resistance (to ground) 0.3 −−kΩ
load capacitance (to ground) −−25 pF
suppression (comb depth) seeFig.6 and

FPN fixed pattern noise for divided clock

frequencies referenced to 0.7 V (p-p)
black-to-white

α

cr

crosstalk suppression at vertical
transients gray ↔ multi-burst

S/N signal-to-noise ratio (0.7 V/V

α

cr

V

14(p-p)

crosstalk between different inputs 0 to 5 MHz −−60 −40 dB
FSC residue in BYPASS-mode related

noise) unweighted;

eff

to 700 mV (p-p)

G

d

differential gain 0.95 −−

CVBSO (pin 15)

V

15/V17

BYPASS-mode: CVBSO/CVBS 0 to 5 MHz −1 0 +1 dB

COMB-mode: transfer function CVBS-path see Fig.9
V

15

 DC jump when forcing into

∆V

15

DC offset voltage −400 0 +400 mV

BYPASS-mode

R

15

R

L

C

L

output resistance − 10 100 Ω
load resistance (to ground) 0.3 −−kΩ
load capacitance (to ground) −−25 pF

FPN fixed pattern noise for divided clock

frequencies referenced to 0.7 V (p-p)
black-to-white

S/N signal-to-noise ratio (0.7 V/V

noise) unweighted;

eff

0 to 5 MHz −1 0 +1 dB

− 200 450 mV

note 3

283.75 × f

H

(283.75 − 43) × f
(283.75 + 35) × f

0.75f

sc

f

sc

1.5f

sc

2f

sc

26 30 − dB
10 12 − dB

H

18 24 − dB

H

−−−40 dB

−−−30 dB

−−−30 dB

−−−20 dB

see Fig.3 26 30 − dB

56 72 − dB

200 kHz to 5 MHz

−−−60 dB

− 200 450 mV

0.75f
f

sc

1.5f
2f

sc

sc

sc

−−−40 dB

−−−30 dB

−−−30 dB

−−−20 dB

56 72 − dB

200 kHz to 5 MHz

1996 Oct 15 12

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

α

cr

V

15(p-p)

G

d

P

d

Y

/CVBS (pin 17)

ext

V

17

I

17

V

17

Z

17

LPFION (pin 18)

V

IH

V

IL

I

18

C

18

CSY (pin 19)

V

19

V

(pin 22)

DDD

I

DDD

REFDL (pin 24)

V

24

COMBENA (pin 25)

V

OL

V

OH

I

OH

V

CCPLL

I

27

Notes to the characteristics

crosstalk between different inputs 0 to 5 MHz −−60 −40 dB
FSC residue in BYPASS-mode related

−−−60 dB

to 700 mV (p-p)
differential gain 0.95 −−
differential phase − 2 3 deg

input voltage (AC coupled) 12 dB sync

−3 0 +3 dB
attenuation
possible; see Fig.4

input current during sync pulse −10 −8.0 −µA
input current during active video − 0.84 1.5 µA
DC voltage during black level 1.1 1.25 1.4 V
source impedance −−1kΩ

HIGH level input voltage 2 − V

CC

LOW level input voltage 0 − 0.8 V
input current 0.8 V − 820µA

2.0 V − 820µA

input capacitance −−10 pF

DC voltage 0 2.45 V

CC

supply current − 10 20 mA

DC voltage 1.1 1.25 1.4 V

LOW level output voltage 3 mA 0.26 0.4 0.55 V
HIGH level output voltage 4 − V

CC

HIGH level output current 2.4 V −55 −24 −µA

(pin 27)

supply current − 1.5 3 mA

V

V

V

∆VV

1.

∆VV
∆VV

– 300 mV≤= ∆VV

CCAVDDD

– 300 mV≤= ∆VV

CCAVCCO

– 300 mV≤= ∆VV

CCOVDDD

All voltages are related to AGND.

2. Subcarrier frequency f

= 4.43361875 MHz.

sc

3. Line frequency fH= 15.625 kHz.

1996 Oct 15 13

– 300 mV≤=

CCAVCCPLL

– 300 mV≤=

CCOVCCPLL

– 300 mV≤=

DDDVCCPLL

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

handbook, full pagewidth

input

output

line 1 line 2

line 3 line 4 line 5 line 6 line 7 line 8

vertical transient

Fig.3 Vertical transmission by different video signals from line to line.

1.0

MHA367

(V)

0.45

0.3

0.225

0.15

0

Fig.4 EBU colour bar 100/0/75/0 with 12 dB sync attenuation.

1996 Oct 15 14

MHA370

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

U, V: PAL B, G, H, D, I

f

sc

handbook, full pagewidth

U

(n − 0.25)f

Y

H

nf

H

Y

(n − 1)f

V

H

(n − 0.75)f

H

Fig.5 Principle frequency response of a comb filtered PAL chrominance signal.

U, V: PAL B, G, H, D, I

f

sc

MHA368

Y

V

(n − 1)f

H

(n − 0.75)f

H

Fig.6 Principle frequency response of a comb filtered PAL luminance signal.

1996 Oct 15 15

U

(n − 0.25)f

Y

nf

H

H

MHA369

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

SSYN

BYP

H

DET

V

DET

FSC

FSCSW

1

1

&

V

INT

CL3

MCK

1

COMBENA

STOPS

CL3

4

HSEL
V

INT

= 1

&

1

CLOCK

PROCESSING

PLL

Fig.7 Clock control.

1996 Oct 15 16

STOP

MHA371

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

gain
(dB)

+1

0

−1

−3

−25

−30

0.4 0.66 0.85 1 1.12 1.35 2.0 2.26 2.7
frequency (fsc)

Fig.8 Chrominance path: tolerance band with anti-alias filter.



MHA372

handbook, full pagewidth

gain
(dB)

+1

0

−1

−2

−3

−5

−32

0.7 1 1.12 1.5 2.26 2.7

Fig.9 Luminance and CVBSO path: tolerance band with anti-alias filter.

1996 Oct 15 17

frequency (fsc)

MHA373

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

DDDS

V

1

33 µH

DDD

V

i.c.

28

2

µF

100

nF

100

10

nF

CCPLL

V

CCPLL

V

27

CCOS

V

COMBENA

PLLGND

26

1

2

33 µH

100

100

10

CCO

V

COMBENA

25

µF

nF

nF

REFDL

24

100

100

µF

nF

n.c.

CCAS

V

33 µH

V

23

1

CCA

DDD

V

2

100

100

10

DDD

V

22

µF

nF

nF

DGND

21

CCPLLS

1

V

33 µH

CCPLL

V

n.c.

20

2

100

100

10

CSY

µF

nF

nF

19

100 nF

LPFION

18

MHA374

CVBS

/CVBS

ext

Y

17

75 Ω

100 nF

i.c.

10 kΩ

CVBSO

16

15

Fig.10 Test circuit.

SAA4960

FSC

FSC

2

1

i.c.

75 Ω

3

BYP

i.c.

4

5

6

7

CCA

SSYN

100 nF

V

CCA

V

REFBP

47 Ω

1996 Oct 15 18

CCO

V

8

CCO

V

9

AGND

11

12

13

FSCSW

2

1

O

Y

DDD

V

10 kΩ

14

SVHS-Y

10

OGND

O

C

SVHS-C

4

SVHS

10 kΩ

3

ext

C

100 nF

75 Ω

ext

C

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

SVHS-C

SVHS-VBS

CVBS1

CVBS2

5.6 kΩ

TDA8540



SWITCH

I

2

C-bus

COMBENA

C

ext

10 12

SAA4960




Y

/CVBS

ext

COMB FILTER

17

613

SSYN FSCSW

+5 V

325

BYP

1

FSC

14

15

C

Y

CVBSO

Fig.11 Application diagram: SAA4960 with TDA9141.

O

O

CVBSO

TDA9141

MSD

TDA4665

BBDL

2

C-bus

I

−(R − Y)

−(B − Y)

VB

MHA375

handbook, full pagewidth

SVHS-C

SVHS-VBS

CVBS1

CVBS2

TDA8540



SWITCH

I

2

C-bus

Y

ext

I2C-bus

C

ext

/CVBS

PCF8574

2

I

C-I/O PORT

COMBENA

10 12

COMB FILTER

17

613

SSYN FSCSW

+5 V



325

SAA4960




BYP

1

FSC

14

15

3.3 kΩ

C

O

Y

O

CVBSO

Fig.12 Application diagram: SAA4960 with TDA9160/62.

+5 V

BC548

1 kΩ

TDA9160/62

MSD

TDA4665

BBDL

2

I

4.43 MHZ

−(R − Y)

−(B − Y)

VB
TXT

C-bus

MHA376

1996 Oct 15 19

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

handbook, full pagewidth

SVHS-VBS

SVHS-C

CVBS1

CVBS

I2C-bus

C

ext

10 12

TDA8540



SWITCH

int

2

I

C-bus

Y

/CVBS

ext

17

PCF8574



2

I

C-I/O PORT

BYP

3

SAA4960




COMB FILTER

613

SSYN FSCSW

FSC

1

14

15

C

O

Y

O

CVBSO

CVBSO

IF input

TDA8366

MSD

TDA4665

BBDL

2

I

R

G

B

C-bus

MHA377

Fig.13 Application diagram: SAA4960 with TDA8366.

handbook, full pagewidth

SVHS-C

SVHS-VBS

CVBS1

CVBS2

Remark: all switches in LOW position.

TDA8540



SWITCH

2

I

C-bus

I2C-bus

C

ext

10 12

Y

/

ext

CVBS

17

PCF8574

2

I

C-I/O PORT

SAA4960

COMB FILTER

613

SSYN FSCSW



BYP




+5 V

3

1

Fig.14 Application diagram: SAA4960 with TDA4655.

1996 Oct 15 20

FSC

14
15

2 × FSC

C

O

Y

O

CVBSO

CHROMINANCE

BANDPASS

LUMINANCE

TRAP

TDA4655

MSD

TDA4665

BBDL

−(R − Y)

−(B − Y)

VBS

CVBSO

MHA378

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

PACKAGE OUTLINE

handbook, full pagewidth

DIP28: plastic dual in-line package; 28 leads (600 mil)

SOT117-1

seating plane

L

Z

28

1

pin 1 index

D

A

2

A

A

1

e

b

w M

b

1

15

E

14

c

M

(e )

M

E

1

H

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE

VERSION

SOT117-1

1 2

min.

max.

1.7

1.3

0.066

0.051

IEC JEDEC EIAJ

051G05 MO-015AH

b

b

1

0.53

0.38

0.020

0.014

0.32

0.23

0.013

0.009

REFERENCES

cD E weM

(1) (1)

36.0

35.0

1.41

1.34

1996 Oct 15 21

14.1

13.7

0.56

0.54

(1)

92-11-17
95-01-14

Z

max.

1.75.1 0.51 4.0

0.0670.20 0.020 0.16

L

3.9

3.4

EUROPEAN

PROJECTION

M

15.80

15.24

0.62

0.60

H

E

17.15

15.90

0.68

0.63

0.252.54 15.24

0.010.10 0.60

ISSUE DATE

e

1

0.15

0.13

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

(order code 9398 652 90011).

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

stg max

). If the

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Oct 15 22

Philips Semiconductors Preliminary specification

Integrated PAL comb filter SAA4960

NOTES

1996 Oct 15 23

Philips Semiconductors – a worldwide company

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Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
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Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
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20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
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Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 537021/1200/01/pp24 Date of release: 1996Oct 15 Document order number: 9397 750 01366