DATASHEETS saa3323 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA3323

Drive processor for DCC systems

Preliminary specification
File under Integrated Circuits, IC01

Philips Semiconductors

May 1994

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

FEATURES

• Operating supply voltage: 2.7 to 3.6 V

• Low power dissipation: 84 mW (typ)

• Single chip digital equalizer, tape formatting and error

correction

• 8-bit flash analog-to-digital converter (ADC) for low
symbol error rate

• Two switchable Infinite Impulse-Response (IIR) filter
sections

• 10-tap Finite Impulse-Response (FIR) filter per main
data channel, with 8 bit coefficients, identical for all main
channels

• 10-tap FIR filter for the AUX channel

• Analog and digital eye outputs

• Interrupt line triggered by internal auxiliary envelope

processing e.g. label, counter, and others

• Robust programmable digital PLL clock extraction unit

• Low power SLEEP mode

• Slew rate limited Electromagnetic Compatibility (EMC)

friendly output

• Digital Compact Cassette (DCC) optimized error
correction

• Programmable symbol synchronization strategy for tape
input data

• Microcontroller control of capstan servo possible during
playback and recording

• Frequency and phase regulation of capstan servo
during playback

• Choice of Dynamic Random Access Memory (DRAM)
and Static Random Access Memory (SRAM) types for
system Random Access Memory (RAM)

• Scratch pad RAM for microcontroller in system RAM

• Integrated interface for Precision Adaptive Sub-band

Coding (PASC) data bus

• Three wire microcontroller ‘L3’ interface

• Protection against invalid auxiliary data

• Seamless joins between recordings.

GENERAL DESCRIPTION

The SAA3323 performs the drive processor function in the
DCC system. This function is built up of digital equalizer,
error correction and tape formatting functions. The digital
equalizer is intended for use with DCC read amplifiers
TDA1318 or TDA1380. The tape formatting and error
correction circuit is intended for use with PASC ICs
SAA2003 and SAA2013, and write amplifiers TDA1319 or
TDA1381.

ORDERING INFORMATION

TYPE NUMBER

SAA3323H 80 TQFP80
SAA3323GP 80 QFP80

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

Pocketbook”

May 1994 2

are followed. The pocketbook can be ordered using the code 9398 510 34011.

PINS PIN POSITION MATERIAL CODE

(1)

(1)

PACKAGE

plastic SOT315-1
plastic SOT318-2

“Quality Reference

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

BLOCK DIAGRAM

handbook, full pagewidth

SBDIR

SBMCLK

SBEF

SBDA

SBCL

SBWS

SAA3323

SUB-BAND

2

I S

INTERFACE

DIGITAL-

TO-ANALOG

CONVERTER

PHASE

LOCKED

LOOP

TAPE

INPUT

BUFFER

ERROR

CORRECTOR

ZERO

CROSSING

INTERNAL DATA BUS

RAM

INTERFACE

8116

(1)

FIR

IIR

AUXILIARY
ENVELOPE

DETECTION

ANAEYE

RDSYNC

(2)

ANALOG

TO-DIGITAL

CONVERTER

EQUALIZER

MODULE

TAPE

OUTPUT

BUFFER

CONTROL

INTERFACE

RDMUX
BIAS
V

ref(p)

V

ref(n)

TCLOCK
WDATA

SPEED
URDA
RESET
SLEEP

L3REF
L3DATA

(1) FIR = Finite Impulse-Response.
(2) IIR = Infinite Impulse-Response.

OEN

WEN

D0 to D7

A0 to A10

A11 to A16

Fig.1 Block diagram.

PINO1

PINO2

PINI

L3INT

L3CLK

L3MODE

MLB761

May 1994 3

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

PINNING

SYMBOL

PIN

DESCRIPTION TYPE

(1)

QFP80 TQFP80

SBWS 1 79 word select for sub-band PASC interface I/O (1 mA)
SBCL 2 80 bit clock for sub-band PASC interface I/O (1 mA)
SBDA 3 1 data line for sub-band PASC interface I/O (1 mA)
SBDIR 4 2 direction line for sub-band PASC interface O (1 mA)
SBMCLK 5 3 master clock for sub-band PASC interface I
URDA 6 4 unreliable data O (1 mA)
L3MODE 7 5 mode line for L3 interface I
L3CLK 8 6 bit clock line for L3 interface I
L3DATA 9 7 serial data line for L3 interface I/O (2 mA)
L3INT 10 8 L3 interrupt output O (1 mA)
V
V

DD1
SS1

11 9 digital supply voltage S

12 10 digital ground S
L3REF 13 11 L3 bus timing reference O (1 mA)
RESET 14 12 reset SAA3323 I
SLEEP 15 13 sleep mode selection of SAA3323 I
CLK24 16 14 24.576 MHz clock input I
AZCHK 17 15 channel 0 and channel 7 azimuth monitor O (1 mA)
MCLK 18 16 6.144 MHz clock output O (1 mA)
TEST3 19 17 TEST3 output; do not connect O (1 mA)
ERCOSTAT 20 18 ERCO status, for symbol error rate measurements O (1 mA)
OEN 21 19 output enable for RAM O (2 mA)
A10/

RAS 22 20 address SRAM; RAS DRAM O (2 mA)
V
V

DD2
SS2

23 21 digital supply voltage S

24 22 digital ground S
D7 25 23 data SRAM I/O (4 mA)
D6 26 24 data SRAM I/O (4 mA)
D5 27 25 data SRAM I/O (4 mA)
D4 28 26 data SRAM I/O (4 mA)
D3 29 27 data SRAM; data DRAM I/O (4 mA)
D2 30 28 data SRAM; data DRAM I/O (4 mA)
D1 31 29 data SRAM; data DRAM I/O (4 mA)
V
V

DD7
SS7

32 30 digital supply voltage for RAM S

33 31 digital ground for RAM S
D0 34 32 data SRAM; data DRAM I/O (4 mA)
A0 35 33 address SRAM; address DRAM O (2 mA)
A1 36 34 address SRAM; address DRAM O (2 mA)
A2 37 35 address SRAM; address DRAM O (2 mA)
A3 38 36 address SRAM; address DRAM O (2 mA)

May 1994 4

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL

DESCRIPTION TYPE

QFP80 TQFP80

A4 39 37 address SRAM; address DRAM O (2 mA)

PIN

V
V

SS3
DD3

40 38 digital ground S

41 39 digital supply voltage S
A5 42 40 address SRAM; address DRAM O (2 mA)
A6 43 41 address SRAM; address DRAM O (2 mA)
A7 44 42 address SRAM; address DRAM O (2 mA)
A12/PINO5 45 43 address SRAM; Port expander output 5 O (2 mA)
A14/PINO1 46 44 address SRAM; Port expander output 1 O (2 mA)
A16/PINO3 47 45 address SRAM; Port expander output 3 O (2 mA)
A15/PINO4 48 46 address SRAM; Port expander output 4 O (2 mA)
WEN 49 47 write enable for RAM O (2 mA)
A13/PINO2 50 48 address SRAM; Port expander output 2 O (2 mA)
A8 51 49 address SRAM; address DRAM O (2 mA)
V

DD4

V

SS4

CAS 54 52 address SRAM; CAS for DRAM O (2 mA)

A9/

52 50 digital supply voltage S

53 51 digital ground S

A11 55 53 address SRAM O (2 mA)
SPEED 56 54 Pulse Width Modulation (PWM) capstan control output for deck O
PINO2 57 55 Port expander output 2 O

(1 mA)

t

(1 mA)

t

WDATA 58 56 serial output to write amplifier O (1 mA)
TCLOCK 59 57 3.072 MHz clock output for tape I/O O (1 mA)
V

SS5

V

DD5

TEST2 62 60 TEST mode select; do not connect I
RDMUX 63 61 analog multiplexed input from read amplifier I
V

ref(p)

V

ref(n)

SUBSTR 66 64 substrate connection I
BIAS 67 65 bias current for ADC I
V

SSA

V

DDA

ANAEYE 70 68 analog eye pattern output O

60 58 digital ground S

61 59 digital supply voltage S

64 62 ADC positive reference voltage I

65 63 ADC negative reference voltage I

68 66 analog ground S

69 67 analog supply voltage S

pd
A
A
A
A
A

A

RDSYNC 71 69 synchronization output for read amplifier O (1 mA)
V
V

DD6
SS6

72 70 digital supply voltage S

73 71 digital ground S
CHTST1 74 72 channel test pin 1 O (1 mA)
CHTST2 75 73 channel test pin 2 O (1 mA)
TEST0 76 74 TEST mode select; do not connect I
TEST1 77 75 TEST mode select; do not connect I

pd
pd

(1)

May 1994 5

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL

PIN

DESCRIPTION TYPE

(1)

QFP80 TQFP80

PINI 78 76 Port expander input I
PINO1 79 77 Port expander output 1 O (1 mA)
SBEF 80 78 sub-band PASC error flag line O (1 mA)

Note

1. I = input; IA= analog input; Ipd= input with pull-down resistance; I/O = bidirectional; O = output; OA= analog output;
Ot= 3-state output; S = supply.

handbook, full pagewidth

SBDA

SBDIR

SBMCLK

URDA

L3MODE

L3CLK

L3DATA

L3INT

V

DD1

V

SS1

L3REF
RESET
SLEEP

SBWS

SBCL

80
1
2
3
4
5
6
7
8
9

10
11
12
13

SBEF

PINO1

79

78

77

PINI
76

TEST1
75

74

CHTST1

CHTST2
73

72

SAA3323

TEST0

V

SS6

71

DD6

V

70

ANAEYE

RDSYNC
69

68

V

67

DDA

V

SSA

66

BIAS
65

ref(n)Vref(p)

V

SUBSTR

64

63

62

RDMUX
61

60
59
58
57
56
55
54
53
52
51
50
49
48

TEST2

V

DD5

V

SS5

TCLOCK
WDATA

PINO2
SPEED
A11

A9/CAS

V

SS4

V

DD4
A8
A13/PINO2

MCLK

OEN

14
15
16
17
18
19
20

25

26

21

DD2

V

22

SS2

V

23
D7

24
D6

D5

D4

27

D3

28
D2

29
D1

V

CLK24

AZCHK

TEST3

ERCOSTAT

A10/RAS

Fig.2 Pin configuration (SOT315-1; TQFP80).

May 1994 6

30

DD7

31

SS7

V

32
D0

A0

47

WEN
A15/PINO4

46

A16/PINO3

45

A14/PINO1

44

A12/PINO5

43

A7

42

A6

41

35

36

37

38

39

DD3

V

40
A5

MLB762

34

33

A1

A2

A3

A4

SS3

V

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

SBMCLK

L3MODE

L3DATA

ERCOSTAT

A10/RAS

SBWS
SBCL

SBDA

SBDIR

URDA

L3CLK

L3INT

V

DD1

V

SS1

L3REF

RESET

SLEEP

CLK24

AZCHK

MCLK

TEST3

OEN

V

DD2

V

SS2

DD6

SBEF

PINO1

80

79
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PINI
78

TEST1
77

76

CHTST2
75

TEST0

SS6

V

CHTST1
74

73

SAA3323

V

72

ANAEYE

RDSYNC
71

70

DDA

V

69

SSA

V

68

BIAS

67

ref(n)

SUBSTR

V

66

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

V

ref(p)

RDMUX
TEST2

V

DD5

V

SS5

TCLOCK

WDATA
PINO2
SPEED
A11
A9/CAS

V

SS4

V

DD4

A8
A13/PINO2

WEN
A15/PINO4
A16/PINO3
A14/PINO1

A12/PINO5
A7
A6
A5

V

DD3

25

26

D7

D6

27
D5

D4

29

30

31
D1

32

DD7

V

28

D2

D3

Fig.3 Pin configuration (SOT318-2; QFP80).

May 1994 7

33

SS7

V

34
D0

35
A0

36
A1

37
A2

38
A3

39
A4

40

SS3

V

MLB763

May 1994 8

FUNCTIONAL DESCRIPTION

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

RAM

41464

analog

output

analog

input

IEC958

analog CC

L output

analog CC

R output

L

DAC

TDA1305

R

SFC3
SAA2003
STEREO

FILTER CODEC

2

ADAS3

SAA2013

ADAPTIVE

ALLOCATION

L

R

baseband

I S

ADC

SAA7366

DIGITAL

AUDIO I/O

TDA1315

2

filtered I S

AUDIO IN/OUT PASC PROCESSOR

sub-band

2

I S

BUFFER

64K x 4

DRP

SAA2023

OR

SAA3323

DRIVE

PROCESSOR

search data

TAPE DRIVE PROCESSING

speed control

WRAMP

TDA1381

WRITE AMP.

RDAMP

TDA1380

READ AMP.

FIXED
HEAD

CAPSTAN

DRIVE

TAPE

MECHANICS

DRIVERS

detect
switch

SYSTEM CONTROL

Fig.4 DCC system block diagram.

handbook, full pagewidth

SYSTEM

MICROCONTROLLER

MBD620

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

A simplified block diagram of the SAA3323 is shown in
Fig.1.

DCC drive processing

The SAA3323 provides the following functions for the DCC
drive processing.

LAYBACK MODES

P

• Analog-to-digital conversion

• Tape channel equalization

• Tape channel data and clock recovery

• 10-to-8 demodulation

• Data placement in system RAM

• C1 and C2 error correction decoding

• Interfacing to sub-band serial PASC interface

• Interfacing to microcontroller for SYSINFO and AUX

data

• Capstan control for tape deck.

R

ECORD MODES

• Interfacing to sub-band serial PASC interface

• C1 and C2 error correction encoding

• Formatting for tape transfer

• 8-to-10 modulation

• Interfacing to microcontroller for SYSINFO and AUX

data

• Capstan control for tape deck, programmable by
microcontroller.

S

EARCH MODE

Table 1 Basic modes of TFE module.

MODE EXPLANATION

DPAP audio and SYSINFO (main data) play;

AUX play

DPAR audio and SYSINFO (main data) play;

AUX record

DRAR audio and SYSINFO (main data) record;

AUX record

REGISTERS

TFE
The TFE module has 8 writable and 5 readable registers

that are accessible via the L3 interface, one write register
(CMD) and four read registers (STATUS0 to STATUS3)
which are directly addressable, the other registers are
indirectly addressable via commands sent to the CMD
register. The registers are named as shown in Table 2.

Table 2 TFE register names.

REGISTER NAME READ/WRITE

CMD W
STATUS0 R
STATUS1 R
STATUS2 R
STATUS3 R
SET0 W
SET1 W
SET2 W
SET3

(1)

W
SPDDTY W
BYTCNT W
RACCNT W
SPEED R

• Detection and interpretation of AUX envelope
information

• AUX envelope counting

• Search speed estimation.

Tape Formatting and Error (TFE) correction module

The TFE module has 3 basic modes of operation as shown
in Table 1.

May 1994 9

Note

1. The 4 LSBs of register ‘SET3’ set RAM type (RType)
and RAM timing (RTim). See Table 3.

For normal operation the 4 MSBs of register ‘SET3’
should be logic 0.

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 3 RAM settings by register SET3.

RAM REGISTER SET3

RTYPE 0 bit 0
RTYPE 1 bit 1
RTim 0 bit 2
RTim 1 bit 3

TFE

DATA STREAMS

The TFE module has three read/write data streams that
are accessible via the L3 interface and they are shown in
Table 4.

Table 5 TFE commands.

NAME

RDSPEED 00000000read SPEED register
LDSET0 00010000load new TFE settings register 0
LDSET1 00010001load new TFE settings register 1
LDSET2 00010010load new TFE settings register 2
LDSET3 00010011load new TFE settings register 3
LDSPDDTY 00010101load SPDDTY register
LDBYTCNT 00010111load BYTCNT register
LDRACCNT 00011000load RACCNT register
RDAUX 00100000read AUXILIARY information
RDSYS 00100001read SYSINFO
RDDRAC Y Z 100010read RAM data bytes (8 bits) from quarter YZ
RDWDRAC Y Z 100011read RAM data words (12 bits) from quarter YZ
WRAUX 00110000write AUXILIARY information
WRSYS 00110001write SYSINFO
WRDRAC Y Z 110010write RAM data bytes (8 bits) to quarter YZ
WRWDRAC Y Z 110011write RAM data words (12 bits) to quarter YZ

COMMAND BYTE

76543210

Table 4 TFE data streams.

DATA STREAM NAME READ/WRITE

SYSINFO R/W
AUXINFO R/W
Scratch pad RAM R/W

COMMANDS’

TFE ‘
These are the commands that need to be sent to the TFE

in order to access the indirectly accessible registers and
the data streams, see Table 5.

EXPLANATION

Digital equalizer module

The digital equalizer module has 2 basic modes of
operation as shown in Table 6.

Table 6 Basic modes of equalizer module.

MODE EXPLANATION

Play main data and AUX channels are

equalized

Search only AUX channel is processed; AUX

envelope information is processed

May 1994 10

DIGITAL EQUALIZER REGISTERS
The digital equalizer module has 9 write only, 3 read only

and 1 read/write register(s) that are accessible via the
L3 interface, one write register (CMD) and 2 read registers
(STATUS0 and STATUS1) which are directly addressable,
the other registers are indirectly addressable via
commands sent to the CMD register. The registers are
named as shown in Table 7.

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 7 Digital equalizer register names.

REGISTER NAME READ/WRITE

CMD W
STATUS0 R
STATUS1 R
COEFCNT W
FCTRL W
CHT1SEL W
CHT2SEL W
ANAEYE W
AEC R/W
SSPD R
INTMASK W
DEQ2SET W
CLKSET W

Table 9 Digital equalizer commands.

COMMAND BYTE

NAME

76543210

WRCOEF 0 0 1 1 0 0 0 0 write FIR coefficients to the digital equalizer buffer bank
RDCOEF 0 0 1 0 0 0 0 0 read FIR coefficients from the digital equalizer active bank
LDCOEFCNT 0 0 0 1 0 0 1 1 load FIR coefficient counter
LDFCTRL 0 0 0 1 0 1 0 0 load filter control register
LDT1SEL 0 0 0 1 0 1 1 0 load CHTST1 pin selection register
LDT2SEL 0 0 0 1 0 1 1 1 load CHTST2 pin selection register
LDTAEYE 0 0 0 1 1 0 0 0 load ANAEYE channel selection register
LDAEC 0 0 0 1 1 0 0 1 load AEC counter
RDAEC 0 0 1 0 0 0 1 0 read AEC counter
RDSSPD 0 0 1 0 0 1 0 0 read SEARCH speed register
LDINTMSK 0 0 0 1 0 0 1 0 load interrupt mask register
LDDEQ3SET 0 0 0 1 0 0 0 0 load digital equalizer settings register
LDCLKSET 0 0 0 1 0 0 0 1 load PLL clock extraction settings register

DATA STREAMS
The digital equalizer module has one write only and one

read only data stream that are accessible via the
L3 interface and they are shown in Table 8.

Table 8 Digital equalizer data streams.

DATA STREAM NAME READ/WRITE

FIR coefficients to buffer bank W
FIR coefficients from active bank W

IGITAL EQUALIZER “COMMANDS”

D
These are the commands that need to be sent to the digital

equalizer in order to access the indirectly accessible
registers and the data streams.

EXPLANATION

Table 10 Filter control register.

BIT 7654321 0

Meaning −−−µCS
Default 0 0 0 0 1 0 1 1

Note

1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time
that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient
number 9 has been received.

May 1994 11

(1)

SH1 SH0 Reserved

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 11 SH1 and SH2 (FIR output scaling).

SH

10

0 0 FIR mod 256
01

10

11

EFFECT ON FIR OUTPUT

FIR

mod 256

---------­2

FIR

mod 256

---------­4

FIR

mod 256

---------­8

Transfer of FIR coefficients

For the main data channels (tracks 0 to 7) there are
10 coefficients (taps) each of 8 bits, where all of the data
channels make use of the same coefficients. The
addresses for the main data coefficients 0 to 9 are
0to9

There are ten coefficients (taps) each of 8 bits for the aux
channel (CHAUX). The addresses for the auxiliary
coefficients 0 to 9 are 16 to 25

respectively.

dec

respectively.

dec

There are 2 banks of coefficients for both the aux and the
main data channels, namely the ‘buffer’, and the ‘active’
banks. The microcontroller writes only to the ‘buffer’
banks, and reads only from the ‘active’ banks.

The microcontroller can poll the digital equalizer status bit
BKSW to see when the switch occurs. BKSW starts life
LOW, goes HIGH as a result of the bank switching and
goes LOW as result of the complete value of a main data
coefficient being received by the digital equalizer.

The microcontroller sets µCS HIGH before sending the
new set of aux or main data coefficients, the digital
equalizer resets it once the bank switch occurs.

The actual FIR coefficients that are used are a function of
the tape head, read amplifier and type of tape (i.e.
pre-recorded or own recorded) used, such information is
outside of the scope of this data sheet.

Coefficient address counter (COEFCNT)

This 5 bit counter is used to point to the FIR coefficient to
be transferred to or from the digital equalizer.

Table 12 Coefficient address counter.

BIT 7654321 0

Meaning −−−CC4 CC3 CC2 CC1 CC0
Default 0 0 0 0 0 0 0 0

Pin explanations and interfacing to other hardware

RESET
This is an active HIGH input which resets the SAA3323

and brings it into its default mode, DPAP. This reset does
not affect the contents of the FIR filter coefficients in the
digital equalizer. This should be connected to the system
reset, which can be driven by the microcontroller. The
duration of the reset pulse should be at least 15 µs.

SLEEP
This pin is an active HIGH input which puts the SAA3323

in a low power consumption SLEEP mode. This pin should
be connected to the DCC SLEEP signal, which can be
driven by the microcontroller. The CLK24 clock may be
stopped and the VREFP and VREFN inputs brought to
ground while the SAA3323 is in ‘sleep’ mode to further
reduce power consumption. When recovering from sleep

mode, the SLEEP pin should be taken LOW and the
SAA3323 reset.

CLK24
This is the 24.576 MHz clock input and should be

connected directly to the SAA2003 (pin CLK24).

Sub-band serial PASC interface connections

The timing for the sub-band serial PASC interface is given
in Figs 5 to 7.

May 1994 12

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

SBCL(in)
SBWS(in)
SBDA(in)

SBCL(in)
SBWS(in)
SBDA(in)

SBCL(in)

SBWS(in)

SBDA(in)

bit number

2 x t 40 ns

MCLK

40 ns

1514131211109876543210

31302928272625242322212019181716

V

IH

V

OH

V

IH

V

OH

V

IH

V

OH

MGB381

Fig.5 Sub-band serial PASC interface timing; DRAR mode.

May 1994 13

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

SBCL(out)
SBWS(out)
SBDA(out)
SBEF(out)

SBCL(out)
SBWS(out)
SBDA(out)
SBEF(out)

SBMCLK(in)

SBCL(out)

SBWS(out)

SBDA(out)

SBDA(out)

60 ns

7 ns

7 ns

1514131211109876543210

31302928272625242322212019181716

bit number

V

IH

V

IL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

MGB382

Fig.6 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 1.

May 1994 14

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

SBCL(in)
SBWS(in)
SBDA(out)
SBEF(out)

SBCL(in)
SBWS(in)
SBDA(out)
SBEF(out)

SBCL(in)

SBWS(in)

SBDA(out)

SBDA(out)

2 x t 40 ns

MCLK

t (40 85) ns

MCLK

t (40 40) ns

MCLK

40 ns

1514131211109876543210

31302928272625242322212019181716

bit number

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

OH

V

OL

MGB383

Fig.7 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 0.

SBMCLK
This is the sub-band master clock input for the sub-band

serial PASC interface. The frequency of this signal is
nominally 6.144 MHz. When the SAA3323 is used with
SAA2003 this pin is tied to ground, and the TFE settings
bit ‘DRPMAS’ set to logic 1.

SBDIR
This output pin is the sub-band serial PASC bus direction

signal, it indicates the direction of transfer on the sub-band
serial PASC bus. This pin connects directly to the SBDIR
pin on the SAA2003. The transfer directions are shown in
Table 13.

Table 13 PASC bus transfer directions.

SBDIR DIRECTION

1 SAA3323 to SAA2003 transfer (audio play)
0 SAA2003 to SAA3323 transfer (audio record)

SBCL
This input/output pin is the bit clock line for the sub-band

serial PASC interface to the SAA2003. When used with
SAA2003 this pin is input only. It has a nominal frequency
of 768 kHz.

SBWS
This input/output pin is the word select line for the

sub-band serial PASC interface to the SAA2003. When
used with SAA2003 this pin is input only. It has a nominal
frequency of 12 kHz.

SBDA
This input/output pin is the serial data line for the sub-band

serial PASC interface to the SAA2003.

SBEF
This active HIGH output pin is the error-per-byte line for

the sub-band serial PASC interface to the SAA2003.

May 1994 15

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

URDA
This active HIGH output pin indicates that the main data

(audio), the SYSINFO and the AUXILIARY data are NOT
usable, regardless of the state of the corresponding
reliability flags. The state of this pin is reflected in the
URDA bit of STATUS byte 0, which can be read by the
microcontroller. This pin should be connected directly to

handbook, full pagewidth

SNUM

SBWS

L3REF

'FIRST BYTE"

SBDA

0

the URDA pin of the SAA2003. URDA goes active as a
result of a reset, a mode change from mode DRAR to
DPAP, or if the SAA3323 has had to re-synchronize with
the incoming data from tape.

The position of the first sub-band serial PASC bytes in a
tape frame is shown in Figs 8 and 9.

1

MGB384

byte 0

byte 1 byte 2

Fig.8 Position of first sub-band serial PASC bytes in a tape frame in DPAP/DPAR mode.

handbook, full pagewidth

SNUM

SBWS

L3REF

'FIRST BYTE'

SBDA

30

byte 0 byte 1 byte 2

Fig.9 Position of first sub-band serial PASC bytes in a tape frame in DRAR mode.

MGB385

May 1994 16

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

RAM connections

The SAA3323 has been designed to operate with DRAMs
and SRAMs. Suitable DRAMs are 64K × 4-bit or
256K × 4-bit configurations operating in page mode, with
an access time of 80 to 100 ns. The timing for read, write
and refresh cycles for DRAMs is shown in Figs 10 to 12.
The timing for SRAMs is shown in Figs 13 to 19.

For fast SRAMs: (these values are subject to verification
during characterization in). The conditions (most critical at
the required VDD) are shown in Table 14.

Table 14 Fast SRAM conditions.

CONDITION

Write pulse duration t
Data set-up to rising
Write cycle time T
Read access time t

(1)

≤ 140 ns

W

WEN tsu≤ 72 ns

≤ 200 ns

cy

≤ 240 ns

ACC

TIME

Note

1. The SAA3323 should work in: RType = ‘01’;
RTim = ‘00’ mode.

A9/

CAS

When SAA3323 is used with SRAM this output pin is
Address line 9, and should be connected directly to the
corresponding address pin on the SRAM. When SAA3323
is used with DRAM this output pin is the column address
strobe (active LOW), it connects directly to the column
address strobe pin of the DRAM.

A10/

RAS

When SAA3323 is used with SRAM this output pin is
Address line 10, and should be connected to the
corresponding address pin of the SRAM. When SAA3323
is used with DRAM this output pin is the row address
strobe (active LOW), it connects directly to the row
address strobe pin of the DRAM.

OEN
This output pin is the output enable (active LOW) for the

RAM, it connects directly to the output enable pin of the
RAM.

WEN
This output pin is the write enable (active LOW) for the

RAM, it connects directly to the write enable pin of the
RAM.

TO A8

A0
When SAA3323 is used with DRAM these output pins are

the multiplexed column and row address lines. When the
64K × 4-bit DRAM is used, pins A0 to A7 should be
connected to the DRAM address input pins, and pin A8
should be left unconnected. When using the 256K × 4-bit
DRAM the address pins A0 to A8 should be connected to
the address input pins of the DRAM.

When SAA3323 is used with SRAM these are the lower
address pins and should be connected directly to the
SRAM address pins.

A11
This output pin is the an address pin for the SRAM and

when SRAM is used they should be connected directly to
the address pins of the SRAM. When DRAM is used this
pin should not be connected.

A10 AND A12 TO A16
These output pins are the upper address pins for the

SRAM and when SRAM is used they should be connected
directly to the address pins of the SRAM. When DRAM is
used or when the small SRAM is used all or some of these
pins become available as Port expander outputs.

May 1994 17

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 15 Port expander outputs.

PIN NAME

PIN

QFP80 TQFP80

PORT EXPANDER

OUTPUT

CONDITIONS

A14/PINO1 46 44 PINO1 RType = 00
A13/PINO2 50 48 PINO2 RType = 00
A16/PINO3 47 45 PINO3 RType = 00 or RType = 01
A15/PINO4 48 46 PINO4 RType = 00 or RType = 01
A12/PINO5 45 43 PINO5 RType = 00

TO D3

D0
When SAA3323 is used with SRAM these I/O pins form the lower nibble of the data bus connection to the RAM, and

should be connected to the corresponding data I/O pins of the SRAM. When SAA3323 is used with DRAM these
input/output pins are the data lines for the RAM, they should be connected directly to the DRAM data I/O pins.

D4

TO D7

These input/output pins are the upper nibble of the data bus for use with SRAM, and when SRAM is being used they
should be connected directly to the corresponding SRAM I/O pins.

handbook, full pagewidth

WEN

OEN

A10/RAS

A9/CAS

A0 to A8

D0 to D3

t

RAS

t

RP

t

ASR

ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS

t

RAH

t

RCD

t

RAC

t

ASC

t

CAS

t

t

CP

OFF

t

CAH

t

CAC

NIBBLE 0 DATA NIBBLE 1 DATA NIBBLE 2 DATA

Fig.10 DRAM read cycle timing.

t

OEZ

MGB386

May 1994 18

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

WEN

OEN

A10/RAS

A9/CAS

A0 to A8

D0 to D3

t

RP

t

ASR

ROW ADDRESS

t

WCS

t

RAH

t

RCD

t

ASC

t

DS

t

CAS

t

CAH

NIBBLE 0 DATA NIBBLE 2 DATA

t

DH

t

Fig.11 DRAM write cycle timing.

t

RAS

CP

COLUMN ADDRESSCOLUMN ADDRESS

NIBBLE 1 DATA

t

WCH

COLUMN ADDRESS

MGB387

handbook, full pagewidth

WEN

OEN

A10/RAS

A9/CAS

A0 to A8

D0 to D3

t

RP

t

ASR

ROW ADDRESS

t

RAH

Fig.12 DRAM refresh cycle timing.

May 1994 19

t

RAS

MGB388

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

ADDRESS ADDRESS
t

AA

t

OLZ

READ

t

OH

DATADATA

READ

Fig.13 Fast SRAM read cycle timing.

t

OHZ

MGB389

t

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

WP

t

AW

t

WC

ADDRESS ADDRESS

t

DW1

t

WRITE

DH1

t

OLZ

t

AA

READ MODIFY WRITE

Fig.14 Fast SRAM write cycle timing; RTim = “00”.

May 1994 20

t

WP

t

DHO1

DATADATA DATA

t

OHZ

t

DH2

t

DW2

MGB390

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

t

WP

t

AW

t

WC

ADDRESS ADDRESS

t

DAH

t

DW1

WRITE

t

DDH

t

OLZ

t

AA

READ MODIFY WRITE

t

t

OHZ

DHO1

t

WP

t

DW2
DATADATADATA

t

DDH

t

DAH

Fig.15 Fast SRAM write cycle timing; RTim = “01”.

MGB391

t

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

WP

t

AW

t

WC

ADDRESS ADDRESS

t

t

DW1

WRITE

t

DH1

OLZ

t

OHZ

t

AA

READ MODIFY WRITE

Fig.16 Fast SRAM write cycle timing; RTim = “10”.

May 1994 21

t

WOA

t

WP

t

DHO1

t

DW2
DATADATADATA

t

DH2

MGB392

Philips Semiconductors Preliminary specification

,,

Drive processor for DCC systems SAA3323

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

MGB393

WRITE READ MODIFY WRITE

Fig.17 Fast SRAM write cycle timing; RTim = “11”.

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

ADDRESS ADDRESS

t

OLZ

t

AA

READ READ

t

OH

Fig.18 Slow SRAM read cycle timing.

May 1994 22

t

OHZ

DATADATA

MGB394

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

WEN

OEN

A0 to A16

D0 to D7

Table 16 Timing values for Figs 10 to 12.

SYMBOL VALUE (ns)

t

RP

t

RAS

t

RCD

t

CP

t

CAS

t

ASR

t

RAH

t

ASC

t

CAM

t

DS

t

DH

t

WCS

t

WCH

t

RAC

t

CAC

≥110
≥510
≥70
≥30
≥100
≥100
≥25
≥30
≥100
≥25
≥100
≥30
≥100
≤160
≤80

ADDRESSADDRESS

t
DATADATA

WRITE

t

AW
t

DW2

t

WP

WC

t

DH

t

t

AW
t

WC

WP

t

DW1

WRITE

t

DH

Fig.19 Slow SRAM write cycle timing.

Table 17 Timing values for Figs 13 to 17.

SYMBOL VALUE (ns)

t

WP

t

AW

t

WC

t

DW

t

DM

t

AA

t

HC

Table 18 Timing values for Figs 18 and 19.

SYMBOL VALUE (ns)

t

WP

t

AW

t

WC

t

DW

t

DM

t

AA

MGB395

≥140
≥180
≥200
≥72
≥25
≤240
≥250

≥225
≥260
≥300
≥140
≥25
≤280

May 1994 23

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Read/write connections

TCLOCK
This output pin is the 3.072 MHz clock output for the read

and write amplifiers, it should be connected directly to the
WCLOCK pin of the write amplifier and to the RDCLK pin
of the read amplifier.

RDMUX
This input pin carries the time multiplexed analog tape

channel signals from the read amplifier.

V

AND V

ref(n)

ref(p)

These are the lower and upper voltage reference inputs for
the ADC in the digital equalizer part of SAA3323.

BIAS
This pin defines a bias current for the ADC. It should be

connected to the analog supply voltage V

via a 47 kΩ

DDA

resistor.

RDSYNC
This output line provides synchronization information for

the read Amplifier data transfers. The relationship between
TCLOCK, RDSYNC and the channel information carried
by the RDMUX line is given in Fig.20. This pin should be
connected directly to the RDSYNC pin of the read
amplifier. When the digital equalizer in SAA3323 is in
search mode this pin will be HIGH ensuring that only the
AUX channel is processed by the SAA3323.

WDATA
This output pin is the multiplexed data and control line for

the write amplifier. Figure 21 shows the manner in which
this information is multiplexed onto WDATA. The WDATA
pin should be connected directly to the WDATA pin of the
write amplifier.

handbook, full pagewidth

handbook, full pagewidth

TCLOCK
WDATA

TCLOCK
RDMUX

RDSYNC

SYNC

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AUX

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AUX

Fig.20 RDMUX, RDSYNC and TCLOCK timing.

TCH0

TCH1

TCH2

TCH3

TCH4

TDAPLB

TAUPLB

TERAUX

TCH5

Fig.21 WDATA and TCLOCK timing.

TCH6

CH0

CH1

TCHAUX

CH2

CH3

TCH7

CH4

CH5

CH6

MGB397

AUX

CH7

MGB396

May 1994 24

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Tape deck capstan control connections

S

PEED

This pin outputs a pulse width modulated signal that may
be used for controlling the tape capstan of the deck.

Operation of the SPEED control signal

Table 19 gives the sources that determine the duty factor
of the SPEED signal. Note that the 3-state SPEED output
may be put into high-impedance state by programming the
TFE setting by bit HiZSpd.

Table 19 SPEED signal duty factor.

SOURCE FOR

MODE µCSPD

DPAP 0 tape
DPAP 1 µC
DPAR 0 tape
DPAR 1 µC
DRAR 0 50%
DRAR 1 µC

SPEED DUTY

FACTOR

(1)

(2)

(1)

(2)

(3)

(2)

Notes

1. “Tape” means that the duty factor has been calculated
from the played back main data tape signal. When
tape is the source for the duty factor of the SPEED
signal, the type of regulation can be chosen with the
TFE settings bits EnFReg and SeINBand.

2. “µC” means that the microcontroller programs the duty
factor via the SPDDTY register.

3. “50%” means that the duty factor is fixed at 50%.

May 1994 25

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

MEA717

100 %

91 %

duty
factor
speed

50 %

9 %

0

+ 2 blocks

+ 10.6 ms

+ 1.65 blocks
+ 8.8 ms

0

– 1.65 blocks
– 8.8 ms

– 2 blocks
– 10.6 ms

Fig.22 SPEED regulation duty factor as a function of phase characteristic.

If EnFReg is programmed ‘LOW’ then there is phase
regulation of the capstan speed. The period of the pulse
width modulated SPEED signal is 41.66 µs. The SAA3323
performs a new calculation to determine the duty factor of
SPEED once every 21.33 ms, giving a sampling rate of
approximately 46.9 Hz. This calculation is basically a
phase comparison between the incoming Main Data tape
frame and an internally generated reference. The SPEED
duty factor as a function of phase characteristic is shown
in Fig.22. As shown the duty factor increases
monotonously from approximately 9% when the incoming
Main Data tape frame is 1.65 tape blocks (8.8 ms) too
early up to 91% when it is 1.65 tape blocks (8.8 ms) too
late. Outside of a ±2 tape blocks range the pulse width
characteristic overflows and repeats itself forming a
sawtooth pattern. The SAA3323 has an internal buffer of
±8.8 ms outside of which the phase information is invalid.

Table 20 POT and FOT deviation thresholds.

SeINBand

(DEVIATION FROM NOMINAL)

POT

0 ±6% ±9%
1 ±3% ±4.5%

If EnFReg is programmed ‘HIGH’ then the above
description is over-ridden with frequency information. If the
incoming main data bit rate deviation from the nominal
96000 bits/s rate is less than the Phase Only Threshold
(POT) then the control is as described above in the phase
control description. If the deviation is more than the
Frequency Only Threshold (FOT) then the SPEED
information is gated with the phase information resulting in
the SPEED signal being continuously HIGH or LOW while
the condition continues. If the deviation is between the
POT and the FOT then the frequency information is gated
with the Phase information for 50% of the time.

The deviation thresholds POT and FOT are programmable
via the TFE settings bit SeINBand.

FOT

(DEVIATION FROM NOMINAL)

May 1994 26

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

If SLEEP is ‘HIGH’ then the state of the SPEED signal will
be the state that it was in just before the SAA3323 went
into sleep. Thus if SPEED was HIGH just before sleep it
will stay HIGH during sleep. The same applies if it was
LOW or if it was in ‘high-Z’ state. Note that a reset of the
SAA3323 will take the SPEED signals out of ‘high-Z’ state.

Microcontroller connections

L3REF
This active LOW output pin indicates the start of a time

segment, it goes LOW for 5.2 µs once every 42.66 ms
approximately and can be used for generating interrups for
the microcontroller. If a re-synchronization occurs then the
time between the occurrences van vary. This pin can be
connected directly to the interrupt input of the
microcontroller.

L3CLK
This input pin is the clock line for the microcontroller

interface.

L3DATA
This input/output pin is the serial data line for the

microcontroller interface.

Table 21 Timing values for Fig.23.

SYMBOL TIME

t
t
t
t
t
t
t
t
t
t
t
t
t

W1
d1
h2
d2
d5
cL
cH
su1
h1
d3
h3
d4
d4

(2)

T+t

su (L3MODE)+th (L3MODE)

T+t

su (L3MODE)+th (L3CLK)

T+t

su (L3CLK)+th (L3MODE)

T+t

su (L3CLK)+td (L3DATA)

0 ≤ td5≤ 50 ns
T+t

su (L3CLK)+th (L3CLK)

T+t

su (L3CLK)+th (L3CLK)

T+t

su (L3DATA)+th (L3CLK)

T+t

su (L3CLK)+th (L3DATA)

2 × T+t
T+t
2 × T+t
3 × T+t

su (L3MODE)+td (L3DATA)

h (L3CLK)+td (L3DATA)

su (L3CLK)+td (L3DATA)
su (L3CLK)+td (L3DATA)

(1)

; tw1≥ 200 ns
; td1≥ 200 ns
; th2≥ 200 ns

; td2≤ 250 ns

; tcL≥ 200 ns
; tcH≥ 200 ns

; t

≤ 200 ns

su1

; th1≤ 35 ns

; td3≤ 250 ns

; th3≥ 50 ns

; td4≤ 410 ns
; td4≤ 575 ns

Notes

1. T is the period of the master clock on the chip.

2. t

is the delay time between the last bit of a byte and

d4

first bit of the next byte, if no ‘halt’ is used.

L3MODE
This input determines the type of transfer that is occurring

between the microcontroller and the SAA3323. If L3MODE
is LOW then a device address can be sent by the
microcontroller. If L3MODE is HIGH then a data transfer
may be occurring.

L3INT
This pin carries interrupts from the digital equalizer

module. It can also be programmed to reflect the state of
the AENV, LABEL and VIRGIN signals.

May 1994 27

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

t

handbook, full pagewidth

L3MODE

L3CLK

L3DATA
DRP to
microcontroller

L3MODE

L3CLK

L3DATA
microcontroller
to DRP

t

h2

t

d5

t

t

cL

cH

t

d1

t

h1

0 1234 567

t

su1

W1

t

d1

t

d5

a.

t

h2

b.

L3MODE

t

t

cL

cH

L3CLK

L3DATA
microcontroller
to DRP

L3MODE

L3CLK

L3DATA
DRP to
microcontroller

a. Halt mode.
b. Addressing mode.
c. Data mode (transfer from microcontroller to SAA3323).
d. Data mode (transfer from SAA3323 to microcontroller).

t

d1

t

d1

t

d3

t

h1

0 1234 567

t

su1

t

t

cL

cH

t

h3

0 1234 567

t

d2

t

d4

t

h2

c.

t

h2

t

d5

MGB398

d.

Fig.23 L3 interface timing and typical transfers (1).

May 1994 28

May 1994 29

L3MODE
L3CLK
L3DATA

L3MODE
L3CLK
L3DATA

L3MODE
L3CLK
L3DATA

L3MODE
L3CLK
L3DATA

L3MODE
L3CLK
L3DATA

TFE3 WCMD

LDSET0 TFE3 WDAT SET0 DATA TFE3 WCMD LDSET1 TFE3 WDAT SET1 DATA

a.

TFE3 RSTAT

STATUS0

DATA

STATUS1

DATA

STATUS2

DATA

STATUS3

DATA

b.

TFE3 WCMD LDBYCYNT TFE3 WDAT D8HEX TFE3 WCMD RDSYS TFE3 RDAT SYSINFO(8)

c.

TFE3 WCMD STATUS0

TFE3 RSTAT

LDBYCYNT TFE3 WDAT D8HEX TFE3 WCMD RDSYS TFE3 RSTAT SYSINFO(8) TFE3 RDAT

STATUS0

DATA

TFE3 RDAT SYSINFO(9)

d.

DATA

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYSINFO(9)

MGB399

a. Write settings bytes 0 and 1 to TFE3 part of SAA3323.
b. Read all 4 status bytes from TFE part of SAA3323.
c. Read 2 SYSINFO bytes starting at byte 8 (in high-speed transfer part of program).
d. Read 2 SYSINFO bytes starting at byte 8 (in low-speed transfer part of program).

Fig.24 L3 interface timing and typical transfers (2).

handbook, full pagewidth

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SAA3323 test pins

TEST0

TO TEST3

These input pins are for test only, do not connect.

AZCHK
This output pin indicates the occurrence of a tape channel

sync symbol on tape channels TCH0 and TCH7, the
distance between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment. Figure 25 shows the typical
timing for this signal.

ERCOSTAT
This output pin can be connected to a symbol error rate

measurement system.

Port expansion pins

PINI
This input pin is connected directly to the PINI bit in the

status byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.

PINO1
This output pin is connected directly to the PINO1 bit of the

TFE settings 0 register. The microcontroller can set or
reset this pin.

PINO2

TO PINO5

Depending upon the type and the size of system RAM
used, some or all of these Port expander output pins may
be available, (please see Section “RAM connections”
“A10 and A12 to A16” on interfacing to the RAM pins).

Supply pins

V

TO V

DD1

DD6

These are the supply pins, all of these pins must be
connected. We recommend that each power supply pin
pair (i.e. V

DD1

to V

SS1

, V

DD2

to V

, etc.) be decoupled

SS2

using a 22 nF capacitor as close as is physically possible
to the pins of the SAA3323.

TO V

V

SS1

SS6

These are the supply ground pins, all of which must be
connected.

Duration of the one tape block

handbook, full pagewidth

AZCHK

(8 periods MCLK)

1.3 µs

This is a measure of the azimuth error.

Nominal Inter Frame Gap (IFG) lasts 660 µs.

5.3 ms

MEA705

Fig.25 AZCHK timing.

May 1994 30

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

V

DD7

This is the supply pin for the output buffers to the data lines
of the system RAM. It should always be connected
externally. Decouple this pin with a 22 nF capacitor to the
V

pin.

SS7

V

SS7

This is the ground supply pin for the output buffers of the

internally to all the supply ground pins (V
however it should always be connected externally.

Auxiliary envelope detection

INTMASK
INTMASK is a interrupt mask register. This register sets

the mode of operation for the interrupt interface, and is
writable only.

SS1

to V

SS6

data lines of the system RAM. This pin is connected

Table 22 Interrupt mask register.

BIT 7 6 5 4 3 2 1 0

Meaning BP1 BP0 Vup

(1)

AEup

(2)

AEdn

(3)

Lup

(4)

Ldn

(5)

ECZ

Default 0 0 0 0 0 0 0 0

Notes

1. Vup ≡ rising edge of VIRGIN interrupt.

2. AEup ≡ rising edge of AUX envelope interrupt.

3. AEdn ≡ falling edge of AUX envelope interrupt.

4. Lup ≡ rising edge of LABEL interrupt.

5. Ldn ≡ falling edge of LABEL interrupt.

6. ECZ ≡ AUX envelope counter has just reached zero interrupt.

),

(6)

BP1 AND BP0 (BYPASS)
If any of the bypass bits are HIGH then the interrupts are

not passed on to the microcontroller, instead the level of
the corresponding signal is available an the interrupt pin.

Table 23 BP1 and BP0.

BP

EFFECT OF BYPASS

10

0 0 no bypass
0 1 LAB on L3INT pin; note 1
1 0 AENV on L3INT pin; note 2
1 1 VIR on L3INT pin; note 3

Notes

1. LAB = LABEL (HIGH if a LABEL condition is detected
in the envelope of the AUX channel).

2. AENV = envelope of the AUX channel (1 bit binary).

3. VIR = VIRGIN (indicated by the total [continuous]
absence of signal on the AUX channel).

The AUX envelope information is only valid when the
digital equalizer is in search mode and when the tape
speed is between the values of
3to48×nominal tape speed. The timing relationships
between the AUX channel input signal, AENV, LAB and
VIR are shown in Figs 26 to 28. The delays td1 and td2 are
between 0.25 and 0.5t
delays td3, td4, td5 and td6 are between 2 and 6t

(AUX envelope periods). The

AUX

AUX

(AUX envelope periods).
When using the digital equalizer in search mode first

program the digital equalizer to search mode, then
program the INTMASK register.

MASK
If the BP1 and BP0 bits are LOW then the mask bits take

effect. Any combination of the mask bits may be HIGH,
enabling the corresponding interrupts. The interrupt pin
L3INT is active LOW when used for interrupts and active
HIGH when used for bypassing. So if it is not in bypass
mode and at least one of the interrupts has occurred it will
go LOW and stays LOW until DEQ status byte 0 has been
read. Extra interrupts that occur after the first interrupt and
before the DEQ status byte 0 is read are seen in the status
register. Extra interrupts that occur after the status byte

May 1994 31

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

has been read will generate a new interrupt. Interrupts that are already noted in the digital equalizer Status 0 are cleared
by reading it.

Table 24 Digital equalizer STATUS0.

BIT 7654321 0

(1)

Meaning BKSW

TEST Vup

Notes

1. BKSW (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been
activated.

2. Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred.

3. AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred.

4. AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred

5. Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred.

6. Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred.

7. ECZ indicates that the AUX envelope counter has reached zero.

(2)

AEup

(3)

AEdn

(4)

Lup

(5)

Ldn

(6)

ECZ

(7)

handbook, full pagewidth

handbook, full pagewidth

RDMUX

AENV

AENV
(internal)

LAB

t

AUX

t

d1

t

d2

Fig.26 AUX channel envelope to AENV delays.

t

AUX

t

d3

MGB400

t

d4

MGB401

Fig.27 AENV to LAB delays.

May 1994 32

Philips Semiconductors Preliminary specification



Drive processor for DCC systems SAA3323

t

handbook, full pagewidth

AENV
(internal)

Vir

AUX

t

d5

t

d6

Fig.28 AENV to VIR delays.

Table 25 Digital equalizer STATUS1.

BIT 76543210

Meaning −−−−−VIR

Notes

1. VIR gives the state of the VIRGIN signal.

2. AENV represents the state of the AENV signal.

3. LAB gives the state of the LAB signal.

AUX envelope count (AECNT) register

This 16 bit register is used for loading the AUX envelope
counter and for reading the state of that counter, it is
therefore readable and writable as 2 bytes. Least
Significant Byte first.

Table 26 AECNT register.

(1)

MGB402

AENV

(2)

LAB

(3)

AECNT LEAST SIGNIFICANT BYTE MOST SIGNIFICANT BYTE

BIT 7654321076543210

7

Meaning 2

262524232221202152142132122112

Search speed (SSPD) register

Search speed 2



SR

51.2



× normal speed×=

-----------



SV

Table 27 Search speed register.

BIT 76543210

Meaning SVF

(1)

SV4

(2)

SV3

(2)

SV2

(2)

SV1

(2)

Notes

1. SVF speed validation flag, if HIGH then the search speed measurement is invalid.

2. SV4 to SV0 search speed value.

3. SR1 and SR0 search speed range.

May 1994 33

SV0

(2)

SR1

1029

(3)

SR0

(3)

8

2

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

ANAEYE register

Table 28 ANAEYE register analog eye pattern selection register.

BIT 76543210

Meaning −−−AEN

(1)

ACHN3

Default 00000000

Notes

1. AEN analog eye pattern output enable. If this bit is LOW the Digital-to-Analog Converter (DAC) is switched off and
the output is HIGH.

2. ACHN3 to ACHN0 select channel for analog eye output.

Table 29 ACHN3 to ACHN0 channel selections for analog eye output.

(2)

ACHN2

(2)

ACHN1

(2)

ACHN0

(2)

ACHN

CHANNEL ON ANAEYE

32 1 0

00 0 0 0
00 0 1 1
00 1 0 2
00 1 1 3
01 0 0 4
01 0 1 5
01 1 0 6
01 1 1 7
1 0 0 0 AUX

T1sel register

Table 30 T1SEL register CHTST1 pin selection register.

BIT 7654321 0

Meaning − T1F2 T1F1 T1F0 T1C3 T1C2 T1C1 T1C0
Default 0 0 0 0 0 0 0 0

Table 31 T1C3 to T1C0 CHTST1 pin channel selections.

T1C

CHANNEL ON CHTST1

32 1 0

00 0 0 0
00 0 1 1
00 1 0 2
00 1 1 3
01 0 0 4
01 0 1 5
01 1 0 6
01 1 1 7
1 0 0 0 AUX

May 1994 34

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 32 T1F2 to T1F0 CHTST1 pin function selections.

T1F

21 0

0 0 0 off; logic 0
0 0 1 digital eye pattern
0 1 0 sliced data
0 1 1 bit clock
1 0 0 clock extraction frequency

The digital eye pattern is in 8 bits two’s complement notation, the sliced data and the bit clock give the current binary
state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. The timing
diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig.29.

FUNCTION OF CHTST1 PIN

T2sel register

Table 33 T2SEL register CHTST2 pin selection register.

BIT 7 6 5 4 3 2 1 0

Meaning − T2F2 T2F1 T2F0 T2C3 T2C2 T2C1 T2C0
Default 0 0 0 0 0 0 0 0

Table 34 T2C3 to T2C0 CHTST2 pin channel selections.

T2C

321 0

000 0 0
000 1 1
001 0 2
001 1 3
010 0 4
010 1 5
011 0 6
011 1 7
1 0 0 0 AUX

CHANNEL ON

CHTST2

Table 35 T2F2 to T2F0 CHTST2 pin function selections.

T2F

FUNCTION OF CHTST2 PIN

210

0 0 0 off; logic 0
0 0 1 digital eye pattern
0 1 0 sliced data
0 1 1 bit clock
1 0 0 clock extraction frequency

May 1994 35

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

RDSYNC

TCLOCK

MCLK

CHTST

LSB MSB

01234567 0123

MGB403

Fig.29 CHTST1 and CHTST2 output timing.

Table 36 DEQSET digital equalizer settings.

BIT 76543210

Meaning −−−−−ACup

(1)

DM1 DM0

Default 00000000

Note

1. ACup is the AUX envelope counter direction is up. This setting caused the AUX envelope counter increment or to
decrement by 1 every rising edge of the AUX envelope signal AENV.

DM1 and DM0

Table 37 DM1 and DM0 digital equalizer mode of

operation.

DM

10

0 0 normal
0 1 search
1 0 off
1 1 off

MODE OF OPERATION OF

DIGITAL EQUALIZER

(1)

(2)
(3)
(3)

Notes

1. In normal mode the main data channels and the AUX
channel are processed (equalized), the AUX channel
envelope information is not processed.

2. In search mode only the AUX channel is processed by
the digital equalizer.

3. Off means that the digital equalizer is put to sleep (low
power), this can be used for example in portable
recording equipment. RDSYNC is HIGH if off mode.
Also note that the other digital equalizer registers are
not addressable while the digital equalizer is in off
mode.

May 1994 36

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

CLKSET

Table 38 CLKSET clock extraction settings.

BIT 7654321 0

Meaning LEAE
Default 1 0 0 1 1 0 1 0

Note

1. LEAE (leakage enable): this setting enables a leakage function in the PLL clock extraction loop filter. This gives a
slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance. For
home (static) applications program this bit to logic 1 and for portable applications to logic 0.

(1)

FR1 FR0 GNOR GE1 GE0 RD1 RD0

Table 39 FR1 and FR0 clock extraction frequency range

control.

FR

10

EFFECT ON PLL FREQUENCY

LOOP

0 0 range ±8%
0 1 range ±16%
1 0 range ±22%
1 1 range ±28%

Note that in the (FR = 0) range the clock extraction stays
in its normal range only, hence it does not enter the
extended range.

Figure 30 shows the lock characteristic of the clock
extraction PLL.

bit rate

deviation

(%)

30

(3)

20

(2)

handbook, full pagewidth

Table 40 GNOR gain in normal frequency range mode of

clock extraction.

GNOR EFFECT ON GAIN IN NORMAL RANGE

0 gain 2; for portable (mobile) applications
1 gain 1; for home (static) applications

Table 41 GE1 and GE0 gain in extended frequency

range mode of clock extraction.

GE

10

EFFECT ON PLL GAIN IN EXTENDED

RANGE

0 0 gain 2
0 1 gain 3
1 0 gain 4
1 1 gain 5; do not use

MGB404

28% frequency loop range limitation

22% frequency loop range limitation

16% frequency loop range limitation

10

(1) Gain 4.
(2) Gain 3.
(3) Gain 2.

0

2

10

3

10

Fig.30 Clock extraction PLL lock characteristic.

May 1994 37

(1)

8% frequency loop range limitation

4

f (Hz)

10

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

RD1 and RD0 return delay

This is the delay before returning to normal mode after
being in ‘extended range mode’ (i.e. the number of
consecutive channel clock bit periods where the bit clock
frequency falls within the normal range before the clock
extraction returns to normal frequency mode).

Table 42 RD1 and RD0 return delay.

RD

10

0064
0 1 128
1 0 256
1 1 512

SYSINFO and AUX data offsets in the SAA3323

AUX data consists of 4 blocks of 36 bytes, one block being
transferred in each (n) time segment.

Table 43 Block offsets with respect to time segment.

MODE DESCRIPTION

DPAP SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0; if AUX and

DRAR SYSBLK = SNUM; AUXBLK = (SNUM + 1) MOD4
DPAR SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0

DELAY IN BITS TO RETURN TO

NORMAL MODE

main were recorded simultaneously then AUXBLK = (SNUM + 1) MOD4; else read and interpret
1 AUX block in each time segment.

The 128 bytes in each tape frame contain SYSINFO. The
SYSINFO bytes can for convenience, be considered as
being grouped into 4 SYSINFO blocks with:
SYSBLK0 → SI0 to SI31, SYSBLK1 → SI31 to SI63, etc.

In modes DPAP and DRAR SYSINFO transfers may occur
in two ways:

1. 4 blocks of 36 bytes, one block being transferred to the
SAA3323 in each time segment.

2. 1 block of 128 bytes being transferred in time
segment 1.

In mode DRAR SYSINFO must be transferred as 4 blocks
of 32 bytes, one block in each segment.

Figures 31 to 34 show the offsets between the SYSINFO
and AUX and the time segment counter, for the various
modes of operation of the SAA3323.

May 1994 38

Philips Semiconductors Preliminary specification

,

,

Drive processor for DCC systems SAA3323

SNUM

AUX BLK

SYS BLK

SYS BLK

AUX, MAIN
DATA INPUT
FROM TAPE

01 23 0123012

3012

123012301230123

3012301230122301

*

0
1
2
3

0
1
2
3

0
1
2
3

01 23 01230123012

0
1
2
3

MLB413

Fig.31 SYSINFO and AUX block delays in DPAP mode; audio and AUX simultaneously recorded.

SNUM

AUX BLK

SYS BLK

SYS BLK

AUX, MAIN
DATA INPUT
FROM TAPE

01 23 0123012

DEPENDS ON PHASE OF AUX WRT MAIN DATA CHANNELS

3012301230122301

*

0
1
2
3

0
1
2
3

01 23 01230123012

Fig.32 SYSINFO and AUX block delays in DPAP mode; audio and AUX separately recorded.

May 1994 39

0
1
2
3

3012

0
1
2
3

MLB414

Philips Semiconductors Preliminary specification

,

,

,

,

,,,

,

Drive processor for DCC systems SAA3323

handbook, full pagewidth

SNUM

AUX BLK

SYS BLK

AUX, MAIN
DATA OUTPUT
TO TAPE

01230123012

3012

123012301230123

012301230123012

3012301230122301

Fig.33 SYSINFO and AUX block delays in DRAR mode.

MBG405

SNUM

AUX BLK

SYS BLK

SYS BLK

01 23 0123012

123012301230123

,,,

3012301230122301

*

0
1
2

,

3

MAIN DATA
INPUT
FROM TAPE

AUX OUTPUT
TO TAPE

01 23 01230123012

012301230122301

1

,,,,

Fig.34 SYSINFO and AUX block delays in DPAR mode.

May 1994 40

0
1
2
3

,

0
1
2
3

3012

0
1

,

2
3

MLB416

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Scratch pad RAM

The SAA3323 provides the microcontroller with a scratch
pad RAM that the microcontroller can use for whatever it
likes. The size of the scratch pad depends upon the size
and type of RAM used with the SAA3323. The locations in

Table 44 Availability of RAM quarters for the scratch pad RAM.

RTYPE

TYPE OF RAM USED AVAILABLE RAM QUARTERS YZ

10

0 0 DRAM 64K × 400
0 0 DRAM 256K × 4 00, 01, 10 and 11
0 1 SRAM 32K × 8 fast 00
1 0 SRAM 128K × 8 fast 00, 01, 10 and 11
1 1 SRAM (2×) 32K × 8 slow 00
1 1 SRAM 128K × 8 slow 00 and 10

Note

1. In RAM quarter YZ = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns × 64 rows.
The pages are numbered 0to5, the columns 1to7 and the rows 0to63.
This gives a total of (6 × 7 × 64) 2688 locations.

In each of the RAM quarters YZ = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists
of 8 columns× 448 rows. The pages are numbered 0to5, the columns 0to7 and the rows 0 to 447. This gives then
a total of (6 × 8 × 448) 21504 locations per RAM quarter YZ.

the scratch pad RAM may be written and read in 8 bit or
12 bit units.

The RAM may be viewed as having up to 4 quarters, the
availability of these quarters for the scratch pad RAM is
given in Table 44.

(1)

During communication with the scratch pad RAM, the
RAM quarter YZ is chosen when sending the RDDRAC,
RDWDRAC, WRDRAC or WRWDRAC commands to the
TFE module.

Use of the scratch pad RAM outside the specified ranges
is not allowed and it may upset the operation of the
SAA3323.

As with SYSINFO and AUX transfers can occur at high
speed at all times except the second half of time
segment 0, that is when the status bit SLOWTFR is HIGH.
When SLOWTFR is HIGH the microcontroller must poll the
status bit RFBT to investigate when a transfer can occur.

Two addressing modes are available for the scratch pad,
namely random access and auto-increment. For random
access mode the address of each location is sent by the
microcontroller to the SAA3323 before each location
transfer. For auto-increment mode the address of the first
location is sent by the microcontroller before the first
location transfer, auto-incrementing of the row occurs then
for all transfers until the end of the column.

The 8 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 1 byte per
memory location, therefore the byte counter will increment
after each byte transfer.

The 12 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 2 bytes
per memory location. The first byte contains the 4 Most
Significant Bits (MSBs) of the memory location in its
4 Least Significant Bits (LSBs) positions. The other bit
positions being ‘don’t care’. The second byte contains the
8 LSBs of the memory location. The byte counter is
incremented after the transfer of the second byte.

The RACCNT and BYTCNT registers are used for
addressing the scratch pad.

For RAM quarter YZ = 00 the mapping of the scratch pad
RAM address onto the RACCNT and BYTCNT registers is
shown in Table 45.

May 1994 41

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Table 45 Mapping of scratch pad RAM address for RAM quarter YZ = 00.

REGISTER RACCNT BYTCNT

BIT 654321 076543210

Value P2 P1 P0 C2 C1 C0 1 1 R6 R5 R4 R3 R2 R1 R0

For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT
registers is shown in Table 46.

Table 46 Mapping of scratch pad RAM address for RAM quarter YZ = 01, 10 and 11.

REGISTER RACCNT BYTCNT

BIT 654321 076543210

Value P2 P1 P0 C2 C1 C0 R8 R7 R6 R5 R4 R3 R2 R1 R0

Mode changes

The possible mode changes for the TFE are shown in
Table 47.

Table 47 Mode changes.

CURRENT

MODE

DPAP − yes yes
DRAR yes − no
DPAR yes no −

T

IMING FOR SAA3323 MODE CHANGES

DPAP DRAR DPAR

NEW MODE

Mode change DPAP to DRAR

This mode change occurs at the end of the time segment
in which the TFE module receives the new settings.
Writing of the first Main and AUX data to tape starts at the
start of the time segment 1 which occurs 2 ‘end of time
segment 3’ s after the mode change. The delay to writing
to tape is approximately 222 ms, as shown in Fig.35.

If ‘seamless appending’ is required the new settings
should be sent to the TFE module during time segment 2.

Mode change DPAP to DPAR

This mode change occurs at the first end of time
segment 2 after the TFE module receives the new
settings. Output of AUX to tape begins at the start of the
following time segment 1, (i.e. approximately85.3 ms after
the mode change), as shown in Fig.36.

Mode change DRAR to DPAP

This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
Writing of Main and AUX data stops immediately after the
mode change.The time segment jumps back to logic 0,
URDA goes HIGH and stays HIGH for 5 time segments
(i.e. approximately 213.3 ms) after which it goes LOW, as
shown in Fig.37.

Mode change DPAR to DPAP

This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
The writing of AUX data to tape stops immediately after the
mode change. The first AUX read from tape can be
expected during the following time segment 0 or 1 (i.e.
approximately 128 to 170.67 ms after the mode change),
as shown in Fig.38.

Mode change DPAP to search

This mode change occurs almost instantaneously,
program the digital equalizer module in SAA3323 to go to
search mode, then program the interrupt mask register to
select the required type of interrupt.

Mode change search to DPAP

This mode change occurs almost instantaneously,
program the interrupt mask register to disable interrupts
program the digital equalizer module of SAA3323 to go to
normal mode. A re-synchronization will most likely occur
when as result of the data being read from tape, thus
causing URDA to go HIGH.

May 1994 42

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

ndbook, halfpage

NEW MODE

AUXILIARY, MAIN

TAPE OUT

handbook, halfpage

SNUM

MODE

NEW MODE

URDA

SNUM

MODE

01 230123012

DPAP DRAR

DRAR

≈ 222 ms

Fig.35 Mode change to DRAR.

1230 12301

DRAR

DPAP

0

DPAP

≈

213.3 ms

MEA707 - 2

MEA709 - 1

handbook, halfpage

SNUM

MODE

NEW MODE

AUXILIARY

TAPE OUT

Fig.36 Mode change to DPAR.

handbook, halfpage

NEW MODE

AUXILIARY

TAPE OUT

AUXILIARY

MICROCONTROLLER

1230123012

≈

SNUM

MODE

DPAP

DPAR

85.3 ms

DPAR

1230123012

DPAR DPAP

DPAP

≈ 128 ms

TO

≈ 170.66 ms

MEA708 - 2

MEA710 - 2

Fig.37 Mode change from DRAR.

May 1994 43

Fig.38 Mode change from DPAR.

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

V

I

I

I

V

O

I

O

I

DD

I

SS

P

tot

T

stg

T

amb

V

es1

V

es2

supply voltage 2.7 3.6 V
input voltage note 1 −0.5 VDD + 0.5 V
input current −10 +10 mA
output voltage tbf tbf V
output current −20 +20 mA
supply current − 100 mA
supply current −100 − mA
total power dissipation − 500 mW
storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling note 2 −2000 +2000 V
electrostatic handling note 3 −200 +200 V

Notes

1. The input voltage must not exceed maximum supply voltage unless otherwise specified.

2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

DC CHARACTERISTICS

= 2.7 to 3.6 V; T

V

DD

= −40 to +85 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

supply voltage 2.7 tbf 3.6 V
supply current digital plus analog;

− 28.1 − mA

see Fig.39
inputs with internal

pull-down to V

SS

;
all other inputs to V
or V

DD

−−100 µA

SS

Inputs CLK24, L3CLK, L3MODE, PINI, SLEEP and SBMCLK

V

IL

V

IH

I

I

LOW level input voltage −−0.3V
HIGH level input voltage 0.7V
input current VI=0VtoVDD;

T

=25°C

amb

−10 − +10 µA

DD

−−V

DD

V

Inputs TEST0, TEST1 and TEST2

V

IL

V

IH

I

I

LOW level input voltage −−0.3V
HIGH level input voltage 0.7V
input current VI=VDD; T

=25°C25 − 400 µA

amb

DD

−−V

DD

V

May 1994 44

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Input RESET

V

tLH

V

tHL

V

hys

positive-going threshold −−0.8V
negative-going threshold 0.2V
hysteresis (V

tLH

to V

) − 0.3V

tHL

Outputs AZCHK, CHTST1, CHTST2, ERCOST AT, L3INT,
TCLOCK and WDATA

V

OH

V

OL

Outputs A0 to A8, A9/

V

OH

V

OL

HIGH level output voltage IO= 1 mA VDD− 0.5 −−V
LOW level output voltage IO= −1mA −−0.4 V

CAS, A10/RAS, OEN and WEN

HIGH level output voltage IO= 2 mA VDD− 0.5 −−V
LOW level output voltage IO= −2mA −−0.4 V

Outputs SPEED and PINO2

V

OH

V

OL

I

OZ

HIGH level output voltage IO= 1 mA VDD− 0.5 −−V
LOW level output voltage IO= −1mA −−0.4 V
3-state leakage current VI=0VtoVDD;

T

=25°C

amb

Inputs/outputs SBCL, SBDA and SBWS

V

OH

V

OL

V

IL

V

IH

I

OZ

HIGH level output voltage IO= 1 mA VDD− 0.5 −−V
LOW level output voltage IO= −1mA −−0.4 V
LOW level input voltage outputs in 3-state −−0.3V
HIGH level input voltage outputs in 3-state 0.7V
3-state leakage current VI= 0 V to VDD;

T

=25°C

amb

Inputs/outputs A11 to A16 and L3DATA

V

OH

V

OL

V

IL

V

IH

I

OZ

HIGH level output voltage IO= 2 mA VDD− 0.5 −−V
LOW level output voltage IO= −2mA −−0.4 V
LOW level input voltage outputs in 3-state −−0.3V
HIGH level input voltage outputs in 3-state 0.7V
3-state leakage current VI= 0 V to VDD;

T

=25°C

amb

Inputs/outputs D0 to D7

V

OH

V

OL

V

IL

V

IH

I

OZ

HIGH level output voltage IO= 4 mA VDD− 0.5 −−V
LOW level output voltage IO= −4mA −−0.4 V
LOW level input voltage outputs in 3-state −−0.8 V
HIGH level input voltage outputs in 3-state 2 −−V
3-state leakage current VI=0VtoVDD;

T

=25°C

amb

DD

DD

−−V

DD

− V

L3REF, MCLK, PINO3, RDSYNC, SBDIR, SBEF, URDA,

−10 − +10 µA

DD

DD

−−V

−10 − +10 µA

DD

DD

−−V

−10 − +10 µA

−10 − +10 µA

V

V

V

May 1994 45

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

Average current consumption

MLB778

V (V)

DD

I

DD

(mA)

60

max

40

typ

min

20

0

2.0

2.5

3.0 3.5 4.0

Fig.39 Average current consumption.

AC CHARACTERISTICS

= 2.7 to 3.6 V; T

V

DD

= −40 to +85 °C; CL= 10 pF on all outputs; see Fig.40; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock inputs

C

I

CLK24
f

CLK24

t

24L

t

24H

SBMCLK
f

SBMCLK

t

SCL

t

SCH

input capacitance −−10 pF

clock frequency 24 24.576 25 MHz
pulse width LOW 12 −−ns
pulse width HIGH 12 −−ns

clock frequency 6.144 12.5 MHz
pulse width LOW 30 −−ns
pulse width HIGH 30 −−ns

May 1994 46

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock output MCLK

C

L

t

d

f

MCLK

t

MCL

t

MCH

t

pd

Inputs

C

I

L3CLK, L3MODE AND RESET
t

su

t

h

PINI
t

su

t

h

Outputs

C

L

A0 TO A8
t

pd

A9/CAS, A10/RAS AND OEN
t

pd

t

d

WEN
t

pd

t

d

AZCHK, CHTST1, CHTST2, L3INT, PINO3, RDSYNC, SBEF AND WDATA
t

pd

ERCOSTAT, L3REF, SBDIR, SPEED, PINO2, URDA AND TCLOK
t

pd

load capacitance −−20 pF
delay time from SLEEP HIGH to

− 20 − ns

SLEEP active
clock frequency 6.144 6.25 MHz
MCLK pulse width LOW 50 −−ns
MCLK pulse width HIGH 50 −−ns
propagation delay time from rising

−−65 ns

edge of CLK24

input capacitance −−10 pF

set-up time to rising edge of MCLK 35 −−ns
hold time from rising edge of MCLK 0 −−ns

set-up time to rising edge of MCLK 60 −−ns
hold time from rising edge of MCLK 0 −−ns

load capacitance −−20 pF

propagation delay time from falling

−−50 ns

edge of CLK24

propagation delay time from falling

−−50 ns

edge of CLK24
delay time from SLEEP HIGH to

− 20 − ns

SLEEP active

propagation delay time

from falling edge of CLK24 −−50 ns
from falling edge of

edge of CLK24

delay time from SLEEP HIGH to

WEN to rising

long write pulse
mode

−−50 ns

− 20 − ns

SLEEP active

propagation delay time from rising

−−45 ns

edge of MCLK

propagation delay time from rising

−−55 ns

edge of MCLK

May 1994 47

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Inputs/outputs

C

I

C

L

A11 TO A16
t

d

t

pd

TO D3

D0
t

d

t

su

t

h

t

pd

D4

TO D7

t

d

t

su

t

h

t

pd

L3DATA
t

d

t

su

t

h

t

pd

SBCL AND SBWS
t

d

t

su

t

h

t

pd

input capacitance −−10 pF
load capacitance −−20 pF

delay time from SLEEP HIGH to

− 25 − ns

SLEEP active
propagation delay time from falling

−−55 ns

edge of CLK24

delay time from SLEEP HIGH to

− 20 − ns

SLEEP active
set-up time to falling edge of CLK24 5 −−ns
hold time from falling edge of CLK24 15 −−ns
propagation delay time

from falling edge of CLK24 −−50 ns
from rising edge of CLK24 early write mode −−50 ns

delay time from SLEEP HIGH to

− 25 − ns

SLEEP active
set-up time to falling edge of CLK24 5 −−ns
hold time from falling edge of CLK24 15 −−ns
propagation delay time

from falling edge of CLK24 −−50 ns
from rising edge of CLK24 early write mode −−50 ns

delay time from SLEEP HIGH to

− 25 − ns

SLEEP active
set-up time to rising edge of MCLK 35 −−ns
hold time from rising edge of MCLK 0 −−ns
propagation delay time

from rising edge of MCLK −−50 ns
from L3MODE −−45 ns

delay time from SLEEP HIGH to

− 25 − ns

SLEEP active
set-up time to rising edge of MCLK 40 −−ns
hold time from rising edge of MCLK 0 −−ns
propagation delay time

from rising edge of SBMCLK −−60 ns
from rising edge of MCLK

−−55 ns

(3-state control)

May 1994 48

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SBDA
t

d

delay time from SLEEP HIGH to
SLEEP active

t

su

t

h

t

pd

set-up time to rising edge of MCLK 35 −−ns
hold time from rising edge of MCLK 0 −−ns
propagation delay time from rising

edge of MCLK

handbook, full pagewidth

CLK24

IN1

OUT1

MCLK

IN2

OUT2

SBMCLK

OUT3

t

su1

t

h1

t

d1

t

MCL

t

SCL

t

d2

t

pd

t

su2

t

d5

− 25 − ns

−−55 ns

t

24H

t

24L

t

d4

t

t

SCH

MCH

t

d

t

h2

MGB407

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

OH

V

OL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

V

OH

V

OL

Fig.40 Timing for AC characteristics.

May 1994 49

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

ADC CHARACTERISTICS

V

= 2.7 to 3.6 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

AC RDMUX ADC resolution − 8 − bits

V

ref(p)

V

ref(n)

∆V

ref

Z

i

C

I

I

I

positive reference voltage −−V
negative reference voltage 0 −−V
V

ref(p)

input impedance V

input capacitance (RDMUX) −−15 pF

input current −−90 µA
DNL differential non-linearity −−±0.99 LSB
S/(THD+N) signal-to-total harmonic

distortion plus noise ratio

Timing

T

cy

t

d1

cycle time of CLK24 40 −−ns

TCLOCK delay time from

rising edge of CLK24
t

su

RDMUX set-up time to falling

edge of CLK24
t

h

RDMUX hold time from falling

edge of CLK24

= −40 to +85 °C; CL= 10 pF on TCLOCK output; see Fig.41; unless otherwise specified.

amb

− 0.5 V

DD

to V

ref(n)

to V

V

ref(p)
ref(n)

to V

ref(n)
SS

−20 dB (FS);

2.0 −−V
700 1200 1500 Ω

− 650 −Ω

24 −−dB

100 to 500 kHz

CL=10pF −−80 ns

Z

< 150 Ω 60 −−ns

source

40 −−ns

t

handbook, full pagewidth

CLK24

TCLOCK

CLK ADC

RDMUX

TESTBUS

d1

t

d2

t

d3

t

h

t

d4

t

su

SAMPLE(1)

Fig.41 ADC timing.

May 1994 50

V

IH

V

T

cy

DATA SAMPLE(1-2)DATA SAMPLE(1-3)

MGB408

IL

V

OH

V

OL

V

IH

V

IL

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

DAC CHARACTERISTICS

V

= 2.7 to 3.6 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DIGEYE/ANAEYE resolution − 6 − bits

V

o

ANAEYE output voltage ZL>1MΩ−(VDD− 1.1)

= −40 to +85 °C; unless otherwise specified.

amb

to V

− V

DD

May 1994 51

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

PACKAGE OUTLINES

handbook, full pagewidth

seating plane

80 61

1

pin 1 index

20

21

0.1 S

14.3

13.7

S

B

1.45

(4x)

60

1.05

0.5

14.3

12.1

B

13.7

11.9

0.15 M

0.25

0.13

41

40

0.25

0.5 0.15 M A

0.13

12.1

11.9

1.5

1.3

0.16

0.04

MBB947

Dimensions in mm.

Fig.42 Plastic thin quad flatpack; 80 leads; body 12 × 12 × 1.4 mm (SOT315-1; TQFP80).

May 1994 52

detail X

1.45

1.05

A

(4x)

0.7

0.3

0.70

0.58

X

0.18

0.12

0 to 4

1.7

1.5

o

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

handbook, full pagewidth

seating plane

80 65

1

pin 1 index

24

25 40

0.10

S

18.2

17.6

S

B

64

1.0
(4x)

0.6

0.8

20.1

19.9

24.2

23.6

B

0.20 M

0.45

0.30

41

Dimensions in mm.

0.8

0.45

0.30

0.20 M A

14.1

13.9

2.90

2.65

Fig.43 Plastic quad flatpack; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off

height (SOT318-2; QFP80).

May 1994 53

0.25

0.05

1.2

0.8
A

(4x)

detail X

1.0

0.6

X

1.4

1.2

0.25

0.14

0 to 7

MSA394 - 1

3.2

2.7

o

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

SOLDERING
Plastic quad flatpacks

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

B

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

May 1994 54

Philips Semiconductors Preliminary specification

Drive processor for DCC systems SAA3323

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

May 1994 55

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: INTEGRATED CIRCUITS:

Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. [phone] ext. 2336, Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,

P.O. Box 10 63 23, 20043 HAMBURG,
Tel. [phone], Fax. [phone].

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,

6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. [phone], Fax. [phone]

India: Philips INDIA Ltd, Components Dept,

Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS COMPONENTS S.r.l.,

Viale F. Testi, 327, 20162 MILANO,
Tel. [phone], Fax. [phone].

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD31 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp56 Date of release: May 1994
Document order number: 9397 732 30011

Philips Semiconductors