Datasheets rt9199-02 Datasheet

RT9199

Cost-Effective, 2A Peak Sink/Source Bus

Termination Regulator

General Description

The RT9199 is a simple, cost-effective and high-speed

linear regulator designed to generate termination voltage

in double data rate (DDR) memory system to comply with

the devices requirements. The regulator is capable of

actively sinking or sourcing up to 2A peak while regulating

an output voltage to within 20mV. The output termination

voltage can be tightly regulated to track 1/2V

DDQ

by two

external voltage divider resistors or the desired output

voltage can be pro-grammed by externally forcing the

REFEN pin voltage.

The RT9199 also incorporates a high-speed differential

amplifier to provide ultra-fast response in line/load transient.

Other features include extremely low initial offset voltage,

excellent load regulation, current limiting in bi-directions

and on-chip thermal shut-down protection.

The RT9199 are available in both SOP-8 and SOP-8

(Exposed Pad) surface mount packages.

Ordering Information

RT9199

Package Type
S : SOP-8
SP : SOP-8 (Exposed Pad)

Operating Temperature Range
C : Commercial Standard
P : Pb Free with Commercial Standard

Note :

RichTek Pb-free products are :

−RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

−Suitable for use in SnPb or Pb-free soldering processes.

−100%matte tin (Sn) plating.

Features

zz

z Ideal for DDR-II V

zz

zz

z Sink and Source 2A Peak Current

zz

zz

z Integrated Power MOSFETs

zz

zz

z Generate Termination Voltage for DDR Memory

zz

Applications

TT

Interfaces

zz

z High Accuracy Output Voltage at Full-Load

zz

zz

z Output Adjustment by T wo Extern al Resistors

zz

zz

z Low External Component Count

zz

zz

z Shutdown for Suspend to RAM (STR) Functionality

zz

with High-Impedance Output

zz

z Current Limiting Protection

zz

zz

z On-Chip Thermal Protection

zz

zz

z RoHS Compliant and 100% Lead (Pb)-Free

zz

Applications

z Desktop PCs, Notebooks, and Workstations

z Graphics Card Memory Termination

z Set Top Boxes, Digital TVs, Printers

z Embedded Systems

z Active Termination Buses

z DDR/II Memory Systems

Pin Configurations

(TOP VIEW)

8

VIN

GND

REFEN

VOUT

VIN

GND

REFEN

VOUT

2

3

4

SOP-8

2

GND

3

4

VCNTL

7

VCNTL

6

VCNTL

VCNTL

5

8

NC

7

NC

6

VCNTL

5

NC

SOP-8 (Exposed Pad)

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RT9199

Typical Application Circuit

V

= 5V

CNTL

VIN = 1.8V

2N7002

EN

R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω

C

OUT(MIN)

R

DUMMY

CSS = 1μF, CIN = 470μF (Low ESR), C

Test Circuit

= 10μF (Ceramic) + 1000μF under the worst case testing condition

= 1kΩ as for V

OUT

R

1

R

C

2

SS

VIN

REFEN

VCNTL

RT9199

VOUT

GND

discharge when VIN is not presented but V

= 47μF

CNTL

C

IN

C

CNTL

OUT

C

CNTL

R

DUMMY

is presented

R

TT

V

IN

= 1.8V

0.9V

0.15V

1.25V

A

V

= 1.8V V

IN

VIN

RT9199

REFEN

VCNTL

GND

CNTL

VOUT

= 5V

I

L

Figure 1. Output Voltage Tolerance, ΔV

V

= 5V

CNTL

RT9199

GND

VCNTL

VOUT

V

OUT

R

L

C

VIN

REFEN

V

OUT

OUT

C

OUT

LOAD

0.9V

V

V

0V

and C

R

L

OUT

Figure 2. Current in Shutdown Mode, I

Time deleay

STBY

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2

V

IN

= 1.8V

V

CNTL

= 5V

RT9199

0.9V

Power Supply

with Current Limit

V

= 1.8V

IN

0.9V

VIN

REFEN

RT9199

GND

VCNTL

VOUT

V

OUT

A

I

C

OUT

L

Figure 3. Current Limit for High Side, I

= 5V

V

CNTL

A

RT9199

GND

VCNTL

VOUT

I

L

V

OUT

C

VIN

REFEN

OUT

V

LIM

V

V

REFEN

V

OUT

0.9V

0.9V

0.15V

0V

Figure 4. Current Limit for Low Side, I

V

= 5V

CNTL

V

= 1.8V

IN

VIN

VCNTL

RT9199

REFEN

VOUT

GND

V

and C

R

L

Time deleay

OUT

would be low if V

OUT

V

would be high if V

OUT

REFEN

REFEN

< 0.15V

Figure 5. REFEN Pin Shutdown Threshold, V

R

> 0.6V

LIM

V

OUT

C

IH

& V

IL

OUT

V

L

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RT9199

Functional Pin Description

VIN

Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the

input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor

should be placed as close as possible to the VIN pin.

GND

Common Ground.

VCNTL

VCNTL supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is

proportioned to the VCNTL. Connect this pin to 5V bias supply to handle large output current with at least 10μF capacitor

from this pin to GND. An important note to be aware of the VCNTL always should be exposed to voltages that exceed VIN

(i.e. VCNTL ≥ VIN).

REFEN

Reference voltage input and active low shutdown control pin. Two resistors dividing down the VIN voltage on the pin to

create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002,

signal N-Channel MOSFET.

VOUT

Regulator output. VOUT is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking

and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value
of 1000μF Al electrolytic capacitor with 10μF ceramic capacitors are recommended to reduce the effects of current

transients on VOUT.

Function Block Diagram

REFEN

VCNTL

Current Limit

Thermal Protection

+

EA

-

VIN

VOUT

GND

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Absolute Maximum Ratings (Note 1)

RT9199

z Input Voltage, V

z Control Voltage, V

z Power Dissipation, P

------------------------------------------------------------------------------------------------------ 6V

IN

----------------------------------------------------------------------------------------------- 6V

CNTL

@ TA = 25°C

D

SOP-8 ------------------------------------------------------------------------------------------------------------------- 0.909W

SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.176W

z Package Thermal Resistance (Note 4)

SOP-8, θJA-------------------------------------------------------------------------------------------------------------- 110° C/W

SOP-8, θJC-------------------------------------------------------------------------------------------------------------- 60° C/W

SOP-8 (Exposed Pad), θJA------------------------------------------------------------------------------------------ 86° C/W

SOP-8 (Exposed Pad), θJC----------------------------------------------------------------------------------------- 15° C/W

z Junction Temperature ------------------------------------------------------------------------------------------------- 125°C

z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C

z Storage Temperature Range ---------------------------------------------------------------------------------------- –65°C to 150°C

z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV

MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 3)

z Input Voltage, V

z Control Voltage, V

z Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C

------------------------------------------------------------------------------------------------------ 1.6V to 5.5V

IN

----------------------------------------------------------------------------------------------- 5V ± 5%

CNTL

Electrical Characteristics

(V

IN

Input

VCNTL Operation Current I

Standby Current (Note 7) I

Output (DDR II)

Output Offset Voltage (Note 5) VOS I

Load Regulation (Note 6) ΔV

Protection

Current limit I

Thermal Shutdown Temperature TSD V

Thermal Shutdown Hysteresis ΔTSD V

REFEN Shutdown

Shutdown Threshold

= 1.8V,

V

CNTL

= 5V, V

REFEN

= 0.9V, C

= 10μF (Ceramic), T

OUT

Parameter Symbol Test Conditions Min Typ Max Units

I

CNTL

STBY

LOAD

2.0 -- -- A

LIM

OUT

V

REFEN

R

LOAD

OUT

I

OUT

I

OUT

CNTL

CNTL

VIH Enable 0.6 -- --

V

Shutdown -- -- 0.15

IL

= 25°C, unless otherwise specified)

A

= 0A -- 1 2.5 mA

< 0.2V (Shutdown),

= 180Ω

-- 50 90 μA

= 0A −20 -- +20 mV

= +1.5A

−20 -- +20 mV

= −1.5A

= 5V 125 170 -- °C

= 5V -- 35 -- °C

V

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RT9199

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θ

Note 5. V
Note 6. Regulation is measur

Note 7. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on

is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,

JA

2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θ

is on the exposed pad for SOP-8

JC

(Exposed Pad) package.

offset is the voltage measurement defined as V

OS

subtracted from V

OUT

REFEN

.

ed at constant junction temperature by using a 5ms current pulse. Devices are tested for load

regulation in the load range from 0A to 2A peak.

REFEN pin (V

< 0.15V). It is measured with VIN = V

IL

CNTL

= 5V.

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Typical Operating Characteristics

RT9199

Output Voltage vs. Temperature

0.92

V

= 1.8V, V

IN

-50 -25 0 25 50 75 100 125

Output Voltage (V)

0.915

0.91

0.905

0.9

0.895

0.89

0.885

0.88

= 5V

CNTL

Temperature

(°C)

Source Current Limit v s. Temperature

3.5

3

2.5

V

IN

= 1.8V, V

CNTL

= 5V

VCNTL Pin Current vs. Temperature

0.6

V

= 1.8V, V

IN

0.5

0.4

0.3

0.2

Vcntl Pin Current (mA)

0.1

-50 -25 0 25 50 75 100 125

= 5V

CNTL

Temperature

(°C)

Sink Current Limit vs. Temperature

3.5

3

2.5

V

IN

= 1.8V, V

CNTL

= 5V

2

1.5

1

Source Current Limit (A)

0.5

0

-50 -25 0 25 50 75 100 125

Temperature

(°C)

VIN Current vs. Temperature

3

V

VIN Current (mA)

2.5

1.5

0.5

= 1.8V, V

IN

2

1

CNTL

= 5V

2

1.5

1

Source Current Limit (A)

0.5

0

-50 -25 0 25 50 75 100 125

Temperature

(°C)

Shutdown Threshold vs. Temperature

0.6

RT9199SP, V

0.55

0.5

0.45

0.4

0.35

0.3

Shutdown Threshold (V)

0.25

= 5V

CNTL

Turn On

Turn Off

0

-50 -25 0 25 50 75 100 125

Temperature

(°C)

0.2

-50 -25 0 25 50 75 100 125

Temperature

(°C)

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RT9199

Output Short-Circuit Protection

Sink

12

10

8

6

4

2

Output Short Circuit (A)

0

Output Short-Circuit Protection

Source

12

10

8

VIN = 1.8V, V

Time (1ms/Div)

VIN = 1.8V, V

CNTL

CNTL

= 5V

= 5V

Output Short-Circuit Protection

Sink

12

10

8

6

4

2

Output Short Circuit (A)

0

Output Short-Circuit Protection

Source

12

10

8

VIN = 2.5V, V

Time (1ms/Div)

VIN = 2.5V, V

CNTL

CNTL

= 5V

= 5V

6

4

2

Output Short Circuit (A)

0

0.9VTT @ 1.8A Transient Response

VIN = 1.8V, V

Swing Frequency : 10kHz

50

0

-50

Output Voltage

Transient (mV)

2

1

0

(A)

-1

Output Current

-2

Time (1ms/Div)

= 5V, V

CNTL

OUT

= 0.9V

6

4

2

Output Short Circuit (A)

0

1.25VTT @ 1.8A Transient Response

VIN = 2.5V, V

Swing Frequency : 10kHz

50

0

-50

Output Voltage

Transient (mV)

2

1

0

(A)

-1

Output Current

-2

Time (1ms/Div)

= 5V, V

CNTL

OUT

= 1.25V

Time (25μs/Div)

Time (25μs/Div)

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Application Information

Consideration while designing the resistance of
voltage divider

Refer to the “Typical Application Circuit”.Make sure the

current sinking capability of pull-down NMOS is enough

for the chosen voltage divider to pull-down the voltage at

REFEN pin below 0.15V to shutdown the device.

In addition, the capacitor CSS and voltage divider form the

low-pass filter. There are two reasons doing this design;

one is for output voltage soft-start while another is for noise

immunity.

How to reduce power dissipation on Notebook PC
or the dual channel DDR SDRAM application?

In notebook application, using RichTek's Patent

“Distributed Bus Terminator Topology” with choosing

RichTek's product is encouraged.

REFEN

General Regulator

The RT9199 could also serves as a general linear regulator.

The RT9199 accepts an external reference voltage at

REFEN pin and provides output voltage regulated to this

reference voltage as shown in Figure 6, where

V

= V

OUT

As other linear regulator, dropout voltage and thermal issue

should be specially considered. Figure 7 shows the R

over temperature of RT9199. The minimum dropout voltage

Distributed Bus Terminating Topology

Terminator Resistor

RT9199

RT9199

x R1/(R1+R2)

REFEN

VOUT

VOUT

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R(2N)

R(2N+1)

BUS(0)

BUS(1)

BUS(2)

BUS(3)

BUS(4)

BUS(5)

BUS(6)

BUS(7)

BUS(8)

BUS(9)

BUS(2N)

BUS(2N+1)

DS(ON)

RT9199

could be obtained by the product of R

current. For thermal consideration, please refer to the

relative sections.

V

REFEN

R1

R2

VCNTL

REFEN

VIN

RT9199

VOUT

GND

Figure 6

R

0.48

V

= 5V, V

CNTL

0.46

0.44

0.42

0.4

(Ω)

0.38

DS(ON)

0.36

R

0.34

0.32

0.3

0.28

-50-250 255075100125

vs. Temperature

DS(ON)

= 1V

REFEN

Temperature

(°C)

Figure 7

Input Capacitor and Layout Consideration

Place the input bypass capacitor as close as possible to

the RT9199. A low ESR capacitor larger than 470uF is

recommended for the input capacitor. Use short and wide

traces to minimize parasitic resistance and inductance.

Inappropriate layout may result in large parasitic inductance

and cause undesired oscillation between RT9199 and the

preceding power converter.

Thermal Consideration

RT9199 regulators have internal thermal limiting circuitry

designed to protect the device during overload conditions.

For continued operation, do not exceed absolute maximum

operation junction temperature 125°C. The power

dissipation definition in device is:

PD = (VIN - V

OUT

) x I

+ VIN x I

OUT

Q

DS(ON)

and output

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RT9199

The maximum power dissipation depends on the thermal

resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junction to ambient. The maximum power dissipation can

be calculated by following formula:

P

Where T

D(MAX)

= ( T

J(MAX)

− TA ) / θ

J(MAX)

JA

is the maximum operation junction

temperature 125°C, TA is the ambient temperature and the

θJA is the junction to ambient thermal resistance. The

junction to ambient thermal resistance for SOP-8 package

(Exposed Pad) is 86°C/W, on standard JEDEC 51-7 (4

layers, 2S2P) thermal test board. The maximum power

dissipation at T

= 25°C can be calculated by following

A

formula:

P

= (125°C − 25°C) / 86°C/W = 1.163W

D(MAX)

Figure 8 shows the package sectional drawing of SOP-8

(Exposed Pad). Every package has several thermal

dissipation paths. As show in Figure 9, the thermal

resistance equivalent circuit of SOP-8 (Exposed Pad). The

path 2 is the main path due to these materials thermal

conductivity. We define the exposed pad is the case point

of the path 2.

Ambient

Molding Compound

PCB

Case (Exposed Pad)

Die Pad

Gold Line

Lead Frame

The thermal resistance θJA of SOP-8 (Exposed Pad) is

determined by the package design and the PCB design.

However, the package design has been decided. If possible,

it’ s useful to increase thermal performance by the PCB

design. The thermal resistance can be decreased by

adding copper under the expose pad of SOP-8 package.

Figure 10 show the relation between thermal resistance

θJA and copper area on a standard JEDEC 51-7 (4 layers,

2S2P) thermal test board at TA = 25°C. We have to consider

the copper couldn’ t stretch infinitely and avoid the tin
overflow. We use the “Dog-Bone” copper patterns on the

top layer as Figure 11.

100

90

80

(°C/W)

70

JA

60

50

40

30

20

10

Thermal Resistance θ

0

0 1020304050607080

Copper Area (mm2)

Figure 10. Relation Between Thermal Resistance θJA and

Copper Area

Figure 8. SOP-8 (Exposed Pad) Package Sectional

Drawing

Junction

R

GOLD-LINERLEAD FRAME

path 1

R

DIERDIE-ATTACHRDIE-PAD

path 2

R

MOLDING-COMPOUND

path 3

R

PCB

R

PCB

Case

(Exposed Pad)

Figure 9. Thermal Resistance Equivalent Circuit

10

Exposed Pad

W≦2.28mm

Ambient

Figure 11. Dog-Bone Layout

DS9199-02 September 2005www.richtek.com

RT9199

As shown in Figure 12, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal

performance. When mounted to the standard SOP-8 (Exposed Pad) pad of 2 oz. copper (Figure 12.a), θJA is 86°C/W.

Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 12.b) reduces the θJA to 73°C/W. Even further,

increasing the copper area of pad to 70mm2 (Figure 12.d) reduces the θJA to 65°C/W.

(a) Copper Area = 10mm2, θJA = 86°C/W

(b) Copper Area = 30mm2, θJA = 73°C/W

(c) Copper Area = 50mm2, θJA = 68°C/W

(d) Copper Area = 70mm2, θJA = 65°C/W

Figure 12. Thermal Resistance vs. Copper Area Layout Thermal Design

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RT9199

Outline Information

A

J

I

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197

B

F

C

D

H

M

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

8-Lead SOP Plastic Package

12

DS9199-02 September 2005www.richtek.com

RT9199

H

M

EXPOSED THERMAL PAD
(Bottom of Package)

A

Y

J

I

B

X

F

C

D

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.191 0.254 0.008 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.057 2.515 0.081 0.099

Y 2.057 3.404 0.081 0.134

8-Lead SOP (Exposed Pad) Plastic Package

RICHTEK TECHNOLOGY CORP .

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

RICHTEK TECHNOLOGY CORP .

Taipei Office (Marketing)

8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

DS9199-02 September 2005 www.richtek.com

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