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php2n60
DATASHEETS (Philips)
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DATASHEETS php2n60 DATASHEETS (Philips)

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Page 1
Philips Semiconductors Product specification
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PowerMOS transistor PHP2N60
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GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT field-effect power transistor in a ---------------- ------------------------------------------------------- ----------- ----------­plastic envelope featuring high V avalanche energy capability, stable I off-state characteristics, fast P switching and high thermal cycling R performance with low thermal
D
tot
DS(ON)
resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

Drain-source voltage 600 V Drain current (DC) 2.8 A Total power dissipation 83 W Drain-source on-state resistance 4.4 Ω
PIN DESCRIPTION
tab
d
1 gate 2 drain 3 source
tab drain
123
g
s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
I
D
I
DM
P
D
∆PD/∆TmbLinear derating factor Tmb > 25 ˚C - 0.67 W/K V
GS
E
AS
I
AS
Tj, T
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 2.8 A
Tmb = 100 ˚C; VGS = 10 V - 1.8 A Pulsed drain current Tmb = 25 ˚C - 11 A Total dissipation Tmb = 25 ˚C - 83 W
Gate-source voltage - ± 30 V Single pulse avalanche VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; - 84 mJ energy VGS = 10 V Peak avalanche current VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; - 2.2 A
VGS = 10 V Operating junction and - 55 150 ˚C
stg
storage temperature range

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R
th j-mb
R
th j-a
April 1997 1 Rev 1.001
Thermal resistance junction to - - 1.5 K/W mounting base Thermal resistance junction to - 60 - K/W ambient
Page 2
Philips Semiconductors Product specification
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ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
∆V
(BR)DSS
∆T
j
R
DS(ON)
V
GS(TO)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown VGS = 0 V; ID = 0.25 mA 600 - - V voltage
/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.7 - V/K
voltage temperature coefficient Drain-source on resistance VGS = 10 V; ID = 1.3 A - 4.0 4.4 Ω Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V Forward transconductance VDS = 30 V; ID = 1.3 A 0.7 1.7 - S Drain-source leakage current VDS = 600 V; VGS = 0 V - 1 100 µA
VDS = 480 V; VGS = 0 V; Tj = 125 ˚C - 60 500 µA
Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA Total gate charge ID = 2 A; V
Gate-source charge - 2 3 nC
= 360 V; VGS = 10 V - 25 30 nC
DD
Gate-drain (Miller) charge - 12 15 nC Turn-on delay time VDD = 300 V; ID = 2 A; - 10 - ns
Turn-on rise time RG = 18 Ω; RD = 150 Ω -26-ns Turn-off delay time - 66 - ns Turn-off fall time - 30 - ns
Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 300 - pF Output capacitance - 43 - pF Feedback capacitance - 25 - pF

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
I
SM
V
t
rr
Q
rr
Continuous source current Tmb = 25˚C - - 2.8 A (body diode) Pulsed source current (body Tmb = 25˚C - - 11 A diode) Diode forward voltage IS = 2.2 A; VGS = 0 V - - 1.2 V
Reverse recovery time IS = 2 A; VGS = 0 V; dI/dt = 100 A/µs - 500 - ns Reverse recovery charge - 3 - µC
April 1997 2 Rev 1.001
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Philips Semiconductors Product specification
-------------------------------------------------------------------------------------------------------------­ PowerMOS transistor PHP2N60
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PD%
120 110 100
90 80 70 60 50 40 30 20 10
0
0 20 40 60 80 100 120 140
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
120
100
80
60
40
20
PD% = 100⋅PD/P
ID%
PHP6N60E
D 25 ˚C
Normalised Current Derating
= f(Tmb)
Zth j-mb / (K/W)
10
D =
1
0.5
0.2
0.1
0.1
0.01
0.05
0.02
0
1E-05 1E-03 1E-01 1E+01
t / s
p
t
P
D
T
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-mb
ID, Drain current (Amps)
5
Tj = 25 C
4
3
2
1
PHP2N60
p
t
D =
T
t
PHP2N60 10 V
VGS = 4.5 V
6 V
5.5 V
5 V
0
0 50 100 150
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
ID, Drain current (Amps)
100
10
RDS(ON) = VDS/ID
1
0.1 10 100 1000 10000
= f(Tmb); conditions: VGS ≥ 10 V
D 25 ˚C
tp = 10 us
100 us
DC
VDS, Drain-source voltage (Volts)
1 ms 10 ms
100 ms
PHP2N60
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
0
0 5 10 15 20 25 30
Fig.5. Typical output characteristics
RDS(on), Drain-Source on resistance (Ohms)
10
VGS = 4.5 V Tj = 25 C
8
6
4
2
0
012345
p
VDS, Drain-Source voltage (Volts)
ID = f(VDS); parameter V
5 V
ID, Drain current (Amps)
GS
PHP2N60
5.5 V
Fig.6. Typical on-state resistance
R
= f(ID); parameter V
DS(ON)
GS
.
6 V
10 V
.
April 1997 3 Rev 1.001
Page 4
Philips Semiconductors Product specification
-------------------------------------------------------------------------------------------------------------­ PowerMOS transistor PHP2N60
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ID, Drain current (Amps)
5
VDS = 30 V
4
3
2
1
0
0246810
VGS, Gate-Source voltage (Volts)
PHP2N60
Tj = 25 C
Tj = 150 C
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter T
gfs, Transconductance (S)
3
VDS = 30 V
2.5
2
1.5
1
0.5
150 C
j
PHP2N60
Tj = 25 C
VGS(TO) / V
4
3
2
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
max.
typ.
min.
Tj / C
Fig.10. Gate threshold voltage
V
= f(Tj); conditions: ID = 0.25 mA; VDS = V
GS(TO)
1E-01
1E-02
1E-03
1E-04
1E-05
ID / A
SUB-THRESHOLD CONDUCTION
2 %
typ
.
GS
98 %
0
012345
Fig.8. Typical transconductance
a
2
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
ID, Drain current (A)
gfs = f(ID); parameter T
Normalised RDS(ON) = f(Tj)
Tj / C
.
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)/RDS(ON)25 ˚C
= f(Tj); ID = 2 A; VGS = 10 V
1E-06
0 1 2 3 4
VGS / V
Fig.11. Sub-threshold drain current.
ID = f(V
Junction capacitances (pF)
1000
100
10
1
1 10 100 1000
Fig.12. Typical capacitances, C
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
; conditions: Tj = 25 ˚C; VDS = V
GS)
Ciss
Coss
Crss
VDS, Drain-Source voltage (Volts)
, C
iss
PHP2N60
, C
oss
GS
rss
.
April 1997 4 Rev 1.001
Page 5
Philips Semiconductors Product specification
-------------------------------------------------------------------------------------------------------------­ PowerMOS transistor PHP2N60
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VGS, Gate-Source voltage (Volts)
15
ID = 2.0 A
Tj = 25 C
10
5
0
0 10203040
Qg, Gate charge (nC)
240 V
120 V
PHP2N60
VDD = 360 V
Fig.13. Typical turn-on gate-charge characteristics.
V
= f(QG); parameter V
GS
Switching times (ns)
1000
VDD = 300 V VGS = 10 V
RD = 150 Ohms
ID = 2 A
Tj = 25 C
100
td(off)
tf
10
1
tr
td(on)
0 102030405060
RG, Gate resistance (Ohms)
Fig.14. Typical switching times
t
d(on)
, tr, t
, tf = f(RG)
d(off)
DS
PHP2N60
.
IF, Source-Drain diode current (Amps)
20
VGS = 0 V
15
10
5
0
0 0.5 1 1.5
VSDS, Source-Drain voltage (Volts)
150 C
PHP2N60
Tj = 25 C
Fig.16. Source-Drain diode characteristic.
IF = f(V
EAS, Normalised unclamped inductive energy (%)
120 110 100
90 80 70 60 50 40 30 20 10
0
20 40 60 80 100 120 140
); parameter T
SDS
Starting Tj ( C)
j
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100 -50 0 50 100 150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage
V
(BR)DSS/V(BR)DSS 25 ˚C
= f(Tj)
L
VDS
VGS
0
RGS
.
Fig.18. Unclamped inductive test circuit.
EAS= 0.5 ⋅ LI
2
⋅ V
D
(BR)DSS
T.U.T.
/(V
(BR)DSS−VDD
R 01
shunt
VDD
+
-
-ID/100
)
April 1997 5 Rev 1.001
Page 6
Philips Semiconductors Product specification
-------------------------------------------------------------------------------------------------------------­ PowerMOS transistor PHP2N60
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MECHANICAL DATA

Dimensions in mm Net Mass: 2 g
10,3 max
1,3
3,7
4,5 max
3,0 max
not tinned
1,3
max
(2x)
123
2,54 2,54
2,8
3,0
13,5
min
0,9 max (3x)
5,9
min
15,8
max
0,6
2,4
Fig.19. TO220AB; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".
April 1997 6 Rev 1.001
Page 7
Philips Semiconductors Product specification
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PowerMOS transistor PHP2N60
----------------------------------------------------------------------------------------------------------------------------------------------------------

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
April 1997 7 Rev 1.001
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