Datasheets nx2139ads, nx2139a Datasheet

NX2139A

SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER

PRELIMINARY DATA SHEET

Pb Free Product

DESCRIPTION

The NX2139A controller IC is a compact Buck control­ler IC with 16 lead MLPQ package designed for step
down DC to DC converter in portable applications. It
can be selected to operate in synchronous mode or
non-synchronous mode to improve the efficiency at light
load.Constant on time control provides fast response,
good line regulation and nearly constant frequency un­der wide voltage input range. The NX2139A controller
is optimized to convert single supply up to 24V bus
voltage to as low as 0.75V output voltage. Over cur­rent protection and FB UVLO followed by latch fea­ture. A built-in LDO controller can drive an external N­MOSFET to provide a second output voltage from ei­ther PWM output source or other power source. Both
PWM controller and LDO controller have separate EN
feature. Other features includes: 5V gate drive capa­bility, power good indicator, over voltage protection,
internal Boost schottky diode and adaptive dead band
control.

FEATURES

n Internal Boost Schottky Diode
n Ultrasonic mode operation available
n Bus voltage operation from 4.5V to 24V
n Less than 1uA shutdown current with Enable low
n Excellent dynamic response with constant on time

control

n Selectable between Synchronous CCM mode and

diode emulation mode to improve efficiency at
light load

n Programmable switching frequency
n Current limit and FB UVLO with latch off
n Over voltage protection with latch off
n LDO controller with seperate enable
n Two independent Power Good indicator available
n Pb-free and RoHS compliant

APPLICATIONS

n Notebook PCs and Desknotes
n Tablet PCs/Slates
n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n Hand-held portable instruments

TYPICAL APPLICATION

5V

PGOOD

4

PGOOD

100k

9

PVCC

10

1u

2

VCC

1u

N X 2 1 3 9 A

ENSW

15

/MODE

14

ENLDO

5V

100k

LDOPG

5

LDOPG

GND

TON

HDRV

BST

SW

LDRV

OCSET

VOUT

FB

LDODRV

LDOFB

PAD

1MEG

16

1n

12

2.2

13

11

8

10

1

3

7

50
33n

6

IRF7807

1u

5k

1n

20k

330p

1.5uH

AO4714

10.5k

7.5k

7.5k

7.5k

Figure1 - Typical application of NX2139A

ORDERING INFORMATION

Device Temperature Package Pb-Free
NX2139ACMTR -10oC to 100oC 3X3 MLPQ-16L Yes

2x10uF

VIN 7V~22V

Vout 1.8V/7A

2R5TPE330MC

330uF

M3
SI4800

1.5V@2A

2x10uF

Rev. 2.3
03/19/09

1

NX2139A

CW

θ≈46/

VFB=0.85V, ENLDO=GND,

ABSOLUTE MAXIMUM RATINGS

VCC,PVCC to GND & BST to SW voltage ............ -0.3V to 6.5V

TON to GND ......................................................... -0.3V to 28V

HDRV to SW Voltage .......................................... -0.3V to 6.5V

SW to GND ......................................................... -2V to 30V

All other pins ........................................................ VCC+0.3V

Storage Temperature Range ..................................-65

Operating Junction Temperature Range .................-40oC to 150oC

ESD Susceptibility ............................................... 2kV

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

3x3 16-LEAD PLASTIC MLPQ

o

C to 150oC

o

VO

VCC

16 15 14

1
2

TON

ENSW/MODE

17

ENLDO

BST

13

12

11

JA

HDRV

SW

AGND

OCSET

8

LDRV

10

9

PVCC

FB

PGOOD

3
4

6

LDOFB

7

LDODRV

5

LDOPG

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA =25oC, unless otherwise
specified.

PARAMETER SYM Test Condition Min TYP MAX Units

VIN

recommended voltage range
Shut down current ENLDO=GND, ENSW=GND 1

VCC,PVCC Supply

Input voltage range
Operating quiescent current

Shut down current

Rev. 2.3
03/19/09

V

IN

V

CC

ENSW=5V 1.8 mA
ENLDO=GND, ENSW=GND 1 uA

4.5 24

4.5 5.5 V

V

uA

2

NX2139A

Under-voltage Lockout

OUTPUT voltage

VOUT shut down discharge

SW zero cross comparator

(CL=3300pF)

Ldrv going Low to Hdrv going

(CL=3300pF)

Current

Fall Time

TLdrv(Fall)

90% to 10%

50 ns

PARAMETER SYM Test Condition Min TYP MAX Units

VCC UVLO

VCC_UVLO

threshold
Falling VCC threshold

ON and OFF time

TON operating current VIN=15V, Rton=1Mohm 15 uA

ON -time

VIN=9V,VOUT=0.75V,
Rton=1Mohm 312 390 468 ns

Minimum off time

FB voltage

Internal FB voltage

Vref

Input bias current 100 nA
Line regulation

VCC from 4.5V to 5.5V -1 1 %

3.9 4.1 4.5 V

3.7 3.9 4.3 V

380 590 800 ns

0.739 0.75 0.761 V

Output range

0.75 3.3 V

resistance ENSW/MODE=GND 30 ohm
Soft start time 1.5 ms

PGOOD

Pgood high rising threshold 90 % Vref
PGOOD delay after softstart NOTE1 1.6 ms
PGOOD propagation delay
filter NOTE1 2 us

Power good hysteresis
Pgood output switch
impedance

Pgood leakage current

Offset voltage

High Side Driver

N

Output Impedance , Sourcing

5 %

13 ohm

R

(Hdrv) I=200mA 1.5 ohm

source

5 mV

1 uA

Current
Output Impedance , Sinking

R

(Hdrv) I=200mA 1.5 ohm

sink

Current
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(L to

H)

High, 10% to 10%

30 ns

Low Side Driver

Output Impedance, Sourcing
Current
Output Impedance, Sinking

Rise Time TLdrv(Rise) 10% to 90% 50 ns

Rev. 2.3
03/19/09

R

(Ldrv) I=200mA 1.5 ohm

source

R

(Ldrv) I=200mA 0.5 ohm

sink

10 nsDeadband Time Tdead(H to L)SW going Low to Ldrv going

High, 10% to 10%

3

PARAMETER SYM Test Condition Min TYP MAX Units

ENSW/MODE threshold and

80%

VCC+0

60%

80%

Leave it open or use limits in

60%

LDO Controller

PWM OFF, LDOEN=HI,

LDOFB reference voltage

0.728

0.75

0.773

V

LDO PGOOD propagation

C

Under voltage

Over voltage

Internal Schottky Diode

bias current

NX2139A

PFM/Non Synchronous Mode
Ultrasonic Mode

Synchronous Mode

spec 2

VCC
VCC

.3V V
VCC V

VCC V

Shutdown mode 0 0.8 V

Input bias current

ENSW/MODE=VCC 5 uA
ENSW/MODE=GND -5 uA

Quiescent current

IOUT=0mA 1 mA
LDOEN logic high voltage 2 V
LDOEN logic low voltage 0.8 V

Output UVLO threshold 70 %Vref
Open loop gain NOTE1 60 DB
LDOFB input bias current 1 uA
LDODrv sourcing current LDOFB=0.72V 2 mA
LDODrv sinking current LDOFB=0.78V 2 mA
LDO PGOOD threshold 90 %Vref

delay filter NOTE1 2 us
LDO PGOOD impedance 13 ohm

Current Limit

Ocset setting current 20 24 28 uA

Over temperature

Threshold NOTE1

155

Hysteresis 15

o

C

o

FB threshold 70 %Vref

Over voltage tripp point 125 %Vref

Forward voltage drop Forward current=50mA 500 mV

NOTE1: This parameter is guaranteed by design but not tested in production(GBNT).

Rev. 2.3
03/19/09

4

PIN DESCRIPTIONS

PIN NUMBER PIN SYMBOL PIN DESCRIPTION

1

VOUT

This pin is directly connected to the output of the switching regulator and
senses the VOUT voltage. An internal MOSFET discharges the output during
turn off.

NX2139A

2

3

4

5

6
7
8
9

10

VCC

FB

PGOOD

LDOPG

LDOFB

LDODRV

LDRV

PVCC

OCSET

This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is
placed as close as possible to this pin and ground pin.

This pin is the error amplifiers inverting input. This pin is connected via
resistor divider to the output of the switching regulator to set the output DC
voltage from 0.75V to 3.3V.

PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc
or lower voltage. When FB pin reaches 90% of the reference voltage
PGOOD transitions from LO to HI state.

PGOOD indicator for LDO, requires a pull up resistor to Vcc or lower volt­age. When LDOFB pin reaches 90% of the reference voltage PGOOD
transitions from LO to HI state.

This pin is the error amplifiers inverting input. This pin is connected via
resistor divider to the output of the LDO to set the output DC voltage.

The drive signal for external LDO N channel MOSFET.
Low side gate driver output.
Provide the voltage supply to the lower MOSFET drivers. Place a high

frequency decoupling capacitor 1uF X5R to this pin.
This pin is connected to the drain of the external low side MOSFET and is

the input of over current protection(OCP) comparator. An internal current
source is flown to the external resistor which sets the OCP voltage across
the Rdson of the low side MOSFET.

Rev. 2.3
03/19/09

11

12

13

14
15

16

PAD

SW

HDRV

BST

ENLDO

ENSW/

MODE

TON

GND

This pin is connected to source of high side FETs and provide return path for
the high side driver. It is also the input of zero current sensing comparator.

High side gate driver output.
This pin supplies voltage to high side FET driver. A high freq 1uF X7R

ceramic capacitor and 2.2ohm resistor in series are recommended to be
placed as close as possible to and connected to this pin and SW pin.

LDO enable input functions only when ENSW/MODE is not shutdown.
Switching converter enable input. Connect to VCC for PFM/Non synchronous

mode, connected to an external resistor divider equals to 70%VCC for ultra­sonic, connected to GND for shutdown mode, floating or connected to 2V for
the synchronous mode.

VIN sensing input. A resistor connects from this pin to VIN will set the fre­quency. A 1nF capacitor from this pin to GND is recommended to ensure the
proper operation.

Power ground.

5

BLOCK DIAGRAM

VCC(2)

Bias

TON(16)

VIN

VOUT

ENSW
/MODE(15)

VOUT

FB(3)

VCC

ON time
pulse
genearation

VREF=0.75V

soft start

1M

1M

OCP_COMP

start

MODE
SELECTION

4.3/4.1

Mini offtime
400ns

POR
FBUVLO_latch

Disable

PFM_nonultrasonic

Sync

Disable_B

Thermal
shutdown

R

Q

S

POR

start ODB

HD

FET Driver

HD_IN

Diode
emulation

HD

PGND

BST(13)

HDRV(12)

SW(11)

PVCC(9)

LDRV(8)

OCSET(10)

NX2139A

VIN

1.8V

5V

GND(17 PAD)

PGOOD(4)

LDOPG(5)

ENLDO(14)

LDO_EN

OVP

FBUVLO_latch

SS_finished

LDOFBUVLO_latch

LDOSS_finished

LDO_POR

LDOFBUVLO_latch

FB

1.25*Vref/0.7VREF

0.9*Vref

0.9*Vref

soft
start

OCP_COMP

0.7*Vref

0.7*Vref

FB

VOUT

start

Figure 2 - Simplified block diagram of the NX2139A

VOUT(1)

LDODRV(7)

LDOFB(6)

1.5V@2A~5A

Rev. 2.3
03/19/09

6

TYPICAL APPLICATION

(VIN=7V to 22V, SW VOUT=1.8V/7A, LDO VOUT=1.5V/2A)

NX2139A

PGOOD

5V

R1

100k

R2
10

C1 C2

1u

LDOPG

R3

100k

1u

5V

15

14

4

PGOOD

9

PVCC

2

VCC

ENSW
/MODE

ENLDO

5

TON

HDRV

BST

N X 2 1 3 9 A

LDOPG

GND

SW

LDRV

OCSET

VOUT

FB

LDODRV

LDOFB

PAD

R4

1MEG

16

C3
1n

12
13

11

8

10

1

3

7

R8
50

C6

33n

6

M1

R5

C4
1u

5k

C5
1n

R9

20k

M2

IRF7807

AO4714

C8

330p

Lo

1.5uH

10.5k

7.5k

R10

7.5k
R11

7.5k

R12

2.2
C7

1.5n

R6

R7

2.2R13

CI1
2x10uF

VIN 7V~22V

Vout 1.8V/7A

CO1

2R5TPE330MC

330uF

M3
SI4800

1.5V@2A

CO2
2x10uF

Rev. 2.3
03/19/09

Figure 3 - Demo board schematic

7

Bill of Materials

Item Quantity Reference Value Manufacture

1 2 CI1 10uF/25V/X5R
2 2 CO2 10uF/6.3V/X5R
3 1 CO1 2R5TPE330MC SANYO
4 3 C1,C2,C4 1uF
5 2 C3,C5 1nF
6 1 C6 33nF
7 1 C7 1.5nF
8 1 C8 330pF

9 1 Lo DO5010H-152 COILCRAFT
10 1 M1 IRF7807 IR
11 1 M2 AO4714 AOS
12 1 M3 SI4800 PHILIPS
13 2 R1,R3 100k
14 1 R2 10
15 1 R4 1M
16 1 R5 5k
17 1 R6 10.5k
18 3 R7,R10,R11 7.5k
19 1 R8 50
20 1 R9 20k
21 2 R12,R13 2.2
22 1 U1 NX2139A NEXSEM INC.

NX2139A

Rev. 2.3
03/19/09

8

Demoboard Waveforms

NX2139A

Fig.4 Startup (CH1 1.8V OUTPUT, CH2 1.5V LDO,
CH3 SW PGOOD, CH4 LDO PGOOD)

Fig.6 LDO output transient with SW in PFM mode
(CH1 1.8V OUTPUT AC, CH2 1.5V LDO AC, CH4
LDO OUTPUT CURRENT)

Fig.5 Turn off (CH1 1.8V OUTPUT, CH2 1.5V LDO,
CH3 SW PGOOD, CH4 LDO PGOOD)

Fig.7 SW output transient (CH1 1.8V OUTPUT AC,
CH2 1.5V LDO AC, CH4 1.8V OUTPUT CURRENT)

Fig.8 Start into short (CH1 VIN, CH2 5V VCC, CH4
INDUCTOR CURRENT)

Rev. 2.3
03/19/09

Fig. 9 VOUT ripple @ VIN=12V,IOUT=4A (CH1 SW,
CH3 VOUT AC)

9

100.00%

OUTPUT EFFICIENCY(%)

90.00%

80.00%

70.00%

60.00%

50.00%

NX2139A

VIN=12V, VOUT=1.8V

10 100 1000 10000

OUTPUT CURRENT(mA)

Fig. 10 Output efficiency

Rev. 2.3
03/19/09

10

NX2139A

TONOUT

VTON

(

)

INOUT ON

(22V-1.8V)372nS

SOUT

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple

Design Example

The following is typical application for NX2139A,
the schematic is figure 1.
VIN = 7 to 22V
VOUT=1.8V
FS=220kHz
IOUT=7A
DVRIPPLE <=60mV
DVDROOP<=60mV @ 3A step

On_Time and Frequency Calculation

The constant on time control technique used in
NX2139A delivers high efficiency, excellent transient
dynamic response, make it a good candidate for step
down notebook applications.

An internal one shot timer turns on the high side
driver with an on time which is proportional to the input
supply VIN as well inversely proportional to the output
voltage VOUT. During this time, the output inductor
charges the output cap increasing the output voltage
by the amount equal to the output ripple. Once the
timer turns off, the Hdrv turns off and cause the output
voltage to decrease until reaching the internal FB volt­age of 0.75V on the PFM comparator. At this point the
comparator trips causing the cycle to repeat itself. A
minimum off time of 400nS is internally set.

The equation setting the On Time is as follows:

12

TON

F

4.4510RV

=

V

OUT

=

S

×

IN

In this application example, the RTON is chosen
to be 1Mohm, when VIN=22V, the TON is 372nS and

−

×××

V0.5V

−

IN

...(1)

...(2)

FS is around 220kHz.

Output Inductor Selection

The value of inductor is decided by inductor ripple
current and working frequency. Larger inductor value
normally means smaller ripple current. However if the
inductance is chosen too large, it brings slow response
and lower efficiency. The ripple current is a design free­dom which can be decided by design engineer accord­ing to various application requirements. The inductor
value can be calculated by using the following equa­tions:

L=
I=kI××

V-VT

OUT

RIPPLEOUTPUT

I

RIPPLE

...(3)

where k is percentage of output current.

In this example, inductor from COILCRAFT
DO5010H-152 with L=1.5uH is chosen.

Current Ripple is recalculated as below:

(V-V)T

I=

RIPPLE

INOUT ON

=

L

OUT

1.5uH

×

×

...(4)

=5A

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specifica­tion for the load transient. The optimum design may
require a couple of iterations to satisfy both conditions.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(5).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C

is the value of output capaci-

OUT

tors.

Typically POSCAP is recommended to use in
NX2139's applications. The amount of the output volt­age ripple is dominated by the first term in equation(5)

RIPPLE

××

8FC

...(5)

Rev. 2.3
03/19/09

11

NX2139A

ESR=12m

==Ω

ERIPPLE

12m5A

tran

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

23.76H

=µ

Estep

ESRI

0.6

and the second term can be neglected.

For this example, one POSCAP 2R5TPE330MC
is chosen as output capacitor, the ESR and inductor
current typically determines the output voltage ripple.
When VIN reach maximum voltage, the output volt­age ripple is in the worst case.

V

desire

∆

RIPPLE

I5A

∆

RIPPLE

60mV

...(6)

If low ESR is required, for most applications, mul­tiple capacitors in parallel are needed. The number of
output capacitor can be calculate as the following:

ESRI

N

=

N

=

V

∆

Ω×

60mV

×∆

RIPPLE

...(7)

N =1

The number of capacitor has to be round up to a
integer. Choose N =1.

Based On Transient Requirement

Typically, the output voltage droop during tran­sient is specified as

∆V

droop

∆V

<

@step load DI

STEP

During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section
is a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over­shoot when load from high load to light load with a
DI

transient load, if assuming the bandwidth of sys-

STEP

tem is high enough, the overshoot can be estimated
as the following equation.

V

VESRI

overshootstep

OUT

2LC

××

OUT

...(8)

where τ is the a function of capacitor,etc.

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(9

where

ESRCVESRCV

××××

==

II

∆∆

stepstep

...(10)

L

crit

where ESRE and CE represents ESR and capaci­tance of each capacitor if multiple capacitors are used
in parallel.

The above equation shows that if the selected
output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency ca­pacitor such as electrolytic capacitor, the product of

ESR and capacitance is high and

≤ is true. In

that case, the transient spec is mostly like to depen­dent on the ESR of capacitor.

Most case, the output capacitor is multiple ca­pacitor in parallel. The number of capacitor can be cal­culated by the following

ESRI

×∆

N

Estep

V2LCV

∆×××∆

tranEtran

V

OUT

...(11)

where

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(12)

For example, assume voltage droop during tran­sient is 60mV for 3A load step.

If one POSCAP 2R5TPE330MC(330uF, 12mohm
ESR) is used, the crticial inductance is given as

ESRCV

××

EEOUT

==

I

∆

step

Ω×µ×

L

crit

12m3300F1.8V

3A

The selected inductor is 1.5uH which is smaller
than critical inductance. In that case, the output volt­age transient mainly dependent on the ESR.

number of capacitor is

∆

Ω×

60mV

V

×∆

tran

N

=

12m3A

=
=

Rev. 2.3
03/19/09

Choose N=1.

12

NX2139A

SW

F

2ESRC4

IID1-D

×−××

P=I(1D)RK

SWINOUTSWS

PVITF

=××××

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

Based On Stability Requirement

ESR of the output capacitor can not be chosen
too low which will cause system unstable. The zero
caused by output capacitor's ESR must satisfy the re­quirement as below:

F

=≤

ESR

1

×π××

OUT

...(13)

Besides that, ESR has to be bigger enough so
that the output voltage ripple can provide enough volt­age ramp to error amplifier through FB pin. If ESR is
too small, the error amplifier can not correctly dectect
the ramp, high side MOSFET will be only turned off for
minimum time 400nS. Double pulsing and bigger out­put ripple will be observed. In summary, the ESR of
output capacitor has to be big enough to make the sys­tem stable, but also has to be small enough to satify
the transient and DC ripple requirements.

Input Capacitor Selection

Input capacitors are usually a mix of high fre­quency ceramic capacitors and bulk capacitors. Ce­ramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS cur­rent rating. The RMS current in the input capacitors
can be calculated as:

=××

RMSOUT

DTF

=×

ONS

...(14)

When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of
input RMS current is 1.9A.

For higher efficiency, low ESR capacitors are
recommended. One 10uF/X5R/25V and two 4.7uF/
X5R/25V ceramic capacitors are chosen as input
capacitors.

Power MOSFETs Selection

The NX2139A requires at least two N-Channel
power MOSFETs. The selection of MOSFETs is based
on maximum drain source voltage, gate source volt­age, maximum current rating, MOSFET on resistance

and power dissipation. The main consideration is the
power loss contribution of MOSFETs to the overall con­verter efficiency. In this application, one IRF7807 for
high side and one AO4714 with integrated schottky di­ode for low side are used.

There are two factors causing the MOSFET

power loss:conduction loss, switching loss.

Conduction loss is simply defined as:

2

P=IDRK

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

×××

2

...(15)

+

where the RDS(ON) will increases as MOSFET junc­tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case. Conduction loss should not exceed
package rating or overall system thermal budget.

Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.

1
2

...(16)

where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.

Also MOSFET gate driver loss should be consid­ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis­charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:

...(17)

where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS is the high side gate source voltage, and
V

is the low side gate source voltage.

LGS

This power dissipation should not exceed maxi­mum power dissipation of the driver device.

Output Voltage Calculation

Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed

R

Rev. 2.3
03/19/09

13

NX2139A

OUT

REF

2REF

OUT REF

SWLDSON

IR+V

IIR/R

R5k

===Ω

at 0.75V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.75V
when the output voltage is at the desired value.

The following equation applies to figure 11, which

shows the relationship between

V ,

V and volt-

age divider.

Vout

R2

Fb

R1

Vref

Figure 11 - Voltage Divider

RV

R=

1

where R

of R1 value can be set by voltage divider.

×

V-V

is part of the compensator, and the value

2

...(18)

tion of frequency keeps the system running at light light
with high efficiency.

In CCM mode, inductor current zero-crossing
sensing is disabled, low side MOSFET keeps on even
when inductor current becomes negative. In this way
the efficiency is lower compared with PFM mode at
light load, but frequency will be kept constant.

Over Current Protection

Over current protection for NX2139A is achieved
by sensing current through the low side MOSFET. An
typical internal current source of 24uA flows through
an external resistor connected from OCSET pin to SW
node sets the over current protection threshold. When
synchronous FET is on, the voltage at node SW is given
as

V=-IR×

The voltage at pin OCSET is given as

×

OCPOCPSW

When the voltage is below zero, the over current
occurs as shown in figure below.

vbus

Mode Selection

NX2139A can be operated in PFM mode, ultra­sonic PFM mode, CCM mode and shutdown mode by
applying different voltage on ENSW/MODE pin.

When VCC applied to ENSW/MODE pin,
NX2139A is In PFM mode. The low side MOSFET emu­lates the function of diode when discontinuous con­tinuous mode happens, often in light load condition.
During that time, the inductor current crosses the zero
ampere border and becomes negative current. When
the inductor current reaches negative territory, the low
side MOSFET is turned off and it takes longer time for
the output voltage to drop, the high side MOSFET waits
longer to be turned on. At the same time, no matter
light load and heavy load, the on time of high side
MOSFET keeps the same. Therefore the lightier load,
the lower the switching frequency will be. In ultrosonic
PFM mode, the lowest frequency is set to be 25kHz to
avoid audio frequency modulation. This kind of reduc-

OCP

I

24uA

OCP

R

SW

OCP

OCP
comparator

Figure 12 - Over Voltage Protection

The over current limit can be set by the following

equation.

=×

SETOCPOCPDSON

If the low side MOSFET R

=10mΩ at the OCP

DSON

occuring moment, and the current limit is set at 12A,
then

IR

SETDSON

OCP

Choose R

×

I24uA

OCP

=5kΩ

OCP

12A10m

×Ω

Rev. 2.3
03/19/09

14

NX2139A

RDSONLDOINLDOOUTLOAD

(1.8V1.5V)/2A0.15

=−=Ω

(1.8V1.5V)2A0.6W

C=

2FR1+gESR

C= =36pF

Power Good Output

Power good output is open drain output, a pull
up resistor is needed. Typically when softstart is
finised and FB pin voltage is over 90% of V

REF

, the

PGOOD pin is pulled to high after a 1.6ms delay.

Smart Over Output Voltage Protection

Active loads in some applications can leak cur­rent from a higher voltage than V
age to rise. When the FB pin voltage is sensed over
112% of V

, the high side MOSFET will be turned off

REF

and low side MOSFET will be turned on to discharge
the V

. NX2139A resumes its switching operation af-

OUT

ter FB pin voltage drops to V

If FB pin voltage keeps rising and is sensed over
125% of V

, the low side MOSFET will be latched to

REF

be on to discharge the output voltage and over voltage
protection is triggered. To resume the switching opera­tion, resetting voltage on pin VCC or pin EN is neces­sary.

, cause output volt-

OUT

.

REF

P(VV)I

=−×

LOSSLDOINLDOOUTLOAD

=−×=

Select MOSFET SI4800 with 33mΩ R
sufficient.

LDO Compensation

The diagram of LDO controller including VCC

regulator is shown in the following figure.

LDO input

Vref

Rf1

Rf2

LDOFB

Rc Cc

Figure 13 - NX2139A LDO controller.

LDODRV

Rb

Cb

ESR

DSON

Co

is

+

Rload

Under Output Voltage Protection

Typically when the FB pin voltage is under 70%
of V

, the high side and low side MOSFET will be

REF

turned off. To resume the switching operation, VCC or
ENSW has to be reset.

LDO Selection Guide

NX2139A offers a LDO controller. The selection
of MOSFET to meet LDO is more straight forward.
The MOSFET has to be logic level MOSFET and its
Rdson at 4.5V should meet the dropout requirement.
For example.

V

=1.8V

LDOIN

V

I

The maximum Rdson of MOSFET should be

R(VV)I

Most of MOSFETs can meet the requirement.
More important is that MOSFET has to be selected
right package to handle the thermal capability. For LDO,
maximum power dissipation is given as

=1.5V

LDOOUT

=2A

Load

=−×

Rb and Cb have fixed value which is used to com­pensate the comparater of the LDO controller. Set
Rb=50ohm, Cb=33nF.

For most low frequency capacitor such as elec­trolytic, POSCAP, OSCON, etc, the compensation pa­rameter can be calculated as follows.

gESR

C

1

×π×××

Of1m

×

m

×

where FO is the desired crossover frequency.

Typically, when the POSCAP and electrical ca­pacitor is chosen as output capacitor, crossover fre­quency FO has to be 2 to 3 times higher than zero
caused by ESR. In this example, we select Fo=150kHz.

gm is the forward trans-conductance of MOSFET.
For SI4800, gm=19.

Select Rf1=7.5kohm.

Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.

C

119S18m

2150kHz7.5k1+19S18m

×π××Ω×Ω

×

×Ω

Typically CC is chosen to be 1 to 1.5 times smaller
than calculated value to compensate parasitic effect.

Rev. 2.3
03/19/09

15

NX2139A

LDOOUTREF

7.5k0.75V

1.5V0.75V

1.5V

2A

1.5V

1020uF

20k19S

Here CC is chosen to be 33pF. For electrolytic or
POSCAP, RC is typically selected to be zero.

Rf2 is determined by the desired output voltage.

RV

×

R=

=

Ω

f1REF

f2

VV

−

Ω×

−

=7.5k

Choose Rf2=7.5kΩ.
When ceramic capacitors or some low ESR bulk
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency FO has to be chosen much higher
than zero caused by RC and CC and much lower than
zero caused by ESR . For example, 10uF ceramic is
used as output capacitor. We select Fo=300kHz,
Rf1=7.5kohm and select MOSFET SI4800(gm=19). R
and C

can be calculated as follows.

C

2FCI

×π××

R=R

=7.5k

Ω

××

Cf1

Ω××

=14.9k

OOOUT

g

m

2300kHz20uF

×π××

19S

1+g

g

V

OUT

×

m

V

OUT

×

m

I

OUT

1+19S

19S

×

×

2A

Typically RC is chosen to be 1 to 1.5 times smaller
than calculated value to compensate parasitic effect.
Choose RC=20kΩ.

10C

×

C=

C

=

=0.53nF

Choose C

O

Rg

×

Cm

×

Ω×

=1000pF.

C

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below

70% of V

, the IC goes into latch mode. The IC will

REF

turn off all the channel until VCC or ENSW resets.

Power Good for LDO

Power good output is open drain output, a pull
up resistor is needed. Typically when softstart is
finised and LDOFB pin voltage is over 90% of V
the LDOPGOOD pin is pulled to high.

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

There are two sets of components considered in
the layout which are power components and small sig­nal components. Power components usually consist of

C

input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en­vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay­out which includes power plane, ground plane and sig­nal plane is recommended .

Layout guidelines:

1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.

2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-

cally touching the drain pin of the upper MOSFET, a

plane connection is a must.

3. The output capacitors should be placed as close
as to the load as possible and plane connection is re­quired.

4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane and as close as possible. A snubber needs to be
placed as close to this junction as possible.

REF

,

Rev. 2.3
03/19/09

16

5. Source of the lower MOSFET needs to be con­nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by­passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.

8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals, should be kept away from the in­ductor and other noise sources. The resistor divider
must be located as close as possible to the FB pin of
the device.

9. All GNDs need to go directly thru via to GND
plane.

10. In multilayer PCB, separate power ground
and analog ground. These two grounds must be con­nected together on the PC board layout at a single point.
The goal is to localize the high current path to a sepa­rate loop that does not interfere with the more sensi­tive analog control function.

NX2139A

Rev. 2.3
03/19/09

17

Demoboard Schematic

NX2139A

BUS

5V

LDOIN

LDOOUT

1

1

LDOIN

BUS

LDOOUT

CIN3

4.7u/25V

R7
1M

C6

16

U1

R11
100k

5V

R6

10

856

72

R8

100k

C16
1u

VCC

VCC

C2
1u

4

PGOOD

5

LIN_PGOOD

9

VCCP

2

VCC

15

EN

14

LIN_EN

1n

TON

BST

DH

SW

OCP

DL

CIN1

10u/25V

4

4

CIN2

4.7u/25V

856

72

M1
IRF7807

1

3

856

72

M2
AO4714

1

3

Lo

1 2

DO5010H-152

R15

2.2

C9

1.5n

OUT

CO2

CO1

2R5TPE330MC

4.7u/6.3V

VOUT

GND

R4

13

2.2

C17
1u

12

11

10

8

R2

0

R3

10k

NX2139/MLPQ-16/3x3

LDODRV

R18
50

C19
33n

R17
20k

C18
1n

7

LIN_DRV

6

LIN_FB

GND

17

VOUT

FB

1

R5

C15

10.5k

330p

3

R10

7.5k

C7
10u

M3

SI4800

C3
10u

4

1

3

R19

7.5k

R20

7.5k

Figure 14 - NX2139A schematic for the demoboard layout

Rev. 2.3
03/19/09

18

Demoboard Layout

NX2139A

Figure 15 Top layer

Rev. 2.3
03/19/09

Figure 16 Ground layer

19

NX2139A

Figure 17 Power layer

Rev. 2.3
03/19/09

Figure 18 Bottom layer

20

MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS

NX2139A

SYMBOL

Dimensions In Millimeters

Dimensions In Inches

NAME MIN MAX MIN MAX

A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3

0.203REF

0.008REF

B 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 1.600 1.750 0.063 0.069

E 2.950 3.050 0.116 0.120
E2 1.600 1.750 0.063 0.069

e

0.50BSC

0.50BSC

L 0.325 0.450 0.013 0.018

M

1.5REF

0.059REF

Rev. 2.3
03/19/09

21