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mb2823
DATASHEETS (Philips)
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DATASHEETS mb2823 DATASHEETS (Philips)

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Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
2
August 24, 1993 853–1705 10616

FEATURES

flip-flops
• Ideal where high speed, light loading, or increased fan–in are required with MOS microprocessors
• Live insertation/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION

The MB2823 dual bus interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses carrying parity.
The MB2823 has two 9-bit wide buffered registers with Clock Enable (nCE
) and
Master Reset (nMR
) which are ideal for parity bus interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one set–up time before the Low-to-High clock transition is transferred to the corresponding flip–flop’s Q output.

QUICK REFERENCE DATA

SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay nCP to nQx
CL = 50pF; VCC = 5V 4.6 ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
OUT
Output capacitance VO = 0V or VCC; 3-state 7 pF
I
CCZ
Total supply current Outputs disabled; VCC = 5.5V 500 nA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
52-Pin Plastic Quad Flat Pack –40°C to +85°C MB2823BB 1418B

PIN CONFIGURATION LOGIC SYMBOL

Vcc
1Q2
1Q1
1Q0
1OE
1MR
1CP
1CE
1D0
GND
1D1
1D2
Vcc
Vcc
2Q6
2Q7
GND
2Q8
2OE
2MR
2CP
2CE
2D8
2D7
2D6
Vcc
19 2220 231716 25 26241514 2118
1Q7
2Q1
1Q8
2Q2
GND
1Q5
2Q4 2Q5
2Q3
1Q4
2Q0
1Q6
1Q3
1 2
3 4
5 6 7 8
9
10
11 12 13
47 4446 434950 41 40425152 4548
1D8
2D2
2D0
GND
1D6
1D5
2D4 2D5
2D3
1D4
2D1
1D7
1D339 38 37 36
35 34 33 32
31 30 29 28 27
MB2823
52-Pin
Quad Flat Pack
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8
46 45
1CP 1CE
47 48
1MR 1OE
44 42 41 39 38 37 36 35 34
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8
49 50 51 1 2 3 5 6 7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8
21 22
2CP 2CE
20 19
2MR 2OE
33 32 31 29 28 27 25 24 23
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
8 9 10 11 12 13 15 16 18
È
È
È
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
3

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION
48, 19 1OE, 2OE Output enable input (active–Low)
44, 42, 41, 39, 38, 37, 36, 35, 34,
33, 32, 31, 29, 28, 27, 25, 24, 23
1D0-1D8 2D0-2D8
Data inputs
49, 50, 51, 1, 2, 3, 5, 6, 7,
8, 9, 10, 11, 12, 13, 15, 16, 18
1Q0-1Q8 2Q0-2Q8
Data outputs
46, 21 1CP, 2CP Clock pulse input (active rising edge) 45, 22 1CE, 2CE Clock enable input (active–Low) 47, 20 1MR, 2MR Master reset input (active–Low)
4, 17, 30, 43 GND Ground (0V)
14, 26, 40, 52 V
CC
Positive supply voltage

LOGIC DIAGRAM

R Q
nD
nD0
nQ0
nMR
nOE
R Q
nD
nD1
nQ1
R Q
nD
nD2
nQ2
R Q
nD
nD3
nQ3
R Q
nD
nD4
nQ4
R Q
nD
nD5
nQ5
R Q
nD
nD6
nQ6
R Q
nD
nD7
nQ7
R Q
nD
nD8
nQ8
CP CP CP CP CP CP CP CP CP
nCP
nCE

LOGIC SYMBOL (IEEE/IEC)

44 49 42 50 41 51 39 1 38 2 37 3 36 5 35 6
2D
1C2
46
G1
45
13
4
7
R
EN
47
48
33 8 32 9 31 10 29 11 28 12 27 13 25 16 24 16
2D
1C2
21
G1
22
23 18
R
EN
20
19
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
4

FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE
nOE nMR nCE nCP nDx nQ0 – nQ8
L L X X X L Clear L H L ↑ h H Load and read data L H L ↑ l L L H H ↑ X NC Hold
H X X X X Z High impedance
H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state
↑ = Low to High clock transition ↑
= Not a Low-to-High clock transition

ABSOLUTE MAXIMUM RATINGS

1, 2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current output in Low state 128 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT
MIN MAX
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
5

DC ELECTRICAL CHARACTERISTICS

LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
amb
= +25°C
T
amb
= –40°C
to +85°C
UNIT
MIN TYP MAX MIN MAX
V
IK
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
VCC = 4.5V; IOH = –3mA; VI = VIL or V
IH
2.5 2.9 2.5 V
V
OH
High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
IH
3.0 3.4 3.0 V
VCC = 4.5V; IOH = –32mA; VI = VIL or V
IH
2.0 2.4 2.0 V
V
OL
Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
IH
0.42 0.55 0.55 V
V
RST
Power-up output low voltage
3
VCC = 5.5V; IOL = 1mA; VI = GND or V
CC
0.13 0.55 0.55 V
I
I
Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
I
OFF
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
I
PU/PD
Power-up/down 3-State output current
4
VCC = 2.1V; VO = 0.5V; VI = GND or VCC, V
OE
= Don’t care
±5.0 ±50 ±50 µA
I
OZH
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
IH
5.0 50 50 µA
I
OZL
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
IH
–5.0 –50 –50 µA
I
CEX
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
CC
5.0 50 50 µA
I
O
Output current
1
VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA
I
CCH
VCC = 5.5V; Outputs High, VI = GND or V
CC
120 250 250 µA
I
CCL
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
CC
45 68 68 mA
I
CCZ
VCC = 5.5V; Outputs 3–State; V
I
= GND or V
CC
120 250 250 µA
∆I
CC
Additional supply current per input pin
2
VCC = 5.5V; one input at 3.4V, other inputs at V
CC
or GND
0.5 1.5 1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transistion time of up to 100µsec is permitted.

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MAX MIN MAX
f
MAX
Maximum clock frequency 1 140 190 140 MHz
t
PLH
t
PHL
Propagation delay nCP to nQx
1
2.0
2.5
3.8
4.2
5.1
5.6
2.0
2.5
5.7
6.1
ns
t
PHL
Propagation delay nMR
to nQx
2 3.2 5.3 6.6 3.2 7.5 ns
t
PZH
t
PZL
Output enable time to High and Low level
4 5
1.3
2.2
3.2
4.0
4.4
5.3
1.3
2.2
5.1
5.9
ns
t
PHZ
t
PLZ
Output disable time from High and Low level
4 5
1.3
1.5
3.3
3.1
4.6
4.4
1.3
1.5
5.1
5.9
ns
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
6

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
V
CC
= +5.0V
T
amb
= -40 to +85oC
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MIN
ts(H) t
s
(L)
Setup time, High or Low nDx to nCP
3
2.0
1.5
0.6
0.2
2.0
1.5
ns
th(H) t
h
(L)
Hold time, High or Low nDx to nCP
3
1.5
1.5
–0.2 –0.5
1.5
1.5
tw(H) t
w
(L)
nCP pulse width High or Low
1
3.0
3.5
1.0
2.3
3.0
3.5
ns
ts(H) t
s
(L)
Setup time, High or Low nCE
to nCP
3
1.5
2.0
–0.2
1.0
1.5
2.0
ns
th(H) t
h
(L)
Hold time, High or Low nCE
to nCP
3
1.5
1.5
–1.2
0.3
1.5
1.5
ns tw(L) nMR pulse width, Low 2 3.0 1.6 3.0 ns t
rec
Recovery time nMR
to nCP
2 2.5 0.6 2.5 ns

AC WAVEFORMS

NOTE: For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
w
(H) tw(L)
V
M
V
M
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
V
M
V
M
V
M
1/f
MAX
t
PHL
t
PLH
nCP
nQx
V
M
nMR
V
M
nQx
Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time
tw(L)
V
M
t
PHL
V
M
t
REC
nCP
V
M
nDx, nCE
V
M
V
M
V
M
V
MVM
nCP
Waveform 3. Data Setup and Hold Times
ts(H) th(H) ts(L) th(L)
nOE
V
M
t
PZH
t
PHZ
0V
V
OH
–0.3V
nQx
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
M
V
M
nOE
t
PZL
t
PLZ
VOL +0.3V
nQx
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
M
V
M
V
M
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
7

TEST CIRCUIT AND WAVEFORM

PULSE
GENERATOR
R
T
V
IN
D.U.T
V
OUT
C
L
R
L
V
CC
R
L
7.0V
Test Circuit for 3-State Outputs
V
M
V
M
t
W
AMP (V)
NEGATIVE PULSE
10% 10%
90%
90%
0V
V
M
V
M
t
W
AMP (V)
POSITIVE PULSE
90% 90%
10%
10%
0V
t
THL
(tF)
t
TLH
(tR) t
THL
(tF)
t
TLH
(tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
W
t
R
t
F
MB 3.0V 1MHz 500ns 2.5ns 2.5ns
SWITCH POSITION
TEST SWITCH
t
PLZ
closed
t
PZL
closed
All other open
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
8
Adjustment of t
PHL
for
Load Capacitance and # of Outputs Switching
nCp to nQx
t
PLH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nCp to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PLH
for
Load Capacitance and # of Outputs Switching
nCp to nQx
pF
18 switching
9 switching 1 switching
ns
Offset in ns
t
PHL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nCp to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
t
PHL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nMR
x to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PHL
for
Load Capacitance and # of Outputs Switching
nMR
x to nQx
pF
pF
18 switching
9 switching 1 switching
18 switching
9 switching 1 switching
8
7
6
5
4
3
2
1
–40 –15 10 35 60 85
8
7
6
5
4
3
2
1
–40 –15 10 35 60 85
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
8
7
6
5
4
3
2
1
–40 –15 10 35 60 85
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
9
Adjustment of t
PZL
for
Load Capacitance and # of Outputs Switching
nOE
to nQx
t
PZH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOE
to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PZH
for
Load Capacitance and # of Outputs Switching
nOE
to nQx
pF
ns
Offset in ns
t
PZL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOE
to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
t
PHZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOE
x to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PHZ
for
Load Capacitance and # of Outputs Switching
nOE
x to nQx
pF
pF
18 switching
9 switching 1 switching
18 switching
9 switching 1 switching
18 switching
9 switching 1 switching
7
6
5
4
3
2
1
0
–40 –15 10 35 60 85
7
6
5
4
3
2
1
0
–40 –15 10 35 60 85
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
8
7
6
5
4
3
2
1
–40 –15 10 35 60 85
7 6 5 4 3 2 1
0 –1 –2 –3
0 20 40 60 80 100 120 140 160 180 200
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
10
Adjustment of t
TLH
for
Load Capacitance and # of Outputs Switching
nOE
to nQx
t
PLZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOE
to nQx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PLZ
for
Load Capacitance and # of Outputs Switching
nOE
to nQx
pF
18 switching
9 switching 1 switching
ns
Offset in ns
t
TLH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
°C
4.5V
CC
5.5V
CC
18 switching
9 switching 1 switching
ns
Offset in ns
t
THL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
°C
4.5V
CC
5.5V
CC
Adjustment of t
THL
for
Load Capacitance and # of Outputs Switching
pF
18 switching
9 switching 1 switching
pF
8
7
6
5
4
3
2
1
–40 –15 10 35 60 85
4
3
2
1
0
–40 –15 10 35 60 85
6 5 4 3 2 1 0
–1 –2
0 20 40 60 80 100 120 140 160 180 200
8 7 6 5 4 3 2 1 0
–1 –2
0 20 40 60 80 100 120 140 160 180 200
4
3
2
1
0
–40 –15 10 35 60 85
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2823
Dual 9-bit D-type flip-flop with reset and enable (3-State)
August 24, 1993
11
V
OHV
and V
OLP
vs Load Capacitance
V
CC
= 5V, VIN = 0V to 3V
pF
125oC
25
o
C
–55
o
C
125
o
C
25
o
C
–55
o
C
VOLTS
VOLTS
V
OHP
and V
OLV
vs Load Capacitance
V
CC
= 5V, VIN = 0V to 3V
125oC
25
o
C
–55
o
C
125
o
C
25oC
–55
o
C
pF
5
4
3
2
1
0
0 20 40 60 80 100 120 140 160 180 200
6 5 4 3 2 1
0 –1 –2 –3
0 20 40 60 80 100 120 140 160 180 200
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