Datasheets isl6522cb Datasheet

®

ISL6522

Data Sheet November 2002

Buck and Synchronous Rectifier
Pulse-Width Modulator (PWM) Controller

The ISL6522 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous rectified buck
topology. The ISL6522 integrates all of the control, output
adjustment, monitori ng and prot ection functi ons in to a si ngle
package.

The output voltage of the converter can be precisely
regulated to as low as 0.8V, with a maximum tolerance of
±1% over temperature and line voltage variations.

The ISL6522 provides si mp le, s ing le fee dback loop, voltage­mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The er ror
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The result ing PWM duty rati o
ranges from 0–100%.

The ISL6522 protects against overcurrent conditions by
inhibiting PWM ope rati on. Th e ISL6522 monitors t he cu rrent
by using the r

of the upper MOSFET which eliminates

DS(ON)

the need for a current sensing resistor.

Pinout

TOP VIEW

SOIC

and

TSSOP

RT

OCSET

SS

COMP

FB
EN

GND

1
2
3
4
5
6
7

TOP VIEW

14
13
12
11
10
9
8

VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE

FN9030.3

Features

• Drives two N-Channel MOSFETs

• Operates from +5V or +12V input

• Simple single-loop control design

- Voltage-mode PWM control

• Fast transient response

- High-bandwidth error amplifier

- Full 0–100% duty ratio

• Excellent output voltage regulation

- 0.8V internal reference

- ±1% over line voltage and temperature

• Overcurrent fault monitor

- Does not require extra current sensing element

- Uses MOSFETs r

DS(ON)

• Converter can source and sink cu rrent

• Small converter size

- Constant frequency operation

- 200kHz free-running oscillator programmable from
50kHz to over 1MHz

• 14-lead SOIC and TSSOP package and 16-lead 5x5mm
MLFP Package

• MLFP Package

- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat

No Leads-Product Outline.

- Near Ch ip-Scale Package Footpr int; Improves PCB

Efficiency and Thinner in Profile

Applications

• Power supply for Pent ium®, Pentium Pro, PowerPC® and
AlphaPC™ microprocessors

• High-power 5V to 3.xV DC-DC regulators

• Low-voltage distributed power su pplies

Ordering Information

MLFP

MLFP

SS

COMP

FB

EN

NC

16

1
2

3
4

567

NC

PowerPC

OCSET

RT

VCC

15 14 13

PVCC

12

LGATE

GND

GND

1

11
10

PGND

9

BOOT

8

PHASE

UGATE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

®

is a trademark of IBM. AlphaPC™ is a trademark of Digital Equipment Corporation. Pentium® is a registered trademark of Intel Corporation.

PART NUMBER

ISL6522CB 0 to 70 14 Ld SOIC M14.15
ISL6522IB -40 to 85 14 Ld SOIC M14.15
ISL6522CV 0 to 70 14 Ld TSSOP M14.173
ISL6522IV -40 to 85 14 Ld TSSOP M14.173
ISL6522CR 0 to 70 16 Ld 5x5 MLFP L16.5x5B
ISL6522IR -40 to 85 16 Ld 5x5 MLFP L16.5x5B

TEMP.

RANGE (oC) PACKAGE

| Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002, All Rights Reserved

PKG.

NO.

Typical Application

SS

12V

V

CC

MONITOR AND

PROTECTION

ISL6522

+5V OR +12V

OCSET
EN

BOOT

Block Diagram

OCSET

FB

COMP

RT

RT

FB

REFERENCE

REF

OSC

COMP

200µA

0.8V

ISL6522

+

-

REF

UGATE
PHASE

+12V

PV

CC

-

+

+

-

ERROR

AMP

LGATE
PGND

GND

+

-

OVER

CURRENT

4V

PWM

COMPARATOR

OSCILLATOR

POWER-ON

RESET (POR)

+

-

VCC

SOFT-

START

INHIBIT

PWM

GATE

CONTROL

LOGIC

10µA

+V

O

EN

SS

BOOT
UGATE

PHASE

PV

CC

LGATE
PGND
GND

2

ISL6522

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V

Boot Voltage, V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V

ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

BOOT

- V

. . . . . . . . . . . . . . . . . . . . . . +15.0V

PHASE

CC

+0.3V

Thermal Resistance (Typical, Note 1) θ

SOIC Package (Note 1) . . . . . . . . . . . . . . . . . . . 67 n/a

TSSOP Package (Note 1) . . . . . . . . . . . . . . . . . 95 n/a

MLFP Package (Note 2 and Note 3) . . . . . . . . . 36 5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range, ISL6522C. . . . . . . . . . . .0

Ambient Temperature Range, ISL6522I . . . . . . . . . . -40

Junction Temperature Range, ISL6522C . . . . . . . . . . 0

Junction Temperature Range, ISL6522I . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Ma ximum Rat ings” may cause permanen t damage to the devi ce. This is a stress only ra ting and oper ation of th e
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

o

C to 70oC

o

C to 85oC

o

C to 125oC

o

C to 125oC

Maximum Storage Temperature Range . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

NOTE:

1. θ

is measured with the component mounted on a highs effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech

2. θ

JA

Brief TB379.

3. For θ

, the "case temp" location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

V

CC

Nominal Supply I

CC

Shutdown Supply EN = 0V - 50 100 µA

POWER-ON RESET

Rising V
Falling V

Threshold V

CC

Threshold V

CC

Enable-Input Threshold Voltage ISL6522C, V

Rising V

Threshold -1.27- V

OCSET

OSCILLATOR

Free Running Frequency ISL6522C, R

Total Variation 6kΩ < R
Ramp Amplitude ∆V

OSC

REFERENCE

Reference Voltage Tolerance V

REF

Reference Voltage - 0.800 - V

ERROR AMPLIFIER

DC Gain -88- dB
Gain-Bandwidth Product GBW - 15 - MHz
Slew Rate SR COMP = 10pF - 6 - V/µs

GATE DRIVERS

Upper Gate Source I

UGATE

EN = VCC; UGATE and LGATE Open - 5 - mA

= 4.5VDC - - 10.4 V

OCSET

= 4.5VDC 8.8 - - V

OCSET

= 4.5VDC 0.8 - 2.0 V

OCSET

ISL6522I, V

ISL6522I, R

to GND < 200kΩ -20 - +20 %

T

= 4.5VDC 0.8 - 2.1 V

OCSET

= OPEN, VCC = 12 175 200 230 kHz

T

= OPEN, VCC = 12 160 200 230

T

RT = OPEN - 1.9 - V

-1 - 1 %

V

BOOT

- V

PHASE

= 12V, V

= 6V 350 500 - mA

UGATE

(oC/W) θJC(oC/W)

JA

o

C to 150oC

P-P

o

C

o

C

3

ISL6522

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Upper Gate Sink R

Lower Gate Source I
Lower Gate Sink R

PROTECTION

OCSET Current Source I
Soft-Start Current I

UGATE

LGATE

LGATE

OCSETVOCSET

SS

ISL6522C, I
ISL6522I, I
VCC = 12V, V
ISL6522C, I
ISL6522I, I

= 0.3A - 5.5 10 Ω

LGATE

= 0.3A - 5.5 7.2 Ω

LGATE

= 6V 300 450 - mA

LGATE

= 0.3A - 3.5 6.5 Ω

LGATE

= 0.3A - 3.5 4.5 Ω

LGATE

= 4.5VDC 170 200 230 µA

-10- µA

Typical Performance Curves

80

RT PULLUP

1000

100

RESISTANCE (kΩ)

10

10 100 1000

SWITCHING FREQUENCY (kHz)

TO +12V

RT PULLDOWN

TO V

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

Functional Pin Descriptions

SOIC

and

TSSOP

MLFP

RT

OCSET

SS

COMP

FB
EN

GND

1
2
3
4
5
6
7

14
13
12
11
10
9
8

SS

VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE

70

60

50

(mA)

40

VCC

I

30

20

10

0

100 200 300 400 500 600 700 800 900 1000

C

= 3300pF

GATE

C

= 1000pF

GATE

C

= 10pF

GATE

SWITCHING FREQUENCY (kHz)

RT

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
200kHz switching frequency is increased according to the
following equation:

510

Fs 200kHz

•

------------------+≈

R

Conversely, connecting a pull-up resistor (R
to V

reduces the switching frequency according to the

CC

following equation:

410

Fs 200kHz

•

------------------–≈

R

) from this pin to GND, the nominal

T

6

T

T

(RT to GND)

7

(RT to 12V)

) from this pin

T

OCSET

Connect a resistor (R
upper MOSFET. R
(I

), and the upper MOSFET on-resistance (r

OCS

OCSET

4

) from this pin to the drain of the

OCSET

, an internal 200µA current source

DS(ON)

) set

ISL6522

the converter overcurrent (OC) trip point according to the
following equation:

I

•

I

PEAK

An overcurrent trip cycles the soft-start function.

OCSROCSET

------------------------------------------- -=

r

DS ON()

SS

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft­start interval of the converter.

COMP and FB

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.

EN

This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, th e s oft-st ar t pi n is
discharged and the UGATE and LGATE pins are held low.

GND

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PHASE

Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.

UGATE

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET. This pin is
also monitored by the adaptive shoot through protection
circuitry to determine when the upper MOSFET has turned
off.

VCC

Provide a 12V bias supply for the chip to this pin.

Functional Description

Initialization

The ISL6522 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply vo ltages and the enable ( E N) pin . Th e PO R
monitors the bias voltage at the VCC pin and the input
voltage (V
equal to V
protection). With the EN pin held to V
initiates soft-start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V
+12V power source must exceed the rising V
before POR initiates operation.

The POR function inhibits operation with the chip disabled
(EN pin low). With both input supplies above their POR
thresholds, transitioning the EN pin high initiates a soft-start
interval.

) on the OCSET pin. The level on OCSET is

IN

Less a fixed voltage drop (see overcurrent

IN

and VCC are equivalent and the

IN

, the POR function

CC

threshold

CC

Soft-Start

The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (C
the SS pin to 4V. Soft-start clamps the error amplifier output
(COMP pin) to the SS pin voltage. Figure 3 shows the soft­start interval. At t
reach the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2, at which
point the output is in regulation and the clamp on the COMP
pin is released. This method provides a rapid and controlled
output voltage rise.

in Figure 3, the SS and COMP voltages

1

SS

) on

BOOT

This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.

PGND

This is the power groun d connect ion. Tie the lower MOSFET
source to this pin.

LGATE

Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the lower MOSFET has turned off.

PVCC

Provide a bias supply for the lower gate drive to this pin.

5

ISL6522

Voltage

V

OSC(MIN)

t

0

C

t

----------- V

1

I

SS

t

SoftStartt2t1

Where:

4V

2V

0V

15A

10A

Clamp on V

t

t

2

1

SS

⋅=

OSC MIN()

V

OUT

C

–

C

= Soft Start Capacitor

SS

= Soft Start Current = 10µA

I

SS

V

OSC(MIN)

= Input Voltage

V

IN

∆V

OSC

V

OUTSteadyState

FIGURE 3. SOFT-START INTERVAL

SS

-----------

------------------------------------------------ ∆V

⋅⋅==

I

SS

= Bottom of Oscillator = 1.35V

= Peak to Peak Oscillator Voltage = 1.9V

= Steady State Output Voltage

released at Steady State

COMP

SteadyState

V

IN

V

SOFT START

V

V

COMP

OUT

OSC

Time

is reference to V
MOSFET (also referenced to V
across R

OCSET

sequence. The soft-start function discharges C

. When the voltage across the upper

IN

) exceeds the voltage

IN

, the overcurrent func tion ini tiates a soft-start

with a

SS

10µA current sink and inhi bits PWM op eration. The soft-start
function recharges C

, and PWM operation resumes with

SS

the error amplifier clamped to the SS voltage. Should an
overload occur while recharging C
inhibits PWM operation while fully charging C

, the soft-start function

SS

to 4V to

SS

complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the C

charging interval and causes an

SS

overcurrent trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.

The overcurrent function will trip at a peak inductor current
(I

determined by:

PEAK)

I

PEAK

where I

I

---------------------------------------------------=

OCSET

•

OCSETROCSET

r

DS ON()

is the internal OCSET current source (2 00µA
is typical). The OC trip point varies mainly due to the
MOSFETs r
in the normal opera ting l oad ran ge, fi nd the R

variations. To avoid overcurrent tripping

DS(ON)

OCSET

resistor

from the equation above with:
The maximum r

1. The minimum I

2. Determine ,
where ∆I is the output inductor ripple current.

at the highest junction temperature.

DS(ON)

from the specification table.

OCSET

I

PEAK

for I

PEAK

I

OUT MAX()

∆I()2⁄+>

For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.

A small ceramic capacitor should be placed in parallel with
R

to smooth the voltage across R

OCSET

OCSET

in the

presence of switching noise on the input voltage.

5A

OUTPUT INDUCTOR SOFT-START

0A

TIME (20ms/DIV.)

FIGURE 4. OVERCURRENT OPERATION

Overcurrent Protection

The overcurrent function protects the converter from a
shorted output by using the upper MOSFETs on-res is tan ce ,
r
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.

The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault pro tection. A resist or (R
programs the overcurrent trip level. An internal 200µA
(typical) current s ink dev elops a v oltage a cross R

to monitor the current. This method enhances the

DS(ON)

6

OCSET

OCSET

that

Current Sinking

The ISL6522 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as s ource current. Care should be exercised when
designing a converte r with the ISL6522 when it is know n that
the converter may sink current.

When the converter is sinking current, it is behaving as a boost
converter that is regulating its input voltage. This means that
the converter is boosting current into the V
that is being down-converted. If there is nowhere for this current
to go, such as to other distributed loads on the V
a voltage limiting protection device, or other methods, the
capacitance on the V

bus will absorb the current. This

IN

situation will cause the voltage level of the V

)

the voltage level of the rail is boosted to a level that exceeds the
maximum voltage rating of the MOSFETs or the input
capacitors, damage may occur to these parts. If the bias
voltage for the ISL6522 comes from the V

rail, the voltage

IN

rail, through

IN

rail to increase. If

IN

rail, then the

IN

ISL6522

maximum voltage rating of the ISL6522 may be exceeded and
the IC will experience a catastrophic failure and the converter
will no longer be operational. Ensuring that there is a path for
the current to follow other than the capacitance on the rail will
prevent these failure modes.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.

Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wi res indicate d by heavy lines shoul d be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
and C

each represent numerous physical capacitors.

O

Locate the ISL6522 within three in ches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6 522 must be siz ed to
handle up to 1A peak current.

V

Q1

IN

L

O

V

ISL6522

UGATE

PHASE

OUT

IN

+V

Q1

Q2

IN

L

O

C

V

OUT

O

BOOT
C

BOOT

ISL6522

SS

C

SS

GND

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

PHASE

VCC

+12V

D1

C

VCC

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V

) is regulated to the reference voltage level. The error

OUT

amplifier (error amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output filter
(L

and CO).

O

The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

. This function is dominated by a DC
gain and the output filter (L
break frequency at F

and a zero at F

LC

the modulator is simply the input vo ltage (V
peak-to-peak oscillator voltage ∆V

) is compared with the

E/A

at the

IN

and CO), with a double pole

O

OSC

. The DC gain of

ESR

) divided by the

IN

.

LOAD

C

IN

Q2

LGATE

PGND

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

D2

RETURN

C

O

Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C

SS

close to the SS pin because the internal current source is
only 10µA. Provide local V
GND pins. Locate the capacitor, C

decoupling between VCC and

CC

BOOT

as close as

practical to the BOOT and PHASE pins.

7

LOAD

ISL6522

V

IN

L

O

PHASE

(PARASITIC)

IN

Z

FB

Z

IN

C3

R1

FB

R3

C

ESR

V

OUT

O

V

OUT

∆V

OSC

OSC

PWM

COMPARATOR

-

+

Z

FB

V

E/A

-

+

ERROR
AMP

DETAILED COMPENSATION COMPONENTS

COMP

REFERENCE

C2

C1

DRIVER

DRIVER

Z

R2

-

+

ISL6522

REF

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

Modulator Break Frequency Equations

F

LC

2π L

••

OCO

F

ESR

1

-------------------------------------- -=

The compensation network consists of the error amplifier
(internal to the ISL6522) and the impedance networks Z
and Z

. The goal of the compensation network is to provide

FB

a closed loop tran sfe r fu nc tio n with the highest 0d B c ros si ng
frequency (f

) and adequate p hase margin . Phas e ma rgin

0dB

is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R 2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:

1

---------------------------------------------=

2π ES R C

•()•

O

IN

and

0dB

Compensation Break Frequency Equations

1

----------------------------------=

F

Z1

2π R• 2C1•

------------------------------------------------------=

F

Z2

2π R1 R3+()C3••

1

F

P1

F

P2

-------------------------------------------------------=

2π R2•

----------------------------------

=

2π R3 C3••

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole
(~75% F

3. Place 2

)

LC

ND

Zero at Fil ter’s Double Pole

1

C1 C2•



----------------------

•



C1 C 2+

1

4. Place 1

ST

Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F

with the capabilities of the error

P2

amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.

100

80

60

40

20LOG

(R2/R1)

20

GAIN (dB)

0

MODULATOR

-20

-40

-60

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

F

F

F

P1

Z2

Z1

(V

F

LC

F

ESR

FREQUENCY (Hz)

F

P2

OPEN LOOP
ERROR AMP GAIN

20LOG

/∆V

OSC

)

IN

COMPENSATION
GAIN

CLOSED LOOP
GAIN

10M1M100K10K1K10010

The compensation gain uses external impedance networks
Z

and ZIN to provide a stable, high bandwidth (BW)

FB

overall loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is req uired to filter th e outpu t and suppl y
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern microprocessors produce tra nsient loa d rates abov e
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and

8

ISL6522

voltage rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as phy sically possibl e. Be
careful not to add inductance in the circu it board wiri ng that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high sl ew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR availabl e in larger case sizes .
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of sm all cas e size
perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the l oad transient. The ind uctor value determi nes the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

OUT

V

--------------- -•

OUT

V

IN

∆V

= ∆I x ESR

OUT

V

- V

IN

--------------------------------

∆I =

Fs x L

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6522 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following

equations give the approximate response time interval for
application and removal of a transient load:

LOI

LOI

×

TRAN

RISE

where: I

------------------------------- -=
–

V

INVOUT

is the transient load current step, t

TRAN

t

FALL

response time to the application of load, and t

×

TRAN

-------------------------------=t
V

OUT

is the

RISE

is the

FALL

response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capa citor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge­current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The ISL6522 requires two N-Channel power MOSFETs.
These should be selected based upon r
requirements, and thermal management requirements.

In high-current applica tions, the M OSFET power di ssipatio n,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty fact or. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower

DS(ON)

, gate supply

9

ISL6522

switch realizes most of the switching losses when the converter
is sinking current (see the equations below).

Losses while Sourcing Current

1

P

UPPER

P

LOWER

Io2r

= Io2 x r

× D×

DS ON()

x (1 - D)

DS(ON)

-- ­2

Io⋅ V

× tSWFS××+=

IN

Losses while Sinking Current

P

P

= Io2 x r

UPPER

LOWER

Where: D is the duty cycle = V

Io2r

is the switching interval, and

t

SW

F

is the switching frequency.

S

x D

DS(ON)

× 1D–()×

DS ON()

OUT

1

Io⋅ V

-- ­2

/ VIN,

× t

IN

××+=

SWFS

These equations assume linear voltage-current transitions
and do not ad equately model power loss due the reve rse­recovery of the upp er and l ower MO SFET’s b ody di ode. Th e
gate-charge losses are dissipated by the ISL6522 and do
not heat the MOSFETs. However, large gate-charge
increases the switching interval, t

which increases the

SW

upper MOSFET switching losses. Ensure that both
MOSFETs are within t hei r m ax imum ju nc tio n t em pera ture a t
high ambient temperature by calculating the temperature
rise according to packag e therm al -res is tan ce s pec ifi ca tio ns.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient tempera ture and air
flow.

Standard-gate MOSFETs are normally recommended for
use with the ISL6522. However, logic-level gate MOSFETs
can be used under specia l circumstan ces. The input vo ltage,
upper gate drive level, and the MOSFETs absolute gate-to­source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 9 shows the upp er gate dri ve (BOOT p in) sup plied b y
a bootstrap circuit from V

. The boot capacitor, C

CC

BOOT

develops a floating supp ly vol tag e ref eren ce d to t he PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V

) when the lower MOSFET, Q2

D

CC

turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V

. For Q2, a

CC

logic-level MOSFET can be used if its absolute gate-to­source voltage rat ing exceeds the max im um voltage applied
to PVCC.

D

+

GND

BOOT

V

D

BOOT

UGATE
PHASE

PVCC

LGATE
PGND

-

C

BOOT

+5V
OR +12V

+5V OR +12V

Q1

Q2

D2

NOTE:
V

G-S

NOTE:
V

G-S

≈ VCC - V

≈ PVCC

D

+12V

VCC

ISL6522

-

+

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V

. This option should only be used in

CC

DC

or
less. The peak upper gate-to-source voltage is approximately
V

less the input supply. For +5V main power and +12VDC

CC

for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to PV

+12V

VCC

GND

BOOT

UGATE
PHASE

PVCC

LGATE
PGND

+5V
OR +12V

ISL6522

-

+

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

+5V OR LESS

Q1

Q2

CC

D2

.

NOTE:
V

≈ VCC - 5V

G-S

NOTE:
V

G-S

≈ PVCC

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.

10

ISL6522

ISL6522 DC-DC Converter Application
Circuit

Figure 11 shows a DC-DC converter circuit for a
microprocessor applic ati on , origin al ly des ig ned to emplo y
the HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522 controllers, the circuit can be

12V

CC

V

IN

C1-3

3x 680µF

RTN

C12

ENABLE

C13

0.1µF

R2
1K

R7
10K

R1

SPARE

SS
RT

FB

0.01µF

C16

6
3

1

C15

1µF

1206

REF

5

C14

33pF

OSC

+

+

-

-

15K

R5

VCC
14

MONITOR AND

PROTECTION

U1

ISL6522

-

­+

+

COMP

COMP
TP1

implemented using the ISL6522 controller without any
modifications. Deta iled info rmatio n on the circ uit, inc luding a
complete bill of materials and circuit board description, can
be found in Application Note AN9722. See Intersil’s home
page on the web: http://www.intersil.com.

C17-18
2x 1µF

1206

C19

1000pF

OCSET

2

BOOT

10

9

UGATE
PHASE

8

PVCC

13

LGATE

12

PGND

11

74

GND

R6

3.01K

Q1

JP1

Q2

CR1
4148

C20

0.1µF

CR2

MBR
340

PHASE

TP2

L1

C6-9

4x 1000µF

V

OUT

RTN

R3
1K

SPARE

R4
SPARE

Component S election Notes:

C1-C3 - Three each 680µF 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000µF 6.3W VDC, Sanyo MV-GX or equivalent.

L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.

Q1, Q2 - Fairchild MOS FET; RFP 25N05

FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT

11

Small Outline Plastic Packag es (S OIC )

ISL6522

N

INDEX
AREA

123

SEATING PLANE

-A­D

e

B

0.25(0.010) C AM BS

M

E

-B-

A

-C-

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

h x 45

o

C

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0. 50 5
L 0.016 0.050 0.40 1.27 6
N14 147

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMINMAXMINMAX

-

12

ISL6522

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

-A-

0.05(0.002)

D

SEATING PLANE

e

b

0.10(0.004) C AM BS

M

E1

-B-

A

-C-

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE
PLANE

0.25

0.010

A2

L

c

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

FN

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 ­A1 0.002 0. 006 0.05 0.15 ­A2 0.031 0. 051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0. 177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0. 256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 1 6/00

13

ISL6522

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

L16.5x5B

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 ­A1 - - 0.05 ­A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 5.00 BSC ­D1 4.75 BSC 9
D2 2.95 3.10 3.25 7, 8
E 5.00 BSC ­E1 4.75 BSC 9
E2 2.95 3.10 3.25 7, 8
e 0.80 BSC ­k0.25--­L 0.35 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 3
P--0.609
θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

FN

NOTESMIN NOMINAL MAX

Rev. 1 10/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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14