DATASHEETS hef4724b DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4724B MSI

8-bit addressable latch

Product speciﬁcation File under Integrated Circuits, IC04

January 1995

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

DESCRIPTION

The HEF4724B is an 8-bit addressable latch with three address inputs (A0to A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs (O0to O7).

WhenE and CL are HIGH, all outputs (O0to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when CL is HIGH and E is LOW. When CL and E are LOW, the

HEF4724B

MSI

selected output (O D. When E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of A0to A2could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).

to O7; determined by A0to A2) follows

0

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

HEF4724BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4724BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4724BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

PINNING

A

to A

0

2

A data input E enable input (active LOW) CL clear input (active HIGH)

to O

O

0

7

FAMILY DATA, IDDLIMITS category MSI

address inputs

parallel latch outputs

January 1995 2

See Family Specifications

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January 1995 3

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

Fig.3 Logic diagram.

Fig.4 Logic diagram (one latch).

HEF4724B

MSI

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

HEF4724B

MODE SELECTION

E CL MODE

L L addressable latch H L memory L H active HIGH 8-channel demultiplexer H H clear

FUNCTION TABLE

CL

H H X X X X L L L L L L L L clear HLD HLD HLD HLD HLD HLD HLD HLD

LHXXXXO LLD LLD LLD LLD LLD LLD LLD LLD

EDA

1 1 1 1 1 1 1 1

0

LLLD

HLLLD

LHL L LD

HHL L L LD

LLHLLLLD

HLHLLLLLD

LHHLLLLLLD

HHHLLLLLLLD

LLLD

HLLO

LHLO

HHLO

LLHO

HLHO

LHHO

HHHO

A

1

A

2

O

0

1

n-1

1 n-1 n-1 n-1 n-1 n-1 n-1 n-1

O

1

O

2

O

3

O

4

O

5

O

6

O

7

LLLLLLL

LLLLLL

1

LLLLL

1

LLLL

1

LLL

1

LL

1

L

1

O O

O O O O O O

O

n-1

O

n-1

D

O

1

n-1

O

n-1

O

n-1

O

n-1

O

n-1

O

n-1

O

n-1

O

n-1

O

n-1

D

O

1

n-1

O

n-1

O

n-1

O

n-1

O

n-1

O

n-1 n-1 n-1 n-1

D

n-1 n-1 n-1 n-1

n-1On-1On-1On-1

O

n-1On-1On-1On-1

O

n-1On-1On-1On-1

O

n-1On-1On-1On-1

O

1

n-1On-1On-1On-1

D1O O O O

D1O

n-1 n-1On-1D1On-1 n-1On-1On-1D1

n-1On-1On-1

n-1On-1

MSI

MODE

demultiplexer; unaddressed latch is cleared

memory

addressable latch; unaddressed latch holds previous state

Notes

1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial O

= state before the positive transition of E

n-1

D1= either HIGH or LOW

January 1995 4

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

AC CHARACTERISTICS

V

= 0 V; T

SS

Dynamic power 5 700 f

dissipation per 10 3700 f package (P) 15 10 800 f

AC CHARACTERISTICS

= 0 V; T

V

SS

Propagation delays

E → O

HIGH to LOW 10 t

LOW to HIGH 10 t

D → O

HIGH to LOW 10 t

LOW to HIGH 10 t

An→ O

HIGH to LOW 10 t

LOW to HIGH 10 t

CL → O

HIGH to LOW 10 t

=25°C; input transition times ≤ 20 ns

amb

V

DD

V

=25°C; CL= 50 pF; input transition times ≤ 20 ns

amb

V

DD

V

n

5 115 230 ns 88 ns + (0,55 ns/pF) C

TYPICAL FORMULA FOR P (µW)

SYMBOL MIN. TYP. MAX.

PHL

15 35 70 ns 27 ns + (0,16 ns/pF) C

5 95 195 ns 68 ns + (0,55 ns/pF) C

PLH

15 30 55 ns 22 ns + (0,16 ns/pF) C

n

5 95 190 ns 68 ns + (0,55 ns/pF) C

PHL

15 25 55 ns 17 ns + (0,16 ns/pF) C

5 85 170 ns 58 ns + (0,55 ns/pF) C

PLH

15 25 55 ns 17 ns + (0,16 ns/pF) C

n

5 110 225 ns 83 ns + (0,55 ns/pF) C

PHL

15 35 70 ns 27 ns + (0,16 ns/pF) C

5 95 190 ns 68 ns + (0,55 ns/pF) C

PLH

15 30 55 ns 22 ns + (0,16 ns/pF) C

n

5 85 165 ns 58 ns + (0,55 ns/pF) C

PHL

15 25 50 ns 17 ns + (0,16 ns/pF) C

+∑(foCL) × V

i

+∑(foCL) × V

i

+∑(foCL) × V

i

50 95 ns 39 ns + (0,23 ns/pF) C

40 80 ns 29 ns + (0,23 ns/pF) C

35 75 ns 24 ns + (0,23 ns/pF) C

45 95 ns 34 ns + (0,23 ns/pF) C

40 80 ns 29 ns + (0,23 ns/pF) C

35 70 ns 24 ns + (0,23 ns/pF) C

DD DD DD

HEF4724B

MSI

2 2 2

where fi= input freq. (MHz) fo= output freq. (MHz)

= load capacitance (pF)

C

L

∑ (f

) = sum of outputs

oCL

V

= supply voltage (V)

DD

TYPICAL EXTRAPOLATION

FORMULA

L L L L L L L L L L L L L L L L L L L L L

January 1995 5

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

V

DD

V

Set-up times 5 40 20 ns

D →

E10t

15 10 0 ns

54020ns

A

→E10t

n

15 15 5 ns

Hold times 5 20 0 ns

D →

E10t

15 15 5 ns

55025ns

A

→E10t

n

15 15 5 ns

Minimum E 5 75 35 ns

pulse width; LOW 10 t

15 20 10 ns

Minimum CL 5 70 35 ns

pulse width; HIGH 10 t

15 20 10 ns

SYMBOL MIN. TYP. MAX.

su

hold

WEL

WCLH

15 5 ns

20 10 ns

15 5 ns

20 10 ns

30 15 ns

HEF4724B

MSI

TYPICAL EXTRAPOLATION

FORMULA

DATASHEETS hef4724b DATASHEETS (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

PINNING

FAMILY DATA, IDDLIMITS category MSI

MODE SELECTION

FUNCTION TABLE

AC CHARACTERISTICS