DATASHEETS hef4557b DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF4557B
LSI

1-to-64 bit variable length shift
register

Product specification
File under Integrated Circuits, IC04

January 1995

Philips Semiconductors Product specification

1-to-64 bit variable length shift register

DESCRIPTION

The HEF4557B is a static clocked serial shift register
whose length may be programmed to be any number of
bits between 1 and 64. The number of bits selected is
equal to the sum of the subscripts of the enabled length
control inputs (L1, L2, L4, L8, L16and L32) plus one. Serial
data may be selected from the DAor DBdata inputs with
the A/B select input. This feature is useful for recirculation

HEF4557B

LSI

purposes. Information on D
register position and all the data in the register is shifted
one position to the right on the LOW to HIGH transition of
CP0while CP1is LOW or on the HIGH to LOW transition
of CP1while CP0is HIGH. A HIGH on master reset (MR)
resets the register and forces O to LOW and O to HIGH,
independent of the other inputs.

or DBis shifted into the first

A

PINNING

D

, D

A

B

A/

B select data input

CP

0

CP

1

data inputs

clock input

clock enable input
MR asynchronous master reset
L

to L

1

32

O,

O buffered outputs

bit-length control inputs

Fig.1 Functional diagram.

HEF4557BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4557BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4557BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

FAMILY DATA, IDDLIMITS category LSI

See Family Specifications

Fig.2 Pinning diagram.

January 1995 2

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January 1995 3

Philips Semiconductors Product specification

1-to-64 bit variable length shift register

Fig.3 Logic diagram.

HEF4557B

LSI

Philips Semiconductors Product specification

1-to-64 bit variable length shift register

FUNCTION TABLE

INPUTS OUTPUT

MR A/BDADBCP

LLD
LHD
LLD
LHD

1
1
1
1

D

2

D

2

D

2

D

2

CP

O

1

LD

LD
HD
HD

(1)

O

2
1
2
1

HXXX X X L

BIT-LENGTH SELECT FUNCTION TABLE

L

L

32

16

L

L

8

L

4

L

2

REGISTER LENGTH

1

LLLLLL 1-bit
LLLLLH 2-bits
L L L L H L 3-bits
L L L L H H 4-bits
L L L H L L 5-bits
L L L H L H 6-bits
L L L H H L 7-bits
L L L H H H 8-bits

↓↓↓↓↓↓ ↓

LHHHHH 32-bits
HLLLLL 33-bits
HLLLLH 34-bits

↓↓↓↓↓↓ ↓

H H H H L L 61-bits
H H H H L H 62-bits
HHHHHL 63-bits
HHHHHH 64-bits

Notes

1. The moment Dnappears at O depends on the

2. H = HIGH state (the more positive voltage)

3. L = LOW state (the less positive voltage)

4. X = state is immaterial

5. = positive-going transition

6. = negative-going transition

7. Dn= either HIGH or LOW

HEF4557B

LSI

bit-length shown in the table below.

AC CHARACTERISTICS

= 0 V; T

V

SS

Dynamic power 5 3 500 f

dissipation per 10 15 000 f
package (P) 15 37 000 f

=25°C; input transition times ≤ 20 ns

amb

V

DD

V

TYPICAL FORMULA FOR P (µW)

+∑(foCL) × V

i

+∑(foCL) × V

i

+∑(foCL) × V

i

January 1995 4

DD
DD
DD

2

where

2

fi= input freq. (MHz)

2

fo= output freq. (MHz)

= load capacitance (pF)

C

L

∑ (f

oCL

V

= supply voltage (V)

DD

) = sum of outputs

Philips Semiconductors Product specification

1-to-64 bit variable length shift register

HEF4557B

AC CHARACTERISTICS

V

= 0 V; T

SS

Propagation delays

CP0, CP1→ O, O 5 240 480 ns 213 ns + (0,55 ns/pF) C

HIGH to LOW 10 t

LOW to HIGH 10 t

MR → O 5 170 340 ns 143 ns + (0,55 ns/pF) C

HIGH to LOW 10 t

MR → O 5 140 280 ns 113 ns + (0,55 ns/pF) C

LOW to HIGH 10 t

Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C

HIGH to LOW 10 t

LOW to HIGH 10 t

=25°C; CL= 50 pF; input transition times ≤20 ns

amb

V

DD

V

SYMBOL TYP. MAX.

PHL

15 65 130 ns 57 ns + (0,16 ns/pF) C

5 240 480 ns 213 ns + (0,55 ns/pF) C

PLH

15 65 130 ns 57 ns + (0,16 ns/pF) C

PHL

15 60 120 ns 52 ns + (0,16 ns/pF) C

PLH

15 55 110 ns 47 ns + (0,16 ns/pF) C

THL

15 20 40 ns 6 ns + (0,28 ns/pF) C

5 60 120 ns 10 ns + (1,0 ns/pF) C

TLH

15 20 40 ns 6 ns + (0,28 ns/pF) C

TYPICAL EXTRAPOLATION

FORMULA

90 180 ns 79 ns + (0,23 ns/pF) C

90 180 ns 79 ns + (0,23 ns/pF) C

80 160 ns 69 ns + (0,23 ns/pF) C

70 140 ns 59 ns + (0,23 ns/pF) C

30 60 ns 9 ns + (0,42 ns/pF) C

30 60 ns 9 ns + (0,42 ns/pF) C

LSI

L
L
L
L
L
L
L
L
L
L
L
L

L

L
L

L

L
L

Interpolation table (see note next page)

LENGTH CONTROL INPUTS MINIMUM

L

1

L

L

2

L

4

L

8

L

16

32

NUMBER OF

BITS SELECTED

SET-UP, HOLD,

RECOVERY

TIMES

L L L L L L 1 specified
HLLLLL 2 
XHLLLL 3

X X H L L L 5 six equal steps
XXXHLL 9 
XXXXHL 17

X X X X X H 33 specified

Notes

1. H = HIGH state (the more positive voltage)

2. L = LOW state (the less positive voltage)

3. X = state is immaterial

January 1995 5







Philips Semiconductors Product specification

1-to-64 bit variable length shift register

AC CHARACTERISTICS

V

= 0 V; T

SS

Minimum clock

pulse width; 5 t
LOW for CP
HIGH for

Minimum reset 5 150 75 ns

pulse width; 10 t

HIGH 15 50 25 ns

Set-up times

D

, DB, A/B → CP0, 5 360 180 ns

A

CP

1

to L32= LOW 15 90 45 ns

L

1

L

= HIGH 10 t

32

Hold times

D

, DB, A/B → CP0,5 −40 −110 ns

A

CP

1

L

to L32= LOW 15 0 −30 ns

1

L

= HIGH 10 t

32

Recovery times for MR 5 500 250 ns

L

to L32= LOW 10 t

1

L

= HIGH 10 t

32

Minimum clock 5 2,5 5 MHz

pulse frequency 10 f

=25°C; CL= 50 pF; input transition times ≤20 ns; see also waveforms Fig.4

amb

V

DD

V

or 10 or 60 30 ns

0

CP

1

15 t

10 t

SYMBOL MIN. TYP.

WCPL

WCPH

WMRH

su

180 90 ns

40 20 ns

70 35 ns

140 70 ns

540−20 ns

su

35 −10 ns

15 30 −5ns

10 t

hold

−10 −45 ns

59030ns

hold

60 20 ns

15 50 15 ns

RMR

250 125 ns

15 150 75 ns

5 110 50 ns

RMR

70 30 ns

15 60 25 ns

max

7 14 MHz

15 10 20 MHz

HEF4557B

LSI

see note

Note

1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).

January 1995 6

Philips Semiconductors Product specification

1-to-64 bit variable length shift register

HEF4557B

LSI

Fig.4 Waveforms showing recovery time for MR and minimum CP0, CP1and MR pulse widths, set-up and hold

times for DA, DBand A/B to CP0and CP1. Set-up and hold times are shown as positive values but may
be specified as negative values.

January 1995 7