DATASHEETS 87c652, 87c654 DATASHEETS

INTEGRATED CIRCUITS

87C652/87C654

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

Product specification

Replaces data sheets 87C652 of 1998 May 01 and 87C654 of 1998 May 01

IC20 Data Handbook

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C

1999 Jul 23

Philips Semiconductors Product specification

EPROM

TEMPERATURE RANGE C AND PACKAGE

g

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

DESCRIPTION

The 87C652/87C654 single-chip 8-Bit
microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
87C652/87C654 has the same instruction
set as the 80C51. Three versions of the
derivative exist:

80C652—ROMless
83C652/83C654—8 Kbyte, 16 Kbyte ROM
87C652/87C654—8 Kbyte, 16 Kbyte OTP

The ROMless and ROM are in separate
datasheets.

This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 87C654 contains a non-volatile
16k × 8 EPROM and the 87C652 contains an
8k x 8 EPROM. Both have a volatile 256 × 8
read/write data memory, four 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), a multi-source,
two-priority-level, nested interrupt structure,

2

an I

C interface, UART and on-chip oscillator
and timing circuits. For systems that require
extra capability, the 87C652/87C654 can be
expanded using standard TTL compatible
memories and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 0.75 µs and 40%
in 1.5 µs. Multiply and divide instructions
require 3 µs.

C

FEATURES

•80C51 central processing unit

•16k × 8 EPROM or 8k x 8 EPROM

expandable externally to 64k bytes

•256 × 8 RAM, expandable externally to

64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

2

•I

C-bus serial I/O port with byte oriented

master and slave functions

•Full-duplex UART facilities

•Power control modes

– Idle mode
– Power-down mode

•Extended temperature range

•OTP package available

•Two speed ranges

– 16 MHz
– 20 MHz

87C652/87C654

PIN CONFIGURATIONS

P1.0

1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6

SCL/P1.6

SDA/P1.7

RxD/P3.0

TxD/P3.1
INT0
INT1

WR

RST

/P3.2

/P3.3
T0/P3.4
T1/P3.5

/P3.6

/P3.7

RD

XTAL2
XTAL1

V

7

8
9

PLASTIC

DUAL

10

IN-LINE

PACKAGE

11
12
13
14
15
16
17
18
19
20

SS

40

V

39

P0.0/AD0

38

P0.1/AD1

37

P0.2/AD2

36

P0.3/AD3

35

P0.4/AD4

34

P0.5/AD5

33

P0.6/AD6

32

P0.7/AD7

31

EA/V

30

ALE/PROG

29

PSEN

28

P2.7/A15

27

P2.6/A14

26

P2.5/A13

25

P2.4/A12

24

P2.3/A11

23

P2.2/A10

22

P2.1/A9

21

P2.0/A8

CC

PP

SU00259

ORDERING INFORMATION

°

S87C654-4N40 0 to +70, Plastic Dual In-line Package 16 SOT129-1
S87C654-4A44 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2

S87C654–4B44 0 to +70, Plastic Quad Flat Pack 16 SOT307-2

S87C654-5N40 –40 to +85, Plastic Dual In-line Package 16 SOT129-1
S87C654-5A44 –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2

S87C654-5B44 –40 to +85, Plastic Quad Flat Pack 16 SOT307-2
S87C654–7N40 0 to +70, Plastic Dual In-line Package 20 SOT129-1
S87C654–7A44 0 to +70, Plastic Leaded Chip Carrier 20 SOT187-2

S87C652-4N40 0 to +70, Plastic Dual In-line Package 16 SOT129-1

S87C652-4A44 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2

S87C652-4B44 0 to +70, Plastic Quad Flat Pack 16 SOT307-2

S87C652-5A44 –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2

NOTES:

1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet

1999 Jul 23 853-1689 22042

2

FREQ Drawing

MHz

Number

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

BLOCK DIAGRAM

FREQUENCY
REFERENCE

XTAL2 XTAL1

OSCILLATOR

AND

TIMING

CPU

INTERNAL

INTERRUPTS

C

PROGRAM

MEMORY

(16K x 8

EPROM)

DATA

MEMORY

(256 x 8 RAM)

COUNTERS

T0 T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

87C652/87C654

2

I

C SERIAL I/O

SDA

SCL

SHARED

WITH

PORT 1

INT0

INT1

EXTERNAL

INTERRUPTS

LOGIC SYMBOL

64K BYTE BUS

EXPANSION

CONTRTOL

RST

XTAL1
XTAL2

/EA

V

PP

PSEN

PROG/ALE

ALTERNATE

FUNCTIONS

RxD

TxD
INT0
INT1

T0
T1

WR

RD

CONTROL

PORT 3

PROGRAMMABLE I/O

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

VSSV

CC

PORT 0

PORT 1PORT 2

DATA BUS

ADDRESS AND

SCL
SDA

ADDRESS BUS

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

SU00271

1999 Jul 23

SU00262

3

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

/V

CC

C

39

29

PP

SU00260

8K/16K, 256 OTP, I

PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS

6140

7

LCC

17

18 28

Pin Function

1 NC*
2 P1.0
3 P1.1
4 P1.2
5 P1.3
6 P1.4
7 P1.5
8 P1.6/SCL

9 P1.7/SDA
10 RST
11 P3.0/RxD
12 NC*
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 V

SS

* NO INTERNAL CONNECTION

Pin Function

23 NC*
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
31 P2.7/A15
32 PSEN
33 ALE/PROG
34 NC*
35 EA
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 V

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

44 34

1

PQFP

11

12 22

Pin Function

1 P1.5
2 P1.6/SCL
3 P1.7/SDA
4 RST
5 P3.0/RxD
6 NC*
7 P3.1/TxD
8 P3.2/INT0

9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
16 V

SS

17 NC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12

* NO INTERNAL CONNECTION

Pin Function

23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE/PROG
28 NC*
29 EA

/V
30 P0.7/AD7
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 V

CC

39 NC*
40 P1.0
41 P1.1
42 P1.2
43 P.13
44 P1.4

87C652/87C654

33

23

PP

SU00261

1999 Jul 23

4

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

87C652/87C654

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION

V

SS

V

CC

P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

P1.0–P1.7 1–8 2–9 40–44,

P1.6 7 8 2 I/O SCL: I2C-bus serial port clock line.
P1.7 8 9 3 I/O SDA: I2C-bus serial port data line.

P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

P3.0–P3.7 10–17 11,

RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 87C654 is

EA/V

PP

XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

20 22 16 I Ground: 0 V reference.
40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code
bytes during program verification in the 87C654. External pull-ups are required during
program verification.

1–3

13–195,7–13

10 11 5 I RxD (P3.0): Serial input port
11 13 7 O TxD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt
13 15 9 I INT1 (P3.3): External interrupt
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7

which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: I
Port 1 also receives the low-order address byte during program memory verification.
Alternate functions include:

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I
family, as listed below:

device. An internal diffused resistor to V
capacitor to V

address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG

executing code from the external program memory, PSEN
cycle, except that two PSEN
memory. PSEN

enable the device to fetch code from external program memory locations 0000H and 1FFFH
for 87C652 and 3FFFH for 87C654. If EA
program memory unless the program counter contains an address greater than 3FFFH. This
pin also receives the 12.75 V programming supply voltage (V

circuits.

.

CC

is not activated during fetches from internal program memory.

activations are skipped during each access to external data

). Port 3 also serves the special features of the 80C51

IL

) during EPROM programming.

). Port 2 emits the high-order address byte

IL

permits a power-on reset using only an external

SS

is activated twice each machine

is held high, the device executes from internal

) during EPROM programming.

PP

+ 0.5 V or VSS – 0.5 V, respectively.

CC

).

IL

1999 Jul 23

5

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

87C652/87C654

Table 1. 8XC652/654 Special Function Registers

SYMBOL DESCRIPTION

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:

DPH
DPL

IE*# Interrupt enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

IP*# Interrupt priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

P1*# Port 1 90H SDA SCL FFH

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON# Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

S0CON*# Serial 0 port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 data buffer 99H xxxxxxxxB

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00H
S1DAT# Serial 1 data DAH 00H
SP Stack pointer 81H 07H
S1ADR# Serial 1 address DBH

Data pointer
(2 bytes)
Data pointer high
Data pointer low

DIRECT

ADDRESS

83H
82H

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB

AF AE AD AC AB AA A9 A8

BF BE BD BC BB BA B9 B8

87 86 85 84 83 82 81 80

97 96 95 94 93 92 91 90

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

9F 9E 9D 9C 9B 9A 99 98

D7 D6 D5 D4 D3 D2 D1 D0

 SLAVE ADDRESS 

GC 00H

RESET
VALUE

00H
00H

S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H

DF DE DD DC DB DA D9 D8

S1CON*# Serial 1 control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00000000B

8F 8E 8D 8C 8B 8A 89 88
TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer high 1 8DH 00H
TH0 Timer high 0 8CH 00H
TL1 Timer low 1 8BH 00H
TL0 Timer low 0 8AH 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

1999 Jul 23

6

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few

C

milliseconds) plus two machine cycles. At
power-on, the voltage on V
come up at the same time for a proper
start-up.

and RST must

CC

Idle Mode

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is
stopped and the instruction to invoke

87C652/87C654

power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.

I2C SERIAL
COMMUNICATION—SIO1

The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.

Note that in both the 8XC652/4 and the
8XC552 the I
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.

2

C pins are alternate functions

Table 2. External Pin Status During Idle and Power-Down Mode

MODE

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

Serial Control Register (S1CON) – See Table 3

S1CON (D8H)

CR2 ENS1 STA STO SI AA CR1 CR0

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

PROGRAM

MEMORY

ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Table 3. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

CR2 CR1 CR0

0 0 0 23 47 62.5 78 256
0 0 1 27 54 71 89
0 1 0 31.25 62.5 83.3 104
0 1 1 37 75 100 125
1 0 0 6.25 12.5 17 21 960
1 0 1 50 100 133
1 1 0 100 200
1 1 1 0.25 < 62.5

NOTE:

1. These frequencies exceed the upper limit of 100kHz of the I

6 MHZ 12 MHz 16 MHz 20 MHz f

1

0 to 255

0.5 < 62.5
0 to 254

2

OSC

DIVIDED BY

OSC

1

1
1

1
1

267

0.65 < 55.6
0 to 253

C-bus specification and cannot be used in an I2C-bus application.

1

166

1

334

0.81 < 69.4
0 to 253

96 × (256 – (reload value Timer 1))

(Reload value range: 0 – 254 in mode 2)

224
192
160

120

60

1999 Jul 23

7

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Storage temperature range –65 to +150 °C
Voltage on EA/VPP to V
Voltage on any other pin to V
Input, output current on any single pin ±5 mA
Power dissipation (based on package heat transfer

limitations, not device power consumption)

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices
from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All
voltages are with respect to V

DEVICE SPECIFICATIONS

TYPE MIN. MAX. MIN. MAX. (°C)

S87C652-4 and

S87C654-4

S87C652-5 and

S87C654-5

S87C654–7 4.5 5.5 3.5 20 0 to +70

SS

SUPPLY VOLTAGE

(V)

4.5 5.5 3.5 16 0 to +70

4.5 5.5 3.5 16 –40 to +85

C

1, 2, 3

SS

unless otherwise noted.

SS

FREQUENCY

(MHz)

RATING UNIT

–0.5 to + 13 V

–0.5 to + 6.5 V

1 W

TEMPERATURE

RANGE

87C652/87C654

1999 Jul 23

8

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

87C652/87C654

DC ELECTRICAL CHARACTERISTICS

VSS = 0 V

TEST LIMITS

SYMBOL PARAMETER PART TYPE CONDITIONS MIN. MAX. UNIT

V

IL

V

IL1

V

IL2

V

IH

V

IH1

V

IH2

V

OL

V

OL1

V

OL2

V

OH

V

OH1

I

IL

I

TL

I

L1

I

L2

I

CC

R

RST

C

IO

NOTES:

1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
logic 0 while an input voltage above 0.7V

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Under steady state (non-transient) conditions, I
I

OL

the test conditions, V

4. Capacitive loading on ports 0 and 2 may cause the V
address bits are stabilizing.

5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V

6. See Figures 9 through 11 for I

7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
V

IL

8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
V

IH

9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
EA

10.2V ≤ V

Input low voltage,
except EA, P1.6/SCL, P1.7/SDA

Input low voltage to EA 0 to +70°C

Input low voltage to P1.6/SCL, P1.7/SDA

1

Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA

Input high voltage, XTAL1, RST 0 to +70°C

Input high voltage, P1.6/SCL, P1.7/SDA

1

Output low voltage, ports 1, 2, 3,

0 to +70°C

–40 to +85°C

–40 to +85°C

0 to +70°C

–40 to +85°C

–40 to +85°C

IOL = 1.6mA

2, 3

–0.5
–0.5

–0.5
–0.5

–0.5 0.3V

0.2VCC+0.9

0.2VCC+1.0

0.7V

CC

0.7VCC+0.1

0.7V

CC

0.2VCC–0.1

0.2VCC–0.15VV

0.2VCC–0.3

0.2VCC–0.35VV

CC

VCC+0.5
VCC+0.5

VCC+0.5
VCC+0.5

6.0 V

0.45 V

except P1.6/SCL, P1.7/SDA
Output low voltage, port 0, ALE, PSEN IOL = 3.2mA

2, 3

0.45 V
Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA 0.4 V
Output high voltage, ports 1, 2, 3 0 to +70°C

–40 to +85°C

Output high voltage; port 0 in external bus mode,
ALE, PSEN, RST

4

Logical 0 input current, ports 1, 2, 3, 4,
except P1.6/SCL, P1.7/SDA

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

0 to +70°C

–40 to +85°C

0 to +70°C

–40 to +85°C

0 to +70°C

–40 to +85°C
Input leakage current, port 0 0.45V < V
Input leakage current, P1.6/SCL, P1.7/SDA 0V < V

IOH = –60µA
IOH = –25µA

IOH = –400µA
IOH = –150µA

2.4

0.75V

2.4

0.75V

CC

CC

VIN = 0.45V –50

See note 5 –650

< V

I

CC

< 6.0V

I

CC

< 6.0V

0V < V

–75

–750

±10 µA
±10 µA

Power supply current: See note 6

VCC=6.0V

9, 10
9, 10

7

8

25 mA

6 mA

0 to +70°C 50 µA

–40 to +85°C 135 µA

Active mode @ 16 MHz
Idle mode @ 16 MHz
Power down mode

Power down mode
Internal reset pull-down resistor 50 150 kΩ
Pin capacitance Freq.=1 MHz 10 pF

2

will be recognized as a logic 1.

CC

must be externally limited as follows: Maximum IOL = 10 mA per port pin; Maximum

= 26 mA total for Port 0; Maximum IOL = 15 mA total for Ports 1, 2, and 3; Maximum IOL = 71 mA total for all output pins. If IOL exceeds

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

OL

is approximately 2 V.

IN

test conditions.

CC

= VSS + 0.5 V; VIH = V

= V

–0.5 V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC; EA = RST = VSS; f

CC

–0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VCC; f

CC

OL

on ALE and PSEN to momentarily fall below the 0.9VCC specification when the

OH

= RST = VSS. See Figure 11.

≤ VCCmax.

PD

C specification, so an input voltage below 0.3VCC will be recognized as a

s of ALE and ports 1 and 3. The noise is due

OL

can exceed these conditions provided that no

OL

= tf = 10ns;

r

= tf = 10 ns; VIL = VSS + 0.5 V;

r

= 16 MHz. See Figure 10.

CLK

= 16 MHz. See Figure 9.

CLK

CC

;

V
V

V
V

V

V
V

V
V

µA
µA

µA
µA

µA

1999 Jul 23

9

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

AC ELECTRICAL CHARACTERISTICS

C

1, 2

87C652/87C654

16 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

CLCL

2 Oscillator frequency Speed Versions

3.5 16 MHz

87C654 –4, –5
2 ALE pulse width 85 2t
2 Address valid to ALE low 8 t
2 Address hold after ALE low 28 t
2 ALE low to valid instruction in 150 4t
2 ALE low to PSEN low 23 t
2 PSEN pulse width 143 3t
2 PSEN low to valid instruction in 83 3t

–40 ns

CLCL

–55 ns

CLCL

–35 ns

CLCL

–100 ns

CLCL

–40 ns

CLCL

–45 ns

CLCL

–105 ns

CLCL

2 Input instruction hold after PSEN 0 0 ns
2 Input instruction float after PSEN 38 t
2 Address to valid instruction in 208 5t

–25 ns

CLCL

–105 ns

CLCL

2 PSEN low to address float 10 10 ns

Data Memory

t

AVLL

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

DW

t

WHQX

t

RLAZ

t

WHLH

3, 4 Address valid to ALE low 28 t
3, 4 RD pulse width 275 6t
3, 4 WR pulse width 275 6t
3, 4 RD low to valid data in 148 5t

–35 ns

CLCL

–100 ns

CLCL

–100 ns

CLCL

–165 ns

CLCL

3, 4 Data hold after RD 0 0 ns
3, 4 Data float after RD 55 2t
3, 4 ALE low to valid data in 350 8t
3, 4 Address to valid data in 398 9t
3, 4 ALE low to RD or WR low 138 238 3t
3, 4 Address valid to WR low or RD low 120 4t
3, 4 Data valid to WR transition 3 t
3, 4 Data setup time before WR 288 7t
3, 4 Data hold after WR 13 t

–50 3t

CLCL

–130 ns

CLCL

–60 ns

CLCL

–150 ns

CLCL

–50 ns

CLCL

–70 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

+50 ns

CLCL

3, 4 RD low to address float 0 0 ns
3, 4 RD or WR high to ALE high 23 103 t

–40 t

CLCL

+40 ns

CLCL

Shift Register

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

5 Serial port clock cycle time
5 Output data setup to clock rising edge
5 Output data hold after clock rising edge
5 Input data hold after clock rising edge
5 Clock rising edge to input data valid

3

3

3

3

3

0.75 12t
492 10t

80 2t

CLCL

–133 ns

CLCL

–117 ns

CLCL

0 0 ns

492 10t

–133 ns

CLCL

External Clock

t

CHCX

t

CLCX

t

CLCH

t

CHCL

6 High time
6 Low time
6 Rise time
6 Fall time

3

3

3

3

20 20 t
20 20 t

20 20 ns
20 20 ns

CLCL –
CLCL –

t

t

LOW
HIGH

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. These values are characterized but not 100% production tested.

µs

ns
ns

1999 Jul 23

10

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

AC ELECTRICAL CHARACTERISTICS

C

1, 2

87C652/87C654

20 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

CLCL

2 Oscillator frequency: Speed Versions

3.5 20 MHz

87C654 –7, –8

2 ALE pulse width 60 2t
2 Address valid to ALE low 25 t
2 Address hold after ALE low 25 t
2 ALE low to valid instruction in 135 4t
2 ALE low to PSEN low 25 t
2 PSEN pulse width 105 3t
2 PSEN low to valid instruction in 90 3t

–40 ns

CLCL

–25 ns

CLCL

–25 ns

CLCL

–65 ns

CLCL

–25 ns

CLCL

–45 ns

CLCL

–60 ns

CLCL

2 Input instruction hold after PSEN 0 0 ns
2 Input instruction float after PSEN 25 t
2 Address to valid instruction in 170 5t

–25 ns

CLCL

–80 ns

CLCL

2 PSEN low to address float 10 10 ns

Data Memory

t

AVLL

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

DW

t

WHQX

t

RLAZ

t

WHLH

3, 4 Address valid to ALE low 25 t
3, 4 RD pulse width 200 6t
3, 4 WR pulse width 200 6t
3, 4 RD low to valid data in 160 5t

–25 ns

CLCL

–100 ns

CLCL

–100 ns

CLCL

–90 ns

CLCL

3, 4 Data hold after RD 0 0 ns
3, 4 Data float after RD 72 2t
3, 4 ALE low to valid data in 250 8t
3, 4 Address to valid data in 285 9t
3, 4 ALE low to RD or WR low 100 200 3t
3, 4 Address valid to WR low or RD low 125 4t
3, 4 Data valid to WR transition 20 t
3, 4 Data setup time before WR 220 7t
3, 4 Data hold after WR 25 t

–50 3t

CLCL

–75 ns

CLCL

–30 ns

CLCL

–130 ns

CLCL

–25 ns

CLCL

–28 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

+50 ns

CLCL

3, 4 RD low to address float 0 0 ns
3, 4 RD or WR high to ALE high 25 75 t

–25 t

CLCL

+25 ns

CLCL

Shift Register

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

5 Serial port clock cycle time
5 Output data setup to clock rising edge
5 Output data hold after clock rising edge
5 Input data hold after clock rising edge
5 Clock rising edge to input data valid

3

3

3

3

3

0.6 12t
367 10t

40 2t

CLCL

–133 ns

CLCL

–60 ns

CLCL

0 0 ns

367 10t

–133 ns

CLCL

External Clock

t

CHCX

t

CLCX

t

CLCH

t

CHCL

6 High time
6 Low time
6 Rise time
6 Fall time

3

3

3

3

17 17 t
17 17 t

20 20 ns
20 20 ns

CLCL –
CLCL –

t

t

LOW
HIGH

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. These values are characterized but not 100% production tested.

µs

ns
ns

1999 Jul 23

11

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

87C652/87C654

AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE

SYMBOL PARAMETER INPUT OUTPUT

SCL TIMING CHARACTERISTICS

tHD; STA ST ART condition hold time ≥ 14 t
t

LOW

t

HIGH

t

RC

t

FC

SCL LOW time ≥ 16 t
SCL HIGH time ≥ 14 t
SCL rise time ≤ 1 µs –
SCL fall time ≤ 0.3 µs < 0.3 µs

CLCL
CLCL
CLCL

SDA TIMING CHARACTERISTICS

tSU; DAT1 Data set-up time ≥ 250 ns > 20 t
tSU; DAT2 SDA set-up time (before rep. START cond.) ≥ 250 ns > 1 µs
tSU; DAT3 SDA set-up time (before STOP cond.) ≥ 250 ns > 8 t
tHD; DAT Data hold time ≥ 0 ns > 8 t
tSU; STA Repeated START set-up time ≥ 14 t
tSU; STO STOP condition set-up time ≥ 14 t
t

BUF

t

RD

t

FD

Bus free time ≥ 14 t
SDA rise time ≤ 1µs –
SDA fall time ≤ 0.3µs < 0.3 µs

CLCL
CLCL
CLCL

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 t
SCL = 400 pF.

4. t

= 1/f

CLCL

2

C-bus specification for bit-rates up to 100 kbit/s.

the I

= one oscillator clock period at pin XTAL1. For 62 ns < t

OSC

will be filtered out. Maximum capacitance on bus-lines SDA and

CLCL

< 285 ns (16 MHz) > f

CLCL

> 3.5 MHz) the SI01 interface meets

OSC

> 4.0 µs
> 4.7 µs
> 4.0 µs

CLCL

CLCL

CLCL

> 4.7 µs
> 4.0 µs
> 4.7 µs

1
1
1

2

3

– t

RD

1

– t

FC

1
1
1

2

3

TIMING SIO1 (I2C) INTERFACE

START or repeated START condition

SDA

(INPUT/OUTPUT)

t

FDtRC

SCL

(INPUT/OUTPUT)

t

HD;STA

t

LOW

t

RD

t

HIGH

t

FC

t

SU;DAT1

t

HD;DAT

repeated START condition

STOP condition

t

SU;DAT2

t

SU;STA

t

SU;STO

0.7 V

0.3 V
t

t

BUF

CC
CC

SU;DAT3

START condition

0.7 V

CC

0.3 V

CC

SU00107A

1999 Jul 23

12

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN

ALE

PSEN

PORT 0

C

t

LHLL

t

AVLL

A0–A7 A0–A7

Q – Output data
R–RD

signal
t – Time
V – V alid
W– WR

signal
X – No longer a valid logic level
Z – Float
Examples: t

= Time for address valid

AVLL

to ALE low.

t

= Time for ALE low

t

LLPL

t

LLAX

t

LLIV

t

PLIV

LLPL

t

PLPH

t

PLAZ

to PSEN

t

PXIX

INSTR IN

low.

t

PXIZ

87C652/87C654

ALE

PSEN

PORT 0

PORT 2

RD

PORT 2

t

AVLL

t

LLAX

A0–A7

FROM RI OR DPL

t

AVWL

t

AVIV

A0–A15 A8–A15

Figure 1. External Program Memory Read Cycle

t

WHLH

t

LLDV

t

LLWL

t

RLAZ

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

RLDV

t

RLRH

t

RHDZ

t

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

SU00006

1999 Jul 23

SU00177

Figure 2. External Data Memory Read Cycle

13

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

t

A0–A7

LLAX

t

AVWL

C

t

LLWL

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

8K/16K, 256 OTP, I

ALE

PSEN

WR

t

AVLL

PORT 0

PORT 2

FROM RI OR DPL

87C652/87C654

t

WHLH

t

WLWH

t

t

QVWX

t

DW

DATA OUT A0–A7 FROM PCL INSTR IN

WHQX

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

SU00213

Figure 3. External Data Memory Write Cycle

012345678

t

XLXL

t

t

QVXH

t

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHQX

1230 4567

t

XHDX

SET TI

SET RI

SU00027

Figure 4. Shift Register Mode Timing

VCC–0.5

0.45V

0.7V

CC

0.2VCC–0.1

t

CHCL

t

CLCX

t

CLCL

t

CHCX

t

CLCH

SU00009

Figure 5. External Clock Drive

1999 Jul 23

14

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

VCC–0.5

0.45V

NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

V

+0.1V

LOAD

LOAD

V

LOAD

–0.1V

V

NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V

0.2V

+0.9

CC

–0.1

0.2V

CC

Figure 6. AC Testing Input/Output

TIMING

REFERENCE

POINTS

level occurs. IOH/IOL ≥ ±20mA.

OH/VOL

Figure 7. Float Waveform

V

V

OH

OL

87C652/87C654

SU00010

–0.1V

+0.1V

SU00011

CLOCK SIGNAL

NOTE:

* Ports 1.6 and 1.7 should be connected to V

exceed the I

specification.

OL1

V

CC

I

CC

V

CC

EA
P1.6
P1.7

V

CC

P0

*
*

SU00272

(NC)

V

CC

RST

87C652/4

XTAL2
XTAL1

V

SS

Figure 8. ICC Test Condition, Active Mode

All other pins are disconnected

through resistors of sufficiently high value such that the sink current into these pins does not

CC

1999 Jul 23

15

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

(NC)

CLOCK SIGNAL

VCC–0.5

0.45V

Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes

V

CC

I

CC

V

RST

EA

CC

V

CC

P0

87C652/4

XTAL2
XTAL1

V

SS

P1.6
P1.7

SU00273

Figure 9. ICC Test Condition, Idle Mode

All other pins are disconnected

0.7V

CC

0.2VCC–0.1

t

CHCL

t

CLCH

= t

t

CHCL

CLCX

= 10 ns

t

CLCL

t

CHCX

t

CLCH

87C652/87C654

*
*

SU00009

NOTE:

* Ports 1.6 and 1.7 should be connected to V

exceed the I

specification.

OL1

V

CC

I

CC

V

RST
EA

CC

V

CC

P0

87C652/4

(NC)

XTAL2

XTAL1

V

SS

P1.6
P1.7

*
*

SU00274

Figure 11. ICC Test Condition, Power Down Mode

All other pins are disconnected. V

through resistors of sufficiently high value such that the sink current into these pins does not

CC

= 2 V to 5.5 V

CC

1999 Jul 23

16

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

EPROM CHARACTERISTICS

The 87C652/87C654 is programmed by using
a modified Quick-Pulse Programming
algorithm. It differs from older methods in the
value used for V
voltage) and in the width and number of the
ALE/PROG

The 87C652/87C654 contains two signature
bytes that can be read and used by an
EPROM programming system to identify the
device. The signature bytes identify the device
as an 87C652/87C654 manufactured by
Philips Components.

Table 4 shows the logic levels for reading the
signature byte, and for programming the
program memory , the encryption table, and
the lock bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 12 and 13. Figure 14 shows
the circuit configuration for normal program
memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse
programming is shown in Figure 12. Note
that the 87C652/87C654 is running with a
4 to 6 MHz oscillator. The reason the
oscillator needs to be running is that the
device is executing internal address and
program data transfers.

The address of the EPROM location to be
programmed is applied to ports 1 and 2, as

(programming supply

PP

pulses.

C

shown in Figure 12. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN
specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The
ALE/PROG
in Figure 13.

To program the encryption table, repeat the 25
pulse programming sequence for addresses 0
through 1FH, using the ‘Pgm Encryption Table’
levels. Do not forget that after the encryption
table is programmed, verification cycles will
produce only encrypted data.

To program the lock bits, repeat the 25 pulse
programming sequence using the ‘Pgm Lock
Bit’ levels. After one lock bit is programmed,
further programming of the code memory and
encryption table is disabled. However, the
other lock bit can still be programmed.

Note that the EA
to go above the maximum specified V
for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The V
should be well regulated and free of glitches
and overshoot.

Program Verification

If lock bit 2 has not been programmed, the
on-chip program memory can be read out for

and pins of ports 2 and 3

is pulsed low 25 times as shown

/VPP pin must not be allowed

level

PP

source

PP

87C652/87C654

program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 14. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 4.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.

If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.

Reading the Signature Bytes

The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by

Philips

(031H) = 99H

Program/Verify Algorithms

Any algorithm in agreement with the
conditions listed in Table 4, and which
satisfies the timing specifications, is suitable.

Table 4. EPROM Programming Modes

MODE RST PSEN ALE/PROG EA/V

Read signature 1 0 1 1 0 0 0 0
Program code data 1 0 0* V
Verify code data 1 0 1 1 0 0 1 1
Pgm encryption table 1 0 0* V
Pgm lock bit 1 1 0 0* V
Pgm lock bit 2 1 0 0* V

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
= 12.75 V ±0.25 V .

2. V

PP

3. V

= 5 V±10% during programming and verification.

CC

* ALE/PROG

minimum of 10 µs.

Trademark phrase of Intel Corporation.

receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a

PP

PP

PP
PP
PP

P2.7 P2.6 P3.7 P3.6

1 0 1 1

1 0 1 0
1 1 1 1
1 1 0 0

1999 Jul 23

17

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

4–6MHz

C

A0–A7

1
1
1

V

CC

/V

EA

PP

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

P0

P1

RST
P3.6

P3.7
XTAL2

XTAL1

V

SS

87C652/4

Figure 12. Programming Configuration

87C652/87C654

+5V

PGM DATA

+12.75V
25 100µs PULSES TO GROUND
0
1

0

A8–A13

SU00275

ALE/PROG:

ALE/PROG:

1
0

4–6MHz

25 PULSES

1
0

100µs+1010µs MIN

SU00018

Figure 13. PROG Waveform

+5V

V

CC

EA/V

PP

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

P0

PGM DATA

1
1
0
0 ENABLE

0

A8–A13

A0–A7

P1

1
1
1

RST
P3.6

P3.7
XTAL2

XTAL1

87C652/4

1999 Jul 23

V

SS

Figure 14. Program Verification

18

SU00276

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

= 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 15)

amb

SYMBOL

V

PP

I

PP

1/t

CLCL

t

AVGL

t

GHAX

t

DVGL

t

GHDX

t

EHSH

t

SHGL

t

GHSL

t

GLGH

t

AVQV

t

ELQZ

t

EHQZ

t

GHGL

Programming supply voltage 12.5 13.0 V
Programming supply current 50 mA
Oscillator frequency 4 6 MHz
Address setup to PROG low 48t
Address hold after PROG 48t
Data setup to PROG low 48t
Data hold after PROG 48t
P2.7 (ENABLE) high to V
VPP setup to PROG low 10 µs
VPP hold after PROG 10 µs
PROG width 90 110 µs
Address to data valid 48t
ENABLE low to data valid 48t
Data float after ENABLE 0 48t
PROG high to PROG low 10 µs

C

PARAMETER MIN MAX UNIT

PP

48t

87C652/87C654

CLCL
CLCL
CLCL
CLCL
CLCL

CLCL
CLCL
CLCL

PROGRAMMING* VERIFICATION*

P1.0–P1.7
P2.0–P2.3

PORT 0

t

DVGL

t

ALE/PROG

EA/V

PP

P2.7
ENABLE

* FOR PROGRAMMING VERIFICATION SEE FIGURE 12.

FOR VERIFICATION CONDITIONS SEE FIGURE 14.

AVGL

t

GLGH

t

SHGL

t

EHSH

ADDRESS ADDRESS

t

AVQV

DATA IN DATA OUT

t

GHDX

t

GHAX

t

GHGL

t

GHSL

LOGIC 1 LOGIC 1

LOGIC 0

t

ELQV

Figure 15. EPROM Programming and Verification

t

EHQZ

SU00270

1999 Jul 23

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.

19

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

C

87C652/87C654

1999 Jul 23

20

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

C

87C652/87C654

1999 Jul 23

21

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

C

87C652/87C654

1999 Jul 23

22

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

C

87C652/87C654

NOTES

1999 Jul 23

23

Philips Semiconductors Product specification

80C51 8-bit microcontroller

2

8K/16K, 256 OTP, I

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

C

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

87C652/87C654

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1999

All rights reserved. Printed in U.S.A.

Date of release: 07-99

Document order number: 9397-750-06607

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1999 Jul 23

24