Datasheets 74ACT08 Datasheet

74AC08, 74ACT08 — Quad 2-Input AND Gate

January 2008

74AC08, 74ACT08 Quad 2-Input AND Gate

Features

■

I

reduced by 50% on 74AC only

CC

Outputs source/sink 24mA

■

General Description

The AC08/ACT08 contains four, 2-input AND gates.

Ordering Information

Order

Number

74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

74AC08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

74ACT08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Package

Number Package Description

Wide

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names Description

A

, B

n

O

n

Inputs Outputs

=

∆

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Rating

V

CC

I

IK

V

I

OK

V

I

O

or I

I

CC

T

STG

T

Supply Voltage –0.5V to +7.0V DC Input Diode Current

V

–0.5V –20mA

I

V

+ 0.5 +20mA

I

CC

DC Input Voltage –0.5V to V

I

DC Output Diode Current

V

–0.5V –20mA

O

V

O

DC Output Voltage –0.5V to V

O

+ 0.5V +20mA

CC

DC Output Source or Sink Current ±50mA

GND

DC V

or Ground Current per Output Pin ±50mA

CC

Storage Temperature –65°C to +150°C Junction Temperature 140°C

J

CC

+ 0.5V

74AC08, 74ACT08 — Quad 2-Input AND Gate

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

V

CC

V

O

T

A

V

/

∆

V

/

Supply Voltage

AC 2.0V to 6.0V ACT 4.5V to 5.5V

Input Voltage 0V to V

I

Output Voltage 0V to V Operating Temperature –40°C to +85°C

t Minimum Input Edge Rate, AC Devices:

from 30% to 70% of V

V

IN

t Minimum Input Edge Rate, ACT Devices:

from 0.8V to 2.0V, V

V

IN

,

V

CC

@ 4.5V, 5.5V

CC

@ 3.3V, 4.5V, 5.5V

125mV/ns

CC

DC Electrical Characteristics for AC

V

Symbol Parameter

V

I

IN

I

OLD

I

OHD

I

CC

Minimum HIGH Level

IH

Input Voltage

Maximum LOW Level

IL

Input Voltage

Minimum HIGH Level

OH

Output Voltage

Maximum LOW Level

OL

Output Voltage

(3)

Maximum Input Leakage Current

Minimum Dynamic Output Current

(3)

Maximum Quiescent Supply Current

(2)

CC

(V) Conditions

3.0 V

4.5 2.25 3.15 3.15

5.5 2.75 3.85 3.85

3.0 V

4.5 2.25 1.35 1.35

5.5 2.75 1.65 1.65

3.0 I

4.5 4.49 4.4 4.4

5.5 5.49 5.4 5.4

3.0 V

4.5 V

5.5 V

3.0 I

4.5 0.001 0.1 0.1

5.5 0.001 0.1 0.1

3.0 V

4.5 V

5.5 V

5.5 VIN = V

OUT

V

OUT

V

OUT

I

OH

I

OH

I

OH

OUT

I

OL

I

OL

I

OL

OLD

OHD

– 0.1V

CC

– 0.1V

CC

IN

V

I

=

T

+25°C T

A

–40°C to +85°C

A

UnitsTyp. Guaranteed Limits

0.1V or

–50µA 2.99 2.9 2.9 V

V

or V

IL

,

IH

–12mA V

or V

IL

,

IH

–24mA V

or V

(1)

,

IH

IL

–24mA

50µA 0.002 0.1 0.1 V

V

or V

IL

,

IH

12mA V

or V

IL

,

IH

24mA V

or V

IL

24mA

CC

,

IH

(1)

, GND ±0.1 ±1.0 µA

1.65V Max. 75 mA

= 3.85V Min. –75 mA

or GND 2.0 20.0 µA

CC

1.5 2.1 2.1 V

1.5 0.9 0.9 V

2.56 2.46

3.86 3.76

4.86 4.76

0.36 0.44

=

74AC08, 74ACT08 — Quad 2-Input AND Gate

Notes:

1. All outputs loaded; thresholds on input associated with output under test.

2. Maximum test duration 2.0ms, one output loaded at a time.

3. I

and I

IN

@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V

CC

.

DC Electrical Characteristics for ACT

VCC

Symbol Parameter

V

I

CCT

I

OLD

I

OHD

I

CC

Minimum HIGH Level

IH

Input Voltage

Maximum LOW Level

IL

Input Voltage

Minimum HIGH Level

OH

Output Voltage

Maximum LOW Level

OL

Output Voltage

Maximum Input

IN

Leakage Current Maximum ICC/Input 5.5 VI = VCC – 2.1V 0.6 1.5 mA Minimum Dynamic

Output Current

(5)

Maximum Quiescent Supply Current

(V) Conditions

4.5 V

5.5 1.5 2.0 2.0

4.5 V

5.5 1.5 0.8 0.8

4.5 I

5.5 5.49 5.4 5.4

4.5 V

5.5 V

4.5 I

5.5 0.001 0.1 0.1

4.5 V

5.5 V

5.5 VI = VCC, GND ±0.1 ±1.0 µA

5.5 V

5.5 VIN = VCC or GND 4.0 40.0 µA

= 0.1V or

OUT

V

– 0.1V

CC

= 0.1V or

OUT

V

– 0.1V

CC

= –50µA 4.49 4.4 4.4 V

OUT

= VIL or VIH,

IN

= –24mA

I

OH

= VIL or VIH,

IN

= –24mA

I

OH

= 50µA 0.001 0.1 0.1 V

OUT

= VIL or VIH,

IN

= 24mA

I

OL

= VIL or VIH,

IN

= 24mA

I

OL

= 1.65V Max. 75 mA

OLD

= 3.85V Min. –75 mA

OHD

(4)

T

= +25°C TA = –40°C to +85°C

A

UnitsTyp. Guaranteed Limits

1.5 2.0 2.0 V

1.5 0.8 0.8 V

3.86 3.76

4.86 4.76

0.36 0.44

74AC08, 74ACT08 — Quad 2-Input AND Gate

Notes:

4. All outputs loaded; thresholds on input associated with output under test.

5. Maximum test duration 2.0ms, one output loaded at a time.

AC Electrical Characteristics for AC

74AC08, 74ACT08 — Quad 2-Input AND Gate

TA = +25°C,

CL = 50pF

Symbol Parameter V

t

PLH

t

PHL

Note:

6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.

Propagation Delay 3.3 1.5 7.5 9.5 1.0 10.0 ns

Propagation Delay 3.3 1.5 7.0 8.5 1.0 9.0 ns

(6)

(V)

CC

5.0 1.5 5.5 7.5 1.0 8.5

5.0 1.5 5.5 7.0 1.0 7.5

AC Electrical Characteristics for ACT

TA = +25°C,

CL = 50pF

Symbol Parameter V

t

PLH

t

PHL

Note:

7. Voltage range 5.0 is 5.0V ± 0.5V.

Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns

CC

(V)

(7)

TA = –40°C to +85°C,

CL = 50pF

UnitsMin. Typ. Max. Min. Max.

TA = –40°C to +85°C,

CL = 50pF

UnitsMin. Typ. Max. Min. Max.

Capacitance

Symbol Parameter Conditions Typ. Units

C

IN

C

PD

Input Capacitance VCC = OPEN 4.5 pF Power Dissipation Capacitance VCC = 5.0V 20.0 pF

Physical Dimensions

8.75

8.50

7.62

74AC08, 74ACT08 — Quad 2-Input AND Gate

A

0.65

6.00

PIN ONE

INDICATOR

1.75 MAX

1.50

1.25

14

1

1.27

(0.33)

8

7

0.51

0.35

0.25

B

4.00

3.80

1.70 1.27

LAND PATTERN RECOMMENDATION

M

BC A

0.25

0.10

0.10CC

NOTES: UNLESS OTHERWISE SPECIFIED

5.60

SEE DETAIL A

0.25

0.19

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS. D) LANDPATTERN STANDARD:

SOIC127P600X145-14M E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13

R0.10

8° 0°

0.90

0.50

0.25

X45°

GAGE PLANE

SEATING PLANE

0.36

(1.04)

DETAIL A

SCALE: 20:1

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

74AC08, 74ACT08 — Quad 2-Input AND Gate

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

M

74AC08, 74ACT08 — Quad 2-Input AND Gate

0.43 TYP

0.65

1.65

0.45

R0.09 min

6.10

12.00°

TOP & BOTTO

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

1.00

R0.09min

B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

E. LANDPATTERN STANDARD: SOP65P640X110-14M

F. DRAWING FILE NAME: MTC14REV6

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

19.56

18.80

14 8

74AC08, 74ACT08 — Quad 2-Input AND Gate

6.60

6.09

(1.74)

1

1.77

7

1.14

3.56

3.30

0.38 MIN

3.81

3.17

0.58

0.35

2.54

NOTES: UNLESS OTHERWISE SPECIFIED

THIS PACKAGE CONFORMS TO

A)

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS ARE EXCLUSIVE OF BURRS,

C)

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER

ASME Y14.5-1994

E) DRAWING FILE NAME: MKT-N14AREV7

5.33 MAX

8.12

7.62

0.35

0.20

8.82

Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

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74AC08, 74ACT08 — Quad 2-Input AND Gate

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Datasheet Identification Product Status Definition

Advance Information Form

ative or In Design

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be

Preliminary

First Production

published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

This datasheet contains final specifications. Fairchild Semiconductor

No Identification Needed Full Production

reserves the right to make changes at any time without notice to improve the design.

This datasheet contains specifications on a product that has been

Obsolete Not In Production

discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.

Rev. I32

Datasheets 74ACT08 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual