Datasheet ZR36505 Datasheet (ZORAN)

USBvisionTM II Data Decoder

ZR36505

VBI Data and Remote Control Interface for ZR6504

Data Sheet

Revision 1.00 November 1999.

Zoran reserves the right to make changes without further notice to any product herein. Zoran makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Zoran assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. Zoran products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the Zoran product could create a situation
where personal injur y or death may occur.

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Table of Contents:

1. SERIAL CONTROL

2. VBI DATA QUALIFIER

2.1 VBI Input Interface................................................................................................................................ 12

2.2 VBI Lines Qualifier................................ .................................................................................................13

2.3 VBI and IRD (Remote Control) Data Format ...................................................................................... 17

3. Bulk Interface

.......................................................................................................................................... 21

4. Programmable I/O Pins

5. Soft Reset operation

6. Mechanical Specification

............................................................................................................................7

.................................................................................................................. 12

....................................................................................................................... 25

............................................................................................................................. 26

.................................................................................................................... 27

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

ZR36505 -

The ZR36505 is a complimentary chip for the
video decoders, it adds a VBI (Vertical Blank Interval) data pipe to the system, which utilizes the general
purpose Bulk channel of the NT1004. The VBI is used by TV broadcast providers to send digital data
hidden in the analog video signal. One or more video lines, taken from lines 1-21 of each video field are
used for carrying this information - each line providing about 9,600 bits/sec data rate.
The ZR36505 provides the application S/W with access to data such as Teletext, Close-Caption,
Intercast, IR receiver samples, etc. It uses a 1KByte SRAM buffer to grabe the processed data from the
video decoder during the Blank Interval time slot, and sends this data to the USB through the

ZR36504

interface, the input pin IO_1 is sampled at 4Ksamp/sec rate, and the sampled bits are moved to host
computer via the (NT1004) for S/W process.

Features

•

Enables Teletext and Close -Caption

•

Supports WST625, WST525, CC625, CC525, US NABTS, MOJI (Japanese), and JFS formats

•

Provides Remote Control interface with IR receiver (sampled at 4K samp./sec.)

•

Low Cost, Low Power, 3.3v operated

•

24-pin SOIC package

VBI (Teletext) pipe and Remote Control interface for USB TV applications

ZR36504

Bulk pipe during the time left prior to beginning of next Blak Interval. For the remote Control

in USB TV applications. Combined with certain

November-99 Page 3 of 3

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Product Description

Refer to Fig.1 for an internal Block Diagram of the ZR36505.

ZR36505 CHIP

from

ZR36504

Serial

Control

pins

from

Video

Decoder.

27MHz

48MHz

from

ZR36504

IIC

Serial Interface

VBI DATA

QUALIFIER

Control Registers

Status Registers

Remote Control

IR Binary Sampler

(4KHz)

1KB
Buff

INTERFAC

BULK

E

Prog.

I/O

General
purpose

I/O pins

(Remote

Control,

IRD,
etc.)

to
ZR36504
Bulk pins

(0-2Mbps)

Fig.1 ZR36505 Block Diagram

The IIC block uses the LRNACK mode of the ZR36504 serial control bus to provide
access to its internal registers. The address range for output registers and input registers is
0x00-0x07 each.

The internal Input and Output Registers are used by the Host (PC S/W via ZR36504) to
control the parameters of the ZR36505 blocks and to read their status. There are two
general I/O pins to be used by S/W for specific designs.

The VBI DATA QUALIFIER block can be programmed to restrict VBI data capture to
any specified range of lines within the video field. Also, a specific data type can be defined,
to filter out all other types of VBI data.

The 1KByte Buffer is used for capturing all VBI data from every coming video field (after
qualification), and sending it via the Bulk Interface. This is done for one field at a time, and
Write/Read cannot be done simultaneously.

The BULK INTERFACE block is designed to match the ZR36504 specification. It can
coexist with an audio Codec source to share the same clock and data pins of the NT1004.

Finally, The ZR36505 uses 2 clock sources: 27MHz for VBI data, and 48MHz (from
NT1004) for the other blocks. The ZR36505 does not require a crystal of its own.

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

P in Assignments (Top View)

TM

24
23
22
21
20
19
18
17
16
15
14
13

VSYNC_IN

HSYNC_IN

YIN0
YIN1
YIN2
YIN3
YIN4
YIN5
YIN6
YIN7

CLK27

GND 12

1
2

3
4
5
6
7
8

9

10
11

NT1005

USBTeletext

Table 1 - PIN DESCRIPTIONS

PIN NUMBER SIGNAL I/O

24 VDD
12, 14 GND
1 VSYNC_IN I
2 HSYNC_IN I

VDD
IICCK
IICDT

IO1/IRD_IN
IO2

BCLK

FS_L
BLK_FULL
BLK_EN

DAT_OUT

GND
CLK48

DESCRIPTION

Digital 3.3V power supply

Digital ground connection

Video Vertical-Sync input signal from Video Decoder

Video Vertical-Sync input signal from Video Decoder

3-10 YIN0-YIN7 I
11 CLK27 I

VBI data-bus from Video Decoder. Usually used also for delivering
the digital video samples.
VBI clock from Video Decoder. Used to sample the VBI data in
it s positive edge. This clock is used for capturing and storing the
VBI data.

13 CLK48 I
15 DAT_OUT O

This is the ZR36505 Global clock, which comes from the
NT1004.
VBI Data Output pin, goes to DAT_IN pin of the
ZR36504(which is used for both Audio CODEC T x chan and
Bulk Data in This pin is Open Drain, and is set to high -z upon
Power-On or Soft Reset. It requires an external pull-up resistor.

16 BLK_EN O

Bulk Data Enable output. When set to '1', Bulk output data at
DAT_OUT pin is sampled into the ZR36504by falling edge of
BCLK .
This pin is set to Hi-Z upon Power -On or Soft Reset.

17 BLK_FULL I
18 FS_L I

"Bulk-Fifo full" indication signal from NT1004. This signal is
normally '0', and is set to '1' when the ZR36504Bulk -Fifo is full.
Audio Codec Frame-Sync pulse for Left channel., which comes
from the NT1004. The ZR36505 uses this signal to trigger the
beginning of its VBI Bulk data output immediately after the 16th

November-99 Page 5 of 5

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

bit of audio Left.

19 BCLK I

Table 1 - PIN DESCRIPTIONS

(continued)

PIN NUMBER SIGNAL I/O

20-21 IO-1/IRD_IN

I/O

IO-2

22 IICDT I/O

23 IICCK I

Table 2 - ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

(Voltages Referenced to GND)

Bulk -data clock (ZR36504uses this clock for both Audio CODEC
and Bulk Data). This clock must be set to 2.024MHz for proper
operation with ZR36505.

DESCRIPTION

General Programmable I/O pins. Each of these 2 pins has a 5­volt Tolerant Open Drain output, and it is supposed to be
connected to an external pull-up resistor. The host uses these
pins as programmable output ports by writing '0' or '1'. By writing
'1' and read back, the host can use these pins as input ports - as
this allows any external source to force the pull-up resistor.
These outputs are set to high -z upon Power-On or Soft Reset.
The pin IO-1 is also used as the input for IRD data. This pin is
internally sampled at 4KHz sampling rate.
This pin is used for sending and receiving serial control data
between the ZR36505 (slave) and ZR36504(master). It operates
in the LRNACK mode of operation (refer to the ZR36504data
sheet). This pin is Open Drain, and is set to high-z upon Power ­On or Soft Reset.
This pin is used as the sampling clock for sending and receiving
serial control data between the ZR36505 (slave) and
ZR36504(master). It operates in the LRNACK mode of
operation (refer to the ZR36504data sheet).

DC Supply Voltage Vdd - GND -0.5 to 4.6 V
Voltage, any pin to GND V -0.5 to Vdd+0.5 V
DC Current Drain per Pin (Excluding Vdd, GND) I ±10 mA
Operating Temperature Range TA 0 to +70
Storage Temperature Range T

-65 to +150

stg

o

C

o

C

Table 3 - ELECTRICAL CHARACTERISTICS

(Vdd=3.3V, TA = 0 to 70o C)

Characteristic Symbol Min Typ Max Unit

DC Supply Voltage (Vdd to GND) Vdd 3.0 3.3 3.6 V
DC Supply Current (@ V dd=3.3V) ICC - 12 18 mA
High Level Input Voltage

RESIN)

Low Level Input Voltage

RESIN)

Input Current VI = Vdd+0.3 or GND Iin -10 +1 +10

(other than XIN, CAPTRN, and

(other than XIN, CAPTRN, and

VIH 2.0 - Vdd+0.3* V

VIL -0.3 - 0.8 V

µ

A

Input Capacitance Cin - 2.5 7.0 pF

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

3-State Output Leakage Current V
Output Capacitance C
High Level Output Voltage (@ Iout = -4mA) VOH 2.4 - Vdd V
Low Level Output Voltage (@ Iout = 4mA) VOL 0 - 0.4 V

= Vdd+0.3 or GND IOZ -10 +1 +10

O

- 2.0 7.0 pF

out

µ

1. SERIAL CONTROL

The ZR36505 uses a Serial Control Interface to access its internal registers.

Table 4 - ZR36505 Registers List:

Reg.

Address

0 LINE_LEN_L d7-d0: LINE_LEN[7..0] 00H
1 LINE_LEN_H d2-d0: LINE_LEN[10..8]

2 LINE_WIN_L d7-d0: WIN_OFFSET[7..0] 00H
3 LINE_WIN_H d7-d3: WIN_LEN[4..0]

4 VBI_REG d7: EN_TYPE_QUALIFIER '1': enable '0': disable

5 BLK_OPER_

6 IO_REG d0: IO_1 Read/Write level of ZR36505 pin IO-1

7 SOFT_RESET d0: SOFT_RESET '1' : Perform RESET

Reg. Name Function Default

d7-d3: reserved

d2-d1: reserved
d0: WIN_OFFSET[8]

d6: EN_WIN_QUALIFIER '1': enable '0': disable
d5: EN_RAW_SAMP LES '1': enable '0': disable
d4: EN_VBI_QUALIFIER '1': enable '0': disable
d3-d0: DATA_TYPE_QUALIFIER[3..0]
d3: BCLK_RATE '1': 2048KHz '0': 1544KHz

MODE

d2: AUDIO_DAT '1': exists '0': does not exist
d1: AUDIO_RATE '1': 16KS/s '0': 8KS/s
d0: AUDIO_STEREO '1': stereo '0': mono
d7: BLK_IO_EN '1': En bulk output pins. '0': Disable.
d6-d4: reserved

d1: IO_2 Read/Write level of ZR36505 pin IO-2
d7-d2: reserved

This reg is always read 0x00 (even after writing 0x01).
Writing 0x01 to this register will result in a general reset
operation to the ZR36505, leaving all registers in their
default values.

The serial bus consists of a clock signal and a data signal, which relate to the ZR36505 as a
bus slave (where the ZR36504 is used as the bus master).
The ZR36505 device address is 0xEE for a Write operation, and 0xEF for a Read
operation.

Value

00H

00H

00H

00H

00H

00H

A

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

The diagram in the following page specifies general Read and Write transactions. In both
transactions the register address is auto-incremented, which requires from the host computer
to define the address of the first register only. The data bytes are then sent or received one
after the other from the first register to the last one (any number of registers is possible). A
Read transaction requires a Write sequence of 0 data bytes, in order to define the first
address register to be read.

November-99 Page 8 of 8

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Write transaction

S 0xEE

Register

AKAK AK DATA(n) AK DATA(n+1) AK DATA(n+j) AK P

Addrss n

Optional

Read transaction

S 0xEE

Register

AKAK AK P

Addrss n

Define Register Address n

S

= START ConditionP= STOP ConditionAK= Host ACK

DATA

= Host Data

It is recommended to set the ZR36504(master) chip to its IIC LRNACK mode of
operation to communicate with the ZR36505.

The following waveforms and timing diagrams specify the IIC serial interface bus in the
signal level:

S 0xEF AKAK DATA(n) AK DATA(n+1) AK DATA(n+j) NAK

Optional

NAK

= Host NACK

DATA

= NT1005 DataAK= NT1005 ACK

P

November-99 Page 9 of 9

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Start is defined when the IICDT turns from '1' to '0' while the IICCK is '1'. Stop is defined when

IICCK

Data is sampled on the down going edge of IICCK

IICDT

D7 D6 D5 D4 D3 D2 D1 D0xAck

StopStart

IICCK

IICDT

NOTE:

the IICDT turns from '0' to '1' while the IICCK is '1'. The Address byte is written like any other byte.

Write ADDRESS R/W Byte 1 R/W Byte N

IICCK IICCK

Stop Stop

IICDT IICDT

Ack

End of Write sequence End of Read sequence

Nack

Start/Stop Timings

tSU:STA tHD:STA tSU:STO

IICCK

IICDT

Data Timings

tHIGH

tLOW

IICCK

IICDT OUT

IICDT IN

tHD:DI

Data Valid

tHD:DO

Dn Dn+1

tSU:DI

Data Valid

tSU:DO

November-99 Page 10 of 10

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Table 5 - SERIAL CONTROL TIMINGS

Symbol Parameter Min Max Unit

t

SU:STA

tHD:STA
t

SU:STO

t

HIGH

t

LOW

tSU:DO
t

HD:DO

t

SU:DI

t

HD:DI

Fiicck

START condition setup time 5300 - ns
START condition hold time 5300 - ns
STOP condition setup time 5300 - ns
Clock high time 5300 - ns
Clock low time 5300 - ns
Data output setup time 2500 2670 ns
Data output hold time 2500 2670 ns
Data input setup time 20 - ns
Data input hold time 0 - ns
Frequency of IICCK clock signal 0 100 KHz

November-99 Page 11 of 11

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

2. VBI DATA QUALIFIER

2.1 VBI Input Interface

The ZR36505 is designed to connect to the 8-bit VBI output bus of the Video Decoder
(Philips SAA7113 in its CCIR-656 mode of operation). This bus is sampled by the rising
edge of CLK27 (27MHz clock, which is also provided by the Video Decoder chip), and
provides the processed data bytes in the Blank lines. The same bus contains the Y/U/V
video data on the valid video lines, which go directly to the NT1004.

The VBI input interface consists of the following signals:

Y_IN[7..0] ( Inputs )
This is the 8-bit VBI bus (contains also the Y/U/V samples in non-blank lines).

VSYNC_IN ( Input )
This is the negative Vertical Synchronization pulse, which indicates the start of a new video
field (Interlace mode).

HSYNC_IN ( Input )
This is the negative Horizontal Synchronization pulse, which indicates the start of a new
video line.

CLK27 ( Input )
This signal is the video pixel clock. It is used by the ZR 36505 to sample all the other inputs
in the digital video interface. It is also used by all state machines and logic to capture the
VBI data into the 1Kbyte on-chip memory.

The timing of the VBI input bus, as expected by the ZR36505 is specified in the following
timing diagram:

November-99 Page 12 of 12

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

VSYNC_IN

HSYNC_IN

VSYNC_IN

HSYNC_IN

CLK27

Y_IN[7..0]

CLK_27

First Line

in a field

Detail

B0 B1 B2xx xxB3

Last Line

in a field

about 64us

90%

10%

tSU > 15ns tH > 10ns

VSYNC_IN,

HSYNC_IN,

Y_IN[7..0]

90%

VALID

10%

90%

10%

2.2 VBI Lines Qualifier

The VBI lines are defined in the range 2-21 of the 1st and 2nd fields, but in most TV
stations not all the VBI lines are used for digital data.

The ZR36505 provides a way of restricting the search range, and filtering out the undesired
data. This allows the ZR36505 to produce smaller buffers of data to be delivered via the
USB Bulk channel, which do not interfere with the isochroneous video and audio channels.
To do this, the ZR36505 uses the following qualifiers:

November-99 Page 13 of 13

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Line Window Qualifier (Regs. 0-3):

LINE_LEN_L (Reg. 0)

D7 D6 D5 D4 D3 D2 D1 D0

LINE_LEN[7..0]

LINE_LEN_H (Reg. 1)

D7 D6 D5 D4 D3 D2 D1 D0

resrved resrved resrved resrved resrved LINE_LEN[10..8]

LINE_WIN_L (Reg. 2)

D7 D6 D5 D4 D3 D2 D1 D0

WIN_OFFSET[7..0]

LINE_WIN_H (Reg. 3)

D7 D6 D5 D4 D3 D2 D1 D0

WIN_LEN[4..0] resrved resrved WIN_OFFSET[8]

WIN_OFFSET[8..0]

1
2
3
4

LINE_LEN[10..0]

WIN_LEN[4..0]

21
23

24

last
line

The dark window represents the Line Window Qualifier. LINE_LEN[10..0] is counted
from the up-going edge of the HSYNC_IN pulse and relates to CLK27 cycles, and
WIN_OFFSET[8..0] is counted from the up-going edge of the VSYNC_IN pulse and
relates to HSYNC_IN pulses. Note that bit d6 of VBI_REG (reg.4) should be enabled:

VBI_REG (Reg. 4)

November-99 Page 14 of 14

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

D7 D6 D5 D4 D3 D2 D1 D0

EN_WIN_QUALIFIER

November-99 Page 15 of 15

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

VBI Window Qualifier:

To enable VBI Window Qualifier, bit d4 of VBI_REG (reg.4) should be set to '1'. This will
restrict data capture to those lines that are reported "VBI lines" by the video decoder.
Normally, the VBI lines are expected to be lines 2-21.

VBI_REG (Reg. 4)

D7 D6 D5 D4 D3 D2 D1 D0

EN_VBI_QUALIFIER

1
2

VBI QUALIFIER WINDOW (lines 2-21)

21

last

line

Note that if both bits d4 and d6 of VBI_REG (reg.4) are enabled, the data capture window
will consist of all lines that are common to the VBI wondow and the given Line Window.

VBI Type Qualifier:

To enable VBI Type Qualifier, bit d7 of VBI_REG (reg.4) should be set to '1', and the
desired VBI Type code should be defined in the DATA_TYPE_QUALIFIER[3..0] field
(bits d3-d0 of VBI_REG).

VBI_REG (Reg. 4)

D7 D6-D4 D3 D2 D1 D0

EN_TYPE_QUALIFIER DATA_TYPE_QUALIFIER[3..0]
Refer to Table 6 for available VBI Data Type codes for this qualifier. Note that the same
code should be defined to th e video decoder for specific lines in order to get any data that
will match this qualifier.

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

Raw Samples:

To enable Raw Samples, bit d5 of VBI_REG (reg.4) should be set to '1':

VBI_REG (Reg. 4)

D7 D6 D5 D4 D3 D2 D1 D0

EN_RAW_SAMPLES

When Raw Samples are enabled, up to 720 raw samples of a VBI line (or any other video
line) can be provided for S/W processing.

If the EN_RAW_SAMPLES bit is not set, raw samples are filtered out by default.

2.3 VBI and IRD (Remote Control) Data Format

During the Vert ical Blank Time Interval, The VBI Data Qualifier stores the incoming VBI
data into the internal 1KByte SRAM. Soon after that, all binary samples from the IRD input
(IO_1) are added (about 8-12 bytes per video field). It is assumed that the total VBI data
and IRD data in a single video field never exceeds the 1KB boundary, and that all
accumulated data can be transfered via the Bulk port until the beginning of next Blank
Interval.

The data that is transfered to the host computer via the Bulk interface contains an additional
Field Synchronization Burst (which is produced after the VBI data and before the IRD
data), and is specified in the following diagrams:

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

General VBI data

structure

VBI Data for line #

N

VBI Data for line #

N+1

VBI Data for line #

N+2

VBI Data for line #

N+L-1

Field Synchronization

Burst

16 bytes of 0x00

VBI

Data

for

Video

field # i

VBI data structure

for any line

Header Byte # 1:

Header Byte # 2:

Header Byte # 3:

Header Byte # 4:

Data Byte # 1

Data Byte # 2

Data Byte # n

SDID

DC

IDI1

IDI2

Line

Header

bytes

Line

received

data

bytes

IRD Data (8-12 bytes)

VBI Data for line #

N

IRD Data for

Video field # i

VBI Data
for Video

field # i+1

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

The following tables specifies the Line Header bytes:

SDID

D7 D6 D5 D4 D3 D2 D1 D0

'1' '0' '0' '0' '0' '1' '0' '1'

DC

D7 D6 D5 D4 D3 D2 D1 D0

'1' '0' DC5 DC4 DC3 DC2 DC1 DC0

DC[5:0] is the number of data bytes that were actually received in this line. Note that this
number may be different than the expected number of data bytes, due to noise or corruption
in the received analog signal.
DC[5:0]='000000' means that no data bytes follow the Line Header.

IDI1

D7 D6 D5 D4 D3 D2 D1 D0

OP FID L8 L7 L6 L5 L4 L3

L[8:3] : MSbits of Line Number (look for LSbits 2:0 in IDI2 byte).

FID : Field Identifier. '0' means FIRST field, '1' means SECOND field.

OP is Odd Parity bit. Examp.: D6:D0='0000101' ==> OP='1', IDI1=0x85.

IDI2

D7 D6 D5 D4 D3 D2 D1 D0

OP L2 L1 L0 DT3 DT2 DT1 DT0

OP is Odd Parity bit. Examp.: D6:D0='1110000' ==> OP='0', IDI1=0x70.

L[2:0] : LSbits of Line Number (look for MSbits 8:3 in IDI1 byte).

DT[3:0] defines the VBI Data Type for the given line. The host computer should define the
Data Type per every VBI line (lines between 2-21). The video decoder needs this
information in order to look for the given data type per line (there is no auto detect).
Regardless of decoding success, the same data type code that was programmed by the host
controller will be returned in the DT[3:0] nibble.

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

The following table specifies the Data Type codes (DT[3:0]):

Table 6 - VBI DATA TYPE CODES

DT[3:0]

VBI Data Type

Standard

Expected

number of

Data bytes

0000 Teletext EuroWST, CCST WST625 42
0001 European Closed Caption CC625 2
0010 Video Programming Service VPS 26
0011 Wide screen signalling bits WSS 14
0100 US Teletext (WST) WST525 34
0101 US Closed Caption (line 21) CC525 2
0110 Video Component signal S/W mode 718

0111* Oversampled CVBS data (do not use) ** intercast **

1000 Teletext General Text 42
1001 VITC/EBU time codes (Europe) VITC625 11
1010 VITC/EBU time codes (USA) VITC625 11

1011* reserved (do not use)

1100 US NABTS NABTS 34
1101 MOJI (Japanese) Japtext 35
1110 Japanese format switch (L20/22) JFS 26

1111* Active Video Region (do not use) 718

The IRD (Remote Control) data Header byte contains two fields as specified bellow. It is
followed by 7 to 11 bytes (depends one broadcast system PAL/NTSC, and sampling
phase):

IR_HEADER

D7 D6 D5 D4 D3 D2 D1 D0

'0' '1' '1' '1' IRD_LENGTH

IRD_LENGTH contains the number of bytes for IRD data samples that follow the header.

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

BLK_IO_EN

3. Bulk Interface

The Bulk Interface in the ZR36505 is capable of transferring serial data from the 1KB buffer
to the ZR36504 at a bit rate of up to 2Mbit/sec.

The Bulk channel takes advantage of the existing interface for the audio codec. In order to
work simultaneously with the audio channel, the ZR36505 stops the data transfer from time
to time - as specified in the Bulk waveform diagram.

The ZR36505 pins for the Bulk interface are BCLK, DAT_OUT, BLK_EN, BLK_FULL,
and FS_L. The signal FS_L is monitored by the ZR36505 in order to coexist with the audio
channel (if exists).

The following parameters in the BLK_OPER_MODE register (reg. 5) must be properly
defined to match the ZR36504 setup:

BLK_OPER_REG (Reg. 5)

D7 D6-D4

resrved BCLK_RATE AUDIO_DAT AUDIO_RATE AUDIO_STEREO

BLK_IO_EN

- This bit enables the ZR36505 Bulk control output signals. When this bit is

'0', the DAT_OUT and BLK_EN pins are constant Hi-Z.

BCLK_RATE

- This bit defines the BCLK frequency, and must match the appropriate
parameter that is programmed in the AUDO_CONT register of the ZR36504(Reg.50, d7 ­d6). BCLK_RATE='1' defines 2048KHz (= '11' in NT1004), and BCLK_RATE='0'
defines 1544KHz (= '10' in NT1004).

AUDIO_DAT

- This bit defines whether or not the audio channel is active, and must match
the appropriate parameter that is programmed in the AUDO_CONT register of the
ZR36504(Reg.50, d0). AUDIO_DAT='1' defines audio active (= '1' in NT1004), and
AUDIO_DAT='0' defines that there is no audio data sharing the bus (= '0' in NT1004).

AUDIO_RATE

- This bit defines the audio sampling rate, and must match the appropriate
parameter that is programmed in the AUDO_CONT register of the ZR36504(Reg.50, d5).
AUDIO_RATE='1' defines 16Ks/sec (= '1' in NT1004), and AUDIO_RATE='0' defines
8Ks/sec (= '0' in NT1004).

AUDIO_STEREO

- This bit defines the audio stereo/mono mode, and must match the

appropriate parameter that is programmed in the AUDO_CONT register of the

D3 D2 D1 D0

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

ZR36504(Reg.50, d4). AUDIO_STEREO='1' defines Stereo mode (= '1' in NT1004),
and AUDIO_STEREO ='0' defines Mono mode (= '0' in NT1004).

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

The following waveform diagrams specify the procedure and timings for the ZR36505 Bulk
interface. Note that the output data is supposed to be sampled on the falling edge of the
BCLK clock signal. The BLK_EN output is set to '1' to indicate the beginning of a byte
sequence; it always turns to '1' before the most significant bit of the first byte, and returns to
'0' after the least significant bit of the last byte in sequence. When the BLK_FULL input
signal turns '1', the ZR36505 waits (by switching BLK_EN to '0') until the BLK_FULL
indication returns to '0'.

BCLK

BEh

Bn[0]

BLK_EN

DAT_OUT

BEsu

Dh

Hi-Z Hi-Z

B1[7]

B1[6] B1[5] B1[4] Bn[2] Bn[1]

Dsu

If the audio channel is enabled (bit d2 of Reg.5 is '1'), the ZR36505 waits at least 16 clock
cycles after the FS_L pulse before beginning to send its own data (if bit d0 of Reg.5 is '1', it
waits for 32 clock cycles). During this time it keeps the DAT_OUT signal in the Hi-Z state,
in order not to interfere with the audio data.

BCLK

FS_L

BLK_EN

DAT_OUT

1 2

x

Keep Hi-Z in order not to interfere with audio data

3 4

16

(32 in Stereo mode)

B1[7] B1[6]

B1[5]

November-99 Page 23 of 23

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

BFHsu BFLsu

BCLK

BLK_FULL

BLK_EN

DAT_OUT

Bn[1]

Bn[0]

Hi-Z

Bn+1[7]

Bn+1[6]

Table 7 - BULK INTERFACE TIMINGS

Parameter Symbol Min Max Unit

Setup Time from BLK_EN High to BCLK Low BEsu 100 - ns
Hold Time from BCLK Low to BLK_EN Low BEh 100 - ns
Setup Time from DAT_IN valid to BCLK Low Dsu 100 - ns
Hold Time from BCLK Low to DAT_IN valid Dh 100 - ns
Setup Time from BLK_FULL High to BCLK High BFHsu 80 - ns
Hold Time from BLK_FULL Low to BCLK High BFLsu 0 - ns
BCLK frequency Freq.BCLK 1544 2048 KHz

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ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

4. Programmable I/O Pins

The ZR36505 has two programmable I/O pins for general purpose usage. These are IO-1
and IO-2 pins, which are Open-Drain.

Each of these pins - if used - must be conn ected to an external pull-up resistor to 3.3v (if not
used, it can be tied to GND). The external pull-up resistor should be in the range 1-10KΩ.

To use these pins as inputs, the host computer should write '1' to the appropriate bit in the
IO_REG register (reg. 6); these are IO_1 and IO_2 bits respectively. In this condition, the
voltage level presented on the IO-1 or IO-2 pin can be read by the host computer via the
appropriate bit ('0' represents <0.8v, '1' represents >2.0v).

To use these pins as outputs, the host computer should write the output value to the
appropriate bit in the IO_REG register; In this condition, and assuming that no external
device forces the voltage level presented on the IO -1 or IO-2 pin, the written value will be
reflected out ('0' will generate 0v, '1' will generate 3.3-5.0v).

IO_REG (Reg. 6)

D7 D6 D5 D4 D3 D2 D1 D0

resrved resrved resrved resrved resrved resrved IO_2 IO_1

Upon a Soft Reset operation, the IO-1 and IO -2 pins are cleared to '0'.

November-99 Page 25 of 25

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

5. Soft Reset operation

It is strongly recommended that the S/W application will perform a Soft Reset to the
ZR36505 prior to any other operation. All registers will contain their default values after this
operation (refer to table 4 for default values).

To perform a Soft Reset, the value 0x01 must be written in the SOFT_RESET register (reg.

7). There is no need to write 0x00 after writing 0x01, because this register is automatically
cleared.

SOFT_RESET (Reg. 7)

D7-D1

D0

resrved SOFT_RESET

November-99 Page 26 of 26

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

6. Mechanical Specification

Dimensions in inches.

+.007

0.606

-.007

24

-.008

+.017

0.402

.050 Typ

-.004

+.003

0.296
.019 x 45 Typ

1

+.004

0.016

-.003

0.099

+.005

-.006

-.017

+.017

0.033

24-pin 300-Mil SOIC GULL WING

November-99 Page 27 of 27

ZORAN Corporation USBvision II Data Decoder ZR36505 Data Sheet

http://www.zoran.com

For more information, contact Zoran’s San ta Clara office or the office
nearest you:

USA

Zoran Corporation
3112 Scott Boulevard
Santa Clara, CA 95054 -3317
Tel: [phone]
Fax: [phone]

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Zoran Microelectronics Ltd.
Advanced Technology Ctr.
P.O. Box 2495
Haifa, 31024 Israel
Tel : [phone]
Fax: [phone]

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Suite 2507
Electronics Science &
Tech Building
2070 Central Shennan Rd.
Shenzhen, Guangdong,
518031 P.R. China
Tel : [phone]
Fax: [phone]

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Zoran Japan Office
2-2-8 Roppongi, Minato-ku
Tokyo 106 -0032, Japan
Tel : [phone]
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Zoran Taiwan Office
4F-1, No. 5, Alley 22
Lane 513, Reikuang Rd.
Taipei, Taiwan R.O.C.
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Canada

Zoran Toronto Lab
2175 Queen St. East,
Suite 302
Toronto, Ontario
M4E 1E5 Canada
Tel : [phone]
Fax: [phone]

November-99 Page 28 of 28