Datasheet ZR36015 Datasheet (ZORAN)

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ZR36015

PRELIMINARY

FEATURES

Real Time Raster to/from Block Conversion
1/2 Decimation Processing in the Horizontal Direction
30 MHz Maximum Clock Rate
Only Image in Preset Window is Converted
Compatable with Zorans ZR36050 JPEG Coder and

ZR36011 Color Space Converter

APPLICATIONS

Image processing
Multi-media

Scanners
Image Storage

DESCRIPTION

The ZR36015 performes raster to/from block conversion for
image compression and expansion applications, and it can be
connected directly to the ZR36050 JPEG coder and the
ZR36011 Color Space Converter.

An image compression system can be easily constructed using
the ZR36015 with the ZR35060 and ZR36011.

The ZR36015 uses a double buffered external SRAM Strip
Buffer to support raster to/from block conversion and block inter­leave.

The maximum number of pixels that can be processed per line
is 8K. The maximum number of lines that can be prcessed per

RASTER TO BLOCK CONVERTER

Supports 1:0:0,4:2:2,and 4:1:1 data formats
100-pin plastic quad flat package (PQFP)
TTL level Input/Output
Synchronous data and controls
Low power consumption: 0.45W (Typ.)
CMOS circuit operating with a single 5V power supply

Image Capture

image is 16K. These numbers vary according to the mode of
operation.

The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and
one half decimation in horizontal direction during compression.

The maximum data transfer rate to the ZR36050 coder is 30
MHz.

[The ZR36015 is fabricated with an advanced low-power CMOS
technology, making it suitable for use in low-power, cost sensi­tive applications. The device is availiable in a 100 pin , Plastic
Quad Flat Package (PQFP).]

Pixel

Interface

PXDATA(15:0)

HEN
VEN

WINDOW

BSY

CLKCSC

Host Interface

SPH

I/F

Window
Control

RD ADD(1:0)WR

Internal Register Control

1/2

Decimation

Interface Logic

DSYNC

EOS

STOP

Coder Interface

Selector

COE

Figure 1. ZR36015 Block Diagram

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1705 Wyatt Drive

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Santa Clara, CA 95054

Raster/Block

Address

Generator

Buffer

Sub

I/F

BDATA(7:0)

MWE
MOE
MADD(15:0)CBSY

I/F

MDATA(15:0)

RESET
SYSCLK

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[phone]

Memory
Interface

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FAX [phone]

8

PXDATA(15:0)

2

CBUSY
HEN
VEN
WINDOW
BSY
CLKCSC

SPH
RD
WR
ADD(1:0)

SYSCLK

RESET

MADD(15:0)

MDATA(15:0)

BDATA(7:0)

STOP

DSYNC

Pixel

Interface

Host

Interface

System

Clock

System

Reset

Figure 2. ZR36015 Logical Pinout

MWE

MOE

COE
EOS

16

Memory
Interface

16

8

Coder
Interface

June 1993ZORAN Corporation

This document was created with FrameMaker 4.0.4

PRELIMINARY

ZR36015

SIGNAL DESCRIPTION

Name Type

PXDATA(15:0) B Pixel side data bus. Input for compression and output for expansion. High impedance during RESET or IDLE modes.

HEN I Active High Horizontal enable signal (HDelay starts counting from the rise of HEN)
VEN I Active High Verticle enable signal (VDelay starts counting from the rise of VEN)
SYSCLK I System clock (active on rising edge).
MADD(15:0) O Address output for the strip memory. Up to 64K x 16 bits of SRAM is addressable.
MDATA(15:0) B Data bus for the strip memory. Memory A is assigned to MDATA(7:0), and Memory B is assigned to MDATA(15:8).
MWE

O Active Low: Write enable for the Strip Memory.
MOE O Active Low: Output enable for the Strip Memory.
DSYNC B Active Low: Sync. signal for 64 byte block of data. Output during compression and input during expansion. In

STOP B Active Low: Stop sending/receiving. During compression, this signal is an input which indicates that the CODEC is

EOS B Active Low: Signal indicates the end of each scan. Output during compression and input during expasion. In

1

When SPH is active (High), PXDATA(7:0) is controlled by the Host Interface. It will be high impedance except during
a Host read access, in which case it will be driven. The state of PXDATA(15:8) follows that of PXDATA(7:0) in this
case but is unused.

compression, DSYNC marks the start of an 8x8 image data block and should appear as an output one SYSCLK cycle
before the first image data of a block. During expansion DSYNC is input on SYSCLK before the first image data of
a sample block. The width of DSYNC is one SYSCLK. (Connect directly to ZR36050 DSYNC signal).

busy, and the ZR36015 should stop sending data. During expansion, this signal is an output indicating the ZR36015
is not ready to receive data, and for the CODEC to stop sending data. (Connect directly to ZR36050 STOP signal).

compression, EOS is output together with the last image data sample of the last block of each scan. In expansion,
EOS is input together with the last image data sample of the last block of each scan. (Connect directly to ZR36050
EOS signal).

Function

BDATA(7:0) B/Z Data bus interface with the Coder. Output for compression and input for expansion. High impedance during reset.

ADD(1:0) I Address select for Host access to internal registers. Enabled when SPH is high.
WR I Active Low: Write strobe for Host loading of internal registers and tables. Data is writtern on the rising edge of WR.

RD I Active Low: Read strobe for Host reading of internal registers and tables. RD is enabled when SPH is high.
CBSY O Active Low: CBSY indicates that the ZR36015 is not ready for the next strip of data.
COE I Coder bus output enable signal. HIGH for Compression Mode (enabling the output drivers for the CDATA bus, EOS

BSY O Active Low: BSY is active when the ZR36015 is processing an image. Before setting hte GO bit in the Mode Register,

CLKCSC O Clock output for ZR36011 Color Space Converter. Used to synchronize data transfers.
SPH I Active High: Select host access to the ZR36015 via the PXDATA(7:0) data bus. Enables the WR, RD inputs.
WINDOW O Active HIGH; Indicates active (windowed) image area.
RESET I Asynchronous Active LOW reset. All bi-directional signals are tri-stated when this signal is active. After RESET , the

V

DD

V

SS

1. I = Input, O = Output, B = Bidirectional, Z = High Impedance.

Otherwise, the direction of the bus is determined by the COE input. (Connect directly to ZR36050 PIXEL(11:4) bus.)

is enabled when SPH is high.

WR

signal and DSYNC signal. . LOW for Expansion mode (enabling the output drivers for the STOP signal). (Connect
directly to ZR36050 COMP signal).

BSY should be inactive.

ZR36015 will be in idle mode (GO bit cleared) and the PXDATA bus will continue to behigh impedance until the GO

bit is set .
— Power terminal.
— Ground terminal.

2

PRELIMINARY

ZR36015

FUNCTIONAL DESCRIPTION

The ZR36015 performs conversion between raster and block
formatted data, with applications in image compression and
expansion. It is designed to work with the ZR36050 JPEG
Codec.

Figure 1 is a block diagram of the ZR36015.
The ZR36015 is a programmable device with an asynchronous

Host Interface (WR,RD,ADD(1:0) which is enabled by the SPH
input . Data is transferred between the Host and the ZR36015
internal Control Registers and configuration tables via the
PXDATA(7:0) bus. Because PXDATA(7:0) is used to transfer
data to/from the Host, and also for pixel data, an external buffer
is required to prevent bus contention.

The internal control registers of the ZR36015 consist of four reg­isters which set the operating mode of the device and control the
interface between the host and the configuration tables. The
configuration tables are used to specify an active window within
the region defined by the VEN and HEN inputs, and to count the
actual number of lins that were processed.

The ZR36015 interfaces to a pixel data bus PXDATA(15:0),
which transfers 4:0:0, 4:1:1, or 4:2:2 formatted data. Transfer of
data on the Pixel Bus is controlled by the Verticle Enable (VEN)
and Horizontal Enable (HEN) inputs.

During Compression, Pixel data can be optionally decimated by
2 in the horizontal direction.

When the ZR36015 is interfaced to the ZR36011 “Color Space
Converter”, then it is recommended that the Clock for Color
Space Converter (CLKCSC) output be connected to the input
clock for the ZR36011.

The ZR36015 supports a double buffered Strip Buffer SRAM
architecture, with up to 64K 16 bit words. The Strip Buffer stores
the image data in interleaved block format. Interleaved block for­matted data is transferred between the ZR36015 and the
ZR36050 over the BDATA bus.

The figure shows A/D and D/A conversion devices in between
an image source/display and the ZR36011 (Color Space Con­verter).

The bus between the ZR36011 and the D/A and A/D converter­ters is in 24 bit RGB format.

In Compression mode the ZR36011 converts the RGB data into
YUV (luminance/chrominance) data for more efficient compres­sion.

In Compression mode, the ZR36015 (Raster to Block Convert­er), converts the raster data into 8x8 blocks for processing by the
ZR36050 JPEG Codec. The SRAM strip buffer stores 8 lines of
data for conversion into block format.

In Compression mode, the ZR36050 JPEG Codec performes
JPEG compression on the block data, and transfers the com­pressed image over the system bus.

In expansion mode, the process described above is reversed.
The ZR36015 and ZR36050 devices are programmed via the

system bus, and require minimal host intervention during the
compression/expansion processes.

Image Source/Display

24

24

A/D Converter D/A Converter

24

Digital RGB

24

ZR36011

Color Space Converter

Digital YUV

ZR36015

Raster to Block Converter

YCbCr

ZR36050

JPEG Image Processor

24

24

16

SRAM Strip Buffer for

Raster ⇔ Block Conversion

The ZR36015 can be directly interfaced with the ZR36050 JPEG
Codec. Block transfers of data are controlled by the DSYNC
STOP

, EOS, COE signals, with data being transferred on the
BDATA(7:0) bus. These signals are connected directly to the
ZR36050 DSYNC

, STOP, EOS, COMP, and PIXEL(11:4)

signals respectively.
Overflows or underflows of the double buffered Strip Memroy

are indicated by the CBSY output.

System Configuration Example

An example of the ZR36015 system configuration is given in
Figure 3. This figure shows an image compression/expansion
system which uses the ZR36011 (Color Space Converter) and
the ZR36050 (JPEG Codec), in addition to the ZR36015.

,

System Bus

Figure 3. ZR36015 System Configuration Example

Control Registers

The ZR36015 has four Control Registers which allow the Host to
set the mode of operation, and to initiate, terminate, and monitor

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PRELIMINARY

ZR36015

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the status of compression or expansion prcesses. The four
control registers are listed and described below.

Table 1: Control Register Map

ADD(1:0) Contents Host Access

00 Soft Reset W
01 Mode Register R/W
10 Address Pointer Register R/W
11 Configuration Register Tables R/W

Soft Reset Register (Write Only):

A Write to the Soft Reset Register will abort the current process,
and put the ZR36015 in to the IDLE mode. The Soft Reset does
not modify the internal registers of the ZR36015, except for the
GO bit in the Mode Register (which is cleared).

After a soft reset, the ZR36015 will be in the IDLE state.
To start a new process, the GO bit in the Mode Register must be

set by the Host.

Mode Register (Read/Write):

The table below shows the contents of the Mode Register.

Bit Name Description

0 GO Go:

0: ZR36015 IDLE
1: Set to indicate Encode or Decode process.

1 EDC 0: Decode mode selected

1: Encode mode selected

Set this bit to a ‘1’ when interfacing the PIXDATA bus to the
ZR36011 Color Space Converter, and to a ‘0’ otherwise.

Setting the CSC bit to a ‘1‘, will modifies the pixel data
internal delays during compression or expansion to match
the delays in the ZR36011 Color Space Converter. A
description of the modified pixel data delays is TBD.

DCM: Select 1/2 Decimation Write Only)
Set this bit to a ‘1’ when selecting 1/2 decimation mode (for

compression only).

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MOD(1:0): Pixel Data Mode Select
These bits are set to determine the PXDATA bus to/from

BDATA bus mode of operation. Table 3 shows the availiable
combinations.

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EDC: Enclde/Decode select
Selects either encode (EDC = ‘1’), or decode (EDC = ‘0’)

mode.

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GO: Process Go Trigger Bit (Write Only)
Set to ‘1’ to start ZR36015 processing. Prior to setting GO,

the host must...

1) Make sure that the BSY bit is not set.

2) Set all processing parameters in the tables.

When GO is set, the ZR36015 starts counting pixel elements
from the rise of VEN and HEN. When [when is go reset?]

MOD(1:0) PXDATA Format BDATA Format

00 1:0:0 1:0:0
01 4:2:2 4:2:2
10 4:2:2 4:1:1
11 4:1:1 4:1:1

3:2 MOD(1:0) Pixel data Mode Select

(seeTable 2)

4 DCM Decimate data (Compression mode only).

Active High.

5 CSC Select ZR36011 Color Space Converter Mode

(Active High)
6 - Not Used
7 BSY Busy Flag (Active High)

The definition of these bits is given below:

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BSY: Busy Flag (Read Only)
Active High: Indicates that the ZR36015 is busy performing

an encoding or decoding process. The next process should
not be started until the current process completes (indicated
by the ZR36015 clearing this bit).

The BSY flag is set to ‘1’ immediately after the GO bit is set.
The BSY flag is cleared when the processing for an image is
complete and the ZR36015 is ready for the next “GO”.

Before setting the “GO” bit (defined later in this section), the
host should check that the Busy Flag is ‘0‘, indicating that the
previous process has completed.

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CSC: Select ZR36011 Color Space Converter (Write Only)

Address Pointer Register(R/W):

This register is a pointer to the configuration tables and line
count register. A write to the configuration table (ADD(1:0) =
“0b11”) will write to the table element indicated by the address
pointer regstier. A read from the number of lines registers will
access the register indicated by the address pointer register.
The Address pointer Register is automatically incremented by
one after a read or write with ADD(1:0) set to “0b11”.

Configuration Register Tables(R/W):

The contents of the Configuration Table are shown in the below.
The fields of the Configuration Table are defined below and in
Figure 5.

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HDelay(12:0): Horizontal delay in number of pixel elements
before active window. The setting range for WDelay(12:0) is
0 to 8191.

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HWidth(14:0): Horizontal width of the activ e image area. The
setting range for Width(14:0) is up to 8191 for.

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VDelay(12:0):Verticle delay in number of pixel elements
before active window. The setting range for HDelay(12:0) is
0 to 8191.

4

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PRELIMINARY

ZR36015

VHeight(12:0):Verticle height of the active image area. The
maximum setting for Height(12:0) is 8191. Setting
Height(12:0) to ‘0’ in encode mode, lets the Height of the
active image area be determined by the non-active point of
VEN.

Address Pointer Value Window Setting Value

0 HDelay(7:0)
1 HDelay(12:8)
2 HWidth(7:0)
3 HWidth(14:0)
4 VDelay(7:0)
5 VDelay(12:8)
6 VWidth(7:0)
7 VWidth(13:8)
8 Number of Lines(7:0)
9 Number of Lines(13:8)

1. Assigned to LSB’s of PIXDATA(7:0)

1

1

1

1

1

Operating States

The ZR36015 has four Operating States; Reset, Idle, Compres­sion and Expansion.

Reset State

While the RESET input is asserted, the ZR36015 is in the Reset
State. In this state the PXDATA and BDATA busses are high
impedance, and the DSYNC
impedance.

After a RESET, the ZR36015 will be in the IDLE state.

Idle State

After a Soft RESET, or after the RESET input signal has been
applied, or at the end of a compression or expansion process,
the ZR36015 will be in the IDLE state. In the IDLE state, no
active processing is taking place, and the PXDATA bus is high
impedance (the bus drivers for the Coder Interface are con­trolled by the COE signal).

While in the IDLE state, the ZR36015 Configuration Register
Tables can be loaded with the values to select the desired active
image area. Also, the Mode Register is loaded with the desired
Mode of operation, and the number of lines table can be read

, STOP, EOS signals are high

HEN

Enable Area

VDelay

Acitve Image

VEN

HDelay

Area

HWidth

VWidth

Figure 4. Active Image Area

Number of Lines Table:

The Number of Lines Table holds the number of lines processed
in encoding by the ZR36015.

To leave the IDLE state and enter one of the processing states
(compression or expansion), the GO bit in the Mode registe is
set.

Compression

When the GO bit is set to “1”, and the EDC bit equals “1”, then
the ZR36015 enters the Compression State.

Setting the GO bit results in the BSY bit in the mode register
being set.

Once the GO bit is set, then on the falling edge of the Verticle
Sync Signal (VEN), the BSY output signal will be set. The BSY
bit (and output signal) will stay set until the end of the Compres­sion process. The hardware can monitor the BSY signal, to
determine when the Compression process has completed. Note
that the GO bit must be set at least three SYSCLK cycles before
the VEN goes from High to Low (see figure ???).

Following the above, the ZR36015 monitors the VEN input to
detect the transiton of VEN from low to high. This indicates the
beginning of the image to be processed The next VDelay lines
of data are ignored in order to reach the “active image area”.
Then the next VWidth lines of data are processed.

The HEN input synchronizes the line by line transfers of data into
the ZR36015. On the rise of HEN, the next HDelay pixels are
ignored in order to reach the “active image area”. Then the next
HWidth pixels are procesed.

5

PRELIMINARY

ZR36015

The MOD(1:0) bits in the Mode Register determine the format of
the data on the PXDATA bus, and the DCM bit determines if
decimation is performed.

After the last of the data in the “Active Image Area” has been
converted to Block format and transferred to the Coder (as indi­cated by the EOS output), the GO bit and the BSY bit (and BSY
signal) are cleared and the ZR36015 enters the IDLE state.

In order to compress a sequene of images, the GO bit must be
set for each image. However, the table values do not have to be
re-initialized for each image.

Expansion

When the GO bit is set to “1”, and the EDC bit equals “0”, then
the ZR36015 enters the Expansion State.

Setting the GO bit results in the BSY bit in the mode register
being set.

Once the GO bit is set, then on the falling edge of the Verticle
Sync Signal (VEN), the BSY output signal will be set. The BSY
bit (and output signl) will stay set until the end of the Expansion
process. The, to determine when the Expansion process has
completed. Note that the GO bit must be set at least three
SYSCLK cycles before the VEN goes from High to Low (see
figure ???).

Following the above, the ZR36015 monitores the VEN input to
detect the transition of VEN from low to high. This indicates the
beginning of the time interval when the image is to be output to
the PIXEL bus. The ZR36015 waits VDelay lines before putting
the first line of decoded data out to the PIXDATA bus.

PXDATA bus. Once host access is selected, the WE and RD
signals initiate the writing and reading of data (using the
PXDATA bus), to locations specified by the ADD(1:0) inputs.

Since the Host and image source share PXDATA(7:0), an
external bidirectional buffer is required on PXDATA(7:0) in order
to avoid bus contention. The ADD(1:0), RD, and WR inputs are
ignored when Host Access is not selected by SPH. The table
below shows the addressing of the internal control registers by
the ADD(1:0) address inputs.

Pixel Bus Formats

The Pixel Bus “PXDATA(15:0), is divided into two bytes.
PXDATA(15:8) is always used to represent the Y data, while
PXDATA(7:0) is always used to represent the UV data.

The data formats of PXDATA are according to the setting of the
MOD(1:0) bits in the Mode Register.

Table 2 and 3 show the format of PXDATA bus for each mode.

Table 2: Pixel Bus Data Format (Mode 3)

PXDATA 1st 2nd 3rd 4th

PXDATA (15:8) Y1 (7:0) Y1 (7:0) Y1 (7:0) Y1 (7:)
PXDATA (7) U1 (7) U1 (5) U1 (3) U1 (1)
PXDATA (6) U1 (6) U1 (4) U1 (2) U1 (0)
PXDATA (5) V1 (7) V1 (5) V1 (3) V1 (1)
PXDATA (4) V1 (6) V1 (4) V1 (2) V1 (0)
PXDATA (3:0) ––––

The HEN input synchronized the line by line transfers of data to
the PXDATA bus. On the rise of HEN, the ZR36015 waits
HDelay SYSCLKs until outputting the decoded line of pixels
(HWIDTH of them) on the PXDATA bus.

The MOD(1:0) bits in the Mode Register and the data in the Con­figuretino Tables, must match the format and size fo the data
being decodced by the ZR36050.

The DCM bit is not used in expansion.
After the last of the data in the “Active Image Area” has been

transmitted to the PXDATA bus, the GO bit and the BSY bit (and
BSY signal) are cleared, and the ZR36015 enters the IDLE
state.

In order to expand a sequence of images, the GO bit must be set
for each image. However, the table values do not have to be re­initialized for each image.

System Interface

The SPH input is used to select host access to the ZR36015,
(set SPH to ‘1’). Host access for read/write of the ZR36015’s
control registers is carried out using the system interface pins
(RD,WR, and ADD(1:0)), in addition to the lower 8-bits of

Table 3: Pixel Bus Data Format (Modes 0, 1, 3)

Format

(1:0:0) (4:2:2) (4:1:1)

PXDATA

PXDATA (15:8)

(Y)

PXDATA (7:0)

(UV)

PXDATA Syncronization Clock Frequency:

1st 2nd 1st 2nd 1st 2nd 3rd 4th

Y0 Y1 Y0 Y1 Y0 Y1 Y2 Y3

– – U0 V0 U0 (7:6)

V0 (7:6)

U0 (5:4)
V0 (5:4)

U0 (3:2)
V0 (3:2)

U0 (1:0)
V0 (1:0)

The input and output of data on PXDATA(15:0) are carried out
in synchronization with the clock signal of SYSCLK for mode 0,
or SYSCLK/2 for modes 1, 2 and 3. Table 4 shows the PXDATA
bus sync clock frequency for each of the modes of operation.

6

Table 4: PXDATA Bus Sync Clock Frequency

MOD (1:0)

Pixel Side

Format

Coder Side

Format

PXDATA Bus Sync

Clock Freq.

PRELIMINARY

ZR36015

unknown number of lines. At the end of processing, the “Number
of Lines” register will contain the number of lines that have been
processed. Figure 7 illustrates the “active image area” for this

1

special case.

0 (00) (1:0:0) (1:0:0) SYSCLK
1 (01) (4:2:2) (4:2:2) SYSCLK ÷ 2
2 (10) (4:2:2) (4:1:1) SYSCLK ÷ 2
3 (11) (4:1:1) (4:1:1) SYSCLK ÷ 2

1. The sync clock freq. of the coder bus side is SYSCLK in all modes.

The data seen on the Pixel Bus during Compressoin is shown in
Figure 5.

PIXEL PROCESSING TIMING

The leading edge of the frame is identified by the fall of VEN
(after the GO bit is set). Tge VDelay is counted from the follow­ing rise of the VEN input. The HDelay is counted from the rise of
the HEN input. The HEN and VEN signals must remain high at
least until the end of the active image area (as defined by the
Configuration Register table).

HEN must conform to either A or B in Figure 8.
Within the image area defined by the VEN and HEN signals, is

the “Active Image Area”, which is determined by the HDelay,
HWidth, VDelay, and VWidth values in the configuration table.
Pixel processing is performed only on those pixels which lie in
the active image area defined in Figure 4. The width and height
of the active image area are determined by the “HWidth” and
“VHeight” values in the configuration register table.

If VWidth is set to zero (a special case), then lines will continue
to be processed for as long as VEN remains high (maximum of
8K lines). This feature allows processing of frames with an

HEN

Active Image

VEN

Area

EOS Output

Figure 6. Pixel Processing Image Area

HEN

VEN

Active Image

Area

EOS Output

NOL

Figure 7. EOS Asertion

BSY

SYSCLK

HEN

MOD[1:0] = 0

CLKCSC

PXDATA (15:8) Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14

MOD[1:0] = 1, 2

CLKCSC

PXDATA (15:8) Y1 Y2 Y3 Y4 Y5 Y6 Y7

PXDATA (7:0) U1 V1 U2 V2 U3 V3 U4

MOD[1:0] = 3

CLKCSC

PXDATA (15:8) Y1 Y2 Y3 Y4 Y5 Y6 Y7

PXDATA (7:6) U11 U12 U13 U14 U21 U22 U23

PXDATA (5:4) V11 V12 V13 V14 V21 V22 V23

Figure 5. Functional Timing Chart - Pixel Bus Side

7

PRELIMINARY

ZR36015

HEN

A B

A > 48 SYSCLK Cycles
B is an even number of SYSCLK cycles
HEN signal must conform to eather a or B

Figure 8. Setting of HEN Timing

Window Output Signal

The WINDOW output (active high) is aligned with the PDATA bus, identifying the pixels which correspond to the active image area.
Figure 5 shows the functional timing for the window signal for the case where Mode=0, and HDelay = 0 or HDelay = 3.

The Window signal is set “HDelay” pixels after the rise of HEN, and goes inactive “HWidth” pixels later. The timing for the WINDOW
signal is identical for both compression and expansion modes.

SYSCLK

HEN

PXDATA

ex. MOD = 0

ex. HDelay = 3

ex. HDelay = 0

1 2 3

0 4 5

HDelay

HWidthWINDOW

HWidthWINDOW

N = HDelay+HWidth

N

Figure 9. Example of Window Output Timing

Line Counting

The ZR36015 counts the number of lines that were processed during encoding mode, and stores this number in the “number of lines”
registers defined in Table 5.

When “VHeight” is set to zero, the number of lines processed is dependent on the duration of the VEN signal. If the duration of the
VEN signal does not correspond to an active image area with a number of lines that is a multiple of 8 (for modes 0,1,3) or a multiple
of 16 (mode 2) then the number of lines is rounded up to the nearest multiple of 8(16). This feature ensures blocks of data that are
compatible with JPEG image compression algorithms.

If the number of lines being processed exceeds 8192, then the ZR36015 terminates the processing after processing 8192 lines.

“BUSY” Bit and Busy Signal Timing

The BSY (Busy) bit in the Mode Register is set to ‘1’ (active) when the Go bit is aserted. When the ZR365015 finishes processing the
data in the active image area, it clears the BSY and GO bits and the BSY

Setting GO

The GO bit in the Mode Register is set in order to begin processing of an image. Before setting the GO bit, the ZR36015‘s Mode
Register and Table values should be configured for the desired operation, and the BSY bit (in the Mode Register) should be checked
to insure that it is not set. If the BSY bit is set, this indicates that the previous process has not completed, and so the ZR36015 is not
ready to start a new process. If the BSY bit is not set, then the ZR36015 is free to begin a new process. The BSY
itored to determine when the previous process is complete.

signal. The BSY signal follows the BSY bit when VEN falls.

signal can be mon-

When the GO bit is set, then the ZR36015 will respond to the next VEN that is sees. The GO bit must be set at lease 3 SYSCLK
cycles before the trailing edge of VEN in order to respond to the next active high pulse of VEN. If the GO bit is not set at least 3

8

PRELIMINARY

ZR36015

SYSCLKs before the trailing edge of VEN, then the following VEN signal (active high) will be ignored, and the VEN pulse after that
will be processed.

VEN

Line

BSY (signal)

BSY (bit)

GO

At least

3 SYSCLKS

VDelay VWidth

Delay of Internal Processing

Figure 10. Relationship of BSY Terminal and BSY Flag and GO Bit

DECIMATION

Horizontal Decimation of data by a factor of 2 is supported for the ZR36015. This allows for the reduction of the volume of data being
stored in the Strip Buffer (and sent out over the BDATA bus) by half.

The tables below shows how data is decimated for each mode.

Decimation Pixel Elements

Mode 0 (4:0:0) Y0
Mode 1 (4:2:2) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Mode 3 (4:1:1) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 V0 U2 V2 U4 V4 U6 V6

U0/V0 U4/V4

During expansion there is no interpolation mode for the data (except as described below for mode 2).
In mode 2, the data is decimated horizontally as shown above for mode 1. But in addition, the UV data for every other line (starting

with the second line) is dropped. The figure below shows this case.

Decimation Pixel Elements

Mode 2
(1st line)

Mode 2
(2nd line)

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0 V0 U2 V2 U4 V4 U6 V6
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0 V0 U2 V2 U4 V4 U6 V6

During Expansion in mode 2, the UV data for the 1st line is replicated to replace to corresponding UV data for the second line.
Note that the MCU for mode 2 will be H=2, V=2.

Sub-Buffer and Strip Buffer Interface

Figure 12 shows the Sub-Buffer Interfaces between the Pixel Data, the Coder Data, and the double buffered Strip Memory.
The Strip Memory Interface can perform a 16-bit read or write on every SYSCLK cycle. In order to keep up with the required data

throughput, the Pixel Data and Coder Data Sub-Buffers each must be able to perform a 16-bit read or write to the Strip Memory on
every other SYSCLK cycle. Therefore the Strip Memory Interface is shared between the Pixel Data, and Coder Data Sub-Buffers,
with each Sub-Buffer accessing the Strip Memory on alternate SYSCLK cycles. Figure TBD shows the timing for alternate read and
writes to the Strip Memory.

The Pixel Data Sub-Buffer performs conversion of the data between the PXDATA Bus and the Strip Memories. (The A Memory stores
the data for all the even pixels, and the B Memory stores the data for all the odd pixels; (see the section on Strip Memory Format).

9

PRELIMINARY

ZR36015

The Coder Data Sub-Buffer performs the conversion of the data between the Strip Memories and the Coder Data Bus.
During Compression, pixel data is transferred from the PXDATA Bus to the Strip Memories, and data from the Strip Memories is trans-

ferred to the Coder Data Bus. During Expansion, Coder data is transferred to the Strip Memories, and data from the Strip Memories
is transferred to the Pixel Data Bus.

Figure TBDX7 shows the timing for the data and the control signals for the Strip Buffer Interface.
Note that reads and writes to the Strip Memory are asynchronous to one another, in that either can continue to occur (on alternate

SYSCLK cycles) independently of whether or not the other side is ready to transfer data. The only restriction is that a strip buffer must
be emptied (filled) before its time to switch sides (or else the CBSY signal becomes active (see section TBD)

Strip Buffer

In Compression, the raster format data is read into the Strip Buffer and stored in interlaced JPEG Block format in the Strip Buffer. This
data is then read out to the Coder Data Bus in interlaced Block format for compression by the JPEG CODEC (ZR36050). In Expan­sion, the operation is reversed.

For modes 0,1 and 3,the Strip Buffer is filled with the data from 8 lines. For mode 2, data from 16 lines is stored in a Strip Buffer.
The Strip Buffers are composes of an A and B side. The A side stores the even pixel data and the B side stores the odd pixel data.

Figure 12 shows the A and B sides to the Strip Buffers.
In order to provide double buffering (two strip buffers), the A and B memories are separated into high and low address spaces. The

high address space of the A and B Memories is indicated by the A’ and B’ shown in the figure below. The starting address of A’ and
B’ is determined by the mode of operation for the ZR36015 and whether decimation is being performed (see the section on Strip buffer
Capacity).

MD0205DN

Pixel

Data Side

16

Sub Buffer

Coder

Data Side

16

16

ZR36015

Strip Memory

8

16

8

A’

A

B’

B

Figure 11. Double-Buffer Configuration

10

PRELIMINARY

ZR36015

CODER BUSY SIGNAL (CBSY)

Before changing over from the A/B face to the A’/B’ face of from the A’/B’ face to the A/B face the CBSY signal must not be active.
The CBSY signal is active under the following conditions.

1. In compression, when all of the pixel data for the activ e window hav e been written to the Strip Memory , then CBSY will be asserted
if the Coder has not yet read out all data from the other side of the Strip Memory Buffer.

2. In expansion, when all of the pixel data for the current frame has been read out of one face of the double buffered Strip Memory,
and the Coder has not yot filled the other side of the buffer with data for the next frame.

In either Compression or Expansion, if CBSY is set, then the first HEN signal (for the next strip) should not be asserter until the CBSY
signal becomes inactive.

Factors which can alleviate system problems which are caused by CBSY, are the use of decimation and/or the reduction of the “active
image area”.

CONDITIONS FOR CBSY IN ENCODING MODE

The following sections describe the CBSY signal in relation to the timing for loading and unloading the strip memory. Examples are
given for the encoding and for the decoding modes.

The Strip Memory is double buffered, with one buffer being represented by the A,B memories, and the othre buffer represented by
the A’,B’ memories (see figure TBD). For the purpose of the following discussions, we assume that we start loading to the AB side of
the Strip Buffer, and then load the A’B’ side of the strip buffer (see references to AB,A’B’ in figures TBD-TBD).

Encoding Examples of CBSY Timing

Example #1 : No CBSY

Figure 12 shows an example in encoding mode, where the CBSY is not issues.
Referring to Figure 12, following sequence of events occur...

1. HEN goes HIGH, (indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first
HDelay pixels of the line.

2. DSYNC active indicates that data for Strip Buffer AB (previously loaded) is being unloaded to the Coder Bus.

3. The ZR36015 finishes counting HDelay; data for Strip Buffer A’B’ continues to be loaded from the Pixel bus.

4. Readout of data from the A’B’ side of the strip b uffer is complete. The ZR36015 chec ks to make sure that the AB side of the Strip
Buffer is full before switching sides to begin reading data from the AB side to the Code Buffer. In Example 1, The first DSYNC for
the next strip is not issues immediately because the A’B’ side of the Strip Buffer is still being loaded.

5. The writing of a strip to the A’B’ side of the Strip Buffer is complete. At this time the Coder side switches, and data from the A’B’
side of the strip buffer starts to be read out to the Coder interface, as indicated by the active DSYNC signal.

In Example 1, no CBSY was generated because when the strip being loaded into the A’B’ side of the Strip Buffer was completed, the
AB side of the code buffer was already empty and the Pixel Side was able to switch to the AB side immediately in order to begin
writing the next strip.

We assummed in Example 1 that STOP
write data to the ZR36050 Codec) until the STOP

was not active, otherwise new DSYNCs would not be issued (i.e. the ZR36015 would not

signal became inactive.

11

PRELIMINARY

ZR36015

HEN

PXDATA Bus

Write to Strip Buffer

Read From Strip Buffer

DSYNC/ISYNC

NAX

Delay to Memory Write

See table TBD for “Delay to Memory Write”.

1.
The “Buffer Selection Point” happens at the completion of writing a strip (???? line), and indicates

2.
when the ZR36015 switches strip buffer sides to read this new strip.

When a complete strip has been written, then the 1st DSYNC for this strip will be asserted (assuming

3.
that STOP is not active).

1

PAX

PAX

PAX

The pixel side buffer is

monitored as required

Check if all contents of the coder
side buffer have been read out.

Check if all contents of the pixel
side buffer have been entered.

3

Buffer
selection

2

point

Figure 12. Example of Double-Sided Buffer Selection Timing - In Encoding (No CBSY)

Example #2: Short CBSY

Figure 13 shows an example in encoding mode, where the CBSY is issued for a short period (i.e., CBSY becomes inactive before
the beginning of input for the next strip).

1. HEN goes HIGH, indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first
HDelay pixels of the line.

2. The ZR36015 finishes counting HDelay; data for Strip Buffer A’B’ starts to be loaded from the Pixel bus.

3. DSYNC active indicates that data for Strip Buffer AB (previously loaded) continues to be unloaded to the Coder Bus.

4. The writing of a strip to the A’B’ side of the Strip Buffer is complete. At this time the ZR36015 checks to see if the datat from AB
has been unloaded. In example 2, AB is still in the process of being unloaded, so the CBSY signal is asserted to indicate the the
ZR36015 is not ready to accept more input data from the Pixel side.

Readout of data from the AB side of the strip buffer is complete. Now two things happen. First, the ZR36015 detects that data is
already availiable in the A’B’ side of the Strip Buffer, and so it continues to assert DSYNCs, indicataing that the A’B’ side is now being
unloaded to the Coder Bus. Second, the CBSY signal becomes inactive, indicating that the AB side of the strip buffer is now empty
and that data from the Pixel Bus can be loaded into the AB side.

HEN

PXDATA Bus

Write to Strip Buffer

Read From Strip Buffer

CBSY

DSYNC

NAX

When CBSY is outputted at the timing as shown above (completed within one line), the following oine is not ignored.1.
The timing of CBSY when the line is ignored is as shown below.

2.

PAX

PAX

Check if all contents of the coder
side buffer have been read out.

PAX

The coder side buffer is

monitored as required

Buffer selection point

Check if all contents of the pixel
side buffer have been entered.

Figure 13. Example of Double-Sided Buffer Selection Timing - In Encoding (Short CBSY)

Example #3: CBSY active when HDelay + HWidth is set to the maximum period of HEN

Figure 14 shows an example in encoding mode, where the HDelay + HWidth is set to the maximum perion of HEN. Because of this,
the CBSY can become active after the HEN for the 1st line of the next strip becomes active.

1. HEN goes HIGH, (indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first
HDelay pixels of the line.

12

PRELIMINARY

ZR36015

2. DSYNC active indicates that data for Strip Buffer AB (previously loaded) continues to be unloaded to the Coder Bus.

3. The ZR36015 finishes counting HDelay; then data for Strip Buffer A’B’ continues to be loaded from the Pixel bus.

4. The writing of a strip to the A’B’ side of the Strip Buffer is complete. At this time the ZR36015 checks to see if the datat from AB
has been unloaded. In example 3, AB is still in the process of being unloaded, so the CBSY signal is asserted to indicate the the
ZR36015 is not ready to accept more input data from the Pixel side. But before CBSY is asser ted, the next HEN signal (for the
first line of the next strip) becomes active.

HEN has become active because the CBSY signal was not asserted in time to stop it. This is due to the HDelay+HWidth values
being the maximum (length of HEN). Also, we’ve assumed that the low period between HENs is minimal.

In example 3, line 8n+1 will be ignored (lost) due to the CBSY signal. The ZR36015 will begin processing the next new input line after
CBSY is de-asserted.

HEN

PXDATA Bus

Write to Strip Buffer

Read From Strip Buffer

DSYNC/ISNYC

CBSY

NAX

Delay of internal

processing

If PAX + NAX is set to the maximum effective period of HEN as shown above, CBSY may be active on a line following the

1.
8n line (16n line depending on the mode) for the reason of internal delay. In this case, the processing of the line is started
in MD0205, and finished when CBSY

becomes non-active and resumes processing from the rise of next HEN (8n+2 line).

CBSY

is active. In case of the above timing chart, MD0205 ignores the 8n+1 line, waits until

8n 8n+1

PAX

Check if all contents of the coder

PAX

PAX

side buffer have been read out.

The coder side buffer is

monitored as required

Buffer selection point

Check if all contents of the pixel
side buffer have been entered.

Figure 14. Example of CBSY Timing - In Encoding (HDelay + HWidth = Width of HEN)

Example #4: Long CBSY, New lines continue to come in

Figure 15 shows an example in enoding mode, where the CBSY signal is active for a long period (this could be the result of the STOP
signal being active for a long period). Also in this example, new lines continue to be input into the ZR36015 (as indicated by the HEN
signal).

In example #4, lines 8n+1 and 8n+2 will be ignored (lost), and processing will continue with line 8n+3.
For system which must not loose lines of data, the new lines of data must be held up and only input after CBSY becomes inactive.

HEN

PXDATA Bus

Write to Strip Buffer

Read From Strip Buffer

CBSY

DSYNC/ISNYC

8n 8n+1

NAX

If the processing at the coder side is substantially delayed and CBSY is outputted for a long period of time as shown above,

1.
all lines which cover CBSY
ignored and the processing is started from the 8n+3 line.

PAX NAX PAX

PAX

Check if all contents of the coder
side buffer have been read out.

The coder side buffer is monitored as required

are ignored. Accordingly, in case of the above timing chart, the 8n+1 line and the 8n+2 line are

8n+2 8n+3

Buffer selection point

Check if all contents of the pixel
side buffer have been entered.

Figure 15. Example of CBSY Timing

13

PRELIMINARY

ZR36015

Decoding Examples of CBSY Timing

Example #5
BUSY in Decoding Mode. Three examples for Decoding, Figure 24, E2, E3.

DSYNC

BDATA (7:0)

Write to Strip Buffer

Read From Strip Buffer

PXDATA

STOP

DSYNC

BDATA (7:0)

Write to Strip Buffer

Read From Strip Buffer

PXDATA

N1

64 1 2 3 4 5 6 7 8 62 63 64 1 2 3 4

Final line data of the readout side buffer

Delay of internal
processing

1 block data

Check if all contents of the pixel
side buffer have been read out.

PAX

Check if all contents of the coder
side buffer have been entered.

The pixel side buffer is
monitored as required

Buffer selection point

Delay of internal
processing

Figure 16. Example of Double-Sided Buffer Selection Timing - In Decoding

N1

64 1 2 3 4 5 6 7 8 62 63 64

Final line data of the readout side buffer

Delay of internal
processing

Check if all contents of the coder
side buffer have been entered.

PAX

1 block data

Check if all contents of the pixel
side buffer have been read out.

Delay of internal processing

The coder side buffer is monitored as required

1 2 3 4 5 6 7 8 9

Buffer selection point

CBSY

Figure 17. Example of Double-Sided Buffer Selection Timing - In Decoding

14

PRELIMINARY

ZR36015

DSYNC

BDATA (7:0)

Write to Strip Buffer

Read From Strip Buffer

PXDATA

CBSY

STOP

64 1 2 3 4 5 6 7 8 62 63 64

Final line data of the readout side buffer

Delay of internal
processing

1 block data

Check if all contents of the pixel

side buffer have been read out.

PAX

N1

Buffer selection point

Check if all contents of the coder
side buffer have been entered.

Delay of internal
processing

1 2 3 4 5 6

The coder side buffer is
monitored as required

Figure 18. Example of Double-Sided Buffer Selection Timing - In Decoding

Strip Buffer Memory Format

Two SRAMs form a strip buffer. The 16-bit wide strip buffer is divided into 2 areas at point α * HWidth. Where:

α = K * L * HWidth * D

Low Memory High Memory

Memory A
(lower 8 bits)

Memory B
(Upper 8 bits)

Write Area

(RD Area)

Write Area

(RD Area)

Address = α * HWidthAddress 0

Read Area

(Write Area)

Read Area

(Write Area)

An example of the amount of data stored in the strip buffer for each component of an active region of 704 x 240 is given in Figure 16.

15

PRELIMINARY

ZR36015

1 Field

704

240

MOD1:0 = 10MOD1:0 = 01 MOD1:0 = 11

180

180

720

360

360

720

240

240

240

240

240

240

90

90

360

180

180

720

180

180

360

360

360

240

240

Y U VY U VY U VY U VY U V Y U V

240

240

240

240

120

120

240

120

120

360

360

720

240

240

240

720

Figure 19. Mode Selection Table

240

180

240

180

240

360

240

360

240

Y U V Y U V Y U V

DCM = 0 DCM = 1 DCM = 0 DCM = 1 DCM = 0 DCM = 1

360

240

720

240

16

PRELIMINARY

ZR36015

Component interleave

sequence for blocks of data

(as seen on the code data bus)

Memory Data <15:8>

Memory Data <7:0>

Strip Memory

MODE1:0 = 00
MODE1:0 = 01 U01V
MODE1:0 = 10 Y10Y
MODE1:0 = 11 Y02Y03U00V00Y04Y05Y06Y07U01V

MODE = 01 Y

MODE = 10

MODE = 11 Y

Y0Y1Y2Y3Y4Y
Y00Y01U00V00Y02Y
Y00Y

8

8
8

8

Y00Y

8

00

8

Y

00

Y10Y

8

00

01
01

8

Y

01

8

Y

01
11

8

Y

01

11 01U0 01V0Y02Y03Y12Y13 01U1 01V1

88

U

00

8

888

01U0 01V0

888888

Y02Y

03

5

03

V

00

U

00

01

V

00

Note: YX notation indicates the “x”th block of data for component Y

Figure 20. Memory Format - Write Area

Pixel Data0Y

A Memory

B Memory

0 0Y1 0Y2 0Y3 0Y4 0Y5

0Y0 0Y2 0Y4 0Y6 0Y8

0Y1 0Y3 0Y5 0Y7 0Y9

MADD

$20
$40

MADD

$20
$40

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y0 0Y2 0Y4 0Y6 1Y0 1Y2 6Y6 7Y0 7Y2 7Y4 7Y6

0Y8 0Y10 0Y12 0Y14 1Y8 1Y10 6Y14 7Y8 7Y10 7Y12 7Y14

0Y16 0Y18 0Y20 0Y22 1Y16 1Y18 6Y22 7Y16 7Y18 7Y20 7Y22

1st Line

Data

2nd Line

Data

6th Line

Data

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y1 0Y3 0Y5 0Y7 1Y1 1Y3 6Y7 7Y1 7Y3 7Y5 7Y7

0Y9 0Y11 0Y13 0Y15 1Y9 1Y11 6Y15 7Y9 7Y11 7Y13 7Y15

0Y17 0Y19 0Y21 0Y23 1Y17 1Y19 6Y23 7Y17 7Y19 7Y21 7Y23

Note: aYb notation indicates the Y component of the pixel element in row “a” and column “b”.

7th Line

Data

01

1st Block
2nd Block
3rd Block

1st Block
2nd Block
3rd Block

Pixel Data <15:8>

Pixel Data <7:0>

Memory Data <15:8>0Y

Memory Data <7:0>0Y

Strip Memory

Figure 21. Memory Format - MODE 1:0 = 00

0Y0 0Y1 0Y2 0Y3 0Y4 0Y5 0Y6 0Y7 0Y8

0U0 0V0 0U1 0V1 0U2 0V2 0U3 0V3 0U4

0 0Y2 0Y4 0Y6

1 0Y3 0Y5 0Y7 0Y9

MADD

MADD

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y0 0Y2 0Y4 0Y6 1Y0 1Y2 6Y6 7Y0 7Y2 7Y4 7Y6

$20

0Y8 0Y10 0Y12 0Y14 1Y8 1Y10 6Y14 7Y8 7Y10 7Y12 7Y14

$40A Memory

0U0 0U2 0U4 0U6 1U0 1U2 1U4 6U2 6U4 6U6 7U0 7U2 7U4 7U6

$60

0V0 0V2 0V4 0V6 1V0 1V2 1V4 6V2 6V4 6V6 7V0 7V2 7V4 7V6

$80

0Y16 0Y18 0Y20 0Y22 1Y16 1Y18 6Y22 7Y16 7Y18 7Y20 7Y22

1st Line

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y1 0Y3 0Y5 0Y7 1Y1 1Y3 6Y7 7Y1 7Y3 7Y5 7Y7

$20

0Y9 0Y11 0Y13 0Y15 1Y9 1Y11 6Y15 7Y9 7Y11 7Y13 7Y15

$40A Memory

0U1 0U3 0U5 0U7 1U1 1U3 1U5 6U3 6U5 6U7 7U1 7U3 7U5 7U7

$60

0V1 0V3 0V5 0V7 1V1 1V3 1V5 6V3 6V5 6V7 7V1 7V3 7V5 7V7

$80

0Y17 0Y19 0Y21 0Y23 1Y17 1Y19 6Y23 7Y17 7Y19 7Y21 7Y23

0U0 0U2 0V0 0V2 0Y8 0Y10

Data

2nd Line

Data

6

1Y4

1Y12

1Y20

6

1Y5

1Y13

1Y21

0Y110U1 0U3 0V1 0V3

19

6Y2

6Y10

6Y18

19

6Y3

6Y11

6Y19

Note: aYb notation indicates the Y component of the pixel element in row “a” and column “b”.

Data Sequence on Pixel Bus

Data Sequence on Memory Data Bus

1A

6Y4

6Y12

6Y20

7th Line

Data

1A

6Y5

6Y13

6Y21

Figure 22. Memory Format - MODE 1:0 = 01

8th Line

Data

1st Block
2nd Block
3rd Block
4th Block
5th Block

1st Block
2nd Block
3rd Block
4th Block
5th Block

Data Storage in
Strip Memory

17

PRELIMINARY

ZR36015

Pixel Data <15:8>

Pixel Data <7:0>

Odd Line

Memory Data <15:8>0Y

Memory Data <7:0>0Y

Even Line

Memory Data <15:8>1Y

Memory Data <7:0>1Y

Strip Memory

A Memory

B Memory

0Y0 0Y1 0Y2 0Y3 0Y4 0Y5 0Y6 0Y7 0Y8

0U0 0V0 0U1 0V1 0U2 0V2 0U3 0V3 0U4

0 0Y2 0Y4 0Y6

1 0Y3 0Y5 0Y7 0U5

0 1Y2 1Y4 1Y6

1 1Y3 1Y5 1Y7 1V5

MADD

$A0

$C0

MADD

$20
$40
$60
$80
$A0

$C0

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y0 0Y2 0Y4 0Y6 1Y0 1Y2 6Y6 7Y0 7Y2 7Y4 7Y6

$20

0Y8 0Y10 0Y12 0Y14 1Y8 1Y10 6Y14 7Y8 7Y10 7Y12 7Y14

$40

8Y0 8Y2 8Y4 8Y6 9Y0 9Y2 14Y6 15Y0 15Y2 15Y4 15Y614Y4

$60
$800U

8Y10 9Y12 8Y14 9Y8 9Y10 14Y128Y8 14Y14 15Y8 15Y10 15Y12 15Y14

0 0U2 0U4 0U6 2U0 2U2 12U4 12U6 13U0 13U2 13U4 13U6

1V0 1V2 1V4 1V6 3V0 3V2 13V4 13V6 15V0 15V2 15V4 15V6

0Y16 0Y18 0Y20 0Y22 1Y16 1Y18 6Y22 7Y16 7Y18 7Y20 7Y22

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y1 0Y3 0Y5 0Y7 1Y1 1Y3 6Y7 7Y1 7Y3 7Y5 7Y7
0Y9 0Y11 0Y13 0Y15 1Y9 1Y11 6Y15 7Y9 7Y11 7Y13 7Y15
8Y1 8Y3 8Y5 8Y7 9Y1 9Y3 14Y7 15Y1 15Y3 15Y5 15Y714Y5

8Y11 9Y13 8Y15 9Y9 9Y11 14Y138Y9 14Y15 15Y9 15Y11 15Y13 15Y15
0U1 0U3 0U5 0U7 2U1 2U3 12U5 12U7 13U1 13U3 13U5 13U7
1V1 1V3 1V5 1V7 3V1 3V3 13V5 13V7 15V1 15V3 15V5 15V7

0Y17 0Y19 0Y21 0Y23 1Y17 1Y19 6Y23 7Y17 7Y19 7Y21 7Y23

0U0 0U2 0Y8 0Y10 0U4 0U6

1V0 1V2 1Y8 1Y10 1V4 1V6

0U70U1 0U3 0Y9 0Y11

1V71V1 1V3 1Y9 1Y11

1A

6Y4

6Y12

6Y20

1A

6Y5

6Y13

6Y21

Data Sequence on Pixel Bus

Data Sequence on Memory Data Bus

Note: aYb notation indicates the Y component of the pixel element in row “a” and column “b”.

1st Block
2nd Block
3rd Block
4th Block
5th Block
6th Block
7th Block

1st Block
2nd Block
3rd Block
4th Block
5th Block
6th Block
7th Block

Data Storage in
Strip Memory

Pixel Data <15:8>

Pixel Data <7:6>
Pixel Data <5:4>

Memory Data <15:8>0Y

Memory Data <7:0>

Strip Memory

A Memory

B Memory

Note: aYb notation indicates the Y component of the pixel element in row “a” and column “b”.

Figure 23. Memory Format - MODE 1:0 = 10

0Y0 0Y1 0Y2 0Y3 0Y4 0Y5 0Y6 0Y7 0Y8

0U1 0U2 0U3 0U4 0U11 0U12 0U13 0U14 0U21

0V1 0V2 0V3 0V4 0V11 0V12 0V13 0V14 0V21

0 0Y2 0Y4 0Y6

0Y1 0Y3 0Y5 0Y7 0U1 0V1 0Y9 0Y11 0Y13 0Y15 0U3 0V3

MADD

$A0
$C0

MADD

$A0
$C0

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y0 0Y2 0Y4 0Y6 1Y0 1Y2 6Y6 7Y0 7Y2 7Y4 7Y6

$20

0Y8 0Y10 0Y12 0Y14 1Y8 1Y10 6Y14 7Y8 7Y10 7Y12 7Y14

$40

0Y16 0Y18 0Y20 0Y22 1Y16 1Y18 6Y22 7Y16 7Y18 7Y20 7Y22

$60

0Y24 0Y26 0Y28 0Y30 1Y24 1Y26 6Y30 7Y24 7Y26 7Y28 7Y306Y28

$800U

0 0U2 0U4 0U6 1U0 1U2 6U4 6U6 7U0 7U2 7U4 7U6

0V0 0V2 0V4 0V6 1V0 1V2 6V4 6V6 7V0 7V2 7V4 7V6

8Y34 8Y36 8Y38 9Y32 9Y34 14Y368Y32 14Y38 15Y32 15Y34 15Y36 15Y38

0 1 2 3 4 5 1B 1C 1D 1E 1F

0

0Y1 0Y3 0Y5 0Y7 1Y1 1Y3 6Y7 7Y1 7Y3 7Y5 7Y7

$20

0Y9 0Y11 0Y13 0Y15 1Y9 1Y11 6Y15 7Y9 7Y11 7Y13 7Y15

$40

0Y17 0Y19 0Y21 0Y23 1Y17 1Y19 6Y23 7Y17 7Y19 7Y21 7Y236Y21

$60

0Y25 0Y27 0Y29 0Y31 1Y25 1Y27 6Y31 7Y25 7Y27 7Y29 7Y316Y29

$80

0U1 0U3 0U5 0U7 1U1 1U3 6U5 6U7 7U1 7U3 7U5 7U7
0V1 0V3 0V5 0V7 1V1 1V3 6V5 6V7 7V1 7V3 7V5 7V7

8Y35 8Y37 8Y39 9Y33 9Y35 14Y378Y33 14Y39 15Y33 15Y35 15Y37 15Y39

0U0 0V0 0Y8 0Y10 0Y12 0Y14

1A

6Y4
6Y12
6Y20

1A

6Y5
6Y13

Data Sequence on Pixel Bus

0U2 0V2

Data Sequence on Memory Data Bus

1st Block
2nd Block
3rd Block
4th Block
5th Block
6th Block
7th Block

Data Storage in
Strip Memory

1st Block
2nd Block
3rd Block
4th Block
5th Block
6th Block
7th Block

Figure 24. Memory Format - MODE 1:0 = 11

18

PRELIMINARY

ZR36015

Strip Buffer Capacity

The address range for the strip buffer is 64K (limited by the
number of address bits for the strip buffer memory). Given that
the strip buffer is 16 bits wide, this gives a maximum memory
capacity of 128K bytes that can be accessed.

The raster to block process stores even blocks for each element
in the A strip buffer memory, and the odd blocks for each
element in the B strip bufer memory (see figure TBD). This
divides the storage capacity required for the total strip evenly
between the A and B sides of the memory.

The table below is used to calculate the required total strip buffer
memory capacity (evenly distributed between the A and B
memories) of the strip buffer.

Capacity = 2 x K x L x HWidth x D

Where...

■ “2” is required because the strip buffer is double buffered

■ K indicates the number of bytes of data required for each

pixel

■ L indicates the number of lines of data required to form a strip

■ D is equal to “1” for no decimation delected, and is equal to

“1/2” if decimation is selected.

The maximum number of pixels per line that can be entered for
each mode is given in the table below. This number for the
maximum number of pixels per line is determined by the
maximum addressable strip buffer capacity. When less strip
memory is used (i.e., less than 64K x 16-bits), then the numbers
in the table below must be scaled accordingly.

The limitations for the VHeight values are given in the table
below. These limitations are imposed so that the image size cor­responds to a complete Minimum Configurable Unit (as defined
in the JPEG specification)

MOD (1:0)

HWidth maximum value

(Maximum number of pixels in
horizontal direction)

HWidth minimum value

(Minimum number of pixels in
horizontal dirction)

DCM = 1

Setting value of HWidth

0

(1:0:0)1(4:2:2)2(4:1:1)3(4:1:1)

16384 8192 5440 10880

16 32 32 64

Multiple

of 16

Mulitple

of 32

Multiple

of 32

Multiple

of 64

The limitations to PAY are such that the maximum value is 8192
lines and the minimum value for each format is as shown below:

MOD (1:0)

VWIdth minimum value

(Minimum number of lines in vertical
direction)

Setting value of VWIdth

0

(1:0:0)14:2:2)2(4:1:1)3(4:1:1)

8 8 16 8

Multiple

of 8

Multiple

of 8

Multiple

of 16

Multiple

of 8

Coder Bus Interface

The ZR36015 Raster to Block Converter interfaces directely to
the ZR36050 JPEG Codec.

The Coder Bus Interface consists of the DSYNC
STOP

, EOS, and COE signals (see figure 2).

The Direction of these interface for each mode of operation is
given in the table below.

Table 5: Coder Bus Interface

Signal

DSYNC Output Input

Compression Mode

(EDC = 0)

, BDATA(7:0),

Expansion Mode

(EDC = 1)

MOD (1:0)

k 1 2 1.5 1.5
1 8 8168

0

(1:0:0)

1

4:2:2)

2

(4:1:1)

HWidth is limited as shown below:

MOD (1:0)

HWidth maximum value

(Maximum number of pixels in
horizontal direction)

HWidth minimum value

(Minimum number of pixels in
horizontal dirction)

DCM = 0

Setting value of HWidth

0

(1:0:0)1(4:2:2)2(4:1:1)3(4:1:1)

8192 4096 2720 5440

8 161632

Multiple

of 8

Multiple

of 16

Multiple

of 16

3

(4:1:1)

Multiple

of 32

BDATA (7:0) Output Input
STOP Input Output
EOS Output Input
COE Input Input

The data transfer rate on BDATA(7:0) is equal to the SYSCLK
rate for all formats.

The mode of operation is determined by the “EDC” bit in the
Mode Register when the GO bit is asserted.

Bidirectional signals are availiable as inputs immediately after a
hard reset, and as outputs after the GO bit in the Mode Register
has been set.

The COE signal enables the outputs of the bidirectional signals
of the Code Bus Interface. When COE is High, the outputs for
Compression Mode are enabled, when COE is Low, the output
for Expansion mode are enabled. When the ZR36015 is used

19

PRELIMINARY

ZR36015

with the ZR36050, the COE signal is connected to the ZR36050’s “COMP” output.
The DSYNC signal synchronized 64 byte block transfers between the ZR36015 and the ZR36050.
The STOP signal indicates to the sending device that the receiving device is not ready for more data. New blocks of data will not be

sent to the receiving device until the STOP signal becomes inactive.
The EOS signal indicates the end of each component of a scan. This active low signal is an output in encoding modes. EOS indicates

the last image data sample of the last block of each scan leaving the ZR36015. In encoding modes, EOS is output regardless of the
STOP signal.

EOS is an input signal in the decoding mode. It is input together with the last image data sample of the last block of each scan entering
the ZR36015.

The width of EOS is one SYSCLK cycle in encoding mode, and must be on SYSCLK cycle in decoding mode.
Figure 22 shows the functional timing for the DSYNC and EOS signals relative to the BDATA(7:0) data and SYSCLK.
The functional timing relationship for the STOP (when used as an input during compression mode) is given in Figure 23.

SYSCLK

DSYNC

BDATA (7:0)

DSYNC

EOS

BDATA (7:0) 64 1 2 3 4 5 6 61 62 63 64

2 3 4 5 6 61 62 63 64 1 21

3

Figure 25. Functional Timing for DSYNC and EOS Relative to BDATA(7:0)

SYSCLK

DSYNC

BDATA (7:0)

STOP

62 63 0 1 2 3 4 59 60 61 62 63

If STOP is low, do not output DSYNC
If STOP is High, output DSYNC

Figure 26. Functional Timing for STOP When Used as an Input

The “delay to memory write” indicates the number of clock cycles it takes for the pixel data to propagate through the ZR36015 to the
strip buffer memory. This value is shown in the table below.

Table 6: Delay to Memory Write

Mode Delay (in number of SYSCLKS)

0 2 or 3
1 10 or 11
2 10 or 11
3 10 or 11

In the table above, the smaller value corresponds to the even clock PXDATA element, and the larger value corresponds to the odd
PXDATA element (the ZR36015 writes 16 bits to the strip memroy at a time).

20

PRELIMINARY

ZR36015

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias...................................-55°C to +125°C

Storage Temperature ........................................-40°C to +125°C

Supply Voltage to Ground

Potential Continuous......................................-0.5V to V

CC

+0.5V

DC Voltage Applied to Outputs for

High Impedance Output State .......................-0.3V to V

DC Input Voltage............................................-0.5V to V

CC
CC

+0.3V
+0.5V

OPERATING RANGE

Commercial Devices

Temperature.....................................................0°C ≤ TA ≤ +70°C

Supply V oltage........................................... 4.75V ≤ V

≤ 5.25V

CC

DC CHARACTERISTICS

Symbol Parameter Min Max Units Test Conditions

DC Output Current, into or out of Outputs

(not to exceed 200mA total)...................................20mA/output

DC Input Current.............................................................±10mA

NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS ma y

cause permanent device failure. Functionality at or above these limits is
not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.

V

IL

V

IH

V

OL

V

OH

I

CC

I

LI

I

LO

I

OZ

C

IN

C

B

V

II

Input Low Voltage – 0.8 V
Input High Voltage 2.0 – V
Output Low Voltage 0.4 V IOL = 8mA

VSS + 0.05 V IOL = 1A

Output High Voltage 2.4 V IOH = -8mA

VDD - 0.05 V IOH = -1A

Power Supply Current TBD mA VDD = 5V, f=30 MHz,

CL=20pf, TA=25°C
Input Leakage Current -TBD TBD µAVIN = V
Output Leakage Current -TBD TBD µAV
Output Disable Current -TBD TBD µAV
Input Capacitance TBD pF
Bidirectional Capacitance TBD pF
Hysteresis Voltage TBD V

= V

OUT

= VDD or V

OUT

DD

SS

SS

21

PRELIMINARY

ZR36015

AC CHARACTERISTICS

Signal

Number Description Min Max Units Test Conditions

1 CLK Period 33 ns
2 CLK High 15 ns 2.0V
3 Clock Low Width 15 ns
4 Clock Rise Time 3 ns
5 Clock Fall Time 3 ns
6 Input Hold Time
7 Input Setup Time
8 Data Propagation Delay for PIXDATA

1

1

2

5ns
5ns
4 33 ns tbd

9 Data Propagation Delay for CBUSY, WINDOW, BSY 224

Data Propagation Delay for CLKCSC 5 16

10 Data Propagation Delay for DSYNC, STOP, EOS, COE,

BDATA
11 RESET Pulse Width tbd ns
12 Data Propagation Delay for WINDOW 2 24 ns
13 Data Propagation Delay for PIXDATA
18 Memory Write Address Set-up tbd ns
19 Memory Write Address Hold
21 Memory Write Pulse
22 Memory Output Disable to End of Write tbd ns
23 Memory Write Data Valid
24 Memory Write Data Hold
27 Memory Data High-Z Time tbd ns
28 Memory Data Enable Time tbd nd
30 Memory Read Cycle tbd ns
33 Memory Output Enable Pulse Width (Low) tbd ns

4

5

6

4

3

217ns

433ns

1ns

21 ns

tbd ns

5ns

ns

34 Memory Read Data Setup tbd ns
35 Memory Read Data Hold tbd ns
36 Memory Read Address Valid tbd ns
37 Memory Read Address Hold tbd ns
40 Propagation Delay for MWE
41 Propagation Delay for MOE 223ns
50 Time before Trailing SPH that RD, WR Should be High tbd ns
51 Minimum Host Write Pulse Width tbd ns
52 Minimum Host Read Pulse Width tbd ns

223ns

22

Signal

Number Description Min Max Units Test Conditions

53 Host Address Setup tbd ns
54 Host Address Hold tbd ns
55 Minimum Non-Active Time Between Host Read or Write tbd ns
56 Minimum Time After Fall of SPH to 1st Read or Write tbd ns
58 Host Read Address Hold Time tbd ns
59 Host Write Data Valid tbd ns
60 Host Write Data Hold tbd ns
61 Host Read Data Enable tbd ns
62 Host Read Data Valid tbd ns
63 Host Read Data Hold tbd ns
64 Host Read Data Disable tbd ns
70 Propagation Delay for CSCCLK tbd ns

1. TIH and TIS are for the following input signals: PXDATA (15:0), HEN, VEN, DSYNC, STOP, EOS, BDATA

2. Assumes WINDOW signal is high.

3. Measured during clock cycle when WINDOW goes high.

4. Measured from either rise of MWE, or fall of MOE.

5. Time during which MWE = low, and MOE = high.

6. Measured from start of time when MWE = low, and MOE = High.

PRELIMINARY

ZR36015

2.0V

INPUT

A.C. testing, inputs are driven at 2.4V for a logic “1” and 0.45V for a logic “0”. Input
and output timing measurements are made a t 1.5V for both logic “1” and “0”.

1.5V

0.45V

DEVICE

UNDER TEST

1.5V

Figure 1. AC TESTING INPUT, OUTPUT

1

0.8V

5

SYSCLK

2 3

2.0V

1.5V

0.8V

Figure 1. System Clock Timing

OUTPUT

2.0V

1.5V

4

23

From Output

Under Test

50pF

Figure 1. NORMAL AC TEST LOAD

11

RESET

Figure 1. RESET Pulse Width

Test Point

PRELIMINARY

ZR36015

SYSCLK

76

INPUT

Figure 1. Synchronous Input Setup & Hold Times

12 12

SYSCLK

WINDOW

13 8 8

PIXDATA

SYSCLK

9

10

OUTPUT

Figure 1. Output Propogation Delay

Data 0 Data 1 Data n

Figure 1. X4

24

SYSCLK

PRELIMINARY

ZR36015

40

MWE

41

MOE

40

41

Figure 1. Memory Interface Synchronous Timing

SYSCLK

18

MADDR

40

MWE

41

MOE

MDATA (OUT) Write Data

MDATA (IN)

28

23

Write Address Read Address

21

19

27

24

30

33

37

35

34

Read Data

Figure 1. Memory Interface R/W Asynchronous Timing

SPH

53 54

ADDR

50

56

WR

RD

PXDATA (7:0) Write Data Write Data

Write Address

51

59

55

60

Write Address Read Address

Figure 1. System Interface Timing

SYSCLK

9

CSCCLK

SYSCLK

9

CSCCLK

58

52

62

61

64

63

Figure 1. 203CLK Timing - Mode = 0

Figure 1. 203CLK Timing - Mode = 1, 2, 3

25

PRELIMINARY

ZR36015

100-Pin Flat Pack Pin Assignment

Pin NoPin

Name Type

GND

1

CLKCSC

2

VCC

3

VEN

4

HEN

5

GND

6

PXDATA15

7

PXDATA14

8

PXDATA13

9

PXDATA12

10

PXDATA11

11

PXDATA10

12

PXDATA9

13

PXDATA8

14

GND

15

VCC

16

PXDATA7

17

PXDATA6

18

PXDATA5

19

PXDATA4

20

–
O
–

I
I

­B
B
B
B
B
B
B
B

-

­B
B
B
B

Pin NoPin

Name Type

PXDATA3

21

PXDATA2

22

PXDATA1

23

PXDATA0

24

GND

25

SYSCLK

26

VCC

27

ADD1

28

ADD0

29

SPH

30

WR

31
32

RD

33

BSY

34

CBSY

35

WINDOW

36

VCC

37

GND

38

MADD0

39

MADD1

40

GND

B
B
B
B
–

I

–

I
I
I
I

I
O
O
O

-

­O
O
–

Pin NoPin

Name Type

VCC

41

MADD2

42

MADD3

43

MADD4

44

MADD5

45

MADD6

46

MADD7

47

MADD8

48

MADD9

49

GND

50

VCC

51

MADD10

52

MADD11

53

MADD12

54

MADD13

55

MADD14

56

MADD15

57

GND

58

MDATA0

59

MDATA1

60

–
O
O
O
O
O
O
O
O

–

–
O
O
O
O
O
O

O
O

-

Pin NoPin

Name Type

MDATA2

61

MDATA3

62

MDATA4

63

MDATA5

64

MDATA6

65

GND

66

VCC

67

MDATA7

68

MDATA8

69

MDATA9

70

MDATA10

71

MDATA11

72

MDATA12

73

MDATA13

74

MDATA14

75

GND

76

MDATA15

77

MOE

78
79

MWE

80

VCC

O
O
O
O
O
–
–
O
O
O
O
O
O
O
O
–
O
O
O
–

Pin NoPin

Name Type

GND

81

BDATA0

82

BDATA1

83

BDATA2

84

BDATA3

85

BDATA4

86

BDATA5

87

BDATA6

88

BDATA7

89

GND

90

VCC

91

NC

92

COE

93
94

DSYNC

95

STOP

96

EOS

97

GND

98

RESET

99

NC

100

VCC

­B
B
B
B
B
B
B
B
–
–

­O
B
B
B

-

I

–

-

GND

CLKCSC

VCC

VEN
HEN
GND

PXDATA15
PXDATA14
PXDATA13
PXDATA12
PXDATA11
PXDATA10

PXDATA9
PXDATA8

GND
VCC

PXDATA7
PXDATA6
PXDATA5
PXDATA4
PXDATA3
PXDATA2
PXDATA1
PXDATA0

GND

SYSCLK

VCC

ADD1
ADD0

SPH

VCCNCRESET

GND

EOS

STOP

DSYNC

COE

N.C.

VCC

VSS

BDATA7

BDATA6

BDATA5

BDATA4

BDATA3

BDATA2

BDATA1

BDATA0

VSS

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

81

VCC

80

MWE

79

MOE

78

MDATA15

77

GND

76

MDATA14

75

MDATA13

74

MDATA12

73

MDATA11

72

MDATA10

71

MDATA9

70

MDATA8

69

MDATA7

68

VCC

67

GND

66

MDATA6

65

MDATA5

64

MDATA4

63

MDATA3

62

MDATA2

61

MDATA1

60

MDATA0

59

GND

58

MADD15

57

MADD14

56

MADD13

55

MADD12

54

MADD11

53

MADD10

52

VCC

51

31323334353637383940414243444546474849

RD

WR

BSY

CBSY

WINDOW

VCC

GND

MADD0

MADD1

GND

VCC

MADD2

MADD3

MADD4

MADD5

MADD6

MADD7

MADD8

26

50

GND

MADD9

PRELIMINARY

ZR36015

ORDERING INFORMATION

ZR 36015 PQ C -30

SALES OFFICES

U.S. Headquarters

■

Zoran Corporation
1705 Wyatt Drive
Santa Clara, CA 95054 USA
Telephone: [phone]
FAX: [phone]

DATA CLOCK RATE

SCREENING KEY
PACKAGE
PART NUMBER
PREFIX

Israel Design Center

■

Zoran Microelectronics, Ltd.
Advanced Technology Center
P.O. Box 2495
Haifa, 31024 Israel
Telephone: [phone]
FAX: [phone]

PACKAGE

PQ - Plastic Quad Flat Pack (EIAJ)

DATA CLOCK RATE

30.0 MHz

SCREENING KEY

C - 0°C to +70°C (VCC = 4.75V to 5.25V)

Japan Operations

■

Zoran Corporation
1-5-3 Ebisu Kogetsu Bldg.
4th Floor
Shibuya-Ku, Tokyo Japan
Telephone: [phone]
FAX: [phone]

The material in this data sheet is for information only. Zoran Corporation assumes
no responsibility for errors or omissions and reserves the right to change, without
notice, product specifications, operating characteristics, packaging, etc. Zoran

Corporation assumes no liability for damage resulting from the use of information
contained in this document.

DS36015-0693