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DUAL POLARISATION SWITCH TWIN LNB
MULTIPLEX CONTROLLER
ISSUE 1- JANUARY 2001
ZLNB101
DEVICE DESCRIPTION
The ZLNB101 dual polarisation switch
controller is one of a wide range of satellite
receiver LNB support circuits. It features two
completely independent channels, each
providing two logic outputs under the
control of a voltage sensitive input. It is
intended for use in Twin LNB designs,
replacing many dIscrete components to save
both manufacturing cost and PCB size whilst
improving reliability.
The two inputs of the ZLNB101 have a
nominal threshold of 14.5V. Their threshold
is temperature compensated to minimise
drift. Each features a low and stable input
current that enables transient protection to
be achieved with the addition of only a single
resistor per channel.
Normal and an inverted outputs are
provided for each input. All outputs can
source 15mA and sink 10mA making them
suitable to drive TTL and CMOS logic, pin
diodes and for IF-amp supply switching.
FEATURES
provides polarity detection and control
•
transient resistant
•
low input current
•
low supply current
•
temperature compensated input
•
threshold
standard and inverted output available
•
simultaneously wide supply operating
range
dual polarisation switch
•
eliminates external components
•
simplifies design
•
The ZLNB101 operates from a single supply
of between 5-12V. Its quiescent current is
typically only 4mA and this does not change
significantly with load or logic state. It is
available in either the standard SO8 or space
saving MSOP8 surface mount packages.
Device operating temperature is -40°C to
+85°C to suit a wide range of environmental
conditions.
APPLICATIONS
twin LNBs
•
IF switch box
•
LNB switch boxes
•
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ZLNB101
ABSOLUTE MAXIMUM RATINGS
Supply Voltage -0.6V to 15V
Supply Current 50mA
V
and V
POL1
Input Voltage 25V Continuous
POL2
Power Dissipation (T
SO8 500mW
MSOP8 500mW
amb
= 25°C)
Operating Temperature -40 to 85°C
Storage Temperature -40 to 85°
ELECTRICAL CHARACTERISTICS TEST CONDITIONS (Unless otherwise stated):
= 25°C,VCC=5V,ID=10mA (R
T
amb
SYMBOL PARAMETER CONDITIONS
V
I
I
V
CC
POL
Supply Voltage 5 12 V
CC
Supply Current All inputs and outputs open circuit
= I
I
VERT1
= 14V
V
POL2
= I
I
HOR1
HOR2
= 15.0V
V
POL2
V
POL1
Current V
Threshold
TPOL
and V
Inputs
POL2
= V
POL1
(Note 1) (Note 4) 14.0 14.5 15.0
Voltage
T
Switching Speed 100
SPOL
Vert 1/2 Outputs
V
V
V
V
VHIGH
VHIGH
VHIGH
VLOW
Voltage High
Voltage High
Voltage High
Voltage Low
I
VERT1=IVERT2
= V
V
POL1
I
VERT1=IVERT2
= V
V
POL1
I
VERT1=IVERT2
= V
V
POL1
I
VERT1=IVERT2
= V
V
POL1
Hor 1/2 Outputs
V
V
V
V
VHIGH
VHIGH
VHIGH
VLOW
Voltage High
Voltage High
Voltage High
Voltage Low
I
HOR1=IHOR2
= V
V
POL1
I
HOR1=IHOR2
= V
V
POL1
I
HOR1=IHOR2
= V
V
POL1
I
HOR1=IHOR2
= V
V
POL1
=33kΩ)
CAL1
LIMITS
Min Typ Max
= 10mA, V
VERT2
= 10mA, V
= 25V (Note 4) 10 20 40
POL2
POL1
POL1
=
=
=10mA,
POL2
= 14V
V
-1.0
V
CC
=15mA,
POL2
= 14V
V
V
-1.2
CC
=10µA,
POL2
= 14V
V
V
CC
-0.2
=-10mA,
POL2
= 15.0V
0
0.25
=10mA,
POL2
= 15.0V
V
V
-1.0
CC
=15mA,
POL2
= 15.0V
V
V
-1.2
CC
=10µA,
POL2
= 15.0V
V
V
CC
-0.2
=-10mA,
POL2
= 14V
0
0.25
UNITS
10
30
30
mA
mA
mA
µA
µs
-0.8
V
CC
-0.9
V
CC
-0.1
V
CC
0.5
V
-0.8
CC
-0.9
V
CC
-0.1
V
CC
0.5
CC
CC
CC
CC
CC
CC
V
V
V
V
V
V
V
V
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ZLNB101
Note:-
POL1
and V
POL1
1) V
specified above.
2) Inputs V
(10k) resistors. Input V
and Hor2. With either input voltage set at or below 14V, the corresponding Vert pin will be high
and Hor pin low. With either input voltage at or above 15.0V, the corresponding Vert pin will be
low and Hor pin high. Any input or output not required may be left open-circuit.
3) All outputs are designed to be compatible with TTL, CMOS, pin diode and IF Amp loads.
4) Applied via 10k resistors
The following block diagram shows a typical block diagram twin LNB design. The ZLNB101
provides the two polarity switches required to decode the two independent receiver feeds.
Additionally the front end bias requirements of the LNB are provided by the ZNBG4000 or
ZNBG6000 offering a very efficient and cost effective solution.
switching thresholds apply over the whole operating temperature range
POL2
and V
are designed to be wired to the power input of an LNB via high value
POL2
controls outputs Vert1 and Hor1. Input V
POL1
controls outputs Vert2
POL2
Horizontal
Antenna
Ver ti ca l
Antenna
Gain Stage
GaAs/HEMTFET
1
Bias Generator
ZNBG40XX
Series
42
Gain Stage
GaAs/HEMTFET
Control Input
<=14V-Horizontal
Mixer
3
+
>=15V-Vertical
ZLNB101 Series
Dual H/V Switch
Horizontal
Control
Ver ti ca l
PIN
Diode
MUX
DC Input
13-25V
H/V Output 1
IF down feed
950-1750 MHz
- Standard Band
950-2050 MHz
- Enhanced Band
H/V Output 2
+
Mixer
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Page 4
ZLNB101
CONNECTION DIAGRAMS
Ve rt 2
Hor2
G
nd
Vp2
Ve r t1
Hor1
Vert2
Hor2
1
2
3
4
MSOP8
1
2
3
4
SO8
8
7
6
5
8
7
6
5
Hor1
Ve rt 1
V
cc
Vp1
V
cc
Vp1
Vp2
G
nd
ORDERING INFORMATION
Part Number Package Part Mark
ZLNB101X8 MSOP8 ZLNB101
ZLNB101N8 SO8 ZLNB101
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PACKAGE DIMENSIONS
MSOP8
DIM Millimetres Inches
MIN MAX MIN MAX
A 0.91 1.11 0.036 0.044
A1 0.10 0.20 0.004 0.008
B 0.25 0.36 0.010 0.014
C 0.13 0.18 0.005 0.007
D 2.95 3.05 0.116 0.120
e 0.65 NOM 0.0256 NOM
e1 0.33 NOM 0.0128 NOM
E 2.95 3.05 0.116 0.120
H 4.78 5.03 0.188 0.198
L 0.41 0.66 0.016 0.026
θ°
SO8
0° 6° 0° 6°
ZLNB101
D
1
234
B
5678
H
θ°
C
L
E
e X 6
A
1
A
DIM Millimetres Inches
Min Max Min Max
A 4.80 4.98 0.189 0.196
B 1.27 BSC 0.05 BSC
C 0.53 REF 0.02 REF
D 0.36 0.46 0.014 0.018
E 3.81 3.99 0.15 0.157
F 1.35 1.75 0.05 0.07
G 0.10 0.25 0.004 0.010
J 5.80 6.20 0.23 0.24
K0° 8° 0° 8°
L 0.41 1.27 0.016 0.050
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