Page 1
1
0 °
P
RELIMINARY
FEATURES
ROM
Device
Z90365 32 640 8 4.5 to 5.5V
Note: *General-Purpose
■
42-Pin SDIP
■
C to +70 ° C Temperature Range
■
Fully Customized Character Set
(KW)
RAM*
(Words)
PWM
(8-Bit)
Voltage
Range
C
USTOMER
P
ROCUREMENT
Z90365
D
IGITAL
■
■
■
■
■
■
T
ELEVISION
Character-Control and Closed-Caption Modes
Keypad User Control
TV Tuner Serial Interface
Direct Video Signals
Supports Violence Blocking
Speed: 12 MHz
C
ONTROLLER
S
PECIFICATION
1
GENERAL DESCRIPTION
The Z90365 Digital Television Controller is designed to
provide complete audio and video control of television receivers, video recorders, and advanced on-screen display
facilities. The television controller features a Z89C00 RISC
processor core that controls the on-board peripheral functions and registers using the standard processor instruction set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the
modification of attributes on a character-by-character basis. The insertion of control characters permits direction of
other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position offset delay, and background transparency.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
through the industry-standard I
User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
Notes: All Signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
Ground GND V
CC
2
C port.
V
DD
SS
CP97TEL2800
P R E L I M I N A R Y
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Z90365
Digital Television Controller Zilog
GENERAL DESCRIPTION (Continued)
Port 17
Port 00
Capture
IRIN
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0F
PWM
PWM1
PWM2
PWM3
PWM4
PWM5
PWM9
PWM10
Port1
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
RAM
640 x 16
Address
Data
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
CPU
Register Addr/Data
HALFBLNK
ROM Addr
ROM Data
Figure 1. Functional Block Diagram
OSD
V1
V2
V3
VBLANK
Port0F
ROM
32K x 16
P R E L I M I N A R Y
CP97TEL2800
Page 3
1
Z90365
Zilog Digital Television Controller
PIN DESCRIPTION
PWM10
PWM9
PWM5
PWM4
PWM3
PWM2
PWM1
Port03
Port04/ADC4
Port05/ADC3
Port00/ADC2
Port17/ADC1
GND
Port10/R<0>
Port06/Counter
Port18/G<0>
Port13/G<1> HSync
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
Z90365
Shrink
DIP
42
41
40
39
38
37
36
35
34
33
32
31
30
2914
28
27
26
Port12/I2MSD
P11/I2MSC
Port02/I2SSD
Port01/I2SSC
Port09
Port08/R<1>
IRIN
Port07/CSync
Vcc
/Reset
XTAL2
XTAL1
ANGND
LPF
CVI/ADC0
VSync
Port14/B<0>
Port15/B<1>
Port16/SCLK
18
19
20
21Port0F/Half Blank
25
24
23
22
Figure 2. 42-Pin Shrink DIP
VBlank
V1
V2
V3
CP97TEL2800
P R E L I M I N A R Y
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Z90365
Digital Television Controller Zilog
PIN DESCRIPTION (Continued)
Table 1. 42-Pin SDIP Pin Identification
Name Function Z90365 Direction Reset Notes
V
CC
GND 0 V olts 13, 30 PWR –
IRIN Infrared Remote Capture
ADC[4:0] 4-Bit A/D Converter Input 9, 10, 11, 12, 28 AI I
PWM10, PWM9 14-Bit Pulse Width
PWM[5:1] 8-Bit Pulse Width Modulator
Port0[F:0] Bit Programmable
Port1[8:0] Bit Programmable
SCL
SCD
XTAL1 Crystal Oscillator Input 31 AI I
XTAL2 Crystal Oscillator Output 32 AO O
LPF Loop Filter 29 AB O
HSYNC H_SYNC 26 B I
VSYNC V_SYNC 27 B I
/Reset Device Reset 33 I I
V[3:1] OSD Video Output T ypically
Drive B, G, and R Outputs
Blank OSD Blank Output 25 O O
HalfBlank OSD HalfBlank Output 21 O 4
RGB Digital
Outputs
R[1:0], G[1:0], and B[1:0]
Outputs of the RGB Matrix
SCLK Internal Processor SCLK 20 O 6
Notes:
1. SCL I/O pin is shared with Port 0 or Port 11.
2. SCD I/O pin is shared with Port 02 or Port 12.
3. Half Blank output is a function shared with Port 0F.
4. Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0].
5. Internal processor SCLK is shared with Port 16.
PWM outputs are push/pull
+ 5 Volts 34 PWR –
36 I I
Input
1, 2 O O
Modulator Output
3, 4, 5, 6, 7 O O
Output
Input/Output Ports
21, -, -, -, -, -, 38, 37,
35, -, -, 15, 8, 40, 39,
BI 1
11
Input/Output Ports
2
I
C Clock I/O
2
C Data I/O
I
16, 12, 20, 19, 18, 17,
42, 41, 14
39 or 41 BOD 2
40 or 42 BOD 3
BI
22, 23, 24 O O
37, 14, 17, 16, 19, 18 O 5
P R E L I M I N A R Y
CP97TEL2800
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Zilog Digital Television Controller
Z90365
V1, V2, V3 (R, G, B) ANALOG OUTPUT (PRELIMINARY)
T
= 0 ° C to 70 ° C
A
Output Voltage (30 k Ω load) Settling Time
V
= 4.75
CC
data = 00 0.00v .. 0.65v 0.00v .. 0.70v 0.00v .. 0.75v
data = 01 1.70v ± 0.20v 1.80v ± 0.20v 1.90v ± 0.20v
data = 10 2.80v ± 0.25v 2.90v ± 0.25v 3.00v ± 0.25v
data = 11 3.90v ± 0.3v 4.0v ± 0.30v 4.10v ± 0.30v
22 pF
10 MΩ
47 pF
Figure 3. 32 kHz Oscillator Recommended Circuit
5.00V 5.25V 70% of DC level, 10pF load
‹
50 ns
Z90365
XTAL1
32.768 KHz
68 KΩ
XTAL2
Z90365
510 Ω
47 µF
Figure 4. Recommended Low Pass Filter Circuit
0.1 µF
CP97TEL2800
P R E L I M I N A R Y
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Z90365
Digital Television Controller Zilog
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Units Conditions
V
CC
V
ID
V
IA
V
O
V
O
I
OH
I
OH
I
OL
I
Output Current Low 200 mA All Pins
OL
T
A
T
A
Power Supply Voltage 0 7 V
Input V oltage –0.3 V
Input V oltage –0.3 V
Output V oltage –0.3 V
Output V oltage –0.3 V
+0.3 V Digital Inputs
CC
+0.3 V Analog Inputs (A/D0...A/D4)
CC
+0.3 V All Push-Pull Digital Output
CC
+0.3 V Push/Pull PWM Outputs (PWM1...PMW8)
CC
Output Current High –10 mA One Pin
Output Current High –100 mA All Pins
Output Current Low 20 mA One Pin
Operating Temperature 0 70 °C
Storage Temperature –65 150 °C
DC CHARACTERISTICS
T
= 0 ° C to + 70 ° C; V
A
= 4.5V to + 5.5V; F
CC
= 32.768 kHz
OSC
Symbol P arameter Min Max Typical Units Conditions
V
IL
V
IH
V
PU
V
OL
V
OH
V
XL
V
XH
V
HY
I
IR
I
IL
I
CC
I
ADC
Notes:
1. The Z90365 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined powerdown modes. In the event that the Z90365 is operated with the oscillator disconnected, the device may draw higher than typical
current.
2. Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters.
Input V oltage Low 0 0.2 V
Input V oltage High 0.7 V
CC
V
CC
CC
0.4 V
3.6 V
Max. Pull-Up Voltage VCC +0.3 V All Pins
Output Voltage Low 0.4 0.16 V @ IOL = 1 mA
Output V oltage High VCC –0.4 4.75 V @ IOL = 0.75 mA
Input Voltage XTAL1 Low 0.3 V
CC
1.0 V External Clock
Input Voltage XTAL1 High VCC –2.0 3.5 V Generator Driven
Schmitt Hysteresis 3.0 0.75 0.5 V On XTAL1 Input Pin
Reset Input Current 150 90 µAVRL = 0V
Input Leakage –3.0 3.0 0.01 µA @ 0V and V
CC
Supply Current 100 60 mA
Input Current 10 µA
P R E L I M I N A R Y
CP97TEL2800
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Z90365
1
Zilog Digital Television Controller
AC CHARACTERISTICS
= 0°C to 70°C; VCC = 4.5V to 5.25V; F
T
A
= 32.768 kHz
OSC
Symbol Parameter Min Typical Max Units
T
PC
T
RC,TFC
TD
POR
TW
RES
TD
HS
TD
VS
TD
ES
TD
OS
TW
HVS
Note: All timing of the I2C bus interface are defined by related specifications of the I2C bus interface.
Input Clock Period 16 32 100 µS
Clock Input Rise and Fall 12 nS
Power-On Reset Delay 0.8 1.2 S
Power-On Reset Minimum Width 5 TPC µS
H-SYNC Incoming Signal Width 1 10 15 µS
V-SyYNC Incoming Signal Width 1 200 10,000 µS
Time Delay Between Leading Edge of V-SYNC and H-SYNC in
EVEN Field
Time Delay Between Leading Edge of H-SYNC in ODD Field 20 32 44 µS
H_Sync/V_Sync Edge Width 0.5 2.0 µS
–12 0 +12 µS
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
CP97TEL2800 P R E L I M I N A R Y 7
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
Page 8
Z90365
Digital Television Controller Zilog
8 P R E L I M I N A R Y CP97TEL2800
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