Datasheet Z86L7908PSC, Z86L7908SSC, Z86L8008PSC, Z86L8008SSC Datasheet (ZILOG)

DS97LVO0601

P R E L I M I N A R Y

3-1

1

P

RELIMINARY

P

RODUCT

S

PECIFICATION

Z86L79/L80

1

L

OW

-V

OLTAGE

M

ICROCONTROLLER

FEATURES

■

Three Standby Modes (Typical)
– STOP - 2 µ A
– HALT - 0.8 mA
– Low Voltage Standby (<V

LV

)

■

Expanded Register File Control Registers

■

Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:

– One Programmable 8-Bit Counter/Timer with Two

Capture Registers

– One Programmable 16-Bit Counter/Timer with

One Capture Register

– Programmable Input Glitch Filter for Pulse

Reception

■

Five Priority Interrupts

■

Low Voltage Detection and Standby Mode

■

Watch-Dog/Power-On Reset Circuits

■

Two Independent Comparators with Programmable
Interrupt Polarity

■

On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive

■

Mask Selectable 200 kOhm Pull-Ups on Ports 0, 2, 3
– All Eight Port 2 Bits at One Time or Not
– Pull-Ups Automatically Disabled Upon

Selecting Individual Pins as Outputs.

■

Maskable SingleTrip Point Inputs on P00 Through P03.

■

Permanently Enabled WDT Option (Maskable)

■

28-Pin DIP and SOIC Packages

GENERAL DESCRIPTION

The Z86L79/L80 family of IR (InfraRed) Controllers are
ROM-based members of the Z8

®

MCU

single-chip micro­controller family with 237 bytes of general-purpose RAM.
The only differentiating factor between these two versions
is the availability of ROM. Zilog's CMOS microcontrollers
offer fast execution, efficient use of memory, sophisticated
interrupts, input/output bit manipulation capabilities, auto­mated pulse generation/reception, and easy hard­ware/software system expansion along with cost-effective
and low power consumption.

The Z86L7X architecture is based on Zilog's 8-bit micro­controller core with an Expanded Register File to allow ac­cess to register mapped peripherals, I/O circuits, and pow­erful counter/timer circuitry. The Z8

®

MCU offers a flexible
I/O scheme, an efficient register and address space struc­ture, and a number of ancillary features that are useful in
many consumer, automotive, computer peripheral, and
battery operated hand-held applications.

Part

ROM

(KB)

RAM*

(Bytes) I/O Voltage Range

Z86L79 4 237 24 2.0V to 3.9V
Z86L80 8 237 24 2.0V to 3.9V

Note: *General-Purpose

Z86L79/80
Low-Voltage Microcontroller Zilog

3-2

P R E L I M I N A R Y

DS97LVO0601

GENERAL DESCRIPTION (Continued)

Z8

®

applications demand powerful I/O capabilities. The
Z86L79/80 fulfills this with two package options with 24
pins of dedicated input and output. These lines are
grouped into three ports. Each port consists of eight lines
and is configurable under software control to provide tim­ing, status signals, and parallel I/O.

There are three basic address spaces available to support
a wide range of configurations: Program Memory, Register
File, and Expanded Register File. The Register File is
composed of 256 bytes of RAM. It includes four I/O port
registers, ten control and status registers, and the rest are
general purpose registers. The Expanded Register File
consists of three register groups.

To unburden the program from coping with such real-time
problems as generating complex waveforms or receiving
and demodulating complex waveform/pulses, the Z86L7X
family offers a new intelligent counter/timer architecture

with 8-bit and 16-bit counter/timers (Figure 1). Also includ­ed are a large number of user-selectable modes, and two
on-board comparators to process analog signals with sep­arate reference voltages (Figure 2).

Notes: All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).

Power connections follow conventional descriptions be­low:

Connection Circuit Device

Power V

CC

V

DD

Ground GND V

SS

Figure 1. Counter/Timer Block Diagram

HI16

LO16

16-Bit

T16

TC16H

TC16L

HI8 LO8

And/Or

Logic

Clock

Divider

Glitch

Filter

Edge
Detect
Circuit

8-Bit

T8

TC8H

TC8L

8

8

16

8

Input

SCLK

1

2

48

Timer 16

Timer 8/16

Timer 8

8

8

8

8

8

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y

3-3

1

Figure 2. Functional Block Diagram

Port 0

P00
P01
P02
P03
P04
P05
P06
P07

Pref1
P31

P32
P33

Port 3

Register File

256 x 8-Bit

ROM

4K/8K x 8

Z8 Core

Register Bus

Internal

Address Bus

Internal Data Bus

Expanded

Register

File

Expanded

Register Bus

Counter/Timer 8

8-Bit

Counter/Timer 16

16-Bit

Machine

Timing

&

Instruction

Control

Power

XTAL2

VDD
VSS

P34
P35
P36
P37

P20
P21
P22
P23
P24
P25
P26
P27

Port 2

Two Analog

Comparators

Interrupt Control

XTAL1

I/O Bit

Programmable

Z86L79/80
Low-Voltage Microcontroller Zilog

3-4

P R E L I M I N A R Y

PIN DESCRIPTION

Figure 3. 28-Pin DIP Pin Assignments

P24
P25
P26
P27
P03
P04
P05
P06

VDD
XTAL2
XTAL1

P31
P32
P00

P23
P22
P21
P20
P02
P01
P37
PREF1
VSS
P36
P35
P34
P33
P07

28

Z86L79/80

DIP

1

14 15

Figure 4. 28-Pin SOIC Pin Assignments

P24
P25
P26
P27
P03
P04
P05
P06

VDD
XTAL2
XTAL1

P31
P32
P00

P23
P22
P21
P20
P02
P01
P37
Pref1
VSS
P36
P35
P34
P33
P07

28

Z86L79/80

SOIC

1

14 15

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y

3-5

1

Table 1. Pin Identification

28-Pin DIP &

SOIC Symbol Direction Description

14 P00 Input/Output Port 0 is Nibble Programmable.
23 P01 Input/Output
24 P02 Input/Output

5 P03 Input/Output
6 P04 Input/Output Port 0 can be configured as a 0.4 V

DD

single-trip point
7 P05 Input/Output
8 P06 Input/Output

15 P07 Input/Output
25 P20 Input/Output Port 2 pins are individually configurable

as input or output.

26 P21 Input/Output
27 P22 Input/Output
28 P23 Input/Output

1 P24 Input/Output
2 P25 Input/Output
3 P26 Input/Output
4 P27 Input/Output

21 Pref1 Input Analog Ref Input
12 P31 Input IRQ2/Modulator input
13 P32 Input IRQ0
16 P33 Input IRQ1
17 P34 Output T8 output
18 P35 Output T16 output
19 P36 Output T8/T16 output
22 P37 Output
11 XTAL1 Input Crystal, Oscillator Clock
10 XTAL2 Output Crystal, Oscillator Clock

9V

DD

Power Supply

20 V

SS

Ground

Z86L79/80
Low-Voltage Microcontroller Zilog

3-6

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec­tions of these specifications is not implied. Exposure to ab­solute maximum rating conditions for an extended period
may affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 5).

CAPACITANCE

T

A

= 25 ° C, V

CC

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

Sym Description Min Max Units

V

CC

Supply V oltage (*) –0.3 +7.0 V

T

STG

Storage Temp. –65 ° +150 °

C

T

A

Oper. Ambient
Temp.

†C

Notes:

* Voltage on all pins with respect to GND.
† See Ordering Information.

Figure 5. Test Load Diagram

From Output

Under Test

150 pFI

Parameter Max

Input capacitance 12 pF

Output capacitance 12 pF

I/O capacitance 12 pF

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y

3-7

1

DC CHARACTERISTICS

T

A

= 0 ° C to +70 ° C

Typical

Sym Parameter

V

CC

Min Max @ 25 ° C Units Conditions Notes

Max Input Voltage 2.0V

3.9V

7
7

VVI

IN

<250 µ A

I

IN

<250 µ A

V

CH

Clock Input
High V oltage

2.0V

3.9V

0.9 V

CC

0.9 V

CC

V

CC

+ 0.3

V

CC

+ 0.3

V Driven by

External Clock
Generator

V

CL

Clock Input
Low V oltage

2.0V

3.9V

V

SS

– 0.3

V

SS

– 0.3

0.2 V

CC

0.2 V

CC

VVDriven by

External Clock
Generator

V

IH

Input High Voltage 2.0V

3.9V

0.7 V

CC

0.7 V

CC

V

CC

+ 0.3

VCC + 0.3

1.3

2.5

V
V

V

IL

Input Low Voltage 2.0V

3.9V

VSS – 0.3
V

SS

– 0.3

0.2 V

CC

0.2 V

CC

0.5

0.9

V
V

V

OH1

Output High Voltage 2.0V

3.9V

VCC – 0.4
V

CC

– 0.4

1.7

3.7

VVI

OH

= –0.5 mA

I

OH

= –0.5 mA

V

OH2

Output High Voltage
(P36, P37)

2.0V

3.9V

VCC - .8
V

CC

- .8

VVI

OH

= –7 mA

I

OH

= –7 mA

10

V

OL1

Output Low Voltage 2.0V

3.9V

0.4

0.4

0.2

0.1

VVIOL = 1.0 mA

I

OL

= 1.0 mA

V

OL2

Output Low Voltage 2.0V

3.9V

0.8

0.8

0.3

0.3

VVIOL = 2.0 mA

I

OL

= 2.0 mA

V

OL2

Output Low Voltage
(P20-P22, P36, P00,
P01, P07)

2.0V

3.9V

0.8

0.8

0.3

0.5

VVIOL = 10 mA

I

OL

= 10 mA

2 O/P only

9

V

OFFSET

Comparator Input
Offset V oltage

2.0V

3.9V

25
25

10
10

mV
mV

I

IL

Input Leakage 2.0V

3.9V

–1
–1

1
1

<1
<1

µAµAVIN = OV, V

CC

VIN = OV, V

CC

I

OL

Output Leakage 2.0V

3.9V

–1
–1

1
1

<1
<1

µAµAVIN = OV, V

CC

VIN = OV, V

CC

I

IR

Reset Input Current 2.0V

3.9V

–45
–55

–20
–30

µA
µA

I

CC

Supply Current 2.0V

3.9V

2.0V

3.9V

10

15
100
300

4
10
10
10

mA
mA

µA
µA

@ 8.0 MHz
@ 8.0 MHz
@ 32 kHz
@ 32 kHz

4, 5
4,5,11,12

I

CC1

Standby Current 2.0V

3.9V

2.0V

3.9V

3
5
2
4

1

4

0.8

2.5

mA
mA
mA
mA

HALT Mode
VIN = OV, V

CC

@ 8.0 MHz
Clock Divide-by­16 @ 8.0 MHz

4,5
4,5

I

CC2

Standby Current 2.0V

3.9V

8

10

1

2

µAµASTOP Mode

VIN = OV, V

CC

WDT is not
Running

6,8

Z86L79/80
Low-Voltage Microcontroller Zilog

3-8 P R E L I M I N A R Y DS97LVO0601

DC CHARACTERISTICS (Continued)

I

CC2

2.0V

3.9V

500
800

310
600

µAµASTOP Mode

VIN = OV, V

CC

WDT is Running

6,8

V

ICR

Input Common Mode
Voltage Range

2.0V

3.9V

0
0

VCC-1.0V
V

CC

-1.0V

V
V

12

T

POR

Power-On Reset 2.0V

3.9V

7.5

2.5

75
20

13

7

ms
ms

V

LV

VCC Low Voltage
Protection

2.15 1.7 V 8 MHz max
Ext. CLK Freq

7

Notes:

1. GND = 0V

2. 2.0V to 3.9V

3. All outputs unloaded, I/O pins floating, inputs at rail.

4. CL1 = CL2 = 100 pF

5. Same as note [4] except inputs at V

CC

.

6. The V

LV

increases as the temperature decreases.

7. Oscillator stopped.

8. Two outputs at a time, independent to other outputs.

9. One at a time.

10. 32 kHz clock driver input.

11. WDT not running.

12. For analog comparator, inputs when analog comparators are enabled.

TA = 0°C to +70°C

Typical

Sym Parameter

V

CC

Min Max @ 25°C Units Conditions Notes

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-9

1

AC CHARACTERISTICS

Additional Timing Diagram

Figure 6. Additional Timing

Clock

1

3

4

8

2 2 3

T

IRQ

IN

N

6

5

7 7

Clock

Setup

10

9

Stop

Mode

Recovery

Source

11

Z86L79/80
Low-Voltage Microcontroller Zilog

3-10 P R E L I M I N A R Y

AC CHARACTERISTICS

Additional Timing Table

T

A

= 0°C to +70°C

No Symbol Parameter

V

CC

Min Max Units Notes

1 TpC Input Clock Period 2.0V

3.9V

121
121

DC
DC

ns
ns

1
1

2 TrC,TfC Clock Input Rise

and Fall Times

2.0V

3.9V

25
25

ns
ns

1
1

3 TwC Input Clock Width 2.0V

3.9V

37
37

ns
ns

1
1

4 TwTinL Timer Input Low

Width

2.0V

3.9V

100

70

ns
ns

5 TwTinH Timer Input

High Width

2.0V

3.9V

3TpC
3TpC

1
1

6 TpTin Timer Input Period 2.0V

3.9V

8TpC
8TpC

1
1

7 TrTin,TfTin Timer Input Rise

and Fall Timers

2.0V

3.9V

100
100

ns
ns

1
1

8A TwIL Interrupt Request

Low Time

2.0V

3.9V

100

70

ns
ns

1,2
1,2

8B TwIL Int. Request

Low Time

2.0V

3.9V

3TpC
3TpC

1,3
1,3

9 TwIH Interrupt Request

Input High Time

2.0V

3.9V

3TpC
3TpC

1,2
1,2

10 Twsm Stop-Mode

Recovery
Width Spec

2.0V

3.9V

2.0V

3.9V

12

12
5TpC
5TpC

ns
ns

8
8
7
7

11 Tost Oscillator

Start-up Time

2.0V

3.9V

5TpC
5TpC

4
4

12 Twdt Watch-Dog Timer

Delay Time (5 ms)

2.0V

3.9V

12

5

75
20

ms
ms

D0 = 0 [5]
D1 = 0 [5]

15 ms 2.0V

3.9V

25

10

150

40

ms
ms

D0 = 1 [5]
D0 = 1 [5]

25 ms 2.0V

3.9V

50

20

300

80

ms
ms

D0 = 0 [5]
D0 = 0 [5]

100 ms 2.0V

3.9V

225

80

1200

320

ms
ms

Notes:

1. Timing Reference uses 0.9 V

CC

for a logic 1 and 0.1 VCC for a logic 0.

2. Interrupt request through Port 3 (P33-P31).

3. Interrupt request through Port 3 (P30).

4. SMR – D5 = 0

5. Reg. WDTMR

6. 2.0V to 3.9V

7. Reg. SMR – D5 = 0

8. Reg. SMR – D5 = 1

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-11

1

AC CHARACTERISTICS

Handshake Timing Diagram

Figure 7. Port I/O with Input Handshake Timing

Data In

1

3

4

5 6

/DAV

(Input)

RDY

(Output)

Next Data In Valid

Delayed RDY

Delayed DAV

Data In Valid

2

Figure 8. Port I/O with Output Handshake Timing

Data Out

/DAV

(Output)

RDY

(Input)

Next Data Out Valid

Delayed RDY

Delayed DAV

Data Out Valid

7

8 9

10

11

Z86L79/80
Low-Voltage Microcontroller Zilog

3-12 P R E L I M I N A R Y

AC CHARACTERISTICS

Preliminary
Handshake Timing Table

TA = 0°C to +70°C

8 MHz Data

No Symbol Parameter

V

CC

Min Max Direction

1 TsDI(DAV) Data In Setup Time 2.0V

3.9V

0
0

IN
IN

2 ThDI(DAV) Data In Hold Time 2.0V

3.9V

160
115

IN
IN

3 TwDAV Data Available Width 2.0V

3.9V

155
110

IN
IN

4 TdDAVI(RDY) DAV Falling to RDY

Falling Delay

2.0V

3.9V

160
115

IN
IN

5 TdDAVId(RDY) DAV Rising to RDY

Falling Delay

2.0V

3.9V

120

80

IN
IN

6 TdRDYO(DAV) RDY Rising to DAV

Falling Delay

2.0V

3.9V

0
0

IN
IN

7 TdDO(DAV) Data Out to DAV

Falling Delay

2.0V

3.9V

63
63

OUT
OUT

8 TdDAV0(RDY) DAV Falling to RDY

Falling Delay

2.0V

3.9V

0
0

OUT
OUT

9 TdRDY0(DAV) RDY Falling to DAV

Rising Delay

2.0V

3.9V

160
115

OUT
OUT

10 TwRDY RDY Width 2.0V

3.9V

110

80

OUT
OUT

11 TdRDY0d(DAV) RDY Rising to DAV

Falling Delay

2.0V

3.9V

110

80

OUT
OUT

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-13

1

PIN FUNCTIONS

XTAL1 Crystal 1 (time-based input). This pin connects a

parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.

XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.

Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured un­der software control as a nibble I/O port. The output drivers
are push-pull in this configuration.

Using single trip point ROM mask option, Port 00-03 can
be programmed to allow direct interface to applications
that require single point comparison like mouse/trackball
IR sensors. ROM mask option will enable the 0.4 VDD trip
Point Buffers on these inputs.

An optional 200 kOhms (port wide) pull-up is available as
a mask option on all bits for the L79/L80 versions.

These pull-ups are disabled when configured (bit by
bit) as an output.

Figure 9. Port 0 Configuration

Z86L7X

MCU

4

4

Port 0 I/O

OEN

Out

In

PAD

200 kΩ

**Mask Selectable

Mask
Option

In

0.4 VDD

Trip Point Buffer

**

0.5 VDD

Trip Point Buffer

Z86L79/80
Low-Voltage Microcontroller Zilog

3-14 P R E L I M I N A R Y DS97LVO0601

PIN FUNCTIONS (Continued)

Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS

compatible I/O port. These eight I/O lines can be indepen­dently configured under software control as inputs or out­puts. Port 2 is always available for I/O operation. A mask
option is available to connect eight 200 kOhms (±50%)
pull-up resistors on this port. Bits programmed as outputs
are globally programmed as either push-pull or open­drain. Port 2 may be placed under handshake control. In
this configuration, Port 3 lines, P31 and P36 are used as
the handshake controls lines /DAV2 and RDY2. The hand-

shake signal assignment for Port 3, lines P31 and P36 is
dictated by the direction (input or output) assigned to Bit 7,
Port 2 (Figure 6). The CCP wakes up with the eight bits of
Port 2 configured as inputs with open-drain outputs.

Port 2 also has an 8-bit input NOR and an NAND gates
which can be used to wake up the part from STOP mode
(Figure 38). P20 can be programmed to access the edge
selection circuitry (Figure 10).

Figure 10. Port 2 Configuration

Open-Drain

OEN

Out

In

PAD

Port 2 (I/O)

Optional
Handshake Controls
/DAV2 and RDY2
(P31 and P36)

Z86L7X

MCU

VCC

200 kΩ

Mask
Option

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-15

1

Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three

fixed input and four fixed output port. Port 3 consists of
three fixed input (P33-P31) and four fixed output (P37­P34), and can be configured under software control for In­put/Output, Interrupt, Port handshake, Data Memory func­tions and output from the counter/timers. P31, P32, and
P33 are standard CMOS inputs; outputs are push-pull, ex­cept for P34, 35 which are controlled by P3M, D0.

Two on-board comparators process analog signals on P31
and P32 with reference to the voltage on Pref1 and P33.
The analog function is enabled by programming the Port 3
Mode Register (bit 1). P31 and P32 are programmable as

rising, falling, or both edge triggered interrupts (IRQ regis­ter bits 6 and 7). Pref1 and P33 are the comparator refer­ence voltage inputs. Access to the edge detection circuit is
through P31 or P20. Handshake lines Ports 0, 1, and 2 are
available on P31 through P36.

Port 3 provides the following control functions: handshake
for Ports 0, and 2 (/DAV and RDY); four external interrupt
request signals (IRQ3-IRQ0). (See Table 2).

Port 3 also provides output for each of the counter/timers
and the AND/OR Logic. Control is performed by program­ming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.

Comparator Inputs. Port 3, P31 and P32 all have a com­parator front end. The comparator reference voltages are
on P33 and Pref1. The internal P33 register and its corre­sponding IRQ1 is connected to the Stop-Mode Recovery
source selected by the SMR. In this mode, any of the Stop­Mode Recovery sources can be used to toggle the P33 bit
or generate IRQ1. In digital mode, P33 can be used as a
Port 3 register input or IRQ1 for P33 (Figure 8).

Note: The comparators are disabled in STOP mode.
Comparator Outputs. These may be programmed to be

outputted on P34 and P37 through the PCON register (Fig­ure 11).

Table 2. Pin Assignments

Pin I/O C/T Comp. Int. P0 HS P2 HS

Pref1 IN RF1

P31 IN ISP AN1 IRQ2 D/R
P32 IN AN2 IRQ0 D/R
P33 IN RF2 IRQ1
P34 OUT T8 A01
P35 OUT T16 R/D
P36 OUT T8/16 R/D
P37 OUT A02

Notes:

1. HS = Handshake Signals

2. D = /DAV

3. R = RDY

Z86L79/80
Low-Voltage Microcontroller Zilog

3-16 P R E L I M I N A R Y DS97LVO0601

PIN FUNCTIONS (Continued)

Figure 11. Port 3 Comparator Configuration

P34 OUT

P37 OUT

P32

+

-

REF2
(P33)

0 = P34, P37 Standard Output
1 = P34, P37 Comparator Output

PCON

D0

P31

+

-

Pref1

P37

PAD

P34

PAD

*

T8

P34 OUT

0 Normal Control*
1 8-bit Timer output active

CTR0

D0

Counter/Timer

Reset condition.

*

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-17

1

Reset. Program execution begins at location 000CH, 5-10

TpC cycles after the RST is released. For Power-On Re­set, the typical reset output time is 5 ms. The Z86L7X does

not reset WDTMR, SMR, P2M or P3M registers on a Stop­Mode Recovery operation either from WDT or the pro­grammed STOP mode recovery source.

Figure 12. Port 3 Configuration

Port 3

(I/O or Handshake)

Z86L7X

MCU

Pref1
P31

P32
P33

P34
P35

P36
P37

Note:

P31, 32, 33 have a 200 KΩ
mask option.

200 KΩ

Mask
Option

D1

R247 = P3M

P31 (AN1)

P32 (AN2)

P33 (REF2)

From Stop-Mode
Recovery Source

1 = Analog
0 = Digital

IRQ2, P31 Data Latch

IRQ0, P32 Data Latch

IRQ1, P33 Data Latch

DIG.

AN.

-

+

-

+

Pref1

Z86L79/80
Low-Voltage Microcontroller Zilog

3-18 P R E L I M I N A R Y DS97LVO0601

PIN FUNCTIONS (Continued)

Figure 13. Port 3 Configuration

VDD

Out P34

T8_Out

CTR0, D0

Pad

Out P35

T16_Out

CTR2, D0

Out P36

T8/16_Out

CTR1, D6

P34

VDD

Pad

P35

VDD

Pad
P36

MUX

MUX

MUX

P3M D0
open-drain

P3M D0
open-drain

* Default after reset output is push-pull.

*

*

*

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-19

1

FUNCTIONAL DESCRIPTION

The Z8 CCP™ incorporates special functions to enhance
the Z8's functionality in consumer and battery operated ap­plications.

Reset. The device is reset in one of the following condi­tions:

■ Power-On Reset

■ Watch-Dog Timer

■ Stop-Mode Recovery Source

■ Low Voltage Detection

Program Memory. The Z86L7X addresses up to 4K and
8 Kbytes of internal program memory. (Figure 10). The first
12 bytes of program memory are reserved for the interrupt
vectors. These locations contain five 16-bit vectors that
correspond to the five available interrupts. Addresses 12
to 4K, and 8K (dependent on version) consist of on-chip
mask-programmed ROM.

External Data Memory. Not accessible using the 28-pin
Z86L79/80.

Expanded Register File. The register file has been ex­panded to allow for additional system control registers,
and for mapping of additional peripheral devices along
with I/O ports into the register address area. The Z8 regis­ter address space R0 through R15 has now been imple­mented as 16 groups of 16 registers per group. These reg­ister groups are known as the ERF (Expanded Register
File). Bits 7-4 of register RP select the working register
group. Bits 3-0 of register RP select the expanded register
group (Figure 15).

The upper nibble of the register pointer (Figure 12) selects
which group of 16 bytes in the register file, out of the full
256, will be accessed. The lower nibble selects the ex­panded register file bank and, in the case of the Z86L79/80
Banks F and D are implemented. A 0H in the lower nibble
will allow the normal register file to be addressed, but any
other value from 1H to FH will exchange the lower 16 reg­isters in favor of an expanded register group of 16 regis­ters.

For example:
Z86L79/80: (See Figure 15)
R253 RP = 00H

R0 = Port 0
R1 = Port 1
R2 = Port 2

R3 = Port 3
But if:
R253 RP = 0DH

R0 = CTRL0
R1 = CTRL1
R2 = CTRL2
R3 = Reserved

The counter/timers are mapped into ERF group D. Access
is easily done using the following example:

LD RP, #0DH Select ERF D for access and register Bank

0 as the working register group
LDR0,#xx access CTRL0
LD1, #xx access CTRL1
LDRP, #7DH Select expanded register group(ERF) Bank

D for access and register Group 7 as the working regis-

ter Group.
LD R1, 2 CTRL2 → register 71H

Figure 14. Program Memory Map

11

10

9

8

7

6

5

4

3

2

1

0

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

Reserved

IRQ4

IRQ4

IRQ3

IRQ3

IRQ2

IRQ2

IRQ1

IRQ1

IRQ0

IRQ0

Reserved

8191

On-Chip

ROM

Reset Start Address

12

Z86L79/80
Low-Voltage Microcontroller Zilog

3-20 P R E L I M I N A R Y

Figure 15. Expanded Register File Architecture

7

6543210

Working Register

Group Pointer

Expanded Register

Group Pointer

FF
FO

7F

0F

00

Z8 Register File**

REGISTER POINTER

FF
FE
FD
FC
FB
FA
F9

F8
F7
F6

F5

F4

F3

F2

F1

F0

SPL
SPH
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M

U
U

0
U
0

0
U
0

0

1

(F) 0F

(F) 0E
(F) 0D
(F) 0C

(F) 0B

(F) 0A
(F) 09
(F) 08

(F) 07
(F) 06
(F) 05
(F) 04

(F) 03
(F) 02

(F) 01

(F) 00

WDTMR

SMR

U
U
0

U

U
0
U
1
0
1

U
U

0
U
U

0

U

0

0

1

U
U

0
U
U

0
U

0

0

1

U
U
0

U

U
0
U
1
0

1

U
U
0

U

U
0
U
1
0

1

U
U
0
U
U
0
U
0
0
1

U
U
0

U

U
0

U
1
0
1

UUU 0 1

101

001000U0

REGISTER**

EXPANDED REG. GROUP (F)

RESET CONDITION

REGISTER**

Z8® STANDARD CONTROL REGISTERS

RESET CONDITION

D7 D6

D5 D4

D3 D2 D1

D0

Reserved

*
*

*

†

Reserved
SMR2
Reserved

Reserved
Reserved
Reserved
Reserved
Reserved

Reserved

UUUUU

UU

U

UUUUUUUU
UUU

UUUUU

UUUUUUU

U

0

0

000000

0U

U

00

00

0

Reserved
Reserved
Reserved
Reserved
Reserved
PCON

U

0

*

*

00 00UU

UU

UU

UUUUUU

UU

UU

UUU

U

UUU

UUU

UU

REGISTER**

EXPANDED REG. GROUP (0)

RESET CONDITION

(0) 03

P3

(0) 02

P2
(0) 01 P1
(0) 00

P0

U = Unknown
* Will not be reset with a Stop-Mode Recovery

** All addresses are in Hexadecimal

*
*
*
*

† Will not be reset with a Stop-Mode Recovery,
except Bit 0.

Reserved
Reserved

Reserved
Reserved

Reserved

U0U00 0UU

EXPANDED REG. GROUP (D)

REGISTER**

(D) 0C
(D) 0B
(D) 0A

(D) 09
(D) 08

(D) 07

(D) 06

(D) 05

(D) 04
(D) 03
(D) 02

Reserved
HI8

L08
HI16
L016
TC16H

TC16L

TC8H

TC8L

Reserved

CTR2

RESET CONDITION

U

UU

U

UUUUUUU
U
U
U

U

U
U
U

0

UUUUU

U

U

U

U

U

U

U

UUUUUU

U
U
U
U
U

U

U
U
U
U
U

U

UUU0

UUUU

U
U

U
U

UU
UUU
UUU
UUU

(D) 01 CTR1
(D) 00 CTR0

00UUUUU U

0

UUUUUU

Reserved

U

U

U

U

U

U

0

Z86L79/80
Low-Voltage Microcontroller Zilog

3-21 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Register File. The register file consists of four I/O port reg-

isters, 236 general-purpose registers with 10 control and
status registers (R3-R0, R239-R4, and R255-R246, re­spectively), plus three Expanded Register Groups (0, D,
and F) which reside in the expanded register group. In­structions can access registers directly or indirectly
through an 8-bit address field. This allows a short, 4-bit
register address using the Register Pointer (Figure 14). In
the 4-bit mode, the register file is divided into 16 working
register groups, each occupying 16 continuous locations.
The Register Pointer addresses the starting location of the
active working register group.

Note: Register Bank E0-EF is only accessed through
working registers and indirect addressing modes. R240­R245 registers are reserved.

Stack. The Z86L7X external data memory or the internal
register file is used for the stack. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides within the
general-purpose registers (R4-R239). SPH is used as a
general-purpose register only when using internal stacks.

Note: When SPH is used as a general-purpose register
and Port 0 is in address mode, the contents of SPH will be
loaded into Port 0 whenever the internal stack is accessed

Figure 16. Register Pointer

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register
File Pointer

Working Register
Pointer

R253 RP

Default Setting After Reset = 0000 0000

Figure 17. Register Pointer

The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group

r7r6r5r

4

R253

I/O Ports

Specified Working

Register Group

The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register

r3r2r1r

0

Register Group 0

FF

Register Group 1

2F

1F

0F

00

10

20

F0

R15 to R4
R3 to R0

R15 to R0

R15 to R0

Z86L79/80
Low-Voltage Microcontroller Zilog

3-22 P R E L I M I N A R Y

Counter/Timer Register Description

.

HI8(D)%0B: Holds the captured data from the output of the
8-bit Counter/Timer0. This register is typically used to hold
the number of counts when the input signal is 1.

L08(D)%0A: Holds the captured data from the output of
the 8-bit Counter/Timer0. This register is typically used to
hold the number of counts when the input signal is 0.

HI16(D)%09: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the MS­Byte of the data.

L016(D)%08: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the LS­Byte of the data.

TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register.

TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register.

TC8H(D)%05: Counter/Timer8 High Hold Register.

TC8L(D)%04: Counter/Timer8 Low Hold Register.

Expanded Register Group D

(D)%0C Reserved
(D)%0B HI8
(D)%0A LO8

(D)%09 HI16
(D)%08 LO16
(D)%07 TC16H
(D)%06 TC16L
(D)%05 TC8H
(D)%04 TC8L
(D)%03 Reserved
(D)%02 CTR2
(D)%01 CTR1

Field Bit Position Description

T8_Capture_HI 76543210 RWCaptured Data

No Effect

Field Bit Position Description

T8_Capture_L0 76543210 RWCaptured Data

No Effect

Field

Bit

Position Description

T16_Capture_HI 76543210 RWCaptured Data

No Effect

Field Bit Position Description

T16_Capture_LO 76543210 RWCaptured Data

No Effect

Field

Bit

Position Description

T16_Data_HI 76543210 R/W Data

Field Bit Position Description

T16_Data_LO 76543210 R/W Data

Field Bit Position Description

T8_Level_HI 76543210 R/W Data

Field

Bit

Position Description

T8_Level_LO 76543210 R/W Data

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-23

1

CTR0 (D)00: Counter/Timer8 Control Register.

Field Bit Position Value Description

T8_Enable 7------- R

W

0*

1
0
1

Counter Disabled
Counter Enabled
Stop Counter
Enable Counter

Single/Modulo-N -6------- R/W 0*

1

Modulo-N
Single Pass

Time_Out --5------ R0

1
0
1

No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0

T8 _Clock ---43--- R/W 0 0*

0 1
1 0
1 1

SCLK
SCLK/2
SCLK/4
SCLK/8

Capture_INT_MASK -----2-- R/W 0

1

Disable Data Capture Int.
Enable Data Capture Int.

Counter_INT_Mask ------1- R/W 0

1

Disable Time-Out Int.
Enable Time-Out Int

P34_Out -------0 R/W 0

1

P34 as Port Output
T8 Output on P34

Notes:

* Indicates the value upon Power-On Reset.

Z86L79/80
Low-Voltage Microcontroller Zilog

3-24 P R E L I M I N A R Y

CTR0: Counter/Timer8 Control Register Description
T8 Enable. This field enables T8 when set (written) to 1.
Single/Modulo-N. When set to 0 (modulo-n), the counter

reloads the initial value when the terminal count is
reached. When set to 1 (single pass), the counter stops
when the terminal count is reached.

Time-Out. This bit is set when T8 times out (terminal count
reached). To reset this bit, a 1 should be written to this lo­cation. This is the only way to reset this status condi-

tion, therefore, care should be taken to reset this bit
prior to using/enabling the counter/timers.

Note: Care must be taken when utilizing the OR or AND

commands to manipulate CTR0, bit 5 and CTR1, bits 0
and 1 (Demodulation Mode). These instructions use a
Read-Modify-Write sequence in which the current status
from the CTR0 and CTR1 registers will be ORed or ANDed
with the designated value and then written back into the
registers. Example: When the status of bit 5 is 1, a reset
condition will occur.

T8 Clock. Defines the frequency of the input signal to T8.
Capture_INT_Mask. Set this bit to allow interrupt when

data is captured into either LO8 or HI8 upon a positive or
negative edge detection in demodulation mode.

Counter_INT_Mask. Set this bit to allow interrupt when T8
has a time out.

P34_Out. This bit defines whether P34 is used as a normal
output pin or the T8 output.

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-25

1

CTR1(D)%01: Controls the functions in common with the T8 and T16.

Field Bit Position Value Description

Mode 7------- R/W 0

1

Transmit Mode
Demodulation Mode

P36_Out/
Demodulator_Input

-6------ R/W
0
1

0
1

Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
P20

T8/T16_Logic/
Edge _Detect

--54---- R/W

00
01
10
11

00
01
10
11

Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved

Transmit_Submode/
Glitch_Filter

----32-- R/W

00
01
10
11

00
01
10
11

Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out =0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
16 SCLK Cycle

Initial_T8_Out/
Rising_Edge

------1-

R/W

R

W

0
1

0
1
0
1

Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0

Initial_T16_Out/
Falling _Edge

-------0

R/W

R
R

0
1

0
1
0
1

Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0

Z86L79/80
Low-Voltage Microcontroller Zilog

3-26 P R E L I M I N A R Y

CTR1 Register Description
Mode. If it is 0, the Counter/Timers are in the transmit

mode, otherwise they are in the demodulation mode.
P36_Out/Demodulator_Input. In Transmit Mode, this bit

defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.

In Demodulation Mode, this bit defines whether the input
signal to the Counter/Timers is from P20 or P31.

T8/T16_Logic/Edge _Detect. In Transmit Mode, this field
defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).

In Demodulation Mode, this field defines which edge
should be detected by the edge detector.

Transmit_Submode/Glitch Filter. In Transmit Mode, this
field defines whether T8 and T16 are in the "Ping-Pong"
mode or in independent normal operation mode. Setting
this field to "Normal Operation Mode" terminates the "Ping­Pong Mode" operation. When set to 10, T16_OUT is im­mediately set to A0. When set to 11, T16 is immediately
forced to a 1.

In Demodulation Mode, this field defines the width of the
glitch that should be filtered out.

Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the
output of T8 is set to 0 when it starts to count. If 1, the out­put of T8 is set to 1 when it starts to count. Note: When
(CTR1, D1, D0) Bits are loaded, T8_OUT and T16_OUT
will switch to the opposite state. This ensures a transition
to the initial value once the counters are enabled. There­fore, it is not advisable to change (CTR1, D1, D0) Bits
while the counters are running.

In Demodulation Mode, this bit is set to 1 when a rising
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.

Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,
the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This
bit is effective only in Normal or Ping-Pong Mode (CTR1,
D3, D2).

In Demodulation Mode, this bit is set to 1 when a falling
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-27

1

CTR2 (D)%02: Counter/Timer16 Control Register.

Field Bit Position Value Description

T16_Enable 7------- R

W

0*

1
0
1

Counter Disabled
Counter Enabled
Stop Counter
Enable Counter

Single/Modulo-N -6------ R/W

0
1

0
1

Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize Edge

Time_Out --5----- R 0 No Counter Time-Out

Counter Time-Out Occurred
No Effect
Reset Flag to 0

T16 _Clock ---43--- R/W 00

01
10
11

SCLK
SCLK/2
SCLK/4
SCLK/8

Capture_INT_Mask -----2-- R/W 0

1

Disable Data Capture Int.
Enable Data Capture Int.

Counter_INT_Mask ------1- R/W 0

1

Disable Time-Out Int.
Enable Time-Out Int.

P35_Out -------0 R/W 0

1

P35 as Port Output
T16 Output on P35

Note: *Indicates the value upon Power-On Reset.

Z86L79/80
Low-Voltage Microcontroller Zilog

3-28 P R E L I M I N A R Y

CTR2 Description
T16_Enable. This field enables T16 when set to 1.

Single/Modulo-N. In Transmit Mode, when set to 0, the

counter reloads the initial value when terminal count is
reached. When set to 1, the counter stops when the termi­nal count is reached.

In Demodulation Mode, when set to 0 , T16 captures and
reloads on detection of all the edges; when set to 1, T16
captures and detects on the first edge, but ignores the sub­sequent edges. For details, see the description of T16 De­modulation Mode.

Time_Out. This bit is set when T16 times out (terminal
count reached). In order to reset it, a 1 should be written to
this location.

T16_Clock. Defines the frequency of the input signal to
Counter/Timer16.

Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into LO16 and HI16.

Counter_INT_Mask. Set this bit to allow interrupt when
T16 times out.

P35_Out. This bit defines whether P35 is used as a normal
output pin or T16 output.

SMR2(F)%0D: Stop-Mode Recovery Register 2.

Field Bit Position Value Description

Reserved 7------- 0 Reserved (Must be 0)
Recovery Level -6------ W0*

1

Low

High
Reserved --5----- 0 Reserved (Must be 0)
Source ---432-- W 000*

001
010
011
100
101
110
111

A. POR Only

B. NAND of P23-P20

C. NAND or P27-P20

D. NOR of P33-P31

E. NAND of P33-P31

F. NOR of P33-P31, P00,P07

G. NAND of P33-P31,P00,P07

H. NAND of P33-P31,P22-P20
Reserved ------10 00 Reserved (Must be 0)

Note: *Indicates the value upon Power-On Reset.

Z86L79/80
Low-Voltage Microcontroller Zilog

3-29 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Port pins configured as outputs are ignored as an SMR2
recover source. For example, if NAND of P23-P20 is se­lected as the recover source and P20 is configured as out-

put, then P20 is ignored as a recover source. The effective
recover source in this case is NAND of P23-P21.

Figure 18. Glitch Filter Circuitry

Glitch

Filter

Edge

Detector

CTR1 D5,D4

CTR1 D3,D2

Pos Edge
Neg Edge

MUX

CTR1 D6

P31

P20

Figure 19. 8-Bit Counter/Timer Circuits

Z8 Data Bus

Pos Edge
Neg Edge

CTR0 D2

IRQ4

CTR0 D1

T8_OUT

TC8LTC8H

Clock

Select

SCLK

CTR0 D4, D3

Clock

8-Bit

Counter T8

HI8

LO8

Z8 Data Bus

Z86L79/80
Low-Voltage Microcontroller Zilog

3-30 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Input Circuit

The edge detector monitors the input signal on P31 or P20.
Based on CTR1 D5-D4, a pulse is generated at the Pos
Edge or Neg Edge line when an edge is detected. Glitches
in the input signal which have a width less than specified
(CTR1 D3, D2) are filtered out.

T8 Transmit Mode

When T8 is enabled, the output of T8 depends on CTR1,
D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0.

When T8 is enabled, the output T8_OUT switches to the
initial value (CTR1 D1). If the initial value (CTR1 D1) is 0,
TC8L is loaded, otherwise TC8H is loaded into the
counter. In Single-Pass Mode (CTR0 D6), T8 counts down
to 0 and stops, T8_OUT toggles, the time-out status bit
(CTR0 D5) is set, and a time-out interrupt can be generat­ed if it is enabled (CTR0 D1) (Figure 22). In Modulo-N
Mode, upon reaching terminal count, T8_OUT is toggled,
but no interrupt is generated. Then T8 loads a new count
(if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT,

sets the time-out status bit (CTR0 D5) and generates an
interrupt if enabled (CTR0 D1) (Figure 23). This completes
one cycle. T8 then loads from TC8H or TC8L according to
the T8_OUT level, and repeats the cycle.

The user can modify the values in TC8H or TC8L at any
time. The new values take effect when they are loaded.
Care must be taken not to write these registers at the time
the values are to be loaded into the counter/timer, to en­sure known operation. An initial count of 1 is not allowed (a
non-function will occur). An initial count of 0 will cause TC8
to count from 0 to %FF to %FE (Note, % is used for hexa­decimal values). Transition from 0 to %FF is not a time-out
condition.

Note: Using the same instructions for stopping the
counter/timers and setting the status bits is not recom­mended. Two successive commands, first stopping the
counter/timers, then resetting the status bits is necessary.
This is required because it takes one counter/timer clock
interval for the initiated event to actually occur.

Figure 20. T8_OUT in Single-Pass Mode

TC8H Counts

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

T8_OUT Toggles,

Time-Out Interrupt

Figure 21. T8_OUT in Modulo-N Mode

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

T8_OUT Toggles

T8_OUT TC8L TC8H TC8L TC8H TC8L

Time-Out Interrupt

Time-Out Interrupt

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-31

1

T8 Demodulation Mode

The user should program TC8L and TC8H to %FF. After
T8 is enabled, when the first edge (rising, falling, or both
depending on CTR1 D5, D4) is detected, it starts to count
down. When a subsequent edge (rising, falling, or both de­pending on CTR1 D5, D4) is detected during counting, the
current value of T8 is one's complemented and put into
one of the capture registers. If it is a positive edge, data is

put into LO8, if negative edge, HI8. One of the edge detect
status bits (CTR1 D1, D0) is set, and an interrupt can be
generated if enabled (CTR0 D2). Meanwhile, T8 is loaded
with %FF and starts counting again. Should T8 reach 0,
the time-out status bit (CTR0 D5) is set, an interrupt can be
generated if enabled (CTR0 D1), and T8 continues count­ing from %FF (Figure 22).

Figure 22. Demodulation Mode Count Capture Flowchart

T8 (8-Bit)

Count Capture

T8_Enable

(Set By User)

No

Yes

Edge Present

No

Yes

What Kind Of Edge

Pos

T8 → L08

Neg

T8 → HI8

%FF → T8

Z86L79/80
Low-Voltage Microcontroller Zilog

3-32 P R E L I M I N A R Y

Figure 23. Transmit Mode Flowchart

T8 (8-Bit)

Transmit Mode

T8_Enable Bit Set

CTR0, D7

No

Yes

CTR1, D1

Value

1

Load TC8L

Reset T8_OUT

Load TC8H

Set T8_OUT

Enable T8

Reset T8_Enable Bit

Set Time-out Status Bit

(CTR0 D5) and Generate

Timeout_Int If Enabled

No

T8_Timeout

Yes

Single Pass?

Modulo-N

T8_OUT Value

Load TC8L

Reset T8_OUT

Load TC8H

Set T8_OUT

Enable T8

No

T8_Timeout

Disable T8

Yes

Set Time-out Status Bit

(CTR0 D5) and Generate

Timeout_Int If Enabled

Single Pass

0

1

0

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-33

1

Figure 24. Demodulation Mode Flowchart

T8 (8-Bit)

Demodulation Mode

T8_Enable

CTR0, D7

No

Yes

Edge Present

No

T8_Enable Bit Set

Yes

Set Edge Present Status

Bit And Trigger Data

Capture Int. If Enabled

No

%FF → TC8

Yes

Enable TC8

Edge Present

Disable T8

Yes

T8 Time Out

Yes

Set Time-out Status

Bit And Trigger Time

Out Int. If Enabled

No

Continue Counting

Z86L79/80
Low-Voltage Microcontroller Zilog

3-34 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

T16 Transmit Mode

In Normal or Ping-Pong Mode, the output of T16 when not
enabled is dependent on CTR1, D0. If it is a 0, T16_OUT
is a 1; if it is a 1, T16_OUT is 0. The user can force the out­put of T16 to either a 0 or 1 whether it is enabled or not by
programming CTR1 D3, D2 to a 10 or 11.

When T16 is enabled, TC16H * 256 + TC16L is loaded,
and T16_OUT is switched to its initial value (CTR1 D0).
When T16 counts down to 0, T16_OUT is toggled (in Nor­mal or Ping-Pong Mode), an interrupt is generated if en­abled (CTR2 D1), and a status bit (CTR2 D5) is set. Note
that global interrupts will override this function as de­scribed in the interrupts section. If T16 is in Single-Pass
Mode, it is stopped at this point. If it is in Modulo-N Mode,
it is loaded with TC16H * 256 + TC16L and the counting
continues.

The user can modify the values in TC16H and TC16L at
any time. The new values take effect when they are load­ed. Care must be taken not to load these registers at the
time the values are to be loaded into the counter/timer, to
ensure known operation. An initial count of 1 is not al­lowed. An initial count of 0 will cause T16 to count from 0
to %FF FF to %FFFE. Transition from 0 to %FFFF is not a
time-out condition.

Figure 25. 16-Bit Counter/TImer Circuits

Z8 Data Bus

Pos Edge
Neg Edge

CTR0 D2

IRQ4

CTR0 D1

T8_OUT

TC8LTC8H

Clock

Select

SCLK

CTR0 D4, D3

Clock

8-Bit

Counter T8

HI8

LO8

Z8 Data Bus

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-35

1

T16 Demodulation Mode

The user should program TC16L and TC16H to %FF. After
T16 is enabled, when the first edge (rising, falling, or both
depending on CTR1 D5, D4) is detected, begins to count
down.

If D6 of CTR2 is 0: When a subsequent edge (rising, fall­ing, or both depending on CTR1 D5, D4) is detected during
counting, the current count in T16 is one's complemented
and put into HI16 and LO16. When data is captured, one
of the edge detect status bits (CTR1 D1, D0) is set and an
interrupt is generated if enabled (CTR2 D2). T16 is loaded
with %FFFF and starts again.

If D6 of CTR2 is 1: T16 ignores the subsequent edges in
the input signal and continues counting down. A time out
of T8 will cause T16 to capture its current value and gen­erate an interrupt if enabled (CTR2, D2). In this case, T16
does not reload and continues counting. If D6 bit of CTR2
is toggled (by writing a 0 then a 1 to it), T16 will capture and
reload on the next edge (rising, falling, or both depending
on CTR1 D5, D4) but continue to ignore subsequent edg­es.

Should T16 reach 0, it continues counting from %FFFF;
meanwhile, a status bit (CTR2 D5) is set and an interrupt
time-out can be generated if enabled (CTR2 D1).

Figure 26. T16_OUT in Single-Pass Mode

TC16H*256+TC16L Counts

“Counter Enable” Command,

T16_OUT Switches To Its

Initial Value (CTR1 D0)

T16_OUT Toggles,
Time-Out Interrupt

Figure 27. T16_OUT in Modulo-N Mode

TC16H*256+TC16L

“Counter Enable” Command,

T16_OUT Switches To Its

Initial Value (CTR1 D0)

T16_OUT Toggles,
Time-Out Interrupt

TC16H*256+TC16L

TC16H*256+TC16L

T16_OUT Toggles,

Time-Out Interrupt

T16_OUT

Z86L79/80
Low-Voltage Microcontroller Zilog

3-36 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Ping-Pong Mode

This operation mode is only valid in Transmit Mode. T8
and T16 need to be programmed in Single-Pass Mode
(CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be
programmed in CTR1 D3, D2. The user can begin the op­eration by enabling either T8 or T16 (CTR0 D7 or CTR2
D7). For example, if T8 is enabled, T8_OUT is set to this
initial value (CTR1 D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count
is reached, T8 is disabled and T16 is enabled. T16_OUT
switches to its initial value (CTR1 D0), data from TC16H

and TC16L is loaded, and T16 starts to count. After T16
reaches the terminal count it stops, T8 is enabled again,
and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2
D1). To stop the Ping-Pong operation, write 00 to bits D3
and D2 of CTR1.

Note:Enabling Ping-Pong operation while the
counter/timers are running may cause intermittent
counter/timer function. Disable the counter/timers, then

reset the status flags prior to instituting this operation.

To Initiate Ping-Pong Mode

First, make sure both counter/timers are not running. Then
set T8 into Single-Pass Mode (CTR0 D6), set T16 into Sin­gle-Pass Mode (CTR2 D6), and set Ping-Pong Mode
(CTR1 D2, D3). These instructions do not have to be in
any particular order. Finally, start Ping-Pong Mode by en­abling either T8 (CTR0 D7) or T16 (CTR2 D7).

During Ping-Pong Mode

The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will
be cleared by hardware. The time-out bits (CTR0 D5,
CTR2 D5) will be set every time the counter/timers reach
the terminal count.

Figure 28. Ping-Pong Mode

Enable

TC8

Time-Out

Enable

TC16

Time-Out

Ping-Pong

CTR1 D3,D2

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-37

1

Figure 29. T8_OUT and T16_OUT in Ping-Pong Mode

TC8H

Enable T8,

T8_OUT Switches

To Its Initial Value

TC16H*256+TC16L

T16_OUT Toggles

T8_OUT

TC8H

TC16H*256+TC16L

T16_OUT

T16_OUT

T16_OUT Switches To Its Initial
Value When TC16 Is Enabled

T8_OUT Toggles

T8_OUT Toggles

Figure 30. Output Circuit

AND/OR/NOR/NAND

Logic

T8_OUT

CTR1 D5,D4

P34_INTERNAL

CTR0 D0

P36_INTERNAL

CTR1 D6

P35_INTERNAL

CTR2 D0

P35_EXT

P36_EXT

P34_EXT

MUX

MUX

MUX

T16_OUT

MUX

CTR1, D2

CTR1 D3

Z86L79/80
Low-Voltage Microcontroller Zilog

3-38 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Interrupts. The Z86L7X has five different interrupts. The

interrupts are maskable and prioritized (Figure 31). The
five sources are divided as follows: three sources are
claimed by Port 3 lines P33-P31, the remaining two by the

counter/timers (Table 3). The Interrupt Mask Register glo­bally or individually enables or disables the five interrupt
requests.

Figure 31. Interrupt Block Diagram

Interrupt

Edge

Select

IRQ Register (D6, D7)

IRQ 1, 3, 4

IRQ

IMR

IPR

Priority

Logic

5

Vector Select

IRQ0

IRQ2

Global

Interrupt

Enable

Interrupt
Request

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-39

1

When more than one interrupt is pending, priorities are re­solved by a programmable priority encoder controlled by
the Interrupt Priority register. An interrupt machine cycle is
activated when an interrupt request is granted. This dis­ables all subsequent interrupts, saves the Program
Counter and Status Flags, and then branches to the pro­gram memory vector location reserved for that interrupt.
All Z86L7X interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.

An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge trig­gered, and are programmable by the user. The software
can poll to identify the state of the pin.

Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6. The configu­ration is shown in Table 4.

Clock. The Z86L7X on-chip oscillator has a high-gain, par­allel-resonant amplifier for connection to a crystal, LC, ce­ramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 1 MHz to 8 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The Z86L7X on-chip
oscillator may be driven with a cost-effective RC network
or other suitable external clock source.

Table 3. Interrupt Types, Sources, and Vectors

Name Source

Vector

Location Comments

IRQ0 /DAV0, IRQ0 0, 1 External (P32),

Rising Falling Edge
Triggered

IRQ1, IRQ1 2, 3 External (P33),

Falling Edge
Triggered

IRQ2 /DA V2, IRQ2,

T

IN

4, 5 External (P31),

Rising Falling Edge

Triggered
IRQ3 T16 6, 7 Internal
IRQ4 T8 8, 9 Internal
IRQ5 10,11 Software generated

Table 4. IRQ Register

IRQ Interrupt Edge

D7 D6 IRQ2 IRQ0

00FF
01FR
10RF
1 1 R/F R/F

Notes:

F = Falling Edge
R = Rising Edge

In analog mode, the Stop-Mode Recovery sources select­ed by the SMR register are connected to IRQ1 input. Any
of the Stop-Mode Recovery sources for SMR (except P31,
P32, and P33) can be used to generate IRQ1 (falling edge
triggered).

Z86L79/80
Low-Voltage Microcontroller Zilog

3-40 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

The crystal should be connected across XTAL1 and
XTAL2 using the suppliers recommended capacitors from
each pin to ground. The RC oscillator configuration is an
external resistor connected from XTAL1 to XTAL2, with a
frequency-setting capacitor from XTAL1 to ground (Figure

32).
Power-On Reset (POR). A timer circuit clocked by a ded-

icated on-board RC oscillator is used for the Power-On Re­set (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execu­tion begins.

The POR timer circuit is a one-shot timer triggered by one
of three conditions:

1. Power Fail to Power OK status including waking up
from Low Voltage standby mode.

2. Stop-Mode Recovery (if D5 of SMR = 1).

3. WDT Time-Out.

The POR time is a nominal 5 ms. Bit 7 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock, RC,
LC oscillators).

HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter­rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
or internally generated. An interrupt request must be exe­cuted (enabled) to exit HALT mode. After the interrupt ser­vice routine, the program continues from the instruction af­ter the HALT.

STOP. This instruction turns off the internal clock and ex­ternal crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP mode is terminated only
by a reset, such as WDT time-out, POR, SMR, or external
reset. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode = FFH)
immediately before the appropriate sleep instruction, i.e.,

FF NOP ; clear the pipeline
6F STOP ; enter STOP mode

or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode

Note: A WDT time-out during STOP mode will have the
same effect like a recovery from any programmed STOP
mode recovery source except the reset delay of TPOR will
occur.

Note: The comparators are disabled in STOP mode.
Port Configuration Register (PCON). The PCON regis-

ter configures the comparator output on Port 3. It is locat­ed in the expanded register file at Bank F, location 00 (Fig­ure 33).

Figure 32. Oscillator Configuration

XTAL1

XTAL2

C1

C2

C1

C2

C1

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

Ceramic Resonator or Crystal

C1, C2 = 47 pF TYP *
f = 8 MHz

LC

C1, C2 = 22 pF
L = 130 µH *

f = 3 MHz *

RC

@ 3V VCC (TYP)
C1 = 33 pF *

R = 1K *

External Clock

L

R

* Preliminary value including pin parasitics

C1

32 kHz XTAL
C1 = 20 pF, C = 33 pF
Rd = 56 - 470K
Rf =10 M

Rf

C2 Rd

XTAL1

XTAL2

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-41

1

Comparator Output Port 3 (D0). Bit 0 controls the com-

parator used in Port 3. A 1 in this location brings the com­parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.

Stop-Mode Recovery Register (SMR). This register se­lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 34). All bits are write only ex­cept bit 7, which is read only. Bit 7 is a flag bit that is hard­ware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 con­trols the reset delay after recovery. Bits 2, 3, and 4, the
SMR register, specify the source of the Stop-Mode Recov­ery signal. Bits 0 and 1 determine the frequency of
SCLK/TCLK in relation to the OSC. The SMR is located in
Bank F of the Expanded Register Group at address 0BH.

Figure 33. Port Configuration Register (PCON)

(Write Only)

Reserved (Must be 1)

D7 D6 D5

D4

D3 D2 D1 D0

PCON (FH) 00H

Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output

* Default Setting After Reset

Z86L79/80
Low-Voltage Microcontroller Zilog

3-42 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Figure 34. Stop-Mode Recovery Register

D7 D6 D5 D4 D3 D2 D1 D0

SMR (0F) 0B

SCLK/TCLK Divide-by-16
0 OFF
1 ON

External Clock DIvide By 2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL

Stop-Mode Recovery Source
000

001
010
011
100
101
110
111

Stop Delay
0 OFF
1 ON*

Stop Recovery Level
0 Low*
1 High

Stop Flag
0 POR*
1 Stop Recovery**

* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery

**

POR Only*
Reserved
P31
P32
P33
P27
P2 NOR 0-3
P2 NOR 0-7

Figure 35. SCLK Circuit

SMR, D0

÷

16

OSC

SCLK
TCLK

÷2

SMR, D1

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-43

1

Figure 36. Stop-Mode Recovery Source

P00

P32

VCC

P31

P32

P33

P27

P20
P23

P20
P27

SMR D40D30D2

0

SMR D40D31D2

0

SMR D40D31D2

1

SMR D41D30D2

0

SMR D41D30D2

1

SMR D41D31D2

0

SMR D41D31D2

1

SMR2 D40D30D2

0

SMR2 D40D31D2

0

SMR2 D40D31D2

1

SMR2 D41D30D2

0

SMR2 D41D30D2

1

SMR2 D41D31D2

0

SMR2 D41D31D2

1

SMR2 D40D30D2

1

VCC

P20

P32

P23

P20
P27

P31
P33

P31
P33

P32

P31
P33

P00
P07

P32

P31
P33
P07

P20

P32

P31
P33
P21

P22

SMR2 D6

SMR D6

To RESET and WDT
Circuitry (Active Low)

S1

S2

S3

S4

To IRQ1

Z86L79/80
Low-Voltage Microcontroller Zilog

3-44 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR

controls a Divide-by-16 prescaler of SCLK/TCLK. The pur­pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources interrupt
logic). After Stop-Mode Recovery, this bit is set to a 0.

External Clock divide-by-two (D1). This bit can eliminate
the oscillator divide-by-two-circuitry. When this bit is 0, the
System Clock (SCLK) and Timer Clock (TCLK) are equal
to the external clock frequency divided-by-two. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of
PCON further helps lower EMI (i.e., D7 (PCON)=0, D1
(SMR) = 1). The default setting is zero. Maximum external
clock frequency is 4 MHz when SMR Bit D1=1 where
SCLK/TCLK=XTAL.

Note: When changing the system clock from either to
or to divide-by-two or divide-by-16, you must follow
the instruction with two NOP's in order to avoid clock
conflicts during the internal system clock frequency
change.

Stop-Mode Recovery Source (D2, D3, and D4). These

three bits of the SMR specify the wake up source of the
STOP recovery (Figure 34 and Table 5).

Stop-Mode Recovery Delay Select (D5). This bit, if High,
disables the 5 ms /RESET delay after Stop-Mode Recov­ery. The default configuration of this bit is one. If the "fast"
wake up is selected, the Stop-Mode Recovery source
needs to be kept active for at least 5TpC.

Stop-Mode Recovery Edge Select (D6). A 1 in this bit po­sition indicates that a High level on any one of the recovery
sources wakes the Z86L7X from STOP mode. A 0 indi­cates Low level recovery. The default is 0 on POR (Figure

36).
Cold or Warm Start (D7). This bit is set by the device

upon entering STOP mode. A 0 in this bit (cold) indicates
that the device will be reset by POR/WDT Reset. A 1 in this
bit (warm) indicates that the device awakens by a SMR
source. This is a READ only bit.

Table 5. Stop-Mode Recovery Source

SMR: 432 Operation

D4 D3 D2 Description of Action

0 0 0 POR and/or external

reset recovery
0 0 1 Reserved
0 1 0 P31 transition
0 1 1 P32 transition
1 0 0 P33 transition
1 0 1 P27 transition
1 1 0 Logical NOR of P20

through P23
1 1 1 Logical NOR of P20

through P27

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-45

1

Watch-Dog Timer Mode Register (WDTMR). The WDT

is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be en­abled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.

The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the

time-out period. Bit 2 determines whether the WDT is ac­tive during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 33). This reg­ister is accessible only during the first 64 processor cycles
(64 internal system clocks) from the execution of the first
instruction after Power-On-Reset, Watch-Dog Reset, or a
Stop-Mode Recovery (Figure 40). After this point, the reg­ister cannot be modified by any means, intentional or oth­erwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register Group at address loca­tion 0FH. It is organized as follows:

Figure 37. Watch-Dog Timer Mode Register (Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

WDTMR (0F) F

WDT TAP INT RC OSC External Clock
00 5 ms 256 TpC
01* 10 ms 512 TpC
10 20 ms 1024 TpC
11 80 ms 4096 TpC

WDT During HALT
0 OFF
1 ON *

WDT During STOP
0 OFF
1 ON *

XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL

Reserved (Must be 0)

* Default Setting After Reset

Z86L79/80
Low-Voltage Microcontroller Zilog

3-46 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

WDT Time Select (D0, D1). Selects the WDT time period.

It is configured as shown in Table 6.

Note: The WDT can be permanently enabled through a
mask programming option. The option is selected by the
customer at the time of ROM code submittal. In this mode,
WDT is always activated when the device comes out of re­set. Execution of the WDT instruction serves to refresh the
WDT time-out period. WDT operation in the HALT and
STOP modes is controlled by WDTMR programming. If
this mask option is not selected at the time of ROM code
submission, the WDT must be activated by the user
through the WDT instruction and is always disabled by any
reset to the device.

WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.

WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Since the
XTAL clock is stopped during STOP mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.

Note: A WDT time-out during STOP mode will have the
same effect like a recovery from any programmed STOP
mode recovery source except the reset delay will occur.

Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil­lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu­ration of this bit is 0, which selects the RC oscillator.

Table 6. WDT Time Select

D1 D0

Time-Out of

Internal RC

OSC

Time-Out of
XTAL Clock

0 0 5 ms min 256 TpC
0 1 10 ms min 512 TpC
1 0 20 ms min 1024 TpC
1 1 80 ms min 4096 TpC

Notes:

TpC = XTAL clock cycle.
The default on reset is 10 ms.

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-47

1

Figure 38. Resets and WDT

CLK

18 Clock RESET

Generator

RESET

Clear

WDT TAP SELECT

RC
OSC.

CK

CLR

5 ms POR

5 ms

15 ms 25 ms 100 ms

2V Operating
Voltage Det.

Internal
RESET

WDT Select

(WDTMR)

CK Source

Select

(WDTMR)

XTAL

VDD

2V REF.

From Stop

Mode

Recovery

Source

WDT

Stop Delay

Select (SMR)

12 ns Glitch Filter

+

-

4 Clock

Filter

WDT/POR Counter Chain

M

U
X

Z86L79/80
Low-Voltage Microcontroller Zilog

3-48 P R E L I M I N A R Y DS97LVO0601

FUNCTIONAL DESCRIPTION (Continued)

Low Voltage Protection. An on-board Voltage Compara-

tor checks that VCC is at the required level to ensure cor­rect operation of the device. Reset is globally driven if V

CC

is below VLV (Low Voltage). The minimum operating volt­age varies with the temperature and operating frequency,
while VLV varies with temperature only.

Mask Selectable Options. There are six Mask Selectable
Options to choose from based on ROM code require­ments. These are:

*When WDT is selected as always on, the WDT will run in
HALT or STOP mode regardless of the settings in the
WDTMR Register Bits D2&D3.

The Low Voltage trip voltage (V

LV

) is less than 2.1V under

the following conditions:
Maximum (VLV) Conditions:
TA = 0°C, +55°C Internal clock frequency equal to or less

than 4.0 MHz
Note: The internal clock frequency is one-half the external

clock frequency.

The device functions normally at or above 2.0V under all
conditions. Below 2.0V, the device is guaranteed to func­tion normally until the Low Voltage Protection trip point V

LV

is reached, below which reset is globally driven and then
the device is put in a low current stand by mode with the
oscillator stopped. The device is guaranteed to function
normally at supply voltages above the VLV trip point for the
temperatures and operating frequencies in maximum V

LV

conditions. The actual VLV trip point is a function of tem­perature and process parameters (Figure 39).

Clock Source RC/Other

Port 0 Pull-ups (lower nibble) On/Off

Port 0 Pull-ups (upper nibble) On/Off

Port 2 Pull-ups On/Off
Port 3 Pull-ups On/Off
Mouse/Normal M/N

WDT Always On On/Off*

Figure 39. Typical Z86L7X Low Voltage vs.

Temperature at 8 MHz

0

15

25

35

45

55

1.8

1.6

1.4

1.2
1

1.8

0.6

0.4

0.2
0

VLV

VLV

Temperature

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-49

1

EXPANDED REGISTER FILE CONTROL REGISTERS (0D)

Figure 40. TC8 Control Register

((0D) 0H: Read/Write Accept Where Noted)

D7 D6 D5 D4 D3 D2 D1 D0

CTR0 (0D) 0H

0 P34 as Port Output*
1 Timer8 Output

0 Disable T8 Time Out Interrupt
1 Enable T8 Time Out Interrupt

0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt

00 SCLK on T8
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8

R 0 No T8 Counter Time Out
R 1 T8 Counter Time Out Occured
W 0 No Effect
W 1 Reset Flag to 0

* Default Setting After Reset

0 Modulo-N
1 Single Pass

R 0 T8 Disabled *
R 1 T8 Enabled
W 0 Stop T8
W 1 Enable T8

Z86L79/80
Low-Voltage Microcontroller Zilog

3-50 P R E L I M I N A R Y

Figure 41. T8 and T16 Common Control Functions

((0D) 1H: Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

CTR1 (0D) 1H

0 T16_OUT is 0 Initially
1 T16_OUT is 1 Initially

R/W

R
R

W
W

0 No Falling Edge Detection
1 Falling Edge Detection

0 No Effect
1 Reset Flag to 0

0 T8_OUT is 0 Initially
1 T8_OUT is 1 Initially

0 No Rising Edge Detection
1 Rising Edge Detection

0 0 Normal Operation
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1

Transmit Mode/T8/T16 Logic

0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved

0 P36 as Port Output*
1 P36 as T8/T16_OUT

0 Transmit Mode*
1 Demodulation Mode

0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 16 SCLK Cycle Filter

Demodulation Mode

Transmit Mode

Transmit Mode*
R/W

Demodulation Mode
R

R
W

W
Transmit Mode

Demodulation Mode

0 0 AND
0 1 OR
1 0 NOR
1 1 NAND

Demodulation Mode

Transmit Mode

0 P31 as Demodulator Input
1 P20 as Demodulator Input

Demodulation Mode

Transmit/Demodulation Modes

0 No Effect
1 Reset Flag to 0

Note: Care must be taken in differentiating
Transmit Mode from Demodulation Mode.
Depending on which of these two modes is
operating, the CTR1 bit will have different
functions.

Note: Changing from one mode to
another cannot be done without
disabling the counter/timers.

*Default setting after reset.

Z86L79/80
Low-Voltage Microcontroller Zilog

3-51 P R E L I M I N A R Y DS97LVO0601

EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)

Figure 42. T16 Control Register

((0D) 2H: Read/Write Except Where Noted)

D7 D6 D5 D4 D3 D2 D1 D0

CTR2 (0D) 02H

0 P35 is Port Output*
1 P35 is TC16 Output

0 Disable T16 Time-Out Interrupt
1 Enable T16 Time-Out Interrupt

0 0 SCLK on T16
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16

* Default Setting After Reset

0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt

R 0 No T16 Time Out
R 1 T16 Time Out Occurs
W 0 No Effect
W 1 Reset Flag to 0

0 Modulo-N for T16
1 Single Pass for T16

R 0 T16 Disabled *
R 1 T16 Enabled
W 0 Stop T16
W 1 Enable T16

Transmit Mode

0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge

Demodulator Mode

Z86L79/80
Low-Voltage Microcontroller Zilog

3-52 P R E L I M I N A R Y

Figure 43. Stop-Mode Recovery Register

((F) 0BH: D6-D0 = Write Only,

D7 D6 D5 D4 D3 D2 D1 D0

SMR (0F) 0B

SCLK/TCLK Divide-by-16
0 OFF
1 ON

External Clock DIvide By 2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL

Stop-Mode Recovery Source
000

001
010
011
100
101
110
111

Stop Delay
0 OFF
1 ON*

Stop Recovery Level
0 Low*
1 High

Stop Flag
0 POR*
1 Stop Recovery**

* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery

**

POR Only*
Reserved
P31
P32
P33
P27
P2 NOR 0-3
P2 NOR 0-7

Z86L79/80
Low-Voltage Microcontroller Zilog

3-53 P R E L I M I N A R Y DS97LVO0601

EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)

Figure 44. Stop-Mode Recovery Register 2

((0F) DH: D2-DH, D6 Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

SMR2 (0F) 0DH

Reserved (Must be 0)
Reserved (Must be 0)

Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22

Reserved (Must be 0)
Recovery Level

0 Low*
1 High

Reserved (Must be 0)

Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.

*Default Setting After Reset

Z86L79/80
Low-Voltage Microcontroller Zilog

3-54 P R E L I M I N A R Y

Figure 45. Watch-Dog Timer Mode Register

((F) OFH: Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

WDTMR (0F) F

WDT TAP INT RC OSC External Clock
00 5 ms 256 TpC
01* 10 ms 512 TpC
10 20 ms 1024 TpC
11 80 ms 4096 TpC

WDT During HALT
0 OFF
1 ON *

WDT During STOP
0 OFF
1 ON *

XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL

Reserved (Must be 0)

* Default Setting After Reset

Figure 46. Port Configuration Register (PCON)

((0F) OH: Write Only)

Reserved (Must be 1)

D7 D6 D5

D4

D3 D2 D1 D0

PCON (FH) 00H

Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output

* Default Setting After Reset

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-55

1

Z8® STANDARD CONTROL REGISTER DIAGRAMS

Figure 47. Port 3 Mode Register

(F7H; Write Only)

Figure 48. Port 0 and 1 Mode Register

(F8H: Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

R247 P3M

0 Port 2 Open-Drain*†
1 Port 2 Push-pull

0 P32 = Input*
P35 = Output**
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0

0 Digital
1 Analog

Reserved (Must be 0)

† Effects P34 and P35 as well
* Default setting after reset
** Output status controlled by P3M, D0

D7 D6 D5 D4 D3 D2 D1 D0

R248 P01M

P00-P03 Mode
00 Output
01 Input*
1X A11-A8

P07-P04 Mode
00 Output
01 Input*
1X A15-A12

* Default Setting After Reset.

Reserved (Must be 1)
Reserved (Must be 0)

Figure 49. Interrupt Priority Registers

((0) F9H: Write Only

Figure 50. Interrupt Request Register

((0) FAH: Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt Group Priority

000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved

IRQ3, IRQ5 Priority (Group A)

0 IRQ5 > IRQ3
1 IRQ3 > IRQ5

IRQ0, IRQ2 Priority (Group B)

0 IRQ2 > IRQ0
1 IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0 IRQ1 > IRQ4
1 IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

D7 D6 D5 D4 D3 D2 D1 D0

IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0 (L03 Software only)
IRQ5 = T1

Inter Edge

00 P31 ↓ P32 ↓
01 P31 ↓ P32 ↑
10 P31 ↑ P32 ↓
11 P31 ↑↓ P32 ↑↓

R250 IRQ

Z86L79/80
Low-Voltage Microcontroller Zilog

3-56 P R E L I M I N A R Y DS97LVO0601

Z8® STANDARD CONTROL REGISTER DIAGRAMS (Continued)

Figure 51. Interrupt Mask Register

((0) FBH: Read/Write)

Figure 52. Flag Register

((0) FCH: Read/Write)

Figure 53. Register Pointer

((0) FDH: Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (Must be 0)

1 Enables IRQ4-IRQ0
(D0 = IRQ0)

0 Master Interrupt Disable*
1 Master Interrupt Enable

R251 IMR

* Default Setting After Reset

Reserved (Must be 0)

D7 D6 D5 D4 D3 D2 D1 D0

User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag

R252 Flags

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register
File Pointer

Working Register
Pointer

R253 RP

Default Setting After Reset = 0000 0000

Figure 54. Port 2 Mode Register

(F6H: Write Only)

Figure 55. Stack Pointer High

((0) FEH: Read/Write)

Figure 56. Stack Pointer Low

((0) FFH: Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

P27-P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*

R246 P2M

*Default Setting After Reset

D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer Upper
Byte (SP15-SP8)

R254 RP

D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer Lower
Byte (SP - SP )

7

0

R255 SPL

Z86L79/80

Zilog Low-Voltage Microcontroller

P R E L I M I N A R Y 3-57

1

PACKAGE INFORMATION

Figure 57. 28-Pin DIP Package Diagram

Figure 58. 28-Pin SOIC Package Diagram

Z86L79/80
Low-Voltage Microcontroller Zilog

3-58 P R E L I M I N A R Y

ORDERING INFORMATION
Z86L79/80

8.0 MHz
28-pin DIP 28-pin SOIC

Z86L7908PSC Z86L7908SSC
Z86L8008PSC Z86L8008SSC

For fast results, contact your local Zilog sales office for as­sistance in ordering the part desired.

Codes
Package

P = Plastic DIP
S = SOIC

Temperature

S = 0°C to +70°C

Speed

8 = 8.0 MHz

Environmental

C = Plastic Standard

© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.

Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
FAX [phone]
Internet: http://www.zilog.com

Example:

Z 86L79/80 08 P S C

Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix

is a Z86L79/80, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow