Datasheet Z86127 Datasheet (ZILOG)

GENERAL DESCRIPTION

C

USTOMER PROCUREMENT SPECIFICATION

Z86127

LOW-COST DIGITAL
TELEVISION CONTROLLER (LDTC)

The Z86127 Low-Cost Digital Television Controller (LDTC)
introduces a new level of sophistication to single-chip
architecture. The Z86127 is a member of the Z8® single­chip microcontroller family with 8 Kbytes of ROM and 236
bytes of RAM. The device is housed in a 64-pin DIP
package, in which only 52 are active, and are CMOS
compatible. The LDTC offers mask programmed ROM
which enables the Z8 microcontroller to be used in a high
volume production application device embedded with a
custom program (customer supplied program).

Zilog’s LDTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation
capabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The
device provides an ideal performance and reliability solution
for consumer and industrial television applications.

The Z86127 architecture is characterized by utilizing Zilog’s
advanced Superintegration™ design methodology. The
device has an 8-bit internal data path controlled by a Z8
microcontroller and On Screen Display (OSD) logic circuits/
Pulse Width Modulators (PWM). On-chip peripherals
include two register mapped I/O ports (Ports 2 and Port 3),
interrupt control logic (one software, two external and three
internal interrupts) and a standby mode recovery input
port (Port 3, pin P30).

The OSD control circuits support 8 rows by 20 columns of
characters. The character color is specified by row. One of
the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying either low resolution (5x7 dot pattern)
or high resolution (11x15 dot pattern) characters. The
Z86C97 currently supports high resolution characters only.

A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Five 8-bit
PWM ports are used to vary picture levels.

The LDTC applications demand powerful I/O capabilities.
The Z86127 fulfills this with 27 I/O pins dedicated to input
and output. These lines are grouped into four ports, and
are configurable under software control to provide timing,
status signals, parallel I/O and an address/data bus for
interfacing to external memory.

There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general purpose registers, two I/O Port
registers, 15 control and status registers and three reserved
registers.

To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the LDTC offers two on-chip counter/timers with a large
number of user selectable modes (Functional Block
Diagram).

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

Ground GND V

CC

V

DD

SS

DC-4063-00 (10-16-91)

1

GENERAL DESCRIPTION (Continued)

g

p

g

play

XTAL1
XTAL2

/RESET

P30
P31
P34
P35
P36

P50( P00 )
P51( P01 )
P52( P02 )
P53( P03 )
P54( P04 )
P55( P05 )
P56( P06 )
P57( P07 )
P60( /AS )
P61( /DS )

P62( R//W )

P63( SCLK )

P64( P66 )*
P65( P67 )*

AFCIN

RESET

Oscillator

WDT

Counter

Timer

Counter

Timer

Port 3/

Interru

Port 5

(Port 0)

Port 6

(Control)

8 KByte

ram ROM

Pro

Port 2

Z8 CPU

Core

t

PWM 1

256 Byte

ister File

Re

Port 0

A8:15 AD0:7

160 Byte

Character RAM

4 KByte

Character ROM

Port 1

14 -bit

PWM 6

to

PWM 8

6-bit

PWM 9

to

PWM 13

8-bit

On Screen

Dis

P27
P26
P25
P24
P23
P22
P21
P20

PWM 1

PWM 6
PWM 7
PWM 8
PWM 9
PWM 10
PWM 11
PWM 12
PWM 13

OSCIN
OSCOUT
HSYNC
VSYNC
VRED
VGREEN
VBLUE
VBLANK

Functional Block Diagram

2

PIN CONFIGURATION

T

N/C
N/C
N/C
N/C

PWM1

P35
P36
P34
P31

P30
XTAL1
XTAL2

/RESE

P60

GND

P61

P62

VCC

P63

P64

P65

AFCIN

P50

P51

P52

P53

P54

P55

P56

P57

OSCIN

OSCOUT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Z86127

(LDTC)

64
63
62
61
60
59
58

57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
P27
P26
P25
P24
P23

GND
P22
P21

VCC
P20

N/C

N/C

N/C

N/C

N/C

N/C

N/C

N/C
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC

64-Pin Mask-ROM Plastic DIP

3

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any

sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

condition above those indicated in the operational

Symbol Parameters Min Max Units Notes

V

CC

V

I

V

I

V

O

I

OH

I

OH

I

OL

I

OL

I

OL

T

A

T

STG

Notes:

[1] Port 2 open drain
[2] PWM open-drain outputs
[3] Port 5
* Voltage on all pins with respect to GND.
† See Ordering Information

Power Supply Voltage* -0.3 +7 V
Input Voltage -0.3 VCC+0.3 V
Input Voltage -0.3 VCC+0.3 V [1]
Output Voltage -0.3 VCC+8.0 V [2]
Output Current High -10 mA 1 pin

Output Current High -100 mA All total
Output Current Low 20 mA 1 pin
Output Current Low 40 mA [3] (1 pin)
Output Current Low 200 mA All total
Operating Temperature †
Storage Temperature -65 +150 C

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).

CAPACITANCE

TA=25°C; VCC=GND=0V; Freq=1.0 MHz; unmeasured pins to GND.

Parameter Max Units

From Output
Under Test

150 pF

Test Load Diagram

VDD

RLL

RLH

Input capacitance 10 pF
Output capacitance 20 pF
I/O capacitance 25 pF
AFCIN input capacitance 10 pF

4

DC CHARACTERISTICS

TA=0°C to +70°C; VCC=+4.5V to +5.5V; F

Sym Parameter TA=0°C to +70°C Typical Units Conditions

=4 MHz

OSC

Min Max @ 25°C

V

IL

V

ILC

V

IH

V

IHC

V

HY

V

PU

V

OL

V

00-01

V

01-11

V

OH

I

IR

I

IL

I

OL

I

CC

I

CC1

I

CC2

Notes:

[1] Port 5
[2] PWM open drain

Input Voltage Low 0 0.2 V
Input XTAL/Osc In Low 0.07 V
Input Voltage XTAL/Osc In High 0.7 V

Input XTAL/Osc in High 0.8 V
Schmitt Hysteresis 0.1 V
Maximum Pull-up Voltage 12 V [2]

Output Voltage Low 0.4 0.16 V IOL=1.00mA

AFC Level 01 In 0.45 V
AFC Level 11 In 0.5 V
Output Voltage High VCC-0.4 4.75 V IOH=-0.75mA

Reset Input Current -80 -46 µAVRL=0V
Input Leakage -3.0 3.0 0.01 µA 0V,V
Tri-State Leakage -3.0 3.0 0.02 µA 0V,V

Supply Current 20 13.2 mA All inputs at rail

CC

CC

CC

CC

1.48 V

CC

0.98 V External Clock Generator Driven

CC

V

CC

V

CC

3.2 V External Clock Generator Driven

3.0 V External Clock Generator Driven

0.8 V

0.4 0.19 V IOL=3.2mA, [1]

0.4 0.19 V IOL=0.75mA [2]

1.5 1.00 V IOL=10mA [1]

1.9 V

CC

0.75 V

CC

3.12 V

CC

CC

6 3.2 mA All inputs at rail

10 0 µA All inputs at rail

5

AC CHARACTERISTICS

Timing Diagrams

XTAL1

Tin

1

3

External Clock

7 5

4

6

3

2

2

IRQn

Counter Timer

8 9

Interrupt Request

6

Vcc

Internal /RESET

External /RESET

HSYNC

OSC2

10

Power On Reset

11

12

1413

On Screen Display

7

AC CHARACTERISTICS

TA=0° C to +70° C; VCC=+4.5V to +5.5V; F

No Symbol Parameter Min Max Unit

1 TpC Input Clock Period 250 1000 ns
2 TrC,TfC Clock Input Rise and Fall 15 ns
3 TwC Input Clock Width 70 ns
4 TwTinL Timer Input Low Width 70 ns

5 TwTinH Timer Input High Width 3TpC
6 TpTin Timer Input Period 8TpC
7 TrTin,TfTin Timer Input Rise and Fall 100 ns
8a TwIL Int Req Input Low 70 ns

8b TwIL 3TpC
9 TwIH Int Request Input High 3TpC
10 TdPOR Power On Reset Delay 25 100 ms
11 TdLVIRES Low Voltage Detect to 200 ns

Internal RESET Condition

12 TwRES Reset Minimum Width 5TpC
13 TdHsOI H
14 TdHsOh H
15 TdWDT WDT Refresh Time 12 ms

Note:

Refer to DC Characteristics for details on switching levels.

Start to V

sync

End to V

sync

osc

osc

=4 MHz,

OSC

Stop 2TpV 3TpV

Start 1TpV

© 1991 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-

8

chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
Telex 171-980 A/B ZILOG CPTO
FAX [phone]