Datasheet Z8018110FEC Datasheet (ZILOG)

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Zilog

FEATURES

SMART ACCESS CONTROLLER SAC

Z80181

PRELIMINARY PRODUCT SPECIFICATION

Z80181

SMART ACCESS CONTROLLER (SAC

™

)

™

■ Z80180 Compatible MPU Core with 1 Channel of

Z85C30 SCC, Z80 CTC, Two 8-Bit General-Purpose Parallel Ports, and Two Chip Select Signals.

■ High Speed Operation (10 MHz)

■ Low Power Consumption in Two Operating Modes:

- (TBD) mA Typ. (Run Mode)

- (TBD) mA Typ. (STOP Mode)

■ Wide Operational Voltage Range (5V ±10%)

■ TTL/CMOS Compatible

■ Clock Generator

■ One Channel of Z85C30 Serial Communication

Controller (SCC)

GENERAL DESCRIPTION

The Z80181 SAC™ Smart Access Controller (hereinafter, referred to as Z181 SAC) is a sophisticated 8-bit CMOS microprocessor that combines a Z180-compatible MPU (Z181 MPU), one channel of Z85C30 Serial Communication Controller (SCC), a Z80 CTC, two 8-bit general-purpose parallel ports, and two chip select signals, into a single 100-pin Quad Flat Pack (QFP) package (Figures 1 and 2). Created using Zilog's patented Superintegration methodology of combining proprietary IC cores and cells, this high-end intelligent peripheral controller is well-suited for a broad range of intelligent communication control applications such as terminals, printers, modems, and slave communication processors for 8-, 16- and 32- bit MPU based systems.

■ Z180 Compatible MPU Core Includes:

- Enhanced Z80 CPU Core

- Memory Management Unit (MMU) Enables Access to 1MB of Memory

- Two Asynchronous Channels

- Two DMA Channels

- Two 16-Bit Timers

- Clocked Serial I/O Port

■ On-Board Z84C30 CTC

■ Two 8-Bit General-Purpose Parallel Ports

■ Memory Configurable RAM and ROM Chip Select Pins

■ 100-Pin QFP Package

Information on enhancement/cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 applications is also included in this product specification.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).

™

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

Ground GND V

DD SS

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GENERAL DESCRIPTION (Continued)

SMART ACCESS CONTROLLER SAC

Z80181

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D7-D0

Control

A19-A0

/ROMCS

/RAMCS

Compatible

A19-A12

Z80180

Core

(1 Channel)

Glue

Logic

Address

Decode

Logic

Z80181 = Z180 + SCC/2 + CTC + PIA

SCC

CTC

PIA1

PIA2

Tx Data Rx Data Modem/Control

Signals

Bit Programmable

Bi-directional I/O or I/O Pins of CTC

Bit Programmable Bi-directional I/O

Figure 1. Z80181 Functional Block Diagram

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PIN DESCRIPTION

Z80181

SMART ACCESS CONTROLLER SAC

/WAIT

EXTAL

GND

/RESET

/BUSREQ

/BUSACK

/INTO

/NMI

XTAL

A17

PHI

/RD

/WR

/M1E/MREQ

/IORQ

/RFSH

+5V

/HALT

™

/INT1 /INT2

A0 A1 A2

A15

A4 A5 A6

A7 A8 A9

A10 A11 A12

GND

A13

A14 A16

D0 D1 D2 D3 D4 D5 D6 D7

/RAMCS

100

100-Pin QFP

Z80181

50454035

/TEND1 /DREQ1 CKS RxS//CTS1 TxS CKA1//TEND0 RxA1

TEST TxA1 CKA0//DREQ0 RxA0 TxA0 /DCD0 /CTS0 /RTS0 A18/TOUT A19 GND IEI /ROMCS IEO GND /DCD /CTS /RTS /DTR//REQ TxD /TRxC RxD /W//REQ

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PIA10

+5V

PIA11

PIA12

PIA13

PAI14

PIA15

PIA16

PIA17

GND

PIA20

PIA21

PIA22

PIA23

Figure 2. 100-Pin QFP Pin Configuration

PIA24

PIA25

PIA26

PIA27

/RTxC

/SYNC

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SMART ACCESS CONTROLLER SAC

CPU SIGNALS

Pin Name Pin Number Input/Output, Tri-State Function

A19 - A0 4-17, 19-21, I/O, Active 1 Address Bus. A19 - A0 form a 20-bit address bus which

64, 65, 91 specifies I/O and memory addresses to be accessed.

During the refresh period, addresses for refreshing are output. The address bus enters a high-impedance state during Reset and external bus acknowledge cycles. The bus is an input when the external bus master is accessing the on-chip peripherals. Address line A18 is multiplexed

Z80181

with the output of PRT Channel 1 (T output on Reset).

D0-D7 22-29 I/O, Active 1 8-Bit Bidirectional Data Bus. When the on-chip CPU is

accessing on-chip peripherals, these lines are outputs and hold the data to/from the on-chip peripherals.

/RD 89 I/O, Active 0 Read Signal. CPU read signal for accepting data from

memory or I/O devices. When an external master is accessing the on-chip peripherals, it is an input signal.

/WR 88 I/O, Active 0 Write Signal. This signal is active when data to be stored

in a specified memory or peripheral device is on the MPU data bus. When an external master is accessing the onchip peripherals, it is an input signal.

, selected as address

OUT

™

/MREQ 85 I/O, tri-state, Active 0 Memory Request Signal. When an effective address for

memory access is on the address bus, /MREQ is active. This signal is analogous to the /ME signal of the Z64180.

/IORQ 84 I/O, tri-state, Active 0 I/O Request Signal. When addresses for I/O are on the

lower 8 bits (A7-A0) of the address bus in the I/O operation, “0” is output. In addition, the /IORQ signal is output with the /M1 signal during the interrupt acknowledge cycle to inform peripheral devices that the interrupt response vector is on the data bus. This signal is analogous to the /IOE signal of the Z64180.

/M1 87 I/O, tri-state, Active 0 Machine Cycle “1”. /MREQ and /M1 are active together

during the operation code fetch cycle. /M1 is output for every opcode fetch when a two byte opcode is executed. In the maskable interrupt acknowledge cycle, this signal is output together with /IORQ. It is also used with /HALT and ST signal to decode the status of the CPU Machine cycle. This signal is analogous to the /LIR signal of the Z64180.

/RFSH 83 Out, tri-state, Active 0 The Refresh Signal. When the dynamic memory

refresh address is on the low order 8-bits of the address bus (A7 - A0), /RFSH is active along with the /MREQ signal. This signal is analogous to the /REF signal of the Z64180.

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SMART ACCESS CONTROLLER SAC

Pin Name Pin Number Input/Output, Tri-State Function

/INT0 100 Wired-OR I/O, Active 0 Maskable Interrupt Request 0. Interrupt is generated by

peripheral devices. This signal is accepted if the interrupt enable Flip-Flop (IFF) is set to “1”. Internally, the SCC and CTC’s interrupt signals are connected to this line, and require an external pull-up resistor.

/INT1, 1, 2, In, Active 0 Maskable Interrupt Request 1 and 2. This signal is /INT2 generated by external peripheral devices. The CPU hon-

ors these requests at the end of current instruction cycle as long as the /NMI, /BUSREQ and /INT0 signals are inactive. The CPU will acknowledge these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for /INT0, during this cycle, neither /M1 or /IORQ will become active.

/NMI 99 In, Active 0 Non-Maskable Interrupt Request Signal. This interrupt

request has a higher priority than the maskable interrupt request and does not rely upon the state of the interrupt enable Flip-Flop (IFF).

/HALT 81 Out, tri-state, Active 0 Halt Signal. This signal is asserted after the CPU has

executed either the HALT or SLP instruction, and is waiting for either non-maskable interrupt maskable interrupt before operation can resume. It is also used with the /M1 and ST signals to decode the status of the CPU machine cycle.

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/BUSREQ 97 In, Active 0 BUS Request Signal. This signal is used by external

devices (such as a DMA controller) to request access to the system bus. This request has higher priority than /NMI and is always recognized at the end of the current machine cycle. This signal will stop the CPU from executing further instructions and place the address bus, data bus, /MREQ, /IORQ, /RD and /WR signals into the high impedance state. /BUSREQ is normally wired-OR and a pull-up resistor is externally connected.

/BUSACK 96 Out, Active 0 Bus Acknowledge Signal. In response to /BUSREQ sig-

nal, /BUSACK informs a peripheral device that the address bus, data bus, /MREQ, /IORQ, /RD and /WR signals have been placed in the high impedance state.

/WAIT 95 Wired-OR I/O, Active 0 Wait Signal. /WAIT informs the CPU that the specified

memory or peripheral is not ready for a data transfer. As long as /WAIT signal is active, the MPU is continuously kept in the wait state. Internally, the /WAIT signal from the SCC interface logic is connected to this line, and requires an external pull-up resistor.

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SMART ACCESS CONTROLLER SAC

PERIPHERAL SIGNALS

Pin Name Pin Number Input/Output, Tri-State Function

RXA0, RXA1 70, 74 In, Active 1 ASCI Receive Data 0 and 1. These signals are the receive

data to the ASCI channels.

TXA0, TXA1 69, 72 Out, Active 1 ASCI Transmit Data 0 and 1. These signals are the

receive data to the ASCI channels. Transmit data changes are with respect to the falling edge of the transmit clock.

/RTS0 66 Out, Active 0 Request to Send 0. This is a programmable modem

control signal for ASCI channel 0.

/DCD0 68 In, Active 0 Data Carrier Detect 0. This is a programmable modem

control signal for ASCI channel 0.

/CTS0 67 In, Active 0 Clear To Send 0. This is a programmable modem control

signal for ASCI channel 0.

/CTS1/RXS 77 In, Active 0 Clear To Send 0/Clocked Serial Receive Data. This is a

programmable modem control signal for ASCI channel 0. Also, this signal becomes receive data for the CSIO channel under program control. On power-on Reset, this pin is set as RxS.

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CKA0//DREQ0 71 I/O, Active 1 Asynchronous Clock0/DMAC0 Request. This pin is the

transmit and receive clock for the Asynchronous channel

0. Also, under program control, this pin is used to request a DMA transfer from DMA channel 0. DMA0 monitors this input to determine when an external device is ready for a read or write operation. On power-on Reset, this pin is initialized as CKA0.

CKA1//TEND0 75 I/O, Active 1 Asynchronous Clock1/DMAC0 Transfer End. This pin is

the transmit and receive clock for the Asynchronous channel 1. Also, under program control, this pin becomes /TEND0 and is asserted during the last write cycle of the DMA0 operation and is used to indicate the end of the block transfer. On power-on Reset, this pin initializes as CKA1.

/TEND1 80 Out, Active 0 DMAC1 Transfer End. This pin is asserted during the last

write cycle of the DMA1 operation and is used to indicate the end of the block transfer.

CKS 78 I/O, Active 1 CSIO Clock. This line is the clock for the CSIO channel. TXS 76 Out, Active 1 CSI/O Tx Data. This line carries the transmit data from the

CSIO channel.

/DREQ1 79 In, Active 0 DMAC1 Request. This pin is used to request a DMA

transfer from DMA channel 1. DMA1 monitors this input to determine when an external device is ready for a read or write operation.

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SMART ACCESS CONTROLLER SAC

SCC SIGNALS

Pin Name Pin Number Input/Output, Tri-State Function

/W//REQ 51 Active 0 Wait/Request. Open-drain when programmed for a Wait

function, driven “1” or “0” when programming for a Request function. Used as /WAIT or /REQUEST depending upon SCC programming. When programmed as /WAIT, this signal is asserted to alert the CPU that addressed memory or I/O devices are not ready and that the CPU should wait. When programmed as /REQUEST, this signal is asserted when a peripheral device associated with a DMA port is ready to read/write data. After reset, this pin becomes “/WAIT”.

/SYNC 50 I/O, Active 0 Synchronization. This pin can act either as input, output,

or part of the crystal oscillator circuit. In asynchronous receive mode (crystal oscillator option not selected), this pin is an input similar to /CTS and /DCD. In this mode, transitions on this line affect the state of the Sync/Hunt status bit in Read Register 0 but has no other function.

In external sync mode with crystal oscillator option not selected, this line also acts as an input. In this mode, /SYNC must be driven “0” two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of /SYNC.

Z80181

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In internal sync mode (Monosync and Bisync) with the crystal oscillator option not selected, this line acts as output and is active only during the part of the receive clock cycle in which a synchronous character is recognized (regardless of character boundaries). In SDLC mode, this pin acts as an output and is valid on receipt of a flag.

RxD 52 In, Active 1 Receive Data. This input signal receives serial data at

standard TTL levels.

/RTxC 49 In, Active 0 Receive/Transmit Clock. This pin can be programmed in

several different modes of operation. /RTxC may supply the receive clock, the transmit clock, the clock for the Baud Rate Generator, or the clock for the Digital Phase-Locked Loop. This pin can also be programmed for use with the /SYNC pin as a crystal oscillator. The receive clocks can be 1, 16, 32, or 64 times the data transfer rate in Asynchronous mode.

/TRxC 53 I/O, Active 0 Transmit/Receive Clock. This pin can be programmed in

several different modes of operation. /TRxC can supply the receive clock or the transmit clock in the input mode. Also, it can supply the output of the Digital Phase-Locked Loop, the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode.

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SMART ACCESS CONTROLLER SAC

SCC SIGNALS (Continued)

Pin Name Pin Number Input/Output, Tri-State Function

TxD 54 Out, Active 1 Transmit Data. This Output signal transmits serial data at

standard TTL level.

/DTR//REQ 55 Out, Active 0 Data Terminal Ready/Request. This output follows the

state programmed into the DTR bit. It can also be used as general-purpose output or as Request line for a DMA controller.

/RTS 56 Out, Active 0 Request To Send. When the RTS bit in Write Register 5 is

set, the /RTS signal goes low. When the RTS bit is reset in Asynchronous mode and auto enable is on, the signal goes high after the transmitter is empty. In synchronous mode or in Asynchronous mode, with Auto Enable off, the /RTS pin follows the state of the RTS bit. This pin can be used as a general-purpose output.

/CTS 57 In, Active 0 Clear To Send. If this pin is programmed as auto enable,

a “0” on the input enables the transmitter. If not programmed as Auto Enable, it may be used as a generalpurpose input. This input is Schmitt-trigger buffered to accommodate inputs with slow rise times. The SCC detects pulses on this input and can interrupt the CPU on both logic level transitions.

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/DCD 58 In, Active 0 Data Carrier Detect. This pin functions as receiver enable

if it is programmed for auto enable. Otherwise, it may be used as a general-purpose input. This input is Schmitttrigger buffered to accommodate slow rise-time inputs. The SCC detects pulses on this input and can interrupt the CPU on both logic level transitions.

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SMART ACCESS CONTROLLER SAC

PIA/CTC SIGNALS

Pin Name Pin Number Input/Output, Tri-State Function

PIA17-PIA14 35-38 I/O Port 1 Data 7-Port 1 Data 4 or CTC ZC/TO3 - ZC/TO0.

These lines can be configured as inputs or outputs on a bit

-by-bit basis. Also, under program control, these bits become Z80 CTC’s ZC/TO3 - ZC/TO0, and in either timer or counter mode, pulses are output when the down counter has reached zero. On reset, these signals function as PIA17-14 and are inputs.

PIA13-PIA10 31-34 I/O Port 1 Data 3-Port 1 Data 0 or CTC CLK/TRG3-0. These

lines can be configured as inputs or outputs on a bit by bit basis. Also, under program control, these bits become Z80 CTC’s CLK/TRG3-CLK/TRG0, and correspond to four Counter/Timer Channels. In the counter mode, each active edge causes the downcounter to decrement by one. In timer mode, an active edge starts the timer. It is program selectable whether the active edge is rising or falling. On reset, these signals are set to PIA13-10 as inputs.

PIA27-20 41-48 I/O Port 2 Data. These lines are configured as inputs or

outputs on a bit-by-bit basis. On reset, they are inputs.

Z80181

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SMART ACCESS CONTROLLER SAC

SYSTEM CONTROL SIGNALS

Pin Name Pin Number Input/Output, Tri-State Function

ST 3 Out, Active 1 Status. This signal is used with the /M1 and /HALT output

to decode the status of the CPU machine cycle. Note that the /M1 output is affected by the status of the M1E bit in the OMCR register. The following table shows the status while M1E=1.

ST /HALT /M1 Operation

0 1 0 CPU Operation

(1st Opcode fetch)

1 1 0 CPU Operation

(2nd and 3rd Opcode fetch)

1 1 1 CPU Operation

(MC other than Opcode fetch) 0 X 1 DMA operation 0 0 0 HALT mode 1 0 1 SLEEP mode

(Incl. System STOP mode)

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SMART ACCESS CONTROLLER SAC

Pin Name Pin Number Input/Output, Tri-State Function

IEI 62 In, Active 1 Interrupt enable input signal. IEI is used with the IEO to

form a priority daisy chain when there is more than one interrupt-driven peripheral.

IEO 60 Out, Active 1 The interrupt enable output signal. In the daisy-chain

interrupt control, IEO controls the interrupt of external peripherals. IEO is active when IEI is “1” and the CPU is not servicing an interrupt from the on-chip peripherals.

/ROMCS 61 Out, Active 0 ROM Chip select. Used to access ROM. Refer to “Func-

tional Description” on chip select signals for further explanation.

/RAMCS 30 Out, Active 0 RAM Chip Select. Used to access RAM. Refer to “Func-

tional Description” on chip select signals for further explanation.

/RESET 98 In, Active 0 Reset signal. /RESET signal is used for initializing the MPU

and other devices in the system. It must be kept in the active state for a period of at least 3 system clock cycles.

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™

EXTAL 94 In, Active 1 Crystal oscillator connecting terminal. A parallel reso-

nant crystal is recommended. If an external clock source is used as the input to the Z180 Clock Oscillator unit, supply the clock into this terminal.

XTAL 93 Out Crystal oscillator connecting terminal. PHI 90 Out, Active 1 System Clock. Single-phase clock output from Z181

MPU.

E 86 Out, Active 1 Enable Clock. Synchronous Machine cycle clock output

during a bus transaction.

TEST 73 Out Test pin. Used in the open state.

39, 82 Power Supply. +5 Volts 18, 40, 59, Power Supply. 0 Volts

63, 92

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FUNCTIONAL DESCRIPTION

SMART ACCESS CONTROLLER SAC

Z80181

™

Functionally, the on-chip Z181 MPU, SCC, and CTC are the same as the discrete devices (Figure 1). Therefore, refer to the Product Specification/Technical Manual of

/RD

/RESET

/WR

A18 /TOUT

TxS

RxS//CTS

CKS

XTAL

Timing

Generator

Programmable

Reload Timers

EXTAL

16-Bit

(2)

Clocked

Serial I/O

Port

each discrete product for a detailed description of each individual unit. The following subsections describe each individual functional unit of the SAC.

/M1

/IORQ

/MREQ

/WAIT

/HALT

/BUSREQ

/BUSACK

/RFSH

/NMI

/INT0

/INT1

/INT2

Bus State Control Interrupt

CPU

/DREQ1

DMACs

/TEND

(2)

TxA0 CKA0 /DREQ0

Asynchronous

SCI

(Channel 0)

RxA0 /RTS0 /CTS0 /DCD0

Address Bus (16-Bit)

Data Bus (8-Bit)

MMU

A19-A0 D7-D0

Figure 3. Z181 MPU Block Diagram

Asynchronous

SCI

(Channel 1)

TxA1 CKA1 /TEND0 RxA1

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Z181 MPU

SMART ACCESS CONTROLLER SAC

Z80181

™

This unit provides all the capabilities and pins of the Zilog Z180 MPU. Figure 3 shows the Z181 MPU block diagram. This allows 100% software compatibility with existing Z180 (and Z80) software. Note that the on-chip I/O address should not be relocated to the I/O address (from 0C0h to 0FFh) to avoid address conflicts. The following is an overview of the major functional units of the Z181.

Z181 CPU

The Z181 CPU has 100% software compatibility with the Z80 CPU. In addition, the Z181 CPU has the following features:

Faster execution speed. The Z181 CPU is “fine tuned” making execution speed, on average, 10% to 20% faster than the Z80 CPU.

Enhanced DRAM Refresh Circuit. Z181 CPU’s DRAM refresh circuit does periodic refresh and generates an 8-bit refresh address. It can be disabled or the refresh period adjusted, through software control.

Enhanced Instruction Set. The Z181 CPU has seven additional instructions to those of the Z80 CPU which include the MLT (Multiply) instruction.

HALT and Low Power Modes of Operation. The Z181 CPU has HALT and low power modes of operation, which are ideal for the applications requiring low power consumption like battery operated portable terminals.

System Stop Mode. When the Z181 SAC is in SYSTEM STOP mode, it is only the Z181 MPU which is in STOP mode. The on-chip CTC and SCC continue their normal operation.

Instruction Set. The instruction set of the Z181 CPU is identical to the Z180. For more details about each transaction, please refer to the Data Sheet/Technical Manual for the Z180/Z80 CPU.

■ Maskable interrupt request operation

■ Trap and Non-Maskable interrupt request operation

■ HALT and low power modes of operation

■ Reset Operation

Memory Management Unit (MMU)

The Memory Management Unit (MMU) allows the user to “map” the memory used by the CPU (64K bytes of logical addressing space) into 1M bytes of physical addressing space. The organization of the MMU allows object code compatibility with the Z80 CPU while offering access to an extended memory space. This is accomplished by using an effective “common area-banked area” scheme.

DMA Controller

The Z181 MPU has two DMA controllers. Each DMA controller provides high-speed data transfers between memory and I/O devices. Transfer operations supported are memory to memory, memory to/from I/O, and I/O to I/O. Transfer modes supported are request, burst, and cycle steal. The DMA can access the full 1M bytes addressing range with a block length up to 64K bytes and can cross over 64K boundaries.

Asynchronous Serial Communication Interface (ASCI)

This unit provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels also support a multiprocessor communication format.

Programmable Reload Timer (PRT)

The Z181 MPU has two separate Programmable Reload Timers, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is system clock divided by 20. PRT channel 1 provides an optional output to allow for waveform generation.

Z181 CPU Basic Operation

Z181 CPU’s basic operation consists of the following events. These are identical to the Z180 MPU. For more details about each operation, please refer to the Data Sheet/Technical manual for the Z180.

■ Operation code fetch cycle

■ Memory Read/Write operation

■ Input/Output operation

■ Bus request/acknowledge operation

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Clocked Serial I/O (CSI/O)

The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple highspeed data connection to another CPU or MPU.

Programmable Wait State Generator

To ease interfacing with slow memory and I/O devices, the Z181 MPU unit has a programmable wait state generator. By programming the DMA/WAIT Control Register (DCNTL), up to three wait states are automatically inserted in memory and I/O cycles. This unit also inserts wait states during on-chip DMA transactions.

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FUNCTIONAL DESCRIPTION (Continued)

Baud Rate

Generator

Internal

Control

Logic

Channel

Registers

Internal BUS

10 X 19

Frame

Status

FIFO

Channel

Discrete

Control

& Status

SMART ACCESS CONTROLLER SAC

Z80181

} Serial Data } Channel Clocks

/SYNC /Wait

Modem, DMA, or Other Controls

™

Interrupt

Control

Lines

Interrupt

Control

Logic

Figure 4. SCC Block Diagram

Z85C30 Serial Communication Controller Logic Unit

This logic unit provides the user with a multi-protocol serial I/O channel that is completely compatible with the two channel Z85C30 SCC with the following exceptions:

Their basic functions as serial-to-parallel and parallel-toserial converters can be programmed by the CPU for a broad range of serial communications applications. This logic unit is capable of supporting all common asynchronous and synchronous protocols (Monosync, Bisync, and SDLC/HDLC, byte or bit oriented - Figure 4).

On the discrete version of the SCC (dual channel version), there are two registers shared between channels A and B, and two registers whose functions are different by channel. These are: WR2, WR9 (shared registers), and RR2 and RR3 (different functionality).

Following are the differences in functionality:

■ RR2 - Returns Unmodified Vector or modified vector

depends on the status of “VIS” (Vector Include Status) bit in WR9.

■ RR3 - Returns IP status (Ch.A side).

■ WR9 - Ch.B Software Reset command has no effect.

The PCLK for the SCC is connected to PHI (System clock), the /INT signal is connected to /INT0 signal internally (requires external pull-up resistor) and SCC is reset when /RESET input becomes active. Interrupt from the SCC is handled through Mode 2 interrupt. During the interrupt acknowledge cycle, the on-chip SCC interface circuit inserts two wait states automatically.

Z84C30 Counter/Timer Logic Unit

This logic unit provides the user with four individual 8-bit Counter/Timer Channels that are compatible with the Z84C30 CTC (Figure 5). The Counter/Timers are programmed by the CPU for a broad range of counting and timing applications. Typical applications include event counting, interrupt and interval counting, and serial baud rate clock generation.

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SMART ACCESS CONTROLLER SAC

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Each of the Counter/Timer Channels, designated Channels 0-3, have an 8-bit prescaler (when used in timer mode) and its own 8-bit counter to provide a wide range of count resolution. Each of the channels have their own Clock/Trigger input to quantify the counting process and an output to indicate zero crossing/timeout conditions.

Data

Control

CPU BUS

I/O

Internal Bus

These signals are multiplexed with the Parallel Interface Adapter 1 (PIA1). With only one interrupt vector programmed into the logic unit, each channel can generate a unique interrupt vector in response to the interrupt acknowledge cycle.

Internal

Control

Logic

/INT IEI IEO

ZC/TO

CLK/TRG

Mutiplexed with PIA1

Interrupt

Logic

Counter/

Timer

Logic

/RESET

Figure 5. CTC Block Diagram

Parallel Interface Adapter (PIA)

The SAC has two 8-bit Parallel Interface Adapter (PIA) Ports. The ports are referred to as PIA1 and PIA2. Each port has two associated control registers; a Data Register and a register to determine each bit’s direction (input or output). PIA1 is multiplexed with the CTC I/O pins. When the CTC I/O feature is selected, the CTC I/O functions override the PIA1 feature. Mode Selection is made through the System Configuration Register (Address: EDh; Bit D0). PIA1 has Schmitt-triggered inputs to have a better noise margin. These ports are inputs after reset.

Clock Generator

The SAC uses the Z181 MPU’s on-chip clock generator to supply system clock. The required clock is easily generated by connecting a crystal to the external terminals (XTAL, EXTAL). The clock output runs at half the crystal frequency. The system clock inputs of the SCC and the CTC are internally connected to the PHI output of the Z181 MPU.

XTAL

Crystal

Inputs

EXTAL

Figure 6. Circuit Configuration For Crystal

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FUNCTIONAL DESCRIPTION (Continued)

SMART ACCESS CONTROLLER SAC

Z80181

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Recommended characteristics of the crystal and the values for the capacitor are as follows (the values will change with crystal frequency).

Type of crystal: Fundamental, parallel type crystal (AT cut is recommended).

Frequency tolerance: Application dependent. CL, Load capacitance: Approximately 22 pF (acceptable range is 20-30 pF)

Rs, equivalent-series resistance: ≤ 30 Ohms Drive level: 10 mW (for ≤ 10 MHz crystal) 5 mW (for ≥ 10 MHz crystal)

CIN = C

= 15 ~ 22 pF.

OUT

Chip Select Signals

The SAC has two chip select (/RAMCS, /ROMCS) pins. /ROMCS is the chip select signal for ROM and /RAMCS is the chip select signal for RAM. The boundary value for each chip select signal is 8 bits wide allowing all memory accesses with addresses less than or equal to this boundary value. This causes assertion of the corresponding /CS pin. These features are controlled through the RAM upper boundary address register (I/O address EAh), RAM lower boundary address register (I/O address EBh) and ROM upper boundary address register (I/O address ECh).

These two signals are generated by decoding address lines A19-A12. Note that glitches may be observed on the /RAMCS and /ROMCS signals because the address decoding logic decodes only A19-A12, without any control signals.

Bit D5 of the System Configuration Register allows the option of disabling the /ROMCS signal. This feature is used in systems which, for example, have a shadow RAM. However, prior to disabling the /ROMCS signal, the ROMBR and RAMLBR registers must be re-initialized from their default values.

For more details, please refer to “Programming section”.

ROM Emulator Mode

To ease development, the SAC has a mode to support “ROM emulator” development systems. In this mode, a read data from on-chip registers (except Z181 MPU onchip registers) are available (data bus direction set to output) to make data visible from the outside, so that a ROM Emulator/Logic Analyzer can monitor internal transactions. Otherwise, a read from an internal transaction is not available to the outside (data bus direction set to Hi-Z status). Mode selection is made through the D1 bit in the System Configuration Register (I/O Address: EDh).

Programming

The following subsections explain and define the parameters for I/O Address assignments, I/O Control Register Addresses and all pertinent Timing parameters.

I/O Address Assignment

The SAC has 78 internal 8-bit registers to control on-chip peripherals and features. Sixty-four registers out of 78 registers are occupied by the Z181 MPU control registers;

two for SCC control registers, four for PIA control registers, four for the Counter/Timer, three for RAM/ROM configuration (memory address boundaries) and one for SAC’s system control. The SAC’s I/O addresses are listed in Table 1. These registers are assigned in the SAC’s I/O addressing space and the I/O addresses are fully decoded from A7-A0 and have no image.

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PROGRAMMING (Continued)

SMART ACCESS CONTROLLER SAC

Z80181

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Table 1. I/O Control Register Address

Address Register

00h Z181 MPU Control Registers to 3Fh (Relocatable to 040h-07Fh, or 080h-0BFh) E0h PIA1 Data Direction Register (P1DDR) E1h PIA1 Data Port (P1DP)

E2h PIA2 Data Direction Register (P2DDR) E3h PIA2 Data Register (P2DP) E4h CTC Channel 0 Control Register (CTC0) E5h CTC Channel 1 Control Register (CTC1)

E6h CTC Channel 2 Control Register (CTC2) E7h CTC Channel 3 Control Register (CTC3) E8h SCC Control Register (SCCCR) E9h SCC Data Register (SCCDR)

EAh RAM Upper Boundary Address Register

(RAMUBR)

EBh RAM Lower Boundary Address Register

(RAMLBR)

ECh ROM Address Boundary Register (ROMBR) EDh System Configuration Register (SCR) EEh Reserved EFh Reserved

Z181 MPU Control Registers

The I/O address for these registers can be relocated in 64 byte boundaries by programming of the I/O Control Register (Address xx111111b).

Do not relocate these registers to address from 0C0h since this will cause an overlap of the Z180 registers and the 16 registers of the Z181 (address 0E0h to 0EFh).

Also, the OMCR register (Address: xx111101b) must be programmed as 0x0xxxxxb (x: don’t care) as a part of the initialization procedure. The M1E bit (Bit D7) of this register must be programmed as 0 or the interrupt daisy chain is corrupted. The /IOC bit (Bit D5) of this register is programmed as 0 so that the timing of the /RD and /IORQ signals are compatible with Z80 peripherals.

For detailed information, refer to the Z180 Technical Manual.

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ASCI CHANNELS CONTROL REGISTERS

SMART ACCESS CONTROLLER SAC

Z80181

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Bit

Upon RESET

R/W

CNTLA0

MPE

R/W0R/W0R/W1R/WxR/W0R/W0R/W0R/W

RE TE /RTS0

MPBR/

MOD2 MOD1 MOD0

EFR

0 0 0 Start + 7-Bit Data + 1 Stop 0 0 1 Start + 7-Bit Data + 2 Stop 0 1 0 Start + 7-Bit Data + Parity + 1 Stop 0 1 1 Start + 7-Bit Data + Parity + 2 Stop 1 0 0 Start + 8-Bit Data + 1 Stop 1 0 1 Start + 8-Bit Data + 2 Stop 1 1 0 Start + 8-Bit Data + Parity + 1 Stop 1 1 1 Start + 8-Bit Data + Parity + 2 Stop

Addr 00h

Figure 7. ASCI Control Register A (Ch. 0)

MODE Selection

Read - Multiprocessor Bit Receive Write - Error Flag Reset

Request To Send Transmit Enable Receive Enable Multiprocessor Enable

Bit

Upon RESET

R/W

CNTLA1

MPE RE TE

R/W0R/W0R/W1R/WxR/W0R/W0R/W0R/W

CKA1D

MPBR/

MOD2 MOD1 MOD0

EFR

Addr 01h

Figure 8. ASCI Control Register A (Ch. 1)

MODE Selection

Read - Multiprocessor Bit Receive Write - Error Flag Reset

CKA1 Disable Transmit Enable Receive Enable Multiprocessor Enable

2-18

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Z80181

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Addr 02h

Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear To Send/Prescale Multiprocessor Multiprocessor Bit Transmit

Bit

Upon Reset

CNTLB0

MPBT MP

Invalid

R/W0R/W†R/W0R/W0R/W1R/W1R/W1R/WR/W

† /CTS - Depending on the condition of /CTS pin. PS - Cleared to 0.

/CTS/

SS2 SS1 SS0

DRPE0

General PS = 0 PS = 1 Divide Ratio (Divide Ratio = 10) (Divide Ratio = 30) SS, 2, 1, 0 DR = 0 (x16) DR = 1 (x64) DR = 0 (x16) DR = 1 (x64)

000 Ø ÷ 160 Ø ÷ 640 Ø ÷ 480 Ø ÷ 1920 001 Ø ÷ 320 Ø ÷ 1280 Ø ÷ 960 Ø ÷ 3840 010 Ø ÷ 640 Ø ÷ 2580 Ø ÷ 1920 Ø ÷ 7680 011 Ø ÷ 1280 Ø ÷ 5120 Ø ÷ 3840 Ø ÷ 15360 100 Ø ÷ 2560 Ø ÷ 10240 Ø ÷ 7680 Ø ÷ 30720 101 Ø ÷ 5120 Ø ÷ 20480 Ø ÷ 15360 Ø ÷ 61440 110 Ø ÷ 10240 Ø ÷ 40960 Ø ÷ 30720 Ø ÷ 122880

111 External Clock (Frequency < Ø ÷ 40)

Figure 9. ASCI Control Register B (Ch. 0)

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ASCI CHANNELS CONTROL REGISTERS (Continued)

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Z80181

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Bit

Upon Reset

CNTLB1

MPBT MP

Invalid

R/W0R/W0R/W0R/W0R/W1R/W1R/W1R/WR/W

/CTS/

SS2 SS1 SS0

DRPE0

Addr 03h

Clock Source and Speed Select Divide Ratio Parity Even or Odd Read - Status of /CTS pin

Write - Select PS Multiprocessor Multiprocessor Bit Transmit

General PS = 0 PS = 1 Divide Ratio (Divide Ratio = 10) (Divide Ratio = 30) SS, 2, 1, 0 DR = 0 (x16) DR = 1 (x64) DR = 0 (x16) DR = 1 (x64)

111 External Clock (Frequency < Ø ÷ 40)

Figure 10. ASCI Control Register B (Ch. 1)

2-20

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Bit

Upon Reset

STAT0

RDRF OVRN /DCD0TDRE TIE

† /DCD †† /CTS L 1

H 0

- Depending on the condition of /DCD0 Pin.

Pin TDRE

RIEFE 0 R0R/W R

†

Addr 04h

††

R0R/WR/W

Transmit Interrupt Enable Transmit Data Register

Empty Data Carrier Detect Receive Interrupt Enable

Framing Error Parity Error Over Run Error Receive Data Register Full

Bit

Upon Reset

STAT1

RDRF OVRN

Figure 11. ASCI Status Register

CTS1E

RIEFE

R0R/W R/W1R0R/WR/W

TDRE TIE

Figure 12. ASCI Status Register (Ch. 1)

Addr 05h

Transmit Interrupt Enable Transmit Data Register

Empty /CTS1 Enable Receive Interrupt Enable

Framing Error Parity Error Over Run Error Receive Data Register Full

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TDR0 Write Only Addr 06h

76543210

Transmit Data

Figure 13. ASCI Transmit Data Register (Ch. 0)

TDR1 Write Only

76543210

Addr 07h

Transmit Data

Figure 14. ASCI Transmit Data Register (Ch. 1)

CSI/O Registers

TSR0 Read Only

xxxxxxxx

Addr 08h

Received Data

Figure 15. ASCI Receive Data Register (Ch. 0)

TSR1 Read Only

xxxxxxxx

Addr 09h

Received Data

Figure 16. ASCI Receive Data Register (Ch. 1)

CNTR

EF EIE SS2 SS1 SS0

Bit

Upon Reset

R0R/W0R/W0R/W

SS2, 1, 0 Baud Rate

000 Ø ÷ 20 001 Ø ÷ 40 010 Ø ÷ 80 011 Ø ÷ 100

Addr 0Ah

-TE

R/W1R/W1R/WR/W

Speed Select

Transmit Enable Receive Enable End Interrupt Enable End Flag

SS2, 1, 0 Baud Rate

100 Ø ÷ 320 101 Ø ÷ 640 110 Ø ÷ 1280 111 External Clock

(Frequency < Ø ÷ 20)

2-22

Figure 17. CSI/O Control Register

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TIMER REGISTERS Timer Data Registers

TRDR Read/Write

76543210

Addr 0Bh

Read - Received Data Write - Transmit Data

Figure 18. CSI/O Transmit/Receive Data Register

SMART ACCESS CONTROLLER SAC

Z80181

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TMDR0L Read/Write

76543210

Figure 19. Timer 0 Data Register L

TMDR1L Read/Write

76543210

Figure 20. Timer 1 Data Register L

Timer Reload Registers

Addr 0Ch

Addr 14h

TMDR0H Read/Write

15 14 13 12 11 10 9 8

When Read, read Data Register L before reading Data Register H.

Addr 0Dh

Figure 21. Timer 0 Data Register H

TMDR1H Read/Write

15 14 13 12 11 10 9 8

When Read, read Data Register L before reading Data Register H.

Addr 15h

Figure 22. Timer 1 Data Register H

Figure 23. Timer 0 Reload Register L

DS971800500

RLDR0L Read/Write

76543210

Addr 0Eh

RLDR1L Read/Write

76543210

Addr 16h

Figure 24. Timer 1 Reload Register L

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Timer Reload Registers (Continued)

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RLDR0H Read/Write

15 14 13 12 11 10 9 8

Timer Control Register

TCR

TIF1 TIF0 TOC0 TDE1 TDE0

Bit

Upon Reset

0 R

0 R0R/W0R/W0R/W R/W0R/W0R/WR/W

Addr 0Fh

TIE1

RLDR1H Read/Write

Addr 17h

15 14 13 12 11 10 9 8

Figure 26. Timer 1 Reload Register HFigure 25. Timer 0 Reload Register H

Addr 10h

TOC1TIE0

Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0

TOC1,0 A15/TOUT

00 Inhibited 01 Toggle 10 0 11 1

Free Running Counter

Figure 27. Timer Control Register

FRC Read Only

Addr 18h

76543210

Figure 28. Free Running Counter

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DMA Registers

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SAR0L Read/Write

SA7 SA0

SAR0H Read/Write

SA15 SA8

SAR0B Read/Write

----

Bits 0-2 (3) are used for SAR0B

A19,

A18,

A17,

0 0 1 1

Addr 20h

Addr 21h

Addr 22h

SA16SA19

A16

0 1 0 1

DMA Transfer Request /DREQ0 (external)

RDR0 (ASCI0) TDR0 (ASCI1) Not Used

DAR0L Read/Write

DA7 DA0

DAR0H Read/Write

DA15 DA8

DAR0B Read/Write

----

Bits 0-2 (3) are used for DAR0B

A19,

A18,

A17,

0 0 1 1

Addr 23h

Addr 24h

Addr 25h

DA16DA19

A16

0 1 0 1

DMA Transfer Request /DREQ0 (external)

RDR0 (ASCI0) TDR0 (ASCI1) Not Used

Figure 29. DMA 0 Source Address Registers

Figure 30. DMA 0 Destination Address Registers

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DMA REGISTERS (Continued)

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BCR0L Read/Write

BC7 BC0

BCR0H Read/Write

BC15 BC8

Addr 26h

Addr 27h

Figure 31. DMA 0 Byte Counter Registers

MAR1L Read/Write

MA7 MA0

MAR1H Read/Write

MA15 MA8

Addr 28h

Addr 29h

IAR1L Read/Write

IA7 IA0

IAR1H Read/Write

IA15 IA8

Addr 2Bh

Addr 2Ch

Figure 33. DMA 1 I/O Address Registers

BCR1L Read/Write

BC7 BC0

BCR1H Read/Write

BC15 BC8

Addr 2Eh

Addr 2Fh

MAR1B Read/Write

----

Addr 2Ah

MA16MA19

Figure 32. DMA 1 Memory Address Registers

Figure 34. DMA 1 Byte Count Registers

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Bit

Upon Reset

R/W

DSTAT

DE1 DE0 DIE0 - DIME

R/W0R/W1W

/DWE1

DIE1/DWE0

R/W

Figure 35. DMA Status Register

DMODE

Bit

- - SM0 MMOD -

110

DM1

R/W0R/W

SM1DM0

R/W R/W

R/W

Addr 30h

RR/W

DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Ch 1, 0

Addr 31h

Memory MODE Select

DM1, 0

00 01 10 11

MMOD

0 1

Destination

M M M

I/O

Mode

Cycle Steal Mode Burst Mode

DAR0 Fixed DAR0 Fixed

Figure 36. DMA Mode Registers

Address DAR0+1

DAR0-1

SM1, 0

00 01 10 11

Source

M M M

I/O

Ch 0 Source Mode 1, 0 Ch 0 Destination Mode 1, 0

Address SAR0+1

SAR0-1 SAR0 Fixed SAR0 Fixed

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DMA REGISTERS (Continued)

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Z80181

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Bit

Upon Reset

R/W

DCNTL

MWI1 MWI0 DMS0 DIM1 DIM0

111

MWI1, 0

00 01 10 11

DMSi

IWI1

R/WR/W R/W

R/W1R/W

No. of Wait States

0 1 2 3

Sense

DMS1IWI0

R/W R/W

R/W

IWI1, 0

00 01 10 11

Addr 32h

No. of Wait States

DMA Ch 1 I/O Memory Mode Select

/DREQi Select, i = 1, 0 I/0 Wait Insertion Memory Wait Insertion

0 2 3 4

1 0

DM1, 0

00 01 10 11

Edge Sense

Level Sense

Transfer Mode

M - I/O M - I/O I/O - M I/O - M

Address Increment/Decrement

MAR1+1

MAR1-1 IAR1 Fixed IAR1 Fixed

IAR1 Fixed IAR1 Fixed

MAR1+1

MAR1-1

Figure 37. DMA/WAIT Control Register

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MMU Registers

SMART ACCESS CONTROLLER SAC

Z80181

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Bit

Upon Reset

R/W

Bit

Upon Reset

R/W

CBR

CB7 CB6 CB2 CB1 CB0

000

R/W0R/W

CB3CB4CB5

R/W R/WR/WR/W R/W

R/W

Addr 38h

Figure 38. MMU Common Base Register

BBR

BB7

BB6 BB2 BB1 BB0

000

R/W0R/W

BB3BB4BB5

R/W R/WR/WR/W R/W

R/W

Addr 39h

Figure 39. MMU Bank Base Register

MMU Common Base Register

MMU Bank Base Register

Bit

Upon Reset

R/W

CBAR

CA3 CA2 BA2 BA1 BA0

111

R/W1R/W

BA3CA0CA1

R/W

R/W R/WR/WR/W R/W

Addr 3Ah

Figure 40. MMU Common/Bank Area Register

MMU Bank Area Register MMU Common Area Register

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System Control Registers

SMART ACCESS CONTROLLER SAC

Z80181

™

Bit

Upon Reset

R/W

Bit

Upon Reset

R/W

IL7 IL6 - - -

000

R/WR/W

R/W

00000

--IL5

Addr 33h

Figure 41. Interrupt Vector Low Register

ITC

TRAP UFO ITE2 ITE1 ITE0

001

110

---

R/W

Addr 34h

R/WRR/W R/W

Interrupt Vector Low

/INT Enable 2, 1, 0 Undefined Fetch Object TRAP

Bit

Upon Reset

R/W

Figure 42. INT/TRAP Control Register

RCR

REFE REFW - CYC1 CYC0

111

CYC1, 0

00 01 10 11

11100

Interval of Refresh Cycle

10 states 20 states 40 states 80 states

Addr 36h

R/WR/WR/W R/W

Figure 43. Refresh Control Register

Cycle Select Refresh Wait State Refresh Enable

2-30

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Bit

Upon Reset

R/W

Bit

Upon Reset

R/W

OMCR

M1E /M1TE - - -

111

Note: This register has to be programmed as 0x0xxxxxb(x:don't care) as a part of Initialization.

/IOC

11111

R/W

WR/W

Addr 3Eh

I/O Compatibility /M1 Temporary Enable /M1 Enable

Figure 44. Operation Mode Control Register

ICR

IOA7 IOA6 - - -

000

IOSTP

11111

R/WR/W

R/W

Addr 3Fh

Figure 45. I/O Control Register

I/O Stop I/O Address

Combination of 11 is reserved

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CTC Control Registers

Channel Control Word

This word sets the operating modes and parameters as described below. Bit D0 must be a “1” to indicate that this is a Control Word (Figure 46).

Addr: E4h (Ch 0)

D6 D5 D4 D3 D2 D1 D0

Timer Mode Only

SMART ACCESS CONTROLLER SAC

For more detailed information, refer to the CTC Technical Manual.

E5h (Ch 1) E6h (Ch 2) E7h (Ch 3)

Control or Vector 0 Vector 1 Control Word

Reset 0 Continued Operation 1 Software Reset

Time Constant 0 No Time Constant Follows 1 Time Constant Follows

Time Trigger 0 Automatic Trigger When Time Constant is Loaded 1 CLK/TRG Pulse Starts Timer

CLK/TRG Edge Selection 0 Selects Falling Edge 1 Selects Rising Edge

Prescaler Value * 1 Value of 256 0 Value of 16

Mode 0 Selects Timer Mode 1 Selects Counter Mode

Interrupt 1 Enables Interrupt 0 Disables Interrupt

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Figure 46. CTC Channel Control Word

This register has the following fields:

Bit D7.

Interrupt Enable.

This bit enables the interrupt logic so that an internal INT is generated at zero count. Interrupts are programmed in either mode and may be enabled or disabled at any time.

Bit D6.

Mode Bit.

This bit selects either Timer Mode or

Counter Mode.

Bit D5.

Prescaler Factor.

This bit selects the prescaler factor for use in the timer mode. Either divide-by-16 or divide-by-256 is available.

2-32

Bit D4.

Clock/Trigger Edge Selector.

This bit selects the

active edge of the CLK/TRG input pulses.

Bit D3.

Timer Trigger.

This bit selects the trigger mode for timer operation. Either automatic or external trigger may be selected.

Bit D2.

Time Constant.

This bit indicates that the next word

programmed is time constant data for the downcounter.

Bit D1.

Software Reset.

Writing a “1” to this bit indicates a software reset operation, which stops counting activities until another time constant word is written.

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Time Constant Word

Before a channel can start counting, it must receive a time constant word. The time constant value may be anywhere between 1 and 256, with “0” being accepted as a count of 256 (Figure 47).

D7 D6 D5 D4 D3 D2 D1 D0

TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7

Figure 47. CTC Time Constant Word

Interrupt Vector Word

If one or more of the CTC channels have interrupt enabled, then the Interrupt Vector Word is programmed. Only the five most significant bits of this word are programmed, and bit D0 must be “0”. Bits D2-D1 are automatically modified by the CTC channels after responding with an interrupt vector (Figure 48).

Addr: E4h

D7 D6 D5 D4 D3 D2 D1 D0

0 Interrupt Vector Word 1 Control Word

Channel Identifier (Automatically Inserted by CTC) 0 0 Channel 0 0 1 Channel 1 1 0 Channel 2 1 1 Channel 3

Supplied By User

Figure 48. CTC Interrupt Vector Word

SCC REGISTERS

For more detailed information, please refer to the Z8030/ Z8530 SCC Technical Manual.

Note:

The Address for the Control/Status Register is E8h. The Address for the Data Register is E9h.

Table 2. SCC Read Registers

Bit Description

RR0 Transmit and Receive buffer status

and external status. RR1 Special Receive Condition status. RR2 Interrupt vector (modified if VIS Bit in WR9 is set). RR3 Interrupt pending bits. RR6 SDLC FIFO byte counter lower byte

(only when enabled).

Read Registers

The SCC contains eight read registers. To read the contents of a register (rather than RR0), the program must first initialize a pointer to WR0 in exactly the same manner as a write operation. The next I/O read cycle will place the contents of the selected read registers onto the data bus (Figure 49).

Bit Description

RR7 SDLC FIFO byte count and status

(only when enabled). RR8 Receive buffer. RR10 Miscellaneous status bits. RR12 Lower byte of baud rate. RR13 Upper byte of baud rate generator time constant. RR15 External Status interrupt information.

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SCC REGISTERS (Continued)

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Read Register 0

D7 D6 D5 D4 D3 D2 D1 D0

(a)

Read Register 1

D7 D6 D5 D4 D3 D2 D1 D0

Rx Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort

All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC)

Read Register 2

D7 D6 D5 D4 D3 D2 D1 D0

Modified if VIS bit in Write register 9 is set.

(c)

Read Register 3

D7 D6 D5 D4 D3 D2 D1 D0

V0 V1 V2 V3 V4 V5 V6 V7

0 0 0 Ext/Status IP Tx IP Rx IP 0 0

Interrupt Vector

(b)

(d)

Figure 49. SCC Read Register Bit Functions

2-34

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Read Register 6 *

D7 D6 D5 D4 D3 D2 D1 D0

BC0 BC1 BC2 BC3 BC4 BC5 BC6 BC7

* Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

(e) SDLC FIFO Status and Byte Count (LSB)

Read Register 7

D7 D6 D5 D4 D3 D2 D1 D0

Read Register 10

D7 D6 D5 D4 D3 D2 D1 D0

0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing

(g)

Read Register 12

D7 D6 D5 D4 D3 D2 D1 D0

BC8 BC9 BC10 BC11 BC12 BC13 FDA: FIFO Available Status

1 Status Reads from FIFO FOS: FIFO Overflow Status

1 FIFO Overflowed 0 Normal

Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

(f) SDLC FIFO Status and Byte Count (MSB)

Figure 49. SCC Read Register Bit Functions (Continued)

(h)

TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7

Lower Byte of Time Constant

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SCC REGISTERS (Continued)

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Read Register 13

D7 D6 D5 D4 D3 D2 D1 D0

TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15

Upper Byte of Time Constant

(i)

Figure 49. SCC Read Register Bit Functions (Continued)

Write Registers

The SCC contains fifteen write registers that are programmed to configure the operating modes of the channel. With the exception of WR0, programming the write registers is a two step operation. The first operation is a

Read Register 15

D7 D6 D5 D4 D3 D2 D1 D0

0 Zero Count IE 0 DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE

(j)

pointer written to WR0 that points to the selected register. The second operation is the actual control word that is written into the register to configure the SCC channel (Figure 50).

Table 3. SCC Write Registers

Bit Description

WR0 Register Pointers, various initialization

commands

WR1 Transmit and Receive interrupt enables,

WAIT/DMA commands WR2 Interrupt Vector WR3 Receive parameters and control modes WR4 Transmit and Receive modes and parameters WR5 Transmit parameters and control modes WR6 Sync Character or SDLC address WR7 Sync Character or SDLC flag

Bit Description

WR8 Transmit buffer WR9 Master Interrupt control and reset commands WR10 Miscellaneous transmit and receive control bits WR11 Clock mode controls for receive and transmit WR12 Lower byte of baud rate generator WR13 Upper byte of baud rate generator WR14 Miscellaneous control bits WR15 External status interrupt enable control

2-36

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Write Register 0 (non-multiplexed bus mode)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 Register 0 0 0 1 Register 1 0 1 0 Register 2 0 1 1 Register 3 1 0 0 Register 4 1 0 1 Register 5 1 1 0 Register 6 1 1 1 Register 7 0 0 0 Register 8 0 0 1 Register 9 0 1 0 Register 10 0 1 1 Register 11 1 0 0 Register 12 1 0 1 Register 13 1 1 0 Register 14 1 1 1 Register 15

0 0 0 Null Code 0 0 1 Point High 0 1 0 Reset Ext/Status Interrupts 0 1 1 Send Abort (SDLC) 1 0 0 Enable Int on Next Rx Character 1 0 1 Reset Tx Int Pending 1 1 0 Error Reset 1 1 1 Reset Highest IUS

0 0 Null Code

0 1 Reset Rx CRC Checker

1 0 Reset Tx CRC Generator

1 1 Reset Tx Underrun/EOM Latch

With Point High Command

(a)

Write Register 1

D7 D6 D5 D4 D3 D2 D1 D0

Ext Int Enable Tx Int Enable Parity is Special

Condition

0 0 Rx Int Disable 0 1 Rx Int On First Character or Special Condition 1 0 Int On All Rx Characters or Special Condition 1 1 Rx Int On Special Condition Only

WAIT/DMA Request On Receive//Transmit

/WAIT/DMA Request Function

WAIT/DMA Request Enable

(b)

Write Register 2

D7 D6 D5 D4 D3 D2 D1 D0

V0 V1 V2 V3 V4 V5 V6 V7

Interrupt Vector

DS971800500

(c)

Figure 50. Write Register Bit Functions

2-37

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SCC REGISTERS (Continued)

Write Register 3

D7 D6 D5 D4 D3 D2 D1 D0

0 0 Rx 5 Bits/Character 0 1 Rx 7 Bits/Character 1 0 Rx 6 Bits/Character 1 1 Rx 8 Bits/Character

(d)

Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables

SMART ACCESS CONTROLLER SAC

Z80181

™

Write Register 4

D7 D6 D5 D4 D3 D2 D1 D0

0 0 Sync Modes Enable 0 1 1 Stop Bit/Character 1 0 1 1/2 Stop Bits/Character 1 1 2 Stop Bits/Character

0 0 8-Bit Sync Character 0 1 16-Bit Sync Character 1 0 SDLC Mode (01111110 Flag) 1 1 External Sync Mode

0 0 X1 Clock Mode 0 1 X16 Clock Mode 1 0 X32 Clock Mode 1 1 X64 Clock Mode

(e)

Write Register 5

D7 D6 D5 D4 D3 D2 D1 D0

Parity Enable Parity EVEN//ODD

0 0 Tx 5 Bits(Or Less)/Character 0 1 Tx 7 Bits/Character 1 0 Tx 6 Bits/Character 1 1 Tx 8 Bits/Character

Figure 50. Write Register Bit Functions (Continued)

Tx CRC Enable RTS /SDLC/CRC-16 Tx Enable Send Break

DTR

(f)

2-38

DS971800500

Page 39

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Write Register 6

D7 D6 D5 D4 D3 D2 D1 D0

SMART ACCESS CONTROLLER SAC

Z80181

™

Sync7 Sync1 Sync7 Sync3 ADR7 ADR7

Sync7 Sync5 Sync15 Sync11 0

Sync6 Sync0 Sync6 Sync2 ADR6 ADR6

Sync6 Sync4 Sync14 Sync10 1

Sync5 Sync5 Sync5 Sync1 ADR5 ADR5

Write Register 7

D7 D6 D5 D4 D3 D2 D1 D0

Sync5 Sync3 Sync13 Sync9 1

Sync4 Sync4 Sync4 Sync0 ADR4 ADR4

Sync4 Sync2 Sync12 Sync8 1

Sync3 Sync1 Sync11 Sync7 1

Sync3 Sync3 Sync3 1 ADR3 x

Sync2 Sync2 Sync2 1 ADR2 x

(g)

Sync2 Sync0 Sync10 Sync6 1

Sync1 Sync1 Sync1 1 ADR1 x

Sync1 x Sync9 Sync5 1

Sync0 Sync0 Sync0 1 ADR0 x

Sync0 x Sync8 Sync4 0

Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range)

Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC

DS971800500

(h)

Figure 50. Write Register Bit Functions (Continued)

2-39

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SCC REGISTERS (Continued)

SMART ACCESS CONTROLLER SAC

Z80181

™

Write Register 9

D7 D6 D5 D4 D3 D2 D1 D0

0 0 No Reset 0 1 Reserved 1 0 Channel Reset A 1 1 Force Hardware Reset

(i)

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

0 0 NRZ 0 1 NRZI 1 0 FM1 (Transition = 1) 1 1 FM0 (Transition = 0)

VIS NV DLC MIE Status High//Status Low 0

6 Bit//8 Bit Sync Loop Mode Abort//Flag On Underrun Mark//Flag Idle Go Active On Poll

CRC Preset I//O

Write Register 11

D7 D6 D5 D4 D3 D2 D1 D0

0 0 /TRxC Out - Xtal Output 0 1 /TRxC Out - Transmit Clock 1 0 /TRxC Out - BR Generator Output 1 1 /TRxC Out - DPLL Output

0 0 Transmit Clock - /RTxC Pin 0 1 Transmit Clock - /TRxC Pin 1 0 Transmit Clock - BR Generator Output 1 1 Transmit Clock - DPLL Output

0 0 Receive Clock - /RTxC Pin 0 1 Receive Clock - /TRxC Pin 1 0 Receive Clock - BR Generator Output 1 1 Receive Clock - DPLL Output

(k)

Write Register 12

D7 D6 D5 D4 D3 D2 D1 D0

/TRxC O/I

/RTxC Xtal//No Xtal

TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7

Lower Byte of Time Constant

2-40

(j)

(l)

Figure 50. Write Register Bit Functions (Continued)

DS971800500

Page 41

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SMART ACCESS CONTROLLER SAC

Z80181

™

Write Register 13

D7 D6 D5 D4 D3 D2 D1 D0

(m)

Write Register 14

D7 D6 D5 D4 D3 D2 D1 D0

TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15

Write Register 15

D7 D6 D5 D4 D3 D2 D1 D0

Upper Byte of Time Constant

BR Generator Enable BR Generator Source /DTR/Request Function Auto Echo Local Loopback

0 0 0 Null Command 0 0 1 Enter Search Mode 0 1 0 Reset Missing Clock 0 1 1 Disable DPLL 1 0 0 Set Source = BR Generator 1 0 1 Set Source = /RTxC 1 1 0 Set FM Mode 1 1 1 Set NRZI Mode

(n)

0 Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE

DS971800500

(o)

Figure 50. Write Register Bit Functions (Continued)

2-41

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PIA Control Registers

SMART ACCESS CONTROLLER SAC

Z80181

™

PIA1 Data Direction Register (P1DDR, I/O Address E0h), PIA1 Data Port (P1DP, I/O address E1h), PIA2 Data Direction Register (P2DDR, I/O Address E2h) and PIA2 Data Register (P2DP, I/O Address E3h). These four registers are

E0H

76543210

1 - Input 0 - Output

shown in Figures 51-54. Note that if the CTC/PIA bit in the System Configuration Register is set to one, the CTC I/O functions override the PIA1 function, and programming of P1DDR is ignored.

E2H

76543210

1 - Input 0 - Output

Figure 51. PIA 1 Data Direction Register

E1H

76543210

PIA 1 I/O Data

Figure 52. PIA 1 Data Register

The Data Port is the register to/from the 8-bit parallel port. At power on Reset, they are initialized to 1.

The Data Direction Register has eight control bits. Individual bits specify each bit's direction. When the bit is set to

Figure 53. PIA 2 Data Direction Register

E3H

76543210

PIA 2 I/O Data

Figure 54. PIA 2 Data Register

a "1", the bit becomes an input, otherwise it is an output. On reset, these registers are initialized to 1, resulting in all lines being inputs.

2-42

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REGISTERS FOR SYSTEM CONFIGURATION

SMART ACCESS CONTROLLER SAC

Z80181

™

There are four registers to determine system configuration with the Z181. These registers are: RAM upper boundary address register (RAMUBR, I/O address EAh), RAM lower boundary address register (RAMLBR, I/O address EBh), ROM address boundary register (ROMBR, I/O address ECh) and System Configuration Register (SCR, I/O address EDh).

ROM Address Boundary Register (ROMBR, I/O Address ECh)

This register specifies the address range for the /ROMCS signal. When accessed memory addresses are less than or equal to the value programmed in this register, the /ROMCS signal is asserted (Figure 55).

The A18 signal from the CPU is obtained before it is multiplexed with “TOUT”. This signal can be forced to “1” (inactive state) by setting Bit D5 of the System Configuration Register, to allow the user to overlay the RAM area over the ROM area. At power-up reset, this register contains all 1's so that /ROMCS is asserted for all addresses.

RAM Lower Boundary Address Register (RAMLBR, I/O Address EBh) and RAM Upper Boundary Address Register (RAMUBR, I/O Address EAh)

These two registers specify the address range for the /RAMCS signal. When accessed memory addresses are less than or equal to the value programmed in the RAMUBR and greater than or equal to the value programmed in the

RAMLBR, /RAMCS is asserted. (Figure 13) The A18 signal from the CPU is taken before it is multiplexed with “T

OUT

In the case that these register are programmed to overlap, /ROMCS takes priority over /RAMCS (/ROMCS is asserted and /RAMCS is inactive).

Chip Select signals are going active for the address range: /ROMCS: (ROMBR) ≥ A19-A12 ≥ 0

/RAMCS: (RAMUBR) ≥ A19-A12 > (RAMLBR)

These registers are set to “FFh” at power-on Reset, and the boundary addresses of ROM and RAM are the following:

ROM lower boundary address (fixed) = 00000h

ROM upper boundary address (ROMBR register) = 0FFFFFh

RAM lower boundary address (RAMLBR register) = 0FFFFFh

RAM upper boundary address (RAMUBR register) = 0FFFFFh

Since /ROMCS takes priority over /RAMCS, the latter will never be asserted until the value in the ROMBR and RAMLBR registers are re-initialized to lower values.

”.

EAH

76543210

A12 A13 A14 A15 A16 A17 A18 A19

Figure 55. RAM Upper Boundary Register

EBH

76543210

A12 A13 A14 A15 A16 A17 A18 A19

Figure 56. RAM Lower Boundary Register

DS971800500

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REGISTERS FOR SYSTEM CONFIGURATION (Continued)

ECH

76543210

Figure 57. ROM Boundary Register

A12 A13 A14 A15 A16 A17 A18 A19

SMART ACCESS CONTROLLER SAC

Z80181

™

EDH

76543210

PIA1/CTIO 1 PIA1 Functions as CTC's I/O Pins 0 PIA1 Functions as I/O Port

Reserved - Program as 0 ROM Emulator Mode (REME)

1 Data Bus in ROM Emulator Mode 0 Data Bus in Normal Mode

Reserved - Program as 0 Reserved - Program as 0 Disable /ROMCS

1 /ROMCS is Disabled 0 /ROMCS is Enabled

Daisy Chain Configuration 1 IEI Pin-CTC-SCC-IEO Pin 0 IEI Pin-SCC-CTC-IEO Pin

Reserved - Program as 0

Figure 58. System Configuration Register

2-44

DS971800500

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SMART ACCESS CONTROLLER SAC

Z80181

™

System Configuration Register (I/O address EDh)

This register is to determine the functionality of PIA1 and the Interrupt Daisy-Chain Configuration (Figure 13). This register has the following control bits:

Bit D7. Reserved and should be programmed as “0”.

Bit D6.

Daisy-Chain Configuration.

Determines the

arrangement of the interrupt priority daisy chain.

When this bit is set to “1”, priority is as follows:

IEI pin - CTC - SCC - IEO pin

When this bit is “0”, priority is as follows:

IEI pin - SCC - CTC - IEO pin

This bit’s default (after Reset) is 0.

Bit D5.

Disable /ROMCS.

When this bit is set to “1”. /ROMCS is forced to a “1” regardless of the status of the address decode logic. This bit’s default (after Reset) is 0 and /ROMCS function is enabled.

Bit D4-D3. Reserved and should be programmed as “00”.

Bit D2.

ROM Emulator Mode Enable.

When this bit is set to a 1, the Z181 is in “ROM emulator mode”. In this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions outside the Z80181. This allows the use of ROM emulators/ logic analyzers for applications development. This bit’s default (after Reset) is 0.

Bit D1. Reserved and shall be programmed as “0”.

Bit D0.

CTC/PIA1.

When this bit is set to “1”, PIA1 functions

as the CTC’s I/O pins. This bit’s default (after Reset) is 0.

DS971800500

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SMART ACCESS CONTROLLER SAC

Data Bus Direction

Table 4 shows the state of the SAC’s data bus when in SAC bus master condition.

Table 4. Data Bus Direction (Z181 Is Bus Master)

I/O And Memory Transactions

I/O I/O I/O I/O Write Read Refresh Z80181 Write To Read From Write To Read From To From Idle On-Chip On-Chip Off-Chip Off-Chip Memory Memory Mode Peripherals Peripherals Peripheral Peripheral (SCC/CTC/ (SCC/CTC/ PIA1/PIA2) PIA1/PIA2)

Z80181 Data Bus Out Z Out In Out In Z Z (REME Bit = 0)

Z80181 Data Bus Out Out Out In Out In Z Z (REME Bit = 1)

Z80181

™

Interrupt Acknowledge Transaction

Intack For Intack For On-Chip Off-Chip

Peripheral Peripheral (SCC/CTC)

Z80181 Data Bus Z In (REME Bit = 0)

Z80181 Data Bus Out In (REME Bit = 1)

2-46

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SMART ACCESS CONTROLLER SAC

Table 5 shows the state of the SAC’s data bus when the Z80181 is NOT in bus master condition.

Table 5. Data Bus Direction for External Bus Master (Z80181 Is Not Bus Master)

I/O And Memory Transactions

Z80181 Data Bus In Out Z Z Z In Z Z (REME Bit = 0)

Z80181 Data Bus In Out Z Z Z In Z Z (REME Bit = 1)

Z80181

™

Interrupt Acknowledge Transaction

Intack For Intack For On-Chip Off-Chip Peripheral Peripheral (SCC/CTC)

Z80181 Data Bus Out In (REME Bit = 0)

Z80181 Data Bus Out In (REME Bit = 1)

The word “OUT” means that the Z181 data bus direction is in output mode, “IN” means input mode, and “HI-Z” means high impedance.

“REME” stands for “ROM Emulator Mode” and is the status of D2 bit in the System Configuration Register.

DS971800500

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ABSOLUTE MAXIMUM RATINGS

SMART ACCESS CONTROLLER SAC

Z80181

™

Voltage on VCC with respect to VSS........... –0.3V to +7.0V

Voltages on all inputs

with respect to VSS........................... –0.3V to VCC +0.3V

Storage Temperature ............................–65°C to +150°C

Operating Ambient

Temperature ........................ See Ordering Information

STANDARD TEST CONDITIONS

The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into the referenced pin (Figure 59).

Available operating temperature range is: E = –40°C to +100°C

Voltage Supply Range: +4.50V ≤ Vcc ≤ + 5.50V

All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 150 pF for the data bus and 100 pF for address and control lines. AC timing measurements are referenced to 1.5 volts (except for clock, which is referenced to the 10% and 90% points). Maximum capacitive load for CLK is 125 pF.

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

+5V

2.1 K

From Output

Under Test

100 pf 250 µA

Figure 59. Standard Test Circuit

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SMART ACCESS CONTROLLER SAC

DC CHARACTERISTICS

Z80181

Symbol Parameter Min Typ Max Unit Condition

Z80181

™

IH1

Input “H” Voltage V

–0.6 VCC +0.3 V

/RESET, EXTAL, /NMI

IH2

Input “H” Voltage 2.0 VCC +0.3 V Except /RESET, EXTAL, /NMI

IL1

Input “L” Voltage –0.3 0.6 V /RESET, EXTAL, /NMI

IL2

Input “L” Voltage –0.3 0.8 V Except /RESET, EXTAL, /NMI

Output “H” Voltage 2.4 V IOH = -200 µA All outputs. VCC –1.2 IOH = – 20 µA

Output “L” Voltage 0.45 V IOL = 2.2 mA All outputs.

Input Leakage 10 µAV

= 0.5 – VCC –0.5

Current All Inputs Except XTAL, EXTAL

Tri-State Leakage Current 10 µAV

= 0.5 – VCC –0.5

ICC* Power Dissipation*

(Normal Operation) 25 80 f = 10 MHz Power Dissipation* (SYSTEM STOP mode) 6.3 40 f = 10 MHz

Cp Pin Capacitance 12 pF VIN = 0V, f = 1 MHz

TA = 25°C

Notes:

* VIH Min = VCC -1.0V, V VCC = 5.0V

Max = 0.8V (all output terminals are at no load.)

DS971800500

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SMART ACCESS CONTROLLER SAC

AC CHARACTERISTICS

Z180 MPU Timing

Figures 60-68 show the timing for the Z181 MPU and the referenced parameters appear in Table A.

T1 T2 Tw T3 T1

4 5

Address

70 70

/ROMCS

/RAMCS

20 19 20

/WAIT

Z80181

™

/MREQ

/RD

/M1

/IORQ

/WR

Data In

"H"

8 12

9 14

15 16

6261

2-50

/RESET

67 66 67 66

Figure 60a. Opcode Fetch Cycle

DS971800500

Page 51

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Address

/ROMCS

/RAMCS

/WAIT

/IORQ

Z80181

SMART ACCESS CONTROLLER SAC

™

T1 T2 Twa T3 T1

70 70

2019

11287

/RD

/WR

Data IN

Data OUT

9 12 11

22 24

25, 25a

15 16

"H"

[1] Output buffer is off at this point. [2] Memory Read/Write cycle timing is the same as this figure, except there is no automatic wait status (Twa), and /MREQ is active instead of /IORQ.

[1]

DS971800500

Figure 60b. I/O Read/Write, Memory Read/Write Timing

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AC CHARACTERISTICS (Continued) Z180 MPU Timing

/INTI

/NMI

/INTSCC [4]

/M1 [1]

Z80181

SMART ACCESS CONTROLLER SAC

™

/IORQ [1]

/Data IN [1]

/MREQ [2]

/RFSH [2]

/BUSREQ

/BUSACK

Address

Data /MREQ,

/RD, /WR,

/IORQ

3940 42

34 34

[3]

3635

3737

2-52

/HALT

Notes: [1] During /INT0 acknowledge cycle [2] During refresh cycle

[3] Output buffer is off at this point [4] Refer to Table C, parameter 7

Figure 61. CPU Timing

(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode

HALT Mode, SLEEP Mode, SYSTEM STOP Mode)

DS971800500

Page 53

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Address

Z80181

SMART ACCESS CONTROLLER SAC

I/O Read Cycle I/O Write Cycle

T1 T2 Tw T3 T1 T2 Tw T3

™

/IORQ

/RD

/WR

28 27 28

2422

Figure 62. CPU Timing (/IOC = 0)

(I/O Read Cycle, I/O Write Cycle)

DS971800500

2-53

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AC CHARACTERISTICS (Continued) Z180 MPU Timing

CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)

T1 T2 Tw T3 T1

/DREQi

(At level

sense)

/DREQi

(At edge

sence)

Z80181

SMART ACCESS CONTROLLER SAC

[1]

[2]

[4]

™

/TENDi

[3]

DMA Control Signals

[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3. [2] tDRQS and tDRQH are specified for the rising edge of clock. [3] DMA cycle starts. [4] CPU cycle starts.

Figure 63. DMA Control Signals

2-54

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(Memory

Read/Write)

Z80181

SMART ACCESS CONTROLLER SAC

T1 T2 Tw Tw T3

48 49

™

(I/O Read)

D7-D0

BUS RELEASE Mode

SLEEP Mode SYSTEM STOP Mode

48 49

(a) E Clock Timing

(Memory Read/Write Cycle, I/O Read/Write Cycle)

4848

DS971800500

(b) E Clock Timing

(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)

Figure 64. E Clock Timing

2-55

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AC CHARACTERISTICS (Continued) Z180 MPU Timing

T2 Tw T3 T1 T2

SMART ACCESS CONTROLLER SAC

Z80181

™

(Example:

I/O Read -

Op-code

Fetch)

(I/O Write)

A18/TOUT

Figure 65. E Clock Timing

(Minimum timing example of PWEL and PWEH)

Timer Data Reg = 0000H

Figure 66. Timer Output Timing

2-56

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/INTi

/NMI

A18-A0

SMART ACCESS CONTROLLER SAC

SLP Instruction Fetch Next Op-code Fetch

T3 T1 T2 TS TS T1 T2

Z80181

™

/MREQ, /M1

/RD

/HALT

42 43

Figure 67. SLP Execution Cycle

DS971800500

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AC CHARACTERISTICS (Continued) Z180 MPU Timing

CSI/O Clock

Transmit Data

(Internal Clock)

Transmit Data

(External Clock)

Receive Data

(Internal Clock)

11.5 tcyc

16.5 tcyc 16.5 tcyc

55 55

5656

11 tcyc 11 tcyc

5857 5857

11.5 tcyc

SMART ACCESS CONTROLLER SAC

Z80181

™

Receive Data

(External Clock)

6059 59 60

Figure 68. CSI/O Receive/Transmit Timing

Table A. Z180 CPU & 180 Peripherals Timing

Z8018110

No Symbol Parameter Min Max Unit

1 tcyc Clock Cycle Time 100 2000 ns 2 tCHW Clock Pulse Width (High) 40 ns 3 tCLW Clock Pulse Width (Low) 40 ns 4 tcf Clock Fall Time 10 ns

5 tcr Clock Rise Time 10 ns 6 tAD Address Valid from Clock Rise 70 ns 7 tAS Address Valid to /MREQ, /IORQ Fall 10 ns 8 tMED1 Clock Fall to /MREQ Fall Delay 50 ns 9 tRDD1 Clock Fall to /RD Fall (/IOC=1) 50 ns

Clock Rise to /RD Fall (/IOC=0) 55 ns

10 tM1D1 Clock Rise to /M1 Fall Delay 60 ns

2-58

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SMART ACCESS CONTROLLER SAC

Table A. Z180 CPU & 180 Peripherals Timing (Continued)

Z8018110

No Symbol Parameter Min Max Unit

11 tAH Address Hold Time 10 ns

(/MREQ, /IORQ, /RD, /WR) 12 tMED2 Clock Fall to /MREQ Rise Delay 50 ns 13 tRDD2 Clock Fall to /RD Rise Delay 50 ns 14 tM1D2 Clock Rise to /M1 Rise Delay 60 ns 15 tDRS Data Read Setup Time 25 ns

16 tDRH Data Read Hold Time 0 ns 17 tSTD1 Clock Fall to ST Fall 60 ns 18 tSTD2 Clock Fall to ST Rise 60 ns 19 tWS /WAIT Setup Time to Clock Fall 30 ns 20 tWH /WAIT Hold time from Clock Fall 30 ns

21 tWDZ Clock Rise to Data Float Delay 60 ns 22 tWRD1 Clock Rise to /WR Fall Delay 50 ns 23 tWDO /WR fall to Data Out Delay 10 ns 24 tWRD2 Clock Fall to /WR Rise 50 ns 25 tWRP /WR Pulse Width 110 ns

(Memory Write Cycles)

Z80181

™

25a /WR Pulse Width (I/O Write Cycles) 210 ns 26 tWDH Write Data Hold Time from /WR Rise 10 ns 27 tIOD1 Clock Fall to /IORQ Fall Delay 50 ns

(/IOC=1)

Clock Rise to /IORQ Fall Delay 55 ns

(/IOC=0) 28 tIOD2 Clock Fall /IOQR Rise Delay 50 ns

29 tIOD3 /M1 Fall to /IORQ Fall Delay 200 ns 30 tINTS /INT Setup Time to Clock Fall 30 ns 31 tINTH /INT Hold Time from Clock Fall 30 ns 32 tNMIW /NMI Pulse Width 80 ns 33 tBRS /BUSREQ Setup Time to Clock Fall 30 ns

34 tBRH /BUSREQ Hold Time from Clock Fall 30 ns 35 tBAD1 Clock Rise to /BUSACK Fall Delay 60 ns 36 tBAD2 Clock Fall to /BUSACK Rise Delay 60 ns 37 tBZD Clock Rise to Bus Floating Delay Time 80 ns

38 tMEWH /MREQ Pulse Width (High) 70 ns 39 tMEWL /MREQ Pulse Width (Low) 80 ns 40 tRFD1 Clock Rise to /RFSH Fall Delay 60 ns 41 tRFD2 Clock Rise to /RFSH Rise Delay 60 ns 42 tHAD1 Clock Rise to /HALT Fall Delay 50 ns

43 tHAD2 Clock Rise to /HALT Rise Delay 50 ns 44 tDRQS /DREQi Setup Time to Clock Rise 30 ns 45 tDRQH /DREQi Hold Time from Clock Rise 30 ns 46 tTED1 Clock Fall to /TENDi Fall Delay 50 ns

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AC CHARACTERISTICS (Continued) Z180™ MPU Timing

Table A. Z180 CPU &180 Peripherals Timing (Continued)

No Symbol Parameter Min Max Unit

47 tTED2 Clock Fall to /TENDi Rise Delay 50 ns 48 tED1 Clock Rise to E Rise Delay 60 ns 49 tED2 Clock Edge to E Fall Delay 60 ns 50 PWEH E Pulse Width (High) 55 ns 51 PWEL E Pulse Width (Low) 110 ns

52 tEr Enable Rise Time 20 ns 53 tEf Enable Fall Time 20 ns 54 tTOD Clock Fall to Timer Output Delay 150 ns 55 tSTDI CSI/O Tx Data Delay Time 150 ns

(Internal Clock Operation) 56 tSTDE CSI/O Tx Data Delay Time 7.5tcyc+150 ns

(External Clock Operation)

57 tSRSI CSI/O Rx Data Setup Time 1 tcyc

(Internal Clock Operation) 58 tSRHI CSI/O Rx Data Hold Time 1 tcyc

(Internal Clock Operation) 59 tSRSE CSI/O Rx Data Setup Time 1 tcyc

(External Clock Operation) 60 tSRHE CSI/O Rx Data Hold Time 1 tcyc

(External Clock Operation)

Z8018110

SMART ACCESS CONTROLLER SAC

Z80181

™

61 tRES /RESET Setup Time to Clock Fall 80 ns 62 tREH /RESET Hold Time from Clock Fall 50 ns 63 tOSC Oscillator Stabilization Time 20 ms 64 tEXr External Clock Rise Time (EXTAL) 25 ns 65 tEXf External Clock Fall Time (EXTAL) 25 ns

66 tRr /RESET Rise Time 50 ns 67 tRf /RESET Fall Time 50 ns 68 tIr Input Rise Time 100 ns

(Except EXTAL, /RESET) 69 tIf Input Fall Time 100 ns

(Except EXTAL, /RESET) 70 TdCS(A) Address Valid to /ROMCS, /RAMCS 20 ns

Valid Delay

2-60

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AC CHARACTERISTICS (Continued)

CTC Timing

Figure 69 shows the timing for the on-chip CTC. Parameters referenced in this figure appear in Table B.

Clock

CLK/TRG

Counter

CLK/TRG

Timer

ZC/TO

9 8

SMART ACCESS CONTROLLER SAC

Z80181

™

/INT

Figure 69. CTC Timing

Table B. CTC Timing Parameters

Z8018110

No Symbol Parameter Min Max Unit Note

1 TdCr(INTf) Clock Rise to /INT Fall Delay (TcC+100) ns [B1] 2 TsCTRr(Cr)c CLK/TRG Rise to Clock Rise

Setup Time for Immediate Count 90 ns [B2]

3 TsCTR(Ct) CLK/TRG Rise to Clock Rise

Setup Time for Enabling of Prescaler 90 ns [B1] On Following Clock Rise

4 TdCTRr(INTf) CLK/TRG Rise to /INT Fall Delay

TsCTR(C) Satisfied (1)+(3) ns [B2] TsCTR(C) Not Satisfied TcC+(1)+(3) ns [B2]

5 TcCTR CLK/TRG Cycle Time (2TcC) DC ns [B3] 6 TwCTRh CLK/TRG Width (Low) 90 DC ns 7 TwCTRl CLK/TRG Width (High) 90 DC ns 8 TrCTR CLK/TRG Rise Time 30 ns

9 TfCTR CLK/TRG Fall Time 30 ns 10 TdCr(ZCr) Clock Rise to ZC/TO Rise Delay 80 ns 11 TdCf(ZCf) Clock Fall to ZC/TO Fall Delay 80 ns

Notes for Table B:

[B1] Timer Mode [B2] Counter Mode [B3] Counter Mode Only. When using a cycle time less than 3TcC, parameter #2 must be met.

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AC CHARACTERISTICS (Continued) SCC Timing

Figure 70 shows the AC characteristics for the on-chip SCC. Parameters referenced in this figure appear in Table C.

/WR

/RD

/W//REQ

Wait

Z80181

SMART ACCESS CONTROLLER SAC

™

/W//REQ

Request

/DTR//REQ

Request

/INT

Figure 70. SCC AC Parameters

Table C. SCC Timing Parameters (85C30 AC Characteristics)

Z8018110

No Symbol Parameter Min Max Unit Note

1 TdWR(W) /WR Fall to Wait Valid Delay 180 + TcC ns [C1] 2 TdWR(W) /RD Fall to Wait Valid Delay 180 ns [C1] 3 TdWRf(REQ) /WR Fall to /W//REQ Not Valid Delay 180 + TcC ns 4 TdRDf(REQ) /RD Fall to /W//REQ Not Valid Delay 180 ns

5 TdWRr(REQ) /WR Rise to /DTR//REQ Not Valid Delay 5TcC ns 6 TdPC(INT) Clock to /INT Valid Delay 500 ns [C1] 7 TdRDA(INT) /M1 Fall to /INT Inactive Delay TBS ns [C1]

Note for Table C:

[C1] Open-drain output, measured with open-drain test load.

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Figure 71 shows the general timing for the on-chip SCC. Parameters referenced in this figure appear in Table D.

PCLK

/W//REQ

Request

/W//REQ

Wait

/RTxC, /TRxC

Receive

Z80181

SMART ACCESS CONTROLLER SAC

™

RxD

/SYNC

External

/TRxC, /RTxC

Transmit

TxD

/TRxC

Output

/RTxC

/TRxC

/CTS, /DCD

/SYNC

Input

7 8

9 10

15, 21

18, 21

DS971800500

Figure 71. SCC General Timing

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SMART ACCESS CONTROLLER SAC

AC CHARACTERISTICS (Continued)

SCC General Timing

Table D. SCC General Timing Parameters

Z8018110

No Symbol Parameter Min Max Unit Note

1 TdPC(REQ) Clock Fall to /W//REQ Valid 200 ns 2 TdPC(W) Clock Fall to Wait Inactive 300 ns 3 TsRXD(RXCr) RxD to /RxC Rise Setup Time 0 ns [D1] 4 ThRXD(RXCr) RxD to /RxC Rise Hold Time 125 ns [D1]

5 TsRXD(RXCf) RxD to /RxC Fall Setup Time 0 ns [D1,4] 6 ThRXD(RXCf) RxD to /RxC Fall Hold Time 125 ns [D1,4] 7 TsSY(RXC) /SYNC to /RxC Setup Time –150 ns [D1] 8 ThSY(RXC) /SYNC to /RxC Hold Time 5TcC ns [D1]

9 TdTXCf(TXD) /TxC Fall to TxD Delay 150 ns [D2] 10 TdTXCr(TXD) /TxC Rise to TxD Delay 150 ns [D2,4] 11 TdTXD(TRX) TxD to /TRxC Delay 140 ns 12 TwRTXh /RTxC High Width 120 ns [D5] 13 TwRTXl /RTxC Low Width 120 ns [D5]

Z80181

™

14 TcRTX /RTxC Cycle Time (RxD, TxD) 400 ns [D5,6] 15 TcRTXX Xtal OSC Period 100 1000 ns [D3] 16 TwTRXh /TRxC High Width 120 ns [D5] 17 TwTRXl /TRxC Low Width 120 ns [D5]

18 TcTRX /TRxC Cycle Time 400 ns [D5,7] 19 TwEXT /DCD or /CTS Pulse Width 120 ns 20 TwSY /SYNC Pulse Width 100 ns 21 TxRx(DPLL) DPLL Cycle Time 50 ns [D6,7]

Notes to Table D:

[D1] /RXC is /RTxC or /TRxC, whichever is supplying the receiver clock. [D2] /TXC is /TRxC or /RTxC, whichever is supplying the transmitter clock. [D3] Both /RTxC and /SYNC pins have 30 pF Capacitors (to Ground). [D4] Parameter applies only to FM encoding/decoding. [D5] Parameter applies only to transmitter and receiver; baud rate generator timing requirements are different. [D6] The maximum receive or transmit data rate is 1/4 TcC. [D7] Applies to DPLL clock source only; maximum data rate of 1/4 TcC still applies.

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Figure 72 shows the system timing for the on-chip SCC. Parameters referenced in this figure appear in Table E.

/RTxC, /TRxC

Receive

/W//REQ

Request

/W//REQ

Wait

/SYNC Output

/INT

Z80181

SMART ACCESS CONTROLLER SAC

™

/RTxC, /TRxC

Transmit

/W//REQ

Request

/W//REQ

Wait

/DTR//REQ

Request

/INT

/CTS, /DCD

/SYNC

Input

DS971800500

/INT

Figure 72. SCC System Timing

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SMART ACCESS CONTROLLER SAC

AC CHARACTERISTICS (Continued)

SCC System Timing

Table E. SCC System Timing Parameters

Z8018110

No Symbol Parameter Min Max Unit Note

1 TdRxC(REQ) /RxC to /W//REQ Valid 8 12 TcC [E2] 2 TdRxC(W) /RxC to Wait inactive 8 14 TcC [E1,2] 3 TdRxC(SY) /RxC to /SYNC Valid 4 7 TcC [E2] 4 TdRxC(INT) /RxC to /INT Valid 10 16 TcC [E1,2] 5 TdTxC(REQ) /TxC to /W//REQ Valid 5 8 TcC [E3]

6 TdTxC(W) /TxC to Wait inactive 5 11 TcC [E1,3] 7 TdRxC(DRQ) /TxC to /DTR//REQ Valid 4 7 TcC [E3] 8 TdTxC(INT) /TxC to /INT Valid 6 10 TcC [E1,3] 9 TdSY(INT) /SYNC to /INT Valid 2 6 TcC [E1] 10 TdEXT(INT) /DCD or /CTS to /INT Valid 2 6 TcC [E1]

Notes for Table E:

[E1] Open-drain output, measured with open-drain test load. [E2] /RXC is /RTxC or /TRxC, whichever is supplying the receiver clock. [E3] /TXC is /TRxC or /RTxC, whichever is supplying the transmitter clock.

Z80181

™

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AC CHARACTERISTICS (Continued) PIA General-Purpose I/O Port Timing

Figure 73 shows the timing for the PIA ports. Parameters referenced in this figure appear in Table F.

T1 T2 Tw T3

/IORQ, /RD

PIA Input

Z80181

SMART ACCESS CONTROLLER SAC

™

PIA Output

Figure 73. PIA Timing

Table F. PIA General-Purpose I/O Timing Parameters

Z8018110

No Symbol Parameter Min Max Unit

1 TsPIA(C) PIA Data Setup time to Clock Rise 10 ns 2 TdCr(PIA) Clock Rise to PIA Data Valid Delay 50 ns

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13245

7, 8

AC CHARACTERISTICS (Continued) Interrupt Daisy-Chain Timing

Figure 74 shows the interrupt daisy-chain timing. Parameters referenced in this figure appear in Table G.

CLK

/M1

/IORQ

Data

IEI

SMART ACCESS CONTROLLER SAC

Z80181

™

IEO

/INT

(SCC)

/WAIT

Figure 74. Interrupt Daisy-Chain Timing

Table G. Interrupt Daisy-Chain Timing Parameters

Z8018110

No Symbol Parameter Min Max Unit

1 TsM1(Cr) /M1 Fall to Clock Rise Setup Time 20 ns

2 TsM1(IO)INTA /M1 Fall to /IORQ Fall Setup Time

(During INTACK Cycle) 2TcC ns 3 Th Hold Time 0 4 TdM1r(DOz) /M1 Rise to Data Out Float Delay 0 ns 5 TdCr(DO) Clock Rise to Data Out Delay

2-68

6 TsIEI(TW4) IEI to TW4 Rise Setup Time 95 ns 7 TdIEIf(IEOf) IEI Fall to IEO Fall Delay 8 TdIEIr(IEOr) IEO Rise to IEO Rise Delay 9 TdM1f(IEOf) /M1 Fall to IEO Fall Delay 10 TdCWA(f)INTA Clock Rise to /WAIT Fall Delay 11 TdCWA(r)INTA Clock Rise to /WAIT Rise Delay

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Note for Interrupt Acknowledge Cycle and Daisy Chain

SMART ACCESS CONTROLLER SAC

Z80181

™

When using the interrupt daisy chained device(s) for other than the Z181 (without external logic), the following restrictions/notes apply:

The device(s) must be connected to the higher priority location (Figure 75).

The device(s) IEI-IEO delay must be less than two clock cycles.

The Z181 on-chip interface logic inserts another three wait states into the interrupt acknowledge cycle to meet the onchip SCC and the Z80 CTC timing requirements. (For a total of five wait states, including the two automatically inserted wait states).

To meet the timing requirements, the Z181’s on-chip circuit generates interface signals for the SCC and CTC. Figure 78 has the timing during the interrupt acknowledge cycle, including the internally generated signals.

The following are three separate cases for the daisy-chain settle times:

Case 1 - SCC: The SCC /INTACK signal goes active on the T1 clock fall time. The settle time is from SCC /INTACK active until the SCC /RD signal goes active on the fourth rising wait state clock.

Case 2 - CTC: The settle time for the on-chip /IORQ is between the fall of /M1 until the internal CTC /IORQ goes active on the rise of the fourth wait state (the same time as SCC /RD goes active).

Case 3 - OFF-chip Z80 Peripheral: The settle time for the off-chip Z80 peripheral is from the fall of /M1 until CTC /IORQ goes active. Since the Z181’s external /IORQ signal goes active on the clock fall of the first automatically inserted wait state (TWA), the external daisy-chain device must be connected to the upper chain location. Also, it must settle within two clock cycles.

If any peripheral is connected externally with a lower daisy chain priority than Z181 peripherals, /IORQ must be delayed by external logic as shown in Figure 79.

Vcc

Peripheral

Device(s)

IEI IEO IEI IEOIEI IEO

CTC SCC

Z80181

Figure 75. Peripheral Device as Part of the Daisy Chain

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123

3651110

1239

AC CHARACTERISTICS (Continued) Read Write External BUS Master Timing

CLK

SMART ACCESS CONTROLLER SAC

Z80181

™

Address

/IORQ

/RD

Data

/WR

Data

A7-A0

Data OUT

Data IN

Figure 76. Read/Write External BUS Master Timing

Table H. External Bus Master Interface Timing (Read/Write Cycles)

Z8018110

No Symbol Parameter Min Max Unit

1 TsA(Cr) Address to CLK Rise Setup Time 20 ns 2 TsIO(Cr) /IORQ Fall to CLK Rise Setup Time 20 ns 3 Th Hold Time 0 4 TsRD(Cr) /RD Fall to CLK Rise Setup Time 20 ns 5 TdRD(DO) /RD Fall to Data Out Delay 120 ns

6 TdRIr(DOz) /RD, /IORQ Rise to Read Data Float 0 7 TsWR(Cr) /WR Fall to CLK Rise Setup Time 20 ns 8 TsDi(WRf) Data in to /WR Fall Setup Time 0 9 ThWIr(Di) /IORQ, /WR Rise to Data In Hold Time 0

10 TsA(IORQf) Address to /IORQ Fall Setup Time 50 ns 11 TsA(RDf) Address to /RD Fall Setup Time 50 ns 12 TsA(WRf) Address to /WR Fall Setup Time 50 ns

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SMART ACCESS CONTROLLER SAC

SCC External BUS Master Timing

Valid SCC

Addr * IORQ

/RD or

/WR

DTR/REQ

Request

Figure 77. SCC External BUS Master Timing

Table I. External Bus Master Interface Timing (SCC Related Timing)

Z8018110

No Symbol Parameter Min Max Unit Notes

Z80181

™

1 TrC Valid Access Recovery Time 4TcC ns [1] 2 TdRDr(REQ) /RD Rise to /DTR//REQ Not Valid Delay 4TcC ns

Note for Table I:

[1] Only applies between transactions involving the SCC.

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AC CHARACTERISTICS (Continued)

SMART ACCESS CONTROLLER SAC

Z80181

™

CLK

/M1

/IORQ

SCC

/INTACK

/WAIT

SCC

/RD

CTC

/IORQ

T T T

1 2 WAWAWWW3

Settle Time for Off-chip Z80 Peripherals

/WAIT Signal generated by interface circuit

TTTTT

Settle Time for On-chip CTC

Settle Time for SCC

Vcc

Figure 78. Interrupt Acknowledge Cycle Timing

IEI IEO IEI IEO IEI IEO

CTC SCC

Z80181

/IORQ

External

Logic to

Extend

/IORQ Signal

Peripheral

Device(s)

Figure 79. Peripheral Device as Part of the Daisy Chain

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PACKAGE INFORMATION

SMART ACCESS CONTROLLER SAC

Z80181

™

DS971800500

100-Pin QFP Package Diagram

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ORDERING INFORMATION Z80181 (10 MHz)

Extended Temperature

100-Pin QFP

Z8018110FEC

Package

Longer Lead Time

F = Plastic Quad Flat Pack

Temperature

Longer Lead Time

E = –40°C to +100°C

Environmental

C = Plastic Standard

Speed

10 = 10 MHz

Example:

Z 80181 10 F E C is a Z80181, 10 MHz, QFP, –40°C to +100°C, Plastic Standard Flow

SMART ACCESS CONTROLLER SAC

Z80181

™

Environmental Flow Temperature Package Speed Product Number Zilog Prefix

© 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.

Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com

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Datasheet Z8018110FEC Datasheet (ZILOG)

Specifications and Main Features

Frequently Asked Questions

User Manual

PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DC CHARACTERISTICS

AC CHARACTERISTICS

PACKAGE INFORMATION