Datasheet YMF721 Datasheet (YAMAHA)

YMF721

OPL4-ML2

FM + Wavetable Synthesizer LSI

OVERVIEW

YMF721 (OPL4-ML2) is a high quality and low cost Wavetable synthesizer LSI. YMF721 (OPL4-ML2)
integrates an OPL3 (FM synthesizer), General MIDI processor and 1 Mbyte Wavetable sample ROM into one
chip, and complies with General MIDI (GM) system level 1. Thus, it is best suited to multimedia applications,
sound cards, MIDI synthesis modules and other sound applications.
Since this LSI outputs stereophonic 16 bit digital signal (fs = 44.1 kHz), it can b e connected directly with
YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) or with YAC516(DAC16-L).
Operating voltage, 3.3 V, allows this LSI to be controlled with notebook personal computers.
Power management functions (power d own and suspend/resume functions) of OPL4-ML2 contribute to low
power consumption of personal computers into which this product is built-in.

FEATURES

• The Wavetable synthesizer of this LSI is able to generate up to 24 types of sounds simultaneously.

• Has an interface that makes this LSI compatible with MPU-401 UART mode.

• Has an OPL3 (FM synthesizer) for AdLib/Sound Blaster applications.

• Has a 1 Mbyte built-in Wavetable sample ROM.

• Complies with GM system Level 1. (Thus, it is compatible with DOS applications that support MPU-401.)

• MIDI signal can be transmitted either through seria l input or parallel input.

• FM synthesizer and Wavetable synthesizer of this LSI can generate their sound at the same time.

• FM synthesizer is register-compatible with OPL3.

• All registers are readable.

• Power management functions included power down and suspend/resume can be supported.

• Frequency of master clock signal is 33.8688 MHz.

• Pin compatible with YMF704C-S (100 pin SQPF)

• Voltage of power supply can be 5.0 V or 3.3 V.

• Silicone gate CMOS process

• 100-pin SQFP (YMF721-S).

GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and
indicates GM system level 1 Compliant.

YAMAHA

CORPORATION

CATALOG No.:LSI-4MF721A20

YMF721 CATALOG

July 10, 1997

Jury 10, 1997

YMF721

/
/

PIN CONFIGURATION

YMF721-S

VDD

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS

XOXI5V/3V

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

ADB7

ADB6

VSS

ADB5

ADB4

ADB3

ADB2

ADB1

ADB0

AIRQ

RST

/IOW

/IOR

VSSA2A1A0/OPLCS

9998979695949392919089888786858483828180797877

VDD

/MPUCS

ARDY

ABDIR

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VDD
N.C.
VSS

TEST2

RESETSEL
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0

DO3

DO2

DO1

LRO

WCO

DO0

BCO

CLKO

RXD

/PDOUT

FSP

VDD

T0T1T2T3T4T5T6

T7

VSS

/TEST

/TEST3

/TESTB

/TESTA

100 pin SQFP Top View

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July 10, 1997

YMF721

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p

p

PIN DESCRIPTION

ISA bus interface : 19 pins
Pin name
ADB7-0 8 I/O TTL 2mA Data bus
A2-0 3 I TTL - Address bus
/MPUCS 1 I TTL - MPU401 chip select
/OPLCS 1 I TTL - FM/Wavetable/Command/Control chip select
/IOW 1 I TTL - Write enable
/IOR 1 I TTL - Read enable
RST 1 I TTL - Initial clear input
AIR
ABDIR 1 O TTL 2mA Selection of data transfer direction

ARDY 1 OD TTL 12mA I/O channel ready/busy selection ("L" : Bus

MIDI interface : 2 pins
Pin name
RXD 1 I T TL - MIDI serial data input
FSP 1 I TTL - Selection of MIDI serial/parallel transmission

ins I/O Type Size Function

1 O TTL 2mA Interrupt signal ("H" : Interrupt

(“L” : YMF721®Host)

ins I/O Type Size Function

(“H” : Parallel, “L” : Serial)

Serial audio interface : 8 pins
Pin name
CLKO 1 O CMOS 8mA Clock output (384fs = 16.9344MHz)
BCO 1 O CMOS 2mA Bit clock output (48fs = 2.1168MHz)
LRO 1 O CMOS 2mA L/R clock output (fs = 44.1kHz)
WCO 1 O CMOS 2mA Word clock output (2fs = 88.2kHz)
DO3 1 O CMOS 2mA Effect send output
DO2 1 O CMOS 2mA MIX (FM + Wavetable) output
DO1 1 O CMOS 2mA Wavetable output
DO0 1 O CMOS 2mA FM output

ins I/O Type Size Function

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July 10, 1997

YMF721

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y

p

p

)

Others : 39 pins
Pin name
5V/3V 1 I CMOS - Selection of power suppl
/RESETSEL 1 I+ TTL - RST signal polarity control pin

/PDOUT 1 O CMOS 2mA Power down control output
XI 1 I CMOS 2mA Crystal oscillator connection or master clock input

XO 1 O CMOS 2mA Crystal oscillator connection pin
N.C. 34 - - - To be open at normal use.

LSI test pins : 21 pins
Pin name
/TESTA 1 I+ TTL - To be open at normal use.
/TESTB 1 I+ TTL - To be open at normal use.
/TEST 1 I+ TTL - To be open at normal use.
/TEST2 1 I+ TTL - To be open at normal use.
/TEST3 1 I+ TTL - To be open at normal use.
T7-0 8 O CMOS 2mA To be open at normal use.
TD7-0 8 I/O CMOS 2mA To be open at normal use.

ins I/O Type Size Function

(When this pin is at "L", RST is active at "L".)

(33.8688 MHz)

ins I/O Type Size Function

Power supply, ground : 11 pins
Pin name
VDD 4 - - - Power supply (put on +5.0 V or +3.3V
VSS 7 - - - Ground

Total : 100 pins

Note : I+ : Input pin with built-in pull-up resistor, OD : Open drain output pin

ins I/O Type Size Function

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July 10, 1997

YMF721

,

,

[

]

]

/

BLOCK DIAGRAM

/MPUCS

/RESETSEL

ADB[7-0

A

/OPLCS

/IOW

RXD

2-0

/IOR

RST

FSP

XI

XO

ABDIR

AIRQ

ARDY

5V/3V

ISA BUS

Interface

Decode

Logic

UART

Timing

Generator

Micro Processor

MIDI Interpreter

Command Interpreter

Register

Control

(MPU/Command

/Control)

SRAM

32kbit

Synthesizer

Interface

(arbitration etc.)

ROM

256kbit

TD[7-0]

TEST
Logic

Synthesizer

/TEST

/TEST2

/TEST3

/TESTA

T[7-0

/TESTB

VSS

VDD

Wave ROM

1M byte

Wavetable

DO3
DO1

Synthesizer

DO2

OPL3

FM Synthesizer

Timing Control

MIX(FM+Wave)

DO0

PDOUT
CLKO
BCO
LRO
WCO

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July 10, 1997

YMF721

/

/

/

/

/

/

FUNCTIONS

1. 1. Example of system configuration
1-1. System with MPU401 UART

This section describes two examples of systems that have an MPU401 UART in them.
In these examples, YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) has a built-in MPU401 UART.

(1) ISA BUS Connect System

YMF7xx

(OPL3-SAx)

CLKO

SYNCS
EXTEN

TXD

BCLK_ML
LRCK_ML
SIN_ML

XI

OPLCS

MPUCS
FSP
RXD

BCO
LRO
DO2

ARDY

RST

A2-0

/IOW

/IOR

ADB7-0

YMF721

ABDIR

(OPL4-ML2)

LS245

IOCHRDY
RESETDRV
SA2-0

IOW
IOR

SD7-0

Note :
YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx)
is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2)
is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2).
For the above case, FM synthesizer of YMF7xx (OPL3-SAx) is disabled and the one in YMF721 (OPL4­ML2) is made active. (This c ontrol is made through /EXT EN pin of YMF7xx.) For the above system, the
data bus that connects with YMF721(OPL4-ML2) gains access to FM-synthesizer/Command/Control port
of YMF721(OPL4-ML2). (Chip select signal is outputted from /SYNCS pin of YMF7xx.)
For the source of master clock to be inputted to XI pin of YMF721 (OPL4-ML2), it is recommended to use
CLKO pin of YMF7xx (OPL3-SAx). For other methods, a crystal oscillator can be used by attaching it to
XI and XO pins of YMF721 (OPL4-ML), or a clock of 33.8688 MHz supplied from the system can be used.
When serial data outputs of YMF721 (OPL4-ML2), BCO, LRO and DO2 pins, are connected with external
serial data interface (BCLK_ML, LRCK_ML, SIN_ML) of YMF7xx (OPL3-SAx), the serial data is
converted to analog signal in YMF7xx (OPL3-SAx) and outputted as analog signal.

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July 10, 1997

YMF721

/

I

/

/

/

(2) No ISA BUS Connect System

X

OPLCS

MPUCS
FSP
RXD

PDOUT
CLKO
BCO
LRO
DO2

YMF721

YMF7xx

(OPL3-SAx)

Note :

TXD

LchAUX2L

RchAUX2R

Gain (+12dB)

PDIN
MCLK
BCLK
LRCK
SDATA

YAC516

XO

ARDY

ADB7-0

ABDIR

(OPL4-ML2)

RST

A2-0

/IOW

/IOR

RESET

YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx)
is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2)
is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2).
The above system does not connect YMF721 (OPL4-ML2) and ISA bus, which is an example of Wavetable
upgrade solution represented b y the Wavetable daughter card . Input pins of the ISA bus interface should be
pulled up externally. At this time, FM synthesizer/Command/Control ports are disabled, but the power
down function is enabled by receiving System Exclusive Message on the MIDI data, except that
Suspend/Resume function is disabled.
As a source of master clock for YMF721 (OPL4-ML2), use a crystal oscillator by connecting it to XI and
XO pins, or use the clock of 33.8688 MHz from the system. Connect BCO, LRO, DO2, /PDOUT and
CLKO directly to YAC516 (DAC16-L) as shown to convert serial data output to analog signal. Then, it is
recommended to input the converted analog signal to AUX2L and AUX2R of YMF7xx (OPL3-SAx) after
amplifying the volume of source of YMF721 through the gain of +12 dB as shown for the purpose of
equalizing the volumes of multiple sources.

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July 10, 1997

YMF721

/

/

/

I

/

/

/

1-2. System without MPU401 UART

This section describes an example of a system that does not have MPU401 UART in it.
In this example, MPU401 UART of YMF721 (OPL4-ML2) is used.
FM synthesizer of this LSI is compatible with applications that support AdLib/Sound Blaster, and Wavetable
synthesizer is compatible with applications that support MPU401.

X

SA15-0

AEN

XO

OPLCS

Address

Decoder

PDIN

LchLch out

RchRch out

Gain up

MCLK
BCLK
LRCK
SDATA

YAC516

MPUCS
FSP
RXD

PDOUT
CLKO
BCO
LRO
DO2

ARDY

RESET

A2-0

/IOW

/IOR

ADB7-0

YMF721

ABDIR

(OPL4-ML2)

LS245

IOCHRDY
RESETDRV
SA2-0

IOW
IOR

SD7-0

Note :
For the above case, MPU401 port of YMF721 (OPL4-ML2) must be made active because the system does not
have MPU401 UART in it. Addresses of standard ports through which reading or writing of registers of
YMF721 (OPL4-ML2) is made are as follows.

1) /OPLCS : 388 - 38Fh (8byte)

2) /MPUCS : 330 - 331h (2byte)
As a source of master clock for YMF721 (OPL4-ML2), use a crystal oscillator by connecting it to XI and
XO pins, or use the clock of 33.8688 MHz from the system. Connect BCO, LRO, DO2, /PDOUT and
CLKO directly to YAC516 (DAC16-L) as shown to convert serial data output to analog signal. Then, it is
recommended to amplify the volume of source of YMF721 through the suitable gain as shown for the
purpose of equalizing the volumes of multiple sources.

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July 10, 1997

YMF721

2. ISA bus interface

8 bit parallel I/O of YMF721 (OPL4-ML2) can be connected with ISA bus. The ISA bus interface allows
transfer of commands between the each block of YMF721 (OPL4-ML2) and host.

Data Bus & Address Bus

ADB7-0 : ISA data bus
A2-0 : ISA address bus
/MPUCS : MPU401 chip select
/OPLCS : FM/Wavetable/Command/Control chip select
/IOW : ISA write enable
/IOR : ISA read enable
ABDIR : Data bus direction switching (“L” : YMF721 ® ISA)
ARDY : I/O channel ready (“L” : busy)

Control of the data bus is made with /MPUCS, /OPLCS, /IOW and /IOR signals. The mode of
control of the data bus varies as follows according to the combination of states of the signals.
The direction of data transfer on the data bus is determined by ABDIR. In normal operatio n, the
internal data bus of YMF721 (OPL4-ML2) connects the built-in processor and FM/Wavetable
synthesizer blocks. Every time the ISA bus accesses the register for FM/Wavetable, an internal
arbitration circuit causes the internal bus to connect ISA bus and FM/Wavetable synthesizer
blocks. YMF721 (OPL4-ML2) uses I/O channel ready (ARDY pin) as the internal arbitration
circuit. ARDY becomes "L" (busy) every time data bus accesses the register for FM/Wavetable.

/MPUCS

/OPLCS /IOW /IOR A2 A1 A0 MODE

LHHL
LHLH
LHHL
LHLH
HLHLLLLFM-synth. Status read
H L L H L H/L L FM-synth. Address write
HLLHL
HLHLL
H L H L H L L Wavetable-synth. Status read
H L L H H L L Wavetable-synth. Address write
H L L H H L H Wavetable-synth. Data write
H L H L H L H Wavetable-synth. Data read
HLHLHHLCommand response read
HLLHHHLCommand write
HLLHHHHControl write
H L H L H H H Status read
HLHH
HH

´´´´´

´
´
´
´

´´´

L L MPU401 Acknowledge (FEh)
L L MPU401 MIDI Data write
L H MPU401 Status read
L H MPU401 Command write

´
´

H FM-synth. Data write
H FM-synth. Data read

No-active or UART mode
No-active or UART mode

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July 10, 1997

YMF721

Notes:
´ : Don’t care
When address has been written into FM block, the time required to wait until writing of address
or data into Wavetable block is started is 0 (zero) nsec. When add ress has been written into
Wavetable block, the time required to wait until writing of address or d ata into FM block is
started is also 0 (zero) nsec. When FM block has been accessed, it is necessary to wait 860 nsec
or more before the FM block can be accessed again.

Interrupt

AIRQ : Interrupt signal ("H" : Interrupt)

YMF721 (OPL4-ML2) is able to provide one interrupt signal. There are two types of sources of
this interrupt signal as follows.

1) Two timer flags that are used for tempo counter of FM synthesizer

2) The flag that occurs when internal processor writes data into the Command response register
The flags described in 2) is disabled as a default.

3. Serial audio interface

YMF721 (OPL4-ML2) can be connected directly with an external DAC such as YAC516 through BCO,
LRO, WCO and DO3-0 pins.

BCO... Outputs bit clock. The frequency of this clock is 48 fs. (fs is the sampling

frequency that is equal to the frequency of clock outputted from LRO.) Typical
duty factor of this signal is 50 %.

LRO... Specifies a channel for serial audio data. When LRO is "H", data is outputted

from left channel, or when "L", from right channel. Frequency of this clock is

44.1 kHz. Typical duty factor of this signal is 50 %.
WCO... Frequency of this clock is 88.2 kHz. Typical duty factor of this signal is 50 %.
DO3-0... These pins output serial audio data as follows.

DO3... Outputs data of Wavetable whose effect send level has been adjusted.
DO2... Outputs data that is the mixture of those of FM and Wavetable.
DO1... Outputs Wavetable data.
DO0... Outputs FM data.

Format of the serial audio interface is as follows.

BCO

DO3-0

LRO

WCO

010123456789101115 14 13 12 0123456789101115 14 13 12

Left Channel Right Channel

Format of YMF721 (OPL4-ML2) serial audio interface

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24 BCO24 BCO

July 10, 1997

YMF721

4. MIDI Interface

MIDI serial data can be inputted from RXD pin. It is necessary to input MIDI data complied with MIDI

1.0 detailed specification to RXD pin.
The serial data is the rate of 31.25kbit/sec (+/-1%) and the unit of 10 bits. T he first bit is a start bit, the
next 8 bits are data (LSB to MSB), and the 10th bit is a stop bit.

5. Power management functions

YMF721 (OPL4-ML2) has two types of power management functions as follows.

(1) Global power down mode
(2) Suspend/Resume mode

5-1. Global power down mode

Generation of clock signal is disabled (stopped). Total power consumption of YMF721 (OPL4-ML2) is
approximately 20uA (typ.). Writing "FDh" into command register or receiving System Exclusive MIDI
Message makes in this mode. YMF721 (OPL4-ML2) outputs "L" from /PDOUT pin in this mode,
which can be used as power down control signal for peripheral equipment. Set KON bit (FM
synthesizer register) to "0" for all channels before going into this mode. Check that play back of MIDI
data is stopped.
/RESETSEL pin has a built-in pull up resistor. When this pin is at "L" in this mode, the power
consumption is higher by approximately 30uA than the one when this pin is open or at "H".

5-1-1. ISA BUS Connect System

When "FDh" has been written into command register, the internal pr ocesso r goes into the glo bal p ower
down mode after performing the following internal processes.

1) Disabling synthesizer's internal clock

2) Setting GBUSY bit of status register to "0".
YMF721 (OPL4-ML2) requires over 30 msec to complete the above processes before going into the
power down mode.
Since generation of the clock has been disabled, recovery from the power down mode can not be made
by using command. Thus, it is nec essary to use PDY and P DX bits of co ntrol registe r for the re cove ry.
To resume normal ope ra tion thr o ugh the re co ver y sequence , waiting time of 5 0 to 100 msec is required
before the oscillation of crystal stabilizes when internal oscillation is used, or 3 msec or more before
the recovery of cloc k generated in the synthesizer.
For the details of power down command, refer to 6-3. After the power down command, FDh, has been
written, do not write any command before sending a recovery command to the control register to return
to the normal mode.

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July 10, 1997

YMF721

<Power Down out><Power Down in>

Comma nd write “FDh” Control write PDY=1, PDX=0

(wait time ~100 msec)

Control write PDY=0, PDX=0

Synthesizer clock enable

Normal Operation

~30msec

Synthesizer clock disabl e

Status read GBUSY=0

all clock (X’tal)disable

Power down sequence when connected with ISA bus

~3msec

5-1-2. No ISA BUS Connect System

When YMF721 (OPL4-ML2) is not connected with ISA bus, power down operation can be controlled
by sending Yamaha's original System Exclusive Message as the MIDI data. The System Exclusive
Message includes the following three byte ID.

43h, 79h, 04h : Yamaha YMF721(OPL4-ML2) ID

The System Exclusive Message is as follows.

F0h, <Yamaha YMF721(OPL4-ML2) ID>, <Command>, <Data>, F7h

YMF721 (OPL4-ML2) supports the following commands and data.

Command Data Function

0Eh 6Dh Power Down Command
0Fh 6Bh

Internal Micro-processor Reset Command

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July 10, 1997

YMF721

<Power Down Sequence>

(1) Power Down in

When YMF721 (OPL4-ML2) has received the System Exclusive Message shown above, it goes
into the global power down mode after performing the processes as described in "5-1-1. ISA
BUS Connect System".

(2) Power Down out

Since the clock generation has been disabled, YMF721 (OPL4-ML2) is not able to recover from
the global power down mode by using the System Exclusive Message. Thus, the LSI needs to
receive the "3byte MIDI data" as shown below to recover from the global power down mode.
To resume normal oper ation through the recovery sequence , waiting time of 50 to 100 msec is
required before the oscillation of crystal stabilizes when internal oscillation is used, o r 3 msec or
more before the re covery of clock genera ted in the synthesizer.

<Power Down out><Power Down in>

System Exclusive : F0h, 43h, 79h, 04h,0Eh, 6Dh, F7h receiving MIDI F8h

(wait time ~100 msec)

~30msec

<Micro-processor Reset>

The internal microprocessor is reset by receiving the above System Exchange Message.

Synthesizer clock disabl e

all clock (X’tal)disable

~3msec

Power down sequence without ISA bus

receiving MIDI E0h

receiving MIDI F8h

Synthesizer clock enable

Normal Operation

5-2. Suspend/Resume mode

The state of internal processor is suspended by writing "E0h" into the co mmand register before turning
off the power. When the power has been turned on, it can be resumed by resetting it, writing "E1h" into
the command register and then writing data that has been read before suspended.
On FM synthesizer block, check setting KON bit to "0" for all channels before reading out all register
and turning off the power. Write register that has been read after turning on and resetting at the
recovery sequence.
For the details of suspend/resume, refer to 6-3.

Note :
The system that includes YMF721 not connected with ISA bus can not support the suspend/resume function.

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July 10, 1997

YMF721

6. Registers
6-1. MPU401 compatible register

MPU401 is a generally used interface for controlling MIDI devices on the personal computer. I/O
addresses that are compatible with MPU401 are as follows.

MPU_Base+ 0 (W/R) MIDI Data transmit/acknowledge port
MPU_Base + 1 (R) Status Register port
MPU_Base + 1 (W) Command Register port

MIDI Data Write Port (WO):

port D7D6D5D4D3D2D1D0

MPU_Base + 0

MIDI Data... Port for writing MIDI data (transmitting). Transmission of the

data must be carried out while the transmitter of MIDI data is
watching the state of DRR bit of the status register. An interrupt
occurs in the internal processor when MIDI data has been
written into the register. Since YMF721 (OPL4-ML2) has no
output signal for transmitting MIDI data, the MIDI data written
into this register is used to operate internal Wavetable
synthesizer.

MIDI Data

MPU Acknowledge Port (RO):

port D7D6D5D4D3D2D1D0

MPU_Base + 0

Sends acknowledge for the operation of MPU401.
When operation of the MPU401 is normal, "FEh" is read from this port.

Status Register Port (RO):

port D7D6D5D4D3D2D1D0

MPU_Base + 1

DSR... This bit is "1" when reading the acknowledge from MPU401.

DRR... This bit is "1" while MIDI data is being written into MP U Data

Default : BFh

Command Register Port (WO):

port D7D6D5D4D3D2D1D0

MPU_Base + 1

COMMAND Data... The data written into this register is ignored. DSR bit is set to

“1” “1” “1” “1” “1” “1” “1” “0”

DSR DRR “1” “1” “1” “1” “1” “1”

This bit is "0" when writing commands.

Write port (MPU Base+0 ). This bit is "0" when the MIDI data
can be written into the MPU Data Write port. Do not write
MIDI data when this bit is "1".

COMMAND Data

"0" when data is written into this register.

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July 10, 1997

YMF721

6-2. Command/Response register

I/O port for power down and suspend/resume register is described here.

Command/Response Port (R/W):

port D7D6D5D4D3D2D1D0

OPL_Base + 6
OPL_Base + 6

Command Write... An interrupt occurs when data has been written into this register.
Response Read... Response to a command is read from this register.

Note :
For the details of Command/Response, refer to 6-3.

6-3. Details of command register

Some of commands supported in the command register are as follows.

Command Write
Response Read

Command Sub Command Command Length Response Length

E0h - 1 byte variable Reading suspend information
E1h 00h variable - Resume
FDh - 1 byte - Moving into power down mode
FEh - 1 byte - Checking operating conditions
FFh - 1 byte - Discontinuing command execution

6-3-1. Suspend information

Command and response ha ve the following formats.

Command Response

E0h Command byte FFh Response 1st byte

checksum checksum (8 bit)

Function

length L data length (lower 8bit)
length H data length (upper 8bit)

data_0 data

........... .......

data_n last data

Checksum is determined so that lower eight bits of the sum of values from length L to checksum
becomes "0".
The state of internal processor immediately before execution of this command can be resumed by
writing the data that is read into the internal processor by using resume command described below.

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July 10, 1997

YMF721

6-3-2. Resume

Command and Response have the following formats.

Command Response

E1h Command byte None

0x00 Sub Command

data_0 data

.......... .......

data_n last data

checksum checksum

For Resume, data following the sub command are transmitted as seven bit data. Thus, it is necessary
to send the data obtained with suspend command to the internal processor after encoding it.
Checksum is determined so that the result of logical product (AND) of 7Fh and the sum of sub
command byte, encoded data and checksum becomes "0". The internal processor returns to the state
immediately before execution of Command E0h when it confirms that the data has been received
normally.

6-3-3. Others

YMF721(OPL4-ML2) can use the following special commands that do not send response.

1) Command FDh : Power down mode

Refer to 5-1.
When the power down command FDh has been written into the command register, do not write
any command before the return command to the control register has been executed.

2) Command FEh : Checking operating state of internal processor

This command is used to check if the internal processor is operating normally.
The internal processor is deemed operating normally if GBUSY bit of Status register is "0".

3) Command FFh : Discontinuing command execution

This command is used to discontinue the execution of a command. This command can be used
only when another command is being executed.

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July 10, 1997

YMF721

6-4. Control/Status register

I/O port for Control/Status register is described here.

Control/Status Port (R/W):

port D7D6D5D4D3D2D1D0

OPL_Base + 7(W)
OPL_Base + 7(R)

PDY, PDX... YMF721 recovers from power down mode by using the

MPR... Setting this bit to "0" initializes internal processor. Default

BSEL... This bit shows connection of internal bus of YMF721(OPL4-

RESP... Indicates that a response to a command has been received.
GBUSY... Flag bit that indicates if data can be written into Command write

GDRQ... Flag bit that indicates if data can be read from Response

Default : (00x1 x000)

PDY PDX - - - MPR “0” “1”
PDY PDX - BSEL - RESP GBUSY GDRQ

following sequence.

PDY=“1”, PDX=“0”
¯ wait time (in case of using crystal oscillation)

PDY=“0”, PDX=“0”
D7 and D6 bits of Status register become "1" during power
down mode. In this state, oscillation of clock can be confirmed
by monitoring the status bit during power down mode in/out
sequence.

value of this bit is "1".

ML2). Default value of this bit is "1".

“1” : Connecting synthesizer and internal processor

“0” : Connecting synthesizer a nd ISA bus

register.

“1” : BUSY

“0” : Data can be written

register.

“1” : READY

“0” : Reading is inhibited

b0

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July 10, 1997

YMF721

6-5. FM synthesizer registers

6-5-1. Status register

Status Register (RO):

port D7D6D5D4D3D2D1D0

OPL_Base + 0

Note :
Since NEW2 (index 05h of Register array1) = 1 in default state, both LD and BUSY0 bits are valid.
(LD and BUSY0 bits are invalid when NEW2=0.) BUSY0 is a BUSY flag for both FM and
Wavetable registers.

IRQ FT1 FT2 - - - LD BUSY0

6-5-2. Data register

Data Register Array 0 (R/W):

Index D7 D6 D5 D4 D3 D2 D1 D0

00 - 01h LSI TEST

02h TIMER 1
03h TIMER 2
04h RST MT1 MT2 - - - ST2 ST1

08h - NTS - - - - - ­20 - 35h AM VIB EGT KSR MULT
40 - 55h KSL TL
60 - 75h AR DR
80 - 95h SL RR

A0 - A8h F-NUM (L)
B0 - B8h - - KON BLOCK F-NUM (H)

BDh DAM DVB RHY BD SD TOM TC HH
C0 - C8h CHD CHC CHB CHA FB CNT
E0 - F5h----- WS

- 18 -

July 10, 1997

YMF721

Data Register Array 1 (R/W)

Index D7 D6 D5 D4 D3 D2 D1 D0

00 - 01h LSI TEST

04h - - CONNECTION SEL

05h - - - - - NEW3 NEW2 NEW
20 - 35h AM VIB EGT KSR MULT
40 - 55h KSL TL
60 - 75h AR DR
80 - 95h SL RR

A0 - A8h F-NUM (L)
B0 - B8h - - KON BLOCK F-NUM (H)
C0 - C8h CHD CHC CHB CHA FB CNT
E0 - F5h----- WS

Default :
After initial clear, all the bits of Register Array 1 are cleared to "0" except NEW2 and NEW3 bits of
index 05h, and CHA and CHB bits of index C0-C8h.
For the details of these registers, refer to data sheet for YMF289B(OPL3-L).

Note :
Since NEW2 and 3 (at index 05h of Register array1) = 1 in default state, both LD and BUSY0 bits
are valid. (LD and BUSY0 bits are invalid when NEW2=0.) BUSY0 is a BUSY flag for both FM
and Wavetable registers.

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July 10, 1997

YMF721

6-6. Wavetable synthesizer register

6-6-1. Status register

Status Register (RO):

port D7D6D5D4D3D2D1D0

OPL_Base + 4

6-6-2. Data register

Data Register (R/W):

Index D7 D6 D5 D4 D3 D2 D1 D0

00 - 01h LSI TEST

02h DEVICE ID (“0” “1” “0”) TONE HEADER MTYPE MODE

03h Memory Address (MA21-16)

04h Memory Address (MA15-8)

05h Memory Address(MA7-0)

06h Memory Data(MD7-0)

08-1Fh TONE NUMBER (L)
20-37h F-NUMBER (L)
38-4Fh BLOCK PREV F-NUMBER (H)
50-67h TOTAL LEVEL LDIR
68-7Fh KEYON DAMP LFORST CH PAN POT

80-97h CHORUS SEND LFO VIB
98-AFh AR D1R
B0-C7h DL D2R
C8-DFh RATE INTERPOLATION RR
E0-F7h REVERB SEND - - AM

F8h - - MIX CONTROL (FM-R) MIX CONTROL (FM-L)

F9h - - MIX CONTROL (Wave-R) MIX CONTROL (Wave-L)
FAh-------ATC
FBh--------

------LDBUSY1

TNUM (H)

Default :
After initial clear, index 02h becomes 40h (Device ID) and index F8h becomes 2Dh (-15dB), and all
the other registers are cleared to "0". For the details of these registers, refer to data sheet for
YMF295(OPL4-D).

Note :
BUSY1 is a BUSY flag for Wavetable registers. Wavetable status/Data register is normally accessed
by the internal processor.

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July 10, 1997

YMF721

7. Hardware
7-1. ISA bus interface

(1) Data Bus Connect System

Data BUS

Since driving current of data bus, ADB7-0 pins, of YMF721(OPL4-ML2) is about 2 mA (at VDD =

5.0 V), it is recommended to use bus buffer such as LS245 as necessary. At this time, connect ABDIR
pin which outputs bus direction signal of YMF721(OPL4-ML2) with DIR (direction) pin of the bus
buffer such as LS245.

RESET

Reset (RST) pin of YMF721(OPL4-ML2) can be made "H" active or "L" active. When using "H"
active reset, /RESETSEL pin should be open or set to "H", or to "L" when using "L" active reset.
/RESETSEL pin has a built-in pull-up resistor. When this pin is set to "L", the power consumption
increases approximately by 30uA from the one obtained when the pin is open or set to "H".

I/O Channel Ready

In normal operation, the internal data bus of YMF721 (OPL4-ML2) connects the built-in processor
and FM/Wavetable synthesizer blocks. Every time the ISA bus accesses the register for
FM/Wavetable, an internal arbitration circuit causes the internal bus to connect ISA bus and
FM/Wavetable synthesizer blocks. YMF721 (OPL4-ML2) uses I/O channel ready (ARDY pin) as the
internal arbitration circuit. Connect ARDY pin of YMF721 (OPL4-ML2) and IOCHRDY pin of ISA
bus. Although ARDY pin is an open dr ain output, it is no t necessary to attach p ull up resisto r b ecause
it is usually pulled up at the ISA bus.

(2) No Data Bus Connect System

The input pins ADB7-0, A2-0, /MPUCS, /OPLCS, /IOW and /IOR must be pulled up externally.
Output pins AIRQ, ABDIR and ARDY pins must be open.

7-2. MIDI interface

When using MPU port of YMF721 (OPL4-ML2), RXD and FSP pins must be pulled up. When using
MPU port of the system and receiving MIDI data through RXD pin, FSP pin must be made "L" .

7-3. Serial audio interface

YMF721 (OPL4-ML2) outputs clock signals of CLKO (384 fs = 16.9344 MHz), BCO (48 fs =

2.1168 MHz), LRO (fs = 44.1 kHz) and WCO (2 fs = 88.2 kHz) as the serial audio interface. It also
outputs four types of data including DO0 (FM external out), DO1 (Wavetable external out), DO2
(MIX out) and DO3 (effect-send out). Normally, it uses the output of DO2. When YMF721 (OPL4­ML2) is in power down mode, /PDOUT pin outputs "L" which can be used as the power down control
signal for peripheral systems.

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July 10, 1997

YMF721

7-4. Others

Power Supply

It is recommended to install a line noise filter in the YMF721 (OPL4-ML2). Be sure to install 0.1uF
ceramic capacitor between each of VDD pins and VSS pins as close to the pins as possible, especially
the pin No. 63 (VDD).

5V/3V

When operating YMF721 (OPL4-ML2) with 5 V, 5V/3V pin must be pulled up. When operating it
with 3.3 V, set the pin to "L".

XI, XO

YMF721 (OPL4-ML2) requires the clock frequency of 33.8688 MHz. This signal can be supplied
from the system or from the self-oscillation circuit connected with crystal oscillator

Yamaha recommends either of the following two types of parallel resonance type oscillator
made by Daishinku Co., Ltd.

(i) 3rd Overtone Type

AT-49, SMD-49 : R=5.6K, c

(ii) Fundamental Type

AT-49, SMD-49 : R=1M, c
Use of the Crystal oscillator with frequency deviation within 100 ppm is recommended. Length of
wiring lead from XI and XO pin to each component (crystal, resistor and capacitor) should be 0.5
inch or less respectively and the circuit pattern should be shielded on its periphery to minimize effect
on the peripheral devices.

1=c2

1=c2

=10pF

=5pF

YMF721(OPL4-ML2)

10099

XOXI

33.8688MHz

R

c

1

Since YMF721 (OPL4-ML2) is able to use power down mode, the power consumption can be
minimized when generation of the clock signal is discontinued during this mode.

c

2

- 22 -

July 10, 1997

YMF721

Electrical Characteristics

Absolute Maximum Ratings

Item Symbol Minimum Maximum Unit
Power Supply Voltage (Analog/Digital) V
Input Voltage V
Output Voltage V
Input Current I
Storage Temperature T

Notes : VDD=DVDD=AVDD, VSS=DVSS=AVSS=0[V]

Recommended Operating Conditions

Item Symbol Min. Typ. Max. Unit
Operating voltage 1 (5.0V Spec. 5V/3V=“H”) V
Operating voltage 2 (3.3V Spec. 5V/3V=“L”) V
Operating Ambient Temperature T

Notes : DVSS=AVSS=0[V]

DD

IN

OUT

IN

STG

VSS-0.5 VSS+7.0 V
VSS-0.5 VDD+0.5 V
VSS-0.3 VDD+0.3 V

-20 20 mA

-50 125 °C

DD1

DD2

OP

4.75 5.00 5.25 V

3.00 3.30 3.60 V
02570°C

DC Characteristics

Item Symbol Condition Min. Typ. Max. Unit

TTL-Input Pins

High Level Input Voltage 1
Low Level Input Voltage 1

CMOS-Input Pins

High Level Input Voltage 1
Low Level Input Voltage 1

Input Leakage Current I
Input Capacitance C

Pull up Register R

High Level Output Voltage 1 V
Low Level Output Voltage 1 V
High Level Output Voltage 2 V
Low Level Output Voltage 2 V
Low Level Output Voltage 3 V

Low Level Output Voltage 4 V

Output Capacitance C

Notes : VSS=0[V], TOP=0~70°C, VDD=5.0±0.25[V]

*1) Applicable to output pins except XO and /ARDY.
*2) Applicable to /ARDY pin.

V

IH1

V

IL1

V

IH2

V

IL2

L

I

U1

OH1

OL1IOL1

OH2

OL2IOL2

OLIOL1

OLIOL1

O

Except XI and 5V/3V pins 2.0 V

0.8 V

Applicable to XI and 5V/3V 0.7V

VIN=VSS,V

DD

DD

0.2V

DD

-10 10 mA
10 pF

/TEST, /TEST2
/TEST3, /TESTA
/TESTB, /RESETSEL

I

= -80mA (5V/3V=“L”)

OH1

50 400 kW

2.4 V

= 2mA (*1) 0.4 V

I

= -80mA (5V/3V=“H”) VDD-1.0

OH2

= 2mA (*1)
= 4mA

I

= 2mA (*2)

OL2

= 12mA

I

= 2mA (*2)

OL2

(5V/3V=“L”)

(5V/3V=“H”)

VSS+0.4

0.4 V

0.4 V

10 pF

V
V

V
V

- 23 -

July 10, 1997

YMF721

AC Characteristics

1. CPU interface (Refer to Fig. 1, 2, 3)

Item Symbol Min. Typ. Max. Unit
Address set up to /IOW, /IOR active t
Address hold to /IOW, /IOR inactive t
/IOW Write Pulse Width t
Write Data set up to /IOW active t
Write Data hold to /IOW inactive t
/IOR Read Pulse Width t
Read Data access time t
Read Data hold from /IOR inactive t
Chip select setup time t
Chip select hold time t
RESET Pulse Wid th t

Notes : V

=0[V], TOP=0~70°C, VDD=5.0±0.25[V]

SS

AS

AH

WW

WDS

WDH

RW

ACC

RDH

CS

CH

RST

30 ns
10 ns
50 ns
10 ns
10 ns
80 ns

10 ns

5ns

10 ns

100 ms

60 ns

2. Serial audio interface (Refer to Fig. 4.)

Item Symbol Condition Min. Typ. Max. Unit
CLKO frequenc y f
CLKO duty D

CLKO16

CLKO16

BCO freque ncy f
BCO duty D
Serial data setup time t
Serial data hold tim t
LRO setup time t
LRO hold time t
WCO setup time t
WCO hold time t

Notes : V

=0[V], TOP=0~70°C, VDD=5.0±0.25[V]

SS

Sampling frequency (fs) is 44.1 kHz. Duty factor is measured at 1/2 V

3. Others

Item Symbol Condition Min. Typ. Max. Unit

Master Clock Freq uency f

(X’tal 33) Duty D

Power Consumption I

(during normal operation) I

Power Consumption I

(during power down mode) I

Notes : V

=0[V], TOP=0~70°C

SS

33

f33

OP1

OP2

OP3

OP4

/RESETSEL = "H". Duty factor is measured at 1/2 V

BCK

BCLK

BCO - /DO3-0 - 118 - ns

DS

BCO ¯ /DO3-0 - 118 - ns

DH

LRS

LRH

WCS

WCH

VDD=5.0±0.25[V]
VDD=3.3±0.3[V]
VDD=5.25[V]
VDD=3.60[V]
VDD=5.25[V]
VDD=3.60[V]

BCO - /LRO - 118 - ns
BCO ¯ /LRO - 118 - ns
BCO - /WCO - 118 - ns
BCO ¯ /WCO - 118 - ns

- 16.9344 - MHz

40 50 60 %

- 2.1168 - MHz

40 50 60 %

DD

33.8688 MHz

40 50 60 %

40 50 mA
25 30 mA
25 50 mA
15 30 mA

DD

- 24 -

July 10, 1997

YMF721

I/O write cycle

A2-0

/***CS

/IOW

ADB7-0

t

AS

t

AH

Valid

t

WDH

t

CH

t

CS

t

WW

t

WDS

Fig.1

I/O read cycle

A2-0

/***CS

/IOR

ADB7-0

t

AS

t

AH

Valid

t

RDH

t

CH

t

CS

t

RW

t

ACC

Valid

Fig.2

- 25 -

July 10, 1997

YMF721

Reset pulse width

t

RST

RESET

Fig.3

Serial audio interface

1/f

BCK

BCO

DO3-0

LRO

WCO

t

DS

t

t

LRH

WCH

t

DH

t

LRS

t

WCS

Fig.4

- 26 -

July 10, 1997

YMF721

Supplementary Information 1 (about commands)

The following commands are used to check existence and identification of YMF704C/721(OPL4­ML/ML2) by using device dr iver.

Command Sub Command Command Length Response Length

80h 00h 3byte 11byte Get Processor Device ID
80h 01h 3byte 5byte Get Processor Software Version
80h 02h 3byte 6byte Get Processor Software Capacity
81h 00h 3byte 8byte Get OPL4-MLx Information
82h 00h 3byte 31byte Get wave ROM Copyright Data
82h 01h 3byte 5byte Get wave ROM Version

Function

Command 80h

This command is used mainly to obtain version information of the internal processor. T he device
driver is able to know capability of the internal processor before it controls the hardware.

Sub Command 00h : Get Processor Device ID

Command Response

80h Command byte 8Ah Response 1st byte
00h Sub Command 47h ”G”
00h Check sum 4Dh “M”

50h “P”
5Fh “_” ID Strings
4Fh “O”
50h “P”
4Ch “L”

34h “4”

00h Strings Last Code
1Eh Check sum

The character string "GMP_OPL4" is read from ID strings. Existence of YMF721 (OPL4-ML2) can
be confirmed with this character string.

- 27 -

July 10, 1997

YMF721

Sub Command 01h : Get Processor Software Version

Command Response

80h Command byte 84h Response 1st byte
01h Sub Command 02h Integer part of version number
7Fh Check sum 00h 1st decimal place of version number

00h 2nd decimal place of version number
7Eh Check sum

Version number of firmware stored in the internal processor is read out as shown below.

YMF704B(OPL4-ML) : Version 1.22
YMF704B(OPL4-ML) : Version 1.23
YMF704C(OPL4-ML) : Version 1.24
YMF721C(OPL4-ML2) : Version 2.00

Sub Command 02h : Get Processor Software Capacity

Command Response

80h Command byte 85h Response 1st byte
02h Sub Command 00h No use
7Eh Check sum 00h No use

00h No use
07h Capacity code
79h Check sum

The capacity of internal processor can be known through the capacity code.

bit0 = 1 : The synthesizer is able to add effects such as reverb or chorus send level 1.
bit1 = 1 : Suspend/Resume is supported.
bit2 = 1 :Power down is supported.

YMF704B(OPL4-ML) : Capacity Code=01h
YMF704B(OPL4-ML) : Capacity Code=03h
YMF704C(OPL4-ML) : Capacity Code=03h
YMF721C(OPL4-ML2) : Capacity Code=07h

- 28 -

July 10, 1997

YMF721

Command 81h

Sub Command 00h : Get OPL4-MLx Information

Since the synthesizer of YMF721(OPL4-ML2) is the same as YMF295(OPL4-D), the character
string of "OPL4D" is obtained as described below.

Command Response

81h Command byte 87h Response 1st byte
00h Sub Command 4Fh “O”
00h Check sum 50h “P”

4Ch “L” ID Strings

34h “4”

44h “D”

00h Strings Last Code
1Dh Check sum

Command 82h

These commands are used to know information about the internal Wavetable sample ROM.

Sub Command 00h : Get Wave ROM Copyright Data

Command Response

82h Command byte 9Eh Response 1st byte
00h Sub Command
00h Check sum strings Copyright Data

00h Strings Last Code
46h Check sum

This command is used to know capacity of internal processor. As the strings, character strings of
"copyright yamaha corporation"(28bytes) are returned.

Sub Command 01h : Get Wave ROM Version

Command Response

82h Command byte 84h Response 1st byte
01h Sub Command 01h Integer part of version number
7Fh Check sum 00h First decimal place of version number

03h Second decimal place of version number
7Ch Check sum

This command is used to know version number of internal Wavetabl e sample ROM.

YMF704C(OPL4-ML) : Version 1.02
YMF721C(OPL4-ML2) : Version 1.03

- 29 -

July 10, 1997

YMF721

g

g

Supplementary Information 2 (MIDI Data Format)

1. General

1-1. Application

The following MIDI information applies to the YMF721(OPL4-ML2).

1-2. Applicable Standards

MIDI 1.0 Standard

2. Channel Message

2-1. Send

YMF721(OPL4-ML2) has no transmitting function.

2-2. Receive

2-2-1. Note On/Off

This is a message to inform playing information.

Note On : 9nH kkH vvH
Note Off : 9nH kkH 00H or 8nH kkH vvH

*n : MIDI Channel No.
*kkH : Note No., vvH : Velocity (00 - 7F)

Received note range = C-2 ~ G8 (Note On only)
Verocity range = 1 ~ 127

2-2-2. Control Change <BnH> <Control No.> <Data>

a) Bank Select

This is a message to select a bank of the designated receiving channel. However, the channel 10 does
not receive bank select since it is fixed to drum kit.
The normal voice is selected when Bank Select MSB is “0”, and drum kit when “127”.
After Bank Select MSB is received, it is necessary to receive Program Change.

Control No. Parameter Data ran
0 Bank Select MSB 0 or 127
32 Bank Select LSB don’t care

b) Modulation

This is a message to inform the depth of Vibrato.

Control No. Parameter Data ran
1 Modulation 0 to 127

e

e

- 30 -

July 10, 1997

YMF721

g

g

g

g

g

g

c) Data Entry

This is a message to set control parameter data designated by RPN (Registered Parameter Number).
Refer i) RPN for the relation between the parameter of RPN and the setting data.

Control No. Parameter Data ran
6 Data Entry MSB 0 to 127
38 Data Entry LSB 0 to 127

d) Main Volume

This is a message to control the volume of each part (MIDI channel).

Control No. Parameter Data ran
7 Main Volume 0 to 127

e) Pan

This is a message to control the sound position of each part.

Control No. Parameter Data ran
10 Panpot 0 to 127

0 : left, 64 : center, 127 : right

f) Expression

This is a message to control the volume of each part during playing sound.

e

e

e

Control No. Parameter Data ran
11 Expression 0 to 127

g) Hold

This is a message to control the sustain pedal.
When “Hold ON” is received, sound is kept playing even if “Note OFF” is received.

Control No. Parameter Data ran
64 Hold 0 to 127

0 to 63 : OFF, 64 to 127 : ON

h) Sostenuto

This is a message to control the sostenuto pedal.
When “Sostenuto ON” is received during playing sound, sound is kept playing until “OFF” is received.

Control No. Parameter Data ran
66 Sostenuto 0 to 63, 64 to 127

0 to 63 : OFF, 64 to 127 : ON

e

e

e

- 31 -

July 10, 1997

YMF721

g

g

i) RPN

This is a message to set Pitch Bend Sensitivity and Tuning of each part.
After the modified parameter is designated by RPN MSB and RPN LSB, set the parameter value at
Data Entry.

Control No. Parameter Data ran
100 RPN LSB 0 to 127
101 RPN MSB 0 to 127

RPN
MSB/LSB
00h 00H mmH --- Pitch Bend Sensitivity

00H 01H mmH llH Master Fine Tuning (-100¢ to 100¢)

00H 02H mmH --- Master Coarse Tuning (-24 - 0 - +24 semitone)

2-2-3. Program Change <CnH> <Program No.>

This is a message to select a tone (voice) used in each part. GM tone (Bank Select MSB 0) or drum kit
(Bank Select MSB 127) is received by combination with a Bank Select.

Data Entry
MSB/LSB

mmH : 00H -18H (0-24 semitone)

------ : don’t care
2 octaves in semitone steps
Set to 2 semitones when powered on

mmH,llH : 00H,00H - 40H,00H - 7FH,7FH
(-8192*100/8192 to 0 +8192*100/8192¢)

mmH : 28H -40H - 58H

--- : don’t care

e

GM tone : 128 tones (Program No. 0 to 127)
Drum kit : 9 sets (Program No. 0, 1, 8, 16, 24, 25, 32, 40, 48)

2-2-4. Pitch Bend <EnH> <Data-L> <Data-H>

This is a message to inform Pitch Bend information of each part.
Recieving the Pitch Bend message is valid only when GM tone, and invalid when drum kit.

Parameter Data ran
Data LSB 0 to 127
Data MSB 0 to 127

The resolution is 14 bits (-8192 to 8191).

2-2-5. Channel After Touch <DnH> <Data>

This is a message to inform a degree of pressure after playing a keyboard.

- 32 -

e

July 10, 1997

YMF721

g

g

g

2-2-6. Channel Mode Touch <BnH> <Control No.> < Data>

a) All Sound Off

When this message is received, all sounds are muted. However, states of channel messages, that are
Note ON and Hold ON etc., are kept.

Control No. Parameter Data ran
120 All Sound Off 0

b) Reset All Controllers

When this message is received, controller etc. of the designated channel are set as shown below:

Controller Reset Value
Pitch Bend Change ±0
Modulation 0 (OFF)
Expression 127 (max)
Hold 0 (OFF)
Sostenuto 0 (OFF)
RPN No Number selected.

Control No. Parameter Data ran
121 ResetAll Controllers 0

c) All Note Off

All Notes, that are ON at the designated channel, become OFF.
However, when Hold and Sostenuto are ON, the sound is not stopped until they become OFF.

e

e

Control No. Parameter Data ran
123 All Note Off 0

e

- 33 -

July 10, 1997

YMF721

3. System Realtime Message

3-1. System Reset <FFH>

Notes of all channels are damped.
Controllers of all channels become default value.

3-2. System Exclusive Message

3-2-1. GM System Level 1 ON <F0 7E 7F 09 01 F7>

3-2-2. XG System ON <F0 43 1n 4C 00 00 7E 00 F7>

When this message is received, Notes of all channels are damped.
All setting value become default without MIDI Master Tuning.

3-2-3. MIDI Master Volume <F0 7F 7F 04 01 ss tt F7>

When this message is received, all volumes are set.
Data range of ss and tt is 0 to 127 (00H to 7FH). However, the value of tt is only valid, and ss is
ignored.

00H : Minimum volume, 7FH : Maximum volume

n : Device No. Don’t care.

3-2-4. MIDI Master Tuning <F0 43 1n 27 30 00 00 xm xl cc F7>

n : Device No. Don’t care.
When this message is received, pitch of all channel are changed at the same time.
Data range of xm and xl is 0 to 127 (00H to 7FH). However, 8 bits value (0 to 255), that is composed
of m and l, is valid range.

128 (ml=80H) : Center, ±1 : up/down by 1¢
This parameter is ignored at drum kit (channel 10 and bank 127).
And, this parameter is not reset by System Reset, GM System Level 1 ON and XG System ON.

3-2-5. Power Down Command <F0 43 79 04 0E 6D 7F>

3-2-6. Internal Micro-Processor Reset Command <F0 43 79 04 0F 6B 7F>

- 34 -

July 10, 1997

YMF721

Supplementary Information 3 (MIDI Implementation Chart)

Function Recognized Remarks
Basic Default 1-16
Channel Changed X
Mode Default 3 (Omni off Poly,)

Messages 3 Modes other than 3 are acceptable.

Altered 3
Note 0-127
Number True Voice 0-127
Velocity Note ON O

Note OFF X
After Key’s X
Touch Channel’s O

Pitch Bend O
Control 0 O Bank Select MSB
Change 1 O Modulation

6,38 O Data Entry MSB/LSB
7 O Main Volume
10 O Panpot
11 O Expression
64 O Hold
66 O Sostenuto

100,101 O RPN MSB/LSB
Program O 0-127
Change True No. O 0-127 GM128Voice

Drum Set (0,1,8,16,24,25,32,40,48)

System Exclusive O GM System Level 1 ON

XG System ON
Master Volume
Master Tuning
Power Down Command
Internal Micro-Processor Reset Command

Common Song Position X

Song Select X

Tune X
System Clock X
Real-time Commands O System Reset (FFH)
AUX Local On/Off X
Messages All Sound Off O All Sound Off (Control No. 120)

All Notes Off O All Notes Off (Control No. 123)

Active Sense X

Reset O Reset All Controller (Control No. 121)

Note : YMF721(OPL4-ML2) has no Transmitting function.

- 35 -

July 10, 1997

YMF721

Supplementary Information 4 (Melody Voice List)

Group Voice No. Voice Pitch Key Range Scale
PIANO

Chromatic

Organ

Guitar

Bass

voice(00) Acoustic Grand Piano A3 G#-1 ~ C#7 Temperament
voice(01) Bright Acoustic Piano A3
voice(02) Electric Grand Piano A3
voice(03) Honky-tonk Piano A3
voice(04) Electric Piano1 A3 A-1 ~ C7
voice(05) Electric Piano2 A3 G#-1 ~ C#7
voice(06) Harpsichord A3 A-1 ~ C7
voice(07) Clavi. A3
voice(08) Celesta A3
voice(09) Glockenspiel A3 A-1 ~ C8
voice(10) Music Box A3 A-1 ~ C7
voice(11) Vibraphone A3
voice(12) Marimba A3 A-1 ~ G8
voice(13) Xylophone A3 C-2 ~ G8
voice(14) Tubular Bells A3 C#-2 ~ G8
voice(15) Dulcimer A3 C-2 ~ G8
voice(16) Drawbar Organ A3 C#-2 ~ G8
voice(17) Percussive Organ A3 A-1 ~ C7
voice(18) Rock Organ A3
voice(19) Church Organ A3
voice(20) Reed Organ A3
voice(21) Accordion A3
voice(22) Harmonica A3
voice(23) Tango Accordion A3 C-2 ~ C7
voice(24) Nylon Guitar A3 A-1 ~ C6
voice(25) Steel Guitar A3 A-1 ~ C7
voice(26) Jazz Guitar A3
voice(27) Clean Guitar A3
voice(28) Muted Guitar A3 C#-2 ~ G8
voice(29) Overdriven Guitar A3 C-2 ~ G8
voice(30) Distortion Guitar A3 A-1 ~ C7
voice(31) Guitar Harmonics A3
voice(32) Acoustic Bass A3
voice(33) Finger Bass A3 C#-2 ~ G8
voice(34) Pick Bass A3 A-1 ~ C7
voice(35) Fret-less Bass A3 C#-2 ~ G8
voice(36) Slap Bass1 A3 A-1 ~ C7
voice(37) Slap Bass2 A3 C#-2 ~ G8
voice(38) Synth Bass1 A3 A-1 ~ C7
voice(39) Synth Bass2 A3 C-2 ~ G8

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- 36 -

July 10, 1997

YMF721

Group Voice No. Voice Pitch Key Range Scale

voice(40) Violin A3 A-1 ~ C7 Temperament
voice(41) Viola A3
voice(42) Cello A3
voice(43) Contrabass A3
voice(44) Tremolo Strings A3
voice(45) Pizzicato Strings A3
voice(46) Harp A3
voice(47) Timpani A3

Ensemble

Brass

Reed

Pipe

Lead

voice(48) String Ensemble1 A3
voice(49) String Ensemble2 A3
voice(50) Synth Strings1 A3 F-2 ~ C7
voice(51) Synth Strings2 A3 A-1 ~ C7
voice(52) Aahs Choir A3
voice(53) Oohs Choir A3
voice(54) Synth Choir A3
voice(55) Orchestra Hit A3
voice(56) Trumpet A3
voice(57) Trombone A3
voice(58) Tuba A3
voice(59) Muted Trumpet A3
voice(60) French Horn A3
voice(61) Brass Section A3
voice(62) Synth Brass1 A3 C#-2 ~ G8
voice(63) Synth Brass2 A3
voice(64) Soprano Sax A3 A-1 ~ C7
voice(65) Alto Sax A3
voice(66) Tenor Sax A3 C1 ~ C7
voice(67) Baritone Sax A3 A-1 ~ C7
voice(68) Oboe A3
voice(69) English Horn A3
voice(70) Bassoon A3
voice(71) Clarinet A3
voice(72) Piccolo A3
voice(73) Flute A3
voice(74) Recorder A3 A-1 ~ D#7
voice(75) Pan Flute A3 A-1 ~ C7
voice(76) Blown Bottle A3
voice(77) Shakuhachi A3
voice(78) Whistle A3 C-2 ~ G8
voice(79) Ocarina A3
voice(80) Square Lead A3 C#-2 ~ G8
voice(81) Sawtooth Lead A3
voice(82) Calliope Lead A3 A-1 ~ C7
voice(83) Chiff Lead A3 C#-2 ~ G8
voice(84) Charang Lead A3
voice(85) Voice Lead A3 A-1 ~ C7
voice(86) Fifths Lead A3 C#-2 ~ G8
voice(87) Bass & Lead A3

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- 37 -

July 10, 1997

YMF721

Group Voice No. Voice Pitch Key Range Scale

voice(88) New-Age Pad A3 A-1 ~ C7 Temperament
voice(89) Warm Pad A3
voice(90) Polysynth Pad A3 C#-2 ~ G8
voice(91) Choir Pad A3 A-1 ~ C7
voice(92) Bowed Pad A3
voice(93) Metallic Pad A3
voice(94) Halo Pad A3
voice(95) Sweep Pad A3 C#-2 ~ G8

Synth Effects

Ethnic

Percussive

Sound Effects

voice(96) FX1 (Rain) A3
voice(97) FX2 (Soundtrack) A3 A-1 ~ C7
voice(98) FX3 (Crystal) A3

voice(99) FX4 (Atmosphere) A3 F-2 ~ C6
voice(100) FX5 (Brightness) A3 A-1 ~ C7
voice(101) FX6 (Goblins) A3
voice(102) FX7 (Echoes) A3
voice(103) FX8 (Sci-Fi) A3
voice(104) Sitar A3 C-2 ~ G8
voice(105) Banjo A3 A-1 ~ C#7
voice(106) Shamisen A3 A-1 ~ C7
voice(107) Koto A3 C-2 ~ G8
voice(108) Kalimba A3
voice(109) Bagpipe A3 A-1 ~ C7
voice(110) Fiddle A3
voice(111) Shanai A3
voice(112) Tinkle Bell A3 A-1 ~ G7
voice(113) Agogo A3 A-1 ~ G#7
voice(114) Steel Drums A3 A-1 ~ C7
voice(115) Wood Block F#3
voice(116) Taiko Drum A1 G-1 ~ C7 50¢/note
voice(117) Melodic Tom C#3 A-1 ~ C7 50¢/note
voice(118) Synth Drum **
voice(119) Reverse Cymbal **
voice(120) Guitar Fret Noise A3
voice(121) Breath Noise A3 C#-2 ~ G8
voice(122) Seashore ** A-1 ~ C7 20¢/note
voice(123) Bird Tweet **
voice(124) Telephone Ring **
voice(125) Helicopter ** C-1 ~ G8 10¢/note
voice(126) Applause ** A-1 ~ C7 5¢/note
voice(127) Gunshot **

--

--

--

--

--

--

--

--

--

--

--

--

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

50¢/note

50¢/note
50¢/note

Temperament

-

5¢/note

10¢/note

20¢/note

- 38 -

July 10, 1997

YMF721

Supplementary Information 5 (Drum Set List)

Program # 1 9 17 25 26 33 41 49

24 C 0 Seq Click H
25 C#0
26 D0
27 D#0 Brush Slap
28 E0
29 F0
30 F#0 Castanet Hi Q Hi Q
31 G0 Snare L SD Room L SD Power M Snare M SD Power H Brush Slap L Concert SD
32 G#0 Sticks
33 A0 Bass Drum L BD Room L Bass Drum M Bass Drum H Bass Drum M Gran Casa
34 A#0 Open Rim Shot
35 B0 Bass Drum M BD Room M Bass Drum H BD Power BD Analog L Gran Casa
36 C1 Bass Drum H BD Room H BD Power BD Gate BD Analog H Gran Casa
37 C#1 Side Stick Analog Side Stick
38 D1 Snare M SD Room M SD Rock SD Power L Analog Snare L Brush Slap Concert SD
39 D#1 Hand Clap
40 E1 Snare H SD Room H SD Power Rim SD Power H Analog Snare H Brush Tap Concert SD
41 F1 Floor Tom L Room Tom 1 Power Tom 1 E Tom 1 Analog Tom 1 Jazz Tom 1 Brush Tom 1 Jazz Tom 1
42 F#1 Hi-Hat Closed Analog HH Closed 1
43 G1 Floor Tom H Room Tom 2 Power Tom 2 E Tom 2 Analog Tom 2 Jazz Tom 2 Brush Tom 2 Jazz Tom 2
44 G#1 Hi-Hat Pedal Analog HH Closed 2
45 A1 Low Tom Room Tom 3 Power Tom 3 E Tom 3 Analog Tom 3 Jazz Tom 3 Brush Tom 3 Jazz Tom 3
46 A#1 Hi-Hat Open Analog HH Open
47 B1 Mid Tom L Room Tom 4 Power Tom 4 E Tom 4 Analog Tom 4 Jazz Tom 4 Brush Tom 4 Jazz Tom 4
48 C2 Mid Tom H Room Tom 5 Power Tom 5 E Tom 5 Analog Tom 5 Jazz Tom 5 Brush Tom 5 Jazz Tom 5
49 C#2 Crash Cymbal 1 Hand Cym.Open L
50 D2 High Tom Room Tom 6 Power Tom 6 E Tom 6 Analog Tom 6 Jazz Tom 6 Brush Tom 6 Jazz Tom 6
51 D#2 Ride Cymbal 1 Hand Cym.Closed L
52 E2 Chinese Cymbal
53 F2 Ride Cymbal Cup
54 F#2 Tambourine
55 G2 Spla sh Cymbal
56 G#2 Cowbell
57 A2 Crash Cymbal 2 Hand Cym.Open H
58 A#2 Vibraslap
59 B2 Ride Cymbal 2 Jazz Ride Hand Cym.Closed H
60 C3 Bongo H
61 C#3 Bongo L
62 D3 Conga H Mute
63 D#3 Conga H Open
64 E3 Conga L
65 F3 Timbale H
66 F#3 Timbale L
67 G3 Agogo H
68 G#3 Agogo L
69 A3 Cabasa
70 A#3 Maracas
71 B3
72 C4
73 C#4 Guiro Short
74 D4 Guiro Long
75 D#4 Claves
76 E4 Wood Block H
77 F4 Wood Block L
78 F#4 Cuica Mute Scratch Push Scratch Push
79 G4 Cuica Open Scratch Pull Scratch Pull
80 G#4 Triangle Mute
81 A4 Tri angle Open
82 A#4 Shaker
83 B4 Jingle Bell
84 C5 Bell Tree

O

Brush Tap

O

Brush Swirl L

O

Brush Swirl H Reverse Cymbal Reverse Cymbal

O

Snare Roll

O

Samba Whistle H

O

Samba Whistle L

- 39 -

: Same as Standard kit

July 10, 1997

YMF721

EXTERNAL DIMENSIONS OF PACKAGE

16.00 ± 0.40

14.00 ± 0.30

75 51

76

100

50

14.00 ± 0.30

16.00 ± 0.40

26

125

0.20 ± 0.10
or 0.18 ± 0.10

P-0.50TYP

1.70MAX.

(Installation height)

1.40 ± 0.20

0MIN.(STAND OFF)

LEAD THICKNESS : 0.125TYP or 0.15TYP

The shape of the molded corner may slightly different from the shape
in this diagram.
The figure in the parenthesis ( ) should be used as a reference.
Plastic body dimensions do not include burr of resin.

UNIT : mm

Note : LSIs to be installed on the surface of the printed circuit board require special care

in storage and soldering. Consult your dealer for the details.

(1.0)

0-10º

0.50 ± 0.20

- 40 -

July 10, 1997

YMF721

g

g

IMPORTANT NOTICE

1. Yamaha reserves the right to make changes to its Products and to this document without
notice. The information c ontained in this document has been caref ully checked and is believed
to be reliable. However, Yamaha assumes no respons ibilities for inaccuracies and makes no
commitment to update or to keep current the information contained in this document.

2. These Yamaha Products are desi

ned only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support equipment, nuclear
facilities, critical care equipment or any other application the failure of which could lead to death,
personal injury or environmental or property dama

e. Use of the Products in any such

application is at the customer's sole risk and expense.

3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL
DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICAT ION OR IMPROPER USE
OR OPERATION OF THE PRODUCTS.

4. YAMAHA MAKES NO WARRANTY OR REPRESENT ATION THAT T HE PRODUCTS ARE
SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD
PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON­INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY
EXCLUDES ANY LIABILITY TO THE CUST OMER OR ANY THIRD PARTY ARISING FROM
OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S
INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT,
TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.

5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE
CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES
NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER
PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES
DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE
PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.

Note) The specifications of this product are subject to improvement change without prior notice.

AGENCY

Address inquires to :
Semi-conductor Sales Department

- Head Office

- Tokyo Office

- Osaka Office

- U.S.A. Office

YAMAHA CORPORATION

203, MatsunokiJima, Toyooka-mura.
Iwata-gun, Shizuok a-ken, 438-0192
Tel. [phone] Fax. [phone]
2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568
Tel. [phone] Fax. [phone]
1-13-17, Namba Naka, Naniwa-ku,
Osaka City, Osaka, 556-0011
Tel. [phone] Fax. [phone]
YAMAHA Syst em Technology.
100 Century Center Court, San Jose, CA 95112
Tel. [phone] Fax. [phone]

- 41 -

July 10, 1997