Page 1
YGV619
AVDP6
Advanced Video Display Processor 6
Outline
■
YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the
data broadcasting. The digital image interface of this device for connection with MPEG decoder has been
improved. The use of this device allows screen composition that is suited to mobile information terminals, car
navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.
Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal,
and to produce clock best suited to SDRAM that is adopted as external video memory.
Features
■
●
Display planes: External digital image is overlaid with OSD images composed of regions.
Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted)
+ region, are available.
●
OSD image format:
8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected.
YCbCr conforms to the conversion method of ITU601.
Color palette (256 colors in 16777 k colors) can be specified by region.
●
Digital image input format:
· 18bitR6G6B6 (Max. dot clock frequency: 80 MHz)
· 16bitYCbCr422 (Max. dot clock frequency: 80 MHz)
· 8bitITU656 (Dot clock frequency 27 MHz)
●
Digital image output format:
· R6G6B6 + 2 bit AT
· 18bitYCbCr444 + 2 bit AT
· 16bitYCbCr422 + 2 bit AT
· 8bitITU656 + 2 bit AT + 6 bit
●
Max. OSD resolution: 960 dots × 1080 lines
(However, max. resolution of overlaid external image is 1920 ×1080 lines)
●
Applicable digital TV image format:
· 525i
· 525p
· 1125i
●
Video capture function:
· Draws external image input on the frame memory in real time.
· Can convert resolution.
· Provided with progressive scanning conversion
α blending coefficient
YGV619 CATALOG
CATALOG No.: LSI-4GV619A1
2001.01
Page 2
YGV619
●
Priority of display planes
Regular priority: Plane D > Plane C > Plane B > Plane A > Back drop plane
The priority can be changed by region.
●
α blending function (64 intensity level)
Blending weight can be set by dot.
●
Flicker cancel filter is built in.
Enabling / disabling flicker cancel function can be set by region.
●
8 bit DACs are built in for R, G and B individually. (Max. operating frequency: 80 MHz)
●
Two PLLs are built in. (1: Generates SDRAM clock and system clock 2: Generates dot clock)
●
Display monitor control
· Display resolution and scanning frequency can be set optionally.
This function is compatible with progressive scanning and interlaced scanning modes.
NTSC subcarrier output
●
SDRAM can be added externally as VRAM (SDRAM generation clock frequency: Max. 80 MHz.)
·16 bit bus
512k words × 16 bits × 2 banks × 1 pc. (capacity: 2M bytes)
1M words × 16 bits × 4 banks × 1 pc. (capacity: 8M bytes)
2M words × 16 bits × 2 banks × 1 pc. (capacity: 8M bytes)
·32 bit bus
512k words × 16 bits × 2 banks × 2 pcs. (capacity: 4M bytes)
512k words × 32 bits × 4 banks × 1 pc. (capacity: 8M bytes)
1M words × 16 bits × 4 banks × 2 pcs. (capacity: 16M bytes)
2M words × 16 bits × 2 banks × 2 pcs. (capacity: 16M bytes)
●
CPU interface
Compatible with 16/32 bit CPU. Various built-in tables can be mapped on CPU space.
Compatible with little endian and big endian
●
Package: 240SQFP (YGV619-S)
●
Operating temperature range: -45 to +85°C
●
Power supply: 3.3V, single power supply
Supplementary information:
For YGV619, Application Manual that details the specifications of the device and the evaluation board
(MSY619DB01) are available in addition to this brochure.
The evaluation board is equipped with an SDRAM of 16 MB as a video memory. A high performance system
can be realized when it is used with Hitachi’s CPU board, Super H Solution Engine.
The device driver provided by Yamaha and attached to the evaluation
board consists of the main body of the driver and API related layers,
allowing the user to build it into the system easily according to the
environment.
For the details of these products, inquire of the sales agents or our
business offices.
For CPU board, inquire of: Hitachi ULSI Systems Co., Ltd.
Tel:+81-42-351-6600
2
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YGV619
0
G
D
3
0
T
C
C
N
N
M
T
T
N
T
N
Y
N
T
C
Q
Block Diagram
■
D31A23-2
CSRE
CSME
DRE
A1/WR
WR2-
WAI
READ
RESE
SYCKI
SYCKOU
CSYN
HSYN
HSI
VSI
FS
R
CPU
INTE RF AC E
IN
CRT
CONTROLLER
DRAWING
PROCESSOR
UNIT
VIDEO
CAPTURE
CONTROLLER
SDRAM
INTE RF AC E
SDQ31-0
SA12-0
SBA1-0
SCS
RAS
CAS
WE
DQM3-0
SDCLK
DCKI
DCKOU
GCKI
DRI[5 :0 ]
DGI[5 :0 ]
DBI[5 :0 ]
PIXEL
DATA
CONTROLLER
DAC
AT1-0
GCKOUT
DRO[5:0]
DGO[5:0]
DBO[5:0]
R, G, B
AVDP6 performs parallel processing including operation of writing display data into video memory (SDRAM)
connected on the local bus (drawing function) and operation of sequentially reading bit map image stored in the
video memory in accordance with monitor scanning (display function).
Drawing function:
This function transfers bit map image data configured on the external memory of CPU to video memory. For the
transfer of the data, a method that maps the video memory as external memory managed by CPU and performs the
transfer as the transfer between external memories of CPU, or a method that uses internal drawing processor of
AVDP6 to configure the display image on the video memory can be used.
Display function:
This function displays the bit map image stored in the video memory in accordance with the display parameters
that are stored in the internal registers of AVDP6 and the video memory. Basically, AVDP6 automatically sends out
display data and refreshes SDRAM once initial setting for internal registers are completed. When performing
dynamic processing such as scroll, the processing that synchronizes with the scanning of AVDP6 can be performed
easily by using internal flag polling of AVDP6 or interrupt function.
3
Page 4
Pin Assignment
■
VDD
240
A23
A22
A21
A20
A19
VSS
A18
VDD
A17
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
VDD
A4
A3
A2
VSS
RD
VDD
VSS
INT
D31
VDD
D30
D29
D28
D27
D26
D25
D24
VSS
D23
D22
D21
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
616263646566676869707172737475767778798081828384858687888990919293949596979899
AVSS1
AVDD1
/
A1
WR3
WR2
WR1
WR0
RESET
CSREG
CSMEM
LWD
LEND
SYCKS
DREQ
READY
WAIT
DCKOUT
DCKIN
238
239
VSS
237
TCK80
TCKS
235
236
VSIN
HSIN
233
234
GCKS
GCKIN
231
232
DBI0
230
VDD
229
DBI1
228
DBI2
227
DBI3
226
VSS
225
DBI4
224
DBI5
223
DGI0
DGI1
221
222
DGI2
DGI3
219
220
DGI4
DGI5
217
218
VDD
DRI0
215
216
DRI1
VSS
213
214
DRI2
DRI3
211
212
DRI5
DRI4
209
210
AVDD3
AVSS3
207
208
AVDD4
REXT
AVSS4
204
205
206
R
203
AVSS4
G
201
202
100
AVSS4
B
199
200
101
102
VSS
AVSS4
197
198
103
104
DBO1
DBO0
195
196
105
106
VDD
DBO2
193
194
107
108
DBO4
DBO3
191
192
109
110
YGV619
DGO1
DGO0
187
188
113
114
DGO3
DGO2
185
186
115
116
VSS
184
117
DGO4
DGO5
182
183
118
119
DRO0
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
VSS
190
111
DBO5
189
112
VDD
DRO1
DRO2
VSS
DRO3
DRO4
DRO5
GCKOUT
AT0
VSS
AT1
FSC
BLANK
HSYNC
CSYNC
VDD
SDQ24
VSS
SDQ23
SDQ25
SDQ22
SDQ26
SDQ21
VSS
SDQ27
SDQ20
SDQ28
SDQ19
VDD
SDQ29
VSS
SDQ18
SDQ30
SDQ17
SDQ31
SDQ16
VSS
DQM3
DQM2
SA4
SA3
VDD
SA5
SA2
SA7
VSS
SA6
SA1
SA0
SA8
SA10
SA9
SA12
VDD
SBA0
VSS
SA11
SBA1
SCS
RAS
D20
D19
D18
D17
D16
VSS
D15
D14
D13
D12
D11
VDD
D10
VSS
D3D1D4D2D0
VSS
SYCKIN
SYCKOUT
VDD
TEST1
TEST2
SDQ0
TEST0
VSS
SDQ1
SDQ15
SDQ2
SDQ14
SDQ13
VDD
SDQ3
VSS
SDQ4
SDQ12
SDQ5
SDQ11
SDQ10
VSS
SDQ6
SDQ9
SDQ7
SDQ8
VDD
DQM0
WE
VSS
CAS
DQM1
AVSS2
SDCLK
AVDD2
D8D7D5
D9
D6
Top view
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YGV619
Pin Functions
■
< CPU INTERFACE >
D31-0
l
CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor.
Unused pins are to be open.
((((
I/O: Pull Up
))))
A23-8
l
((((
I: Pull Up
CPU address bus. When accessing
))))
A7-2
,
((((I))))
CSREG
space, signals inputted to A23-8 pins are ignored without regarding to the
bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A72 and
A1
/
WR3
pin for 16 bit CPU. Systems that control AVDP6 only with
CSREG
do not use this address bus.
However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when
accessing
l
CSREG
CSMEM
((((I))))
space.
Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is
inputted when the chip select signal is active.
When this signal is low, inputs to A23-8 pins are ignored.
l
CSMEM
CSMEM
((((I))))
is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory
space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse t hat is inputted with
this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high
level signal must be inputted to
LWD
l
(I: Pull Up)
CSMEM
in this case.
Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or
when low level signal is inputted to this pi n, AVDP6 operates as CPU 16 bit device.
l
A1
WR3
WR2-0
Controls write access to AVDP6 when chip select input signal is active.
D23-16,
controls D15-8, and
WR1
For 16 bit CPU,
A1
/
WR3
((((I))))
controls D7-0.
WR0
function as A1 o f CPU a ddr ess.
control D31-24,
/
WR3
A1
is not used, and thus must be open because the pin is
WR2
WR2
controls
,
/
provided with a pull-up resistor.
((((I))))
l
RD
Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal
and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states
at all times.
WAIT
((((
O: Pull Up, 3-state output
l
Data wait signal output to CPU. When
signal is asserted once for RD or
This pin becomes high impedance state when
RD
and
l
READY
or
A1
((((
O: Pull Up, 3-state output
/
WR3
and
WR2-0
))))
pin or
CSMEM
signals, and then negated when AVDP6 becomes accessible.
A1
/
WR3
CSREG
and
CS
WR2-0
pin is not active, and outputs high level signal when CS pin is active
pins are not active. Use this pin or
))))
pin (hereafter called “CS pin”) is active, the
READY
depending on the type of CPU.
WAIT
Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high
impedance state when
WR2-0
l
pins are not active. Use this pin or
((((O))))
INT
pin is not active, outputs high level signal when CS pin is active and RD or
CS
depending on the type of CPU.
WAIT
A1
/
WR3
Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the
setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed.
,
5
Page 6
YGV619
l
DREQ
DMA request. This pin is asserted when AVDP6 becomes a state where it can accept the DMA transfer. The DMA
transfer should be performed using regular
l
RESET
Initial reset signal input. Inputti ng this signal clears the internal registers of AVDP6 to initialize the internal state of
the device. (Some registers are loaded with initial value.)
l
LEND
Selects an endian of CPU. Big endian is selected when this pin is at high level, or little endian when the level is low.
l
SYCKS
Input high level to t his pin or leave it op en (because it is provided with pull-up resister) when clock inputted through
DCKIN and DCKOUT pins are used as a system clock. VRAM clock and dot clock are generated from DCKIN. At thi s
time, supply of clock to SYCKIN pin is not needed. Input low level signal to this pin when input cloc k fro m SYCKIN and
SYCKOUT pins are used.
((((O))))
((((
I: Schmidt input
((((
I: Pull Up
((((
I: Pull Up
and RD pins. (Use Dual Address Mode of DMAC)
WRn
))))
))))
))))
< SDRAM interface >
SDQ31-0
l
Data bus for SDRAM. AVDP6 uses these pins for data input/out access to SD RAM. The data bus width for SDRAM
can be set to 32 bits or 16 bits by using the register setting. SDQ31-16 pins are not used when SDRAM bus width of 16
bits is used. At this time, SDQ31-16 pins are in output state at all times.
((((
))))
I/O
SA12-0
l
Address bus for SDRAM. This bus uses time-sharing method to output row address and column address of SDRAM
used by AVDP6.
SBA1-0
l
Outputs access bank of SDRAM and ACTIVE command at the same time.
SA12-0 and SBA1-0 pins output the signals as shown below depending on the type of SDRAM.
VRM SBA1 SBA0 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
0
1
2
3
4
5
6
VRM shows the setting value of R#03:VRM[2:0]. Upper row shows the states of the pins when Active command is
issued, and lower column shows the state when Read/Write command is issued.
((((O))))
((((O))))
- BA - - RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
BA1 BA0 - RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
BA1 BA0 - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
- BA - - RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
BA1 BA0 - - RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
BA1 BA0 - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
BA1 BA0 - RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
BA1 BA0 - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA - - - - - CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
l
SDRAMs are used, connect this pin to both SDRAMs.
6
((((O))))
SCS
Output s chip select signal for SDR AM. A command is issued to SDRAM when this signal is act ive. When two 16 bit
Page 7
YGV619
l
l
l
l
SDQ23-16, SDQ15-8 and SDQ7-0 respectively. When masking the data, corresponding DQM pin outputs high level
signal.
l
setup time at SDQ input.
((((O))))
RAS
Outputs row address strobe signal for SDRAM.
When two 16 bit SDRAMs are used, connect this pin to both SDRAMs.
((((O))))
CAS
Outputs column address st robe signal for SDRAM.
When two 16 bit SDRAMs are used, connect this pin to both SDRAMs.
((((O))))
WE
Outputs write strobe signal fo r SDRAM.
When two SDRAMs are used, connect this pin to both SDRAMs.
DQM3-0
Outputs data mask signal for SDRAM. DQM3, DQM2, DQM1 and DQM0 are mask control signals for SDQ31-24,
When one 16 bit SDRAM is used, DQM3-2 pins are not used, thus they are to be kept open.
SDCLK
Outputs CLK for SDRAM. SDCLK inputs the clock once outputted from this pin to use it as fetch clock to obtain
((((
((((O))))
I/O
))))
< Display monitor interface >
R, G, B
l
Outputs linear RGB signal. Termination resistor of 37.5Ω is connected to this pin to make the resolution of output
voltage amplitude 8 bits. Monitor with impedance of 75Ω can be driven directly through this interface as shown below.
((((
O: analog output
))))
R(G,B)
RL=75
REXT
l
A resistor is connected between this pin and GND(AVSS4) for adjusting the amplitude of signal outputted from DAC
for RGB. The standard amplitude of signal outputted from DAC is 0.7 V (rREXT=470 Ω). The amplitude of the output
can be adjusted finely within around ±100Ω by using the following formula.
l
CSYNC
Outputs composite sync signal for external monitor. In interlaced scanning mode, equalizing pulses are added to this
signal. This pin can output
l
HSYNC
Outputs horizontal sync signal for external moni tor.
((((
I: analog input
((((O))))
((((O))))
))))
VSYNC
Vp_p = 470 × 0.7 / rREXT
by using internal register setting.
Ω
RL=75
Ω
((((O))))
((((O))))
((((O))))
7
l
BLANK
Outputs a signal that indicates effective display period when LCD panel is connected to the device.
AT1-0
l
AT1-0 bits of display data are outputted from these pins.
FSC
l
Outputs subcarrier clock for video encoder. The subcarrier clock is created by dividing the clock inputted to DCKIN
pin by 1, 2, 4, or 8, which is determined by register setting. For example, inputting 14.318 MHz to DCKIN pin and
dividing it by “4” give subcarrier clock of 3.58 MHz.
Page 8
YGV619
DRO5-0, DGO5-0, DBO5-0
l
Outputs digital image signal. The output data format can be set to 18 bit RGB, 16 bit YCbCr(ITU601) or ITU656(8bit)
by using R_YRT[1:0] and R_DOF[1:0].
16 bit YCbCr and image data for ITU656 are outputted as described below.
((((O))))
18bit RGB 16 bit YCbCr ITU656(8bit)
DRO[5] n.c.
DRO[4] n.c.
DRO[3] CO[7]
DRO[2] CO[6]
DRO[1] CO[5]
DRO[0] CO[4]
DGO[5] CO[3]
DGO[4] CO[2] n.c.
DGO[3] CO[1] n.c.
DGO[2] CO[0] n.c.
DGO[1] YO[7] DO[7]
DGO[0] YO[6] DO[6]
DBO[5] YO[5] DO[5]
DBO[4] YO[4] DO[4]
DBO[3] YO[3] DO[3]
DBO[2] YO[2] DO[2]
DBO[1] YO[1] DO[1]
DBO[0] YO[0] DO[0]
n.c.: Stands for “no connection”.
α
[6]
α
[5]
α
[4]
α
[3]
α
[2]
α
[1]
α
[0]
GCKOUT
l
Outputs clock for digital image signal output. The state of the digital image signal changes synchronizing with this
clock. Maximum frequency of the clock is 80 MHz
((((O))))
8
Page 9
YGV619
< External video input >
l
horizontal sync pulse signal and low level is detected three times consecutively, this pin resets the internal V counters at
HTL (time where horizontal sync signal starts). This function makes it possible to reset inter nal V counter s ynchronizing
with vertical sync signal when composite sync si gnal is inputted to this pin. At the same time, this funct ion automaticall y
identifies fields in interlaced scanning mode.
l
Resets horizontal timing function of AVDP6. AVDP6 samples the input signal synchronizing with the main clock and
sets horizontal scanning time to the horizontal sync start po sition at the moment the signal falls from high level to low
level, and at the same time, adjust the phase of division clock to
l
Digital image signal input pin. This pin becomes valid when internal register R_ EIE is “1”. The input data format can
be set to 18 bit RGB, 16 bit YCbCr(ITU601) or ITU656(8bit) depending on the value of internal register R_EIF[1:0].
Input a signal to individual pins as shown below in accordance with the input data format.
((((
VSIN
I: Pull Up
Resets vertical timing function of AVDP6. When this input signal is sampled at intervals equivalent to the width of
((((
HSIN
I: Pull Up
DRI5-0, DGI5-0, DBI5-0
))))
))))
.
HSIN
((((
I: Pull Up
18 bit RGB 16 bit YCbCr ITU656(8bit)
DRI[5] not use SDI[7]
DRI[4] not use SDI[6]
DRI[3] CI[7] SDI[5]
DRI[2] CI[6] SDI[4]
DRI[1] CI[5] SDI[3]
DRI[0] CI[4] SDI[2]
DGI[5] CI[3] SDI[1]
DGI[4] CI[2] SDI[0]
DGI[3] CI[1]
DGI[2] CI[0]
DGI[1] YI[7] BDI[7]
DGI[0] YI[6] BDI[6]
DBI[5] YI[5] BDI[5]
DBI[4] YI[4] BDI[4]
DBI[3] YI[3] BDI[3]
DBI[2] YI[2] BDI[2]
DBI[1] YI[1] BDI[1]
DBI[0] YI[0] BDI[0]
HSIN HSIN HSIN
VSIN VSIN VSIN
))))
Data for capture
SHSIN
SVSIN
HSIN for capture
VSIN for capture
Data for BG
HSIN for BG
VSIN for BG
GCKIN
l
Clock for external video input is inputted to this pin.
This pin is valid only when
l
GCKS
W hen external image i nput signal is p resent, low level si gnal is inputted to
used as the video capture clock. When data are displayed on the back drop plane, this signal can be used as dot clock by
using register setting.
When no external image signal is not present, the clock inputted through DCKIN and DCKOUT pins can be used as
GCK by making
((((I))))
((((
I: Pull Up
pin is low. Maximum frequency of this signal is 80 MHz.
GCKS
))))
pin so that the GCKIN pin input is
GCKS
open state or high level. In this case, be sure to input a fixed signal to GCKIN pin.
GCKS
9
Page 10
< PLL >
YGV619
DCKIN
l
XTAL connection pins for generating dot clock. The dot clock is used by sync control, display control and screen
composition blocks. By using t he built-in PLL, dot clock with various frequencies that synchro nizes with the clock of
DCKIN pin ca n be generated. When
clock from input clock of DCKIN pin.
Dot clock can be generated from input clock of DCKIN pin in accordance with the setting of the built-in registers,
however, it is necessary to input some clock to DCKIN pin. (DCKIN pin is used to input initialization clock.)
SYCKIN
l
XTAL connection pins for generating system clock. This clock is supplied to SDRAM interface, CPU interface,
drawing processor, and video capture blocks individually. When making
signal to SYCKIN pin. SYCKOUT pin can be left open.
Externally oscillated clock, if used, should be inputted to SYCKIN.
((((I))))
((((I))))
DCKOUT
,
SYCKOUT
,
((((O))))
((((O))))
SYCKS
pin is brought to high level, system clock is generated together with dot
SYCKS
pin open or high level, input a fixed
< Power supply >
AVDD1
l
Supplies power to PLL (PLLDCK) for dot clock. Connect 3.3 V to AVDD1 and GND level to AVSS1.
When designing the circuit board, take care so that the noise from the lines that supply power to other power supply
pins of AVDP6 does not enter these pins.
AVDD2
l
These pins supply power to PLL (PLLVCK) for system clock. Connect 3.3 V to AVDD2 and GND level to AVSS2.
When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins
of AVDP6 does not enter these pins.
((((I))))
((((I))))
AVSS1
,
AVSS2
,
((((I))))
((((I))))
AVDD3
l
Use these pins to suppl y power to the digital circuit of the build-in 8 bit D AC. Connect 3.3 V to AVDD3 and GND
level to AVSS3. When desi gning the circuit board, take care so that the noise from the lines that supply power to other
power supply pins of AVDP6 does not enter these pins.
AVDD4
l
Use these pins to supply power to the analog circuit of the build-in 8 bit DAC. Connect 3.3 V to AVDD4 and GND
level to AVSS4. When desi gning the circuit board, take care so that the noise from the lines that supply power to other
power supply pins of AVDP6 does not enter these pins.
VDD
l
designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of
AVDP6 does not enter these pins.
((((I))))
These pins supply power to digital circuits and I/O section. Connect 3.3 V to VDD and GND level to VSS. When
((((I))))
((((I))))
VSS
,
AVSS3
,
AVSS4
,
((((I))))
((((I))))
((((I))))
< Others >
l
TEST2-0
Input pins for testing. Input high level signal for regular operations of the device.
,
TCKS
, TCK80
((((I))))
10
Page 11
YGV619
Electrical Characteristics
■
Note!
The values of electrical characteristics shown in this section are target data, and do not
guarantee the specifications at the shipment of this product. The specification data
may be changed without prior not ice. T heref ore, please c onf irm the newest data when
using this product.
●
Absolute maximum rating s
Items Symbol Ratings Unit
Supply Voltage V
Input Voltage
Input Voltage
Output Voltage
*2
*3
*2
Output Current I
Storage temperature T
*1
: Value with respect to VSS (GND) = 0V
*2
:
for no-tolerant pins
*3
:
for tolerant pins
●
Recommended operating conditions
Items Symbol Min. Typ. Max. Unit
Supply Voltage V
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
*2
*2
*3
*3
*4
*4
Ambient operating temperature T
*1
Value with respect to VSS (GND) = 0V
:
*2
: when signal is inputted to I/O pins except DCIKN, SYCKIN and tolerant
*3
DCIKN, SYCKIN pins
:
*4
for tolerant pins
:
*1
DD
*1
I
V
*1
I
V
*1
O
V
O
stg
*1
DD
*1
IL
V
*1
IH
V
*1
IL
V
*1
IH
V
*1
IL
V
*1
IH
V
OP
−
0.5 to +4.6
−
0.5 to V
−
0.5 to V
−
DD
+ 0.5
−
0.5 to 5.5
DD
+ 0.5
−
20 to +20
50 to +125
3.0 3.3 3.6 V
−
0.3
0.8 V
2.0 VDD+ 0.3 V
−
0.3
0.7V
−
0.3
DD
DD
0.3V
VDD+ 0.3 V
0.8 V
2.0 5.5 V
−
45
+85
V
V
V
V
mA
C
°
V
C
°
●
Electrical characteristics under recommended operating conditions
l
DC characteristics
Items Symbol Min. Typ. Max. Unit
*1
Low level output voltage (CMO S) V
High level output voltage (CMOS) V
Input leakage current I
Output leakage current I
Current consumption I
*1
:
Measurement condition I
*2
:
Measurement condition IOH=-100µA
l
Pin Capacitance
OL
=100µA
OL
OH
LO
DD
*2
LI
2.4 V
Items Symbol Min. Typ. Max. Unit
Input Pin Capacitance C
Output Pin Capacitance C
I/O Pin Capacitance C
I
O
IO
0.4 V
µ
10
25
A
µ
A
mA
8pF
10 pF
12 pF
11
Page 12
YGV619
Example of System Configuration
■
AVDP6 is a display control device that operates as 16 bit or 32 bit I/O device on the external general purpose bus
of CPU on the system in which the device is built-in. Because CPU I/F of AVDP6 uses asynchronous I/F, it can be
controlled with general purpose SRAM I/F. SDRAM is connected on the local bus of AVDP6 to be used as video
memory. The timing for this SDRAM is made by AVDP6 independently. In the SDRAM, bit map image and palette
data that are displayed by AVDP6 are stored, and in addition, memory domain of SDRAM can be mapped directly
on the bus of CPU so that the vacant space is utilized as the work domain of CPU. The memory space of SDRAM is
controlled with general purpose SDRAM I/F.
Examples of system configuration are shown below by application.
Independent (free running) system
Independent (free running) system
Independent (free running) systemIndependent (free running) system
RAM ROM
CPU
AVD P6
dot clock
SDRAM
ITU601 8bit
YCbCr 16bit
RGB 18bit
RGB analog
When displaying bit map image stored in the video memory independently, it is possible to output sync
signal and display data that are compatible with various scan timing functions by supplying dot clock that is
suited to the display device and by writing timing parameter into the registers for internal scan timing. Since
the display data are outputted as analog and digital data, an LCD panel can be connected directly to the device
and video signal can be created by Video Encoder device.
OSD of NTSC digital images
OSD of NTSC digital images
OSD of NTSC digital imagesOSD of NTSC digital images
RAM ROM
CPU
27MHz
AV DP 6
SDRAM
MPEG2
decoder
ITU656
ITU656
NTSC
encoder
Video
This is an example of system configuration that uses AVDP6 to display OSD images of digital video
equipment conforming to NTSC (SDTV) such as DVD. Since AVDP6 is equipped with input / output pins for
digital images, the digital video signal can be inputted without converting it to analog signal, processed with
OSD and
α blending without deteriorating the quality of images, and then outputted. When displaying bitmap
image of AVDP6 for external video with OSD, it is necessary to synchronize the external video signal with
scanning of AVDP6. At this time, OSD image can be synchronized with external video by inputting sync
signal of the external video into scan control circuit of AVDP6. (As the dot clock, use the clock that is
synchronized with external video signal.)
The digital image I/F of AVDP6 is compatible with digital I/F that conforms to CCIR-Rec601/656 (ITU656).
12
Page 13
YGV619
OSD of HDTV digital image
OSD of HDTV digital image
OSD of HDTV digital imageOSD of HDTV digital image
RAM ROM
CPU
MPEG2
decoder
74MHz
AV DP 6
YCbCr 16bit
SDRAM
YCbCr 16bit
This is an example of the system configuration that uses AVDP6 as OSD image display device in HDTV.
Since the device is able to input / output YCbCr422 data at the frequency up to 80 MHz, it is possible to
control OSD for video signal of HDTV (1125i). In this case, The frequency of dot clock of OSD image
becomes up to 40 MHz (the resolution equivalent to color difference data).
(As the 74 MHz dot clock, it is necessary to input clock that synchronizes with external video signal.)
OSD of NTSC analog image
OSD of NTSC analog image
OSD of NTSC analog imageOSD of NTSC analog image
RAM ROM
CPU
AV DP 6
14MHz
SDRAM
YS (AT0)
analog
RGB
analog
switch
analog
RGB
analog input
HSYNC,VSYNC
analog RGB
When the external video is analog signal, switching signal for analog switch can be outputted together with
OSD display data. Since the dot clock that synchronizes with sync signal of external video can be regenerated
by using the built-in PLL, the superimposing function can be realized easily also for analog image signal.
13
Page 14
External Dimensions of Package
■
YGV619
14
Page 15
YGV619
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document
without notice. The information contained in this document has been carefully checked
and is believed to be reliable. However, Yamaha assumes no responsibilities for
inaccuracies and makes no commitment to update or to keep current the information
contained in this document.
2. These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support equipment,
nuclear facilities, critical care equipment or any other application the failure of which could
lead to death, personal injury or environmental or property damage. Use of the Products
in any such application is at the customer’s sole risk and expense.
3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR
SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR
IMPROPER USE OR OPERATION OF THE PRODUCTS.
4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS
ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY
THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF
NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY
EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING
FROM OR RELATED TO THE PRODUCTS’ INFRINGEMENT OF ANY THIRD PARTY’S
INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT,
TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.
Notice
5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE
CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA
ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR
OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE
EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH
RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT
LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR USE AND TITLE.
The specification given here are provisional and subject to change without prior notice.
Please confirm the latest documentation before using this product.
AGENCY
Address inquiries to:
Semiconductor Sales & Marketing Department
Head Office 203, Matsunokijima, Toyooka-mura
Iwata-gun, Shizuoka-ken, 438-0192
Tel. +81-539-62-4918 Fax. +81-539-62-5054
Tokyo Office 2-17-11, T akanawa, Minato-ku,
Tokyo, 108-8568
Tel. +81-3-5488-5431 Fax. +81-3-5488-5088
Osaka Office Namba Tsujimoto Nissei Bldg., 4F
1-13-17, Namba Naka, Naniwa-ku,
Osaka City, Osaka, 556-0011
Tel. +81-6-6633-3690 Fax. +81-6-6633-3691
All rights reserved
2001
Printed in Japan
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