Datasheet XPC860TZP80nn, XPC860TZP66nn, XPC860TZP50nn, XPC860TCZP66nn, XPC860ENZP50nn Datasheet (Motorola)
...Page 1
This document contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the MPC860 family.
This document contains the following topics:
Topic Page
Part I, “Overview” 1
Part II, “Features” 2
Part III, “Maximum Tolerated Ratings” 6
Part IV, “Thermal Characteristics” 7
Part V, “Power Dissipation” 8
Part VI, “DC Characteristics” 9
Part VII, “Thermal Calculation and Measurement” 10
Part VIII, “Layout Practices” 13
Part IX, “Bus Signal Timing” 13
Part X, “IEEE 1149.1 Electrical Specifications” 41
Part XI, “CPM Electrical Characteristics” 43
Part XII, “UTOPIA AC Electrical Specifications” 65
Part XIII, “FEC Electrical Characteristics” 66
Part XIV, “Mechanical Data and Ordering Information” 70
Part XV, “Document Revision History” 74
Part I Overview
The MPC860 Quad Integrated Communications Controller (PowerQUICC™)
is a versatile one-chip integrated microprocessor and peripheral combination
designed for a variety of controller applications. It particularly excels in both
communications and networking systems. The Po werQUICC unit is referred to
as the MPC860 in this manual.
The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated
Communications Controller (QUICC
™
), referred to here as the QUICC, that
implements the PowerPC architecture. The CPU on the MPC860 is a 32-bit
Hardware Specification
MPC860EC/D
Rev. 6.1, 11/2002
MPC860 Family
Hardware Specifications
Page 2
2
MPC860 Family Hard ware Specifications
MOT OROLA
Features
MPC8xx core that incorporates memory management units (MMUs) and instruction and
data caches and that implements the PowePC instruction set. The communications
processor module (CPM) from the MC68360 QUICC has been enhanced by the addition of
the inter-integrated controller (I
2
C) channel. The memory controller has been enhanced,
enabling the MPC860 to support any type of memory, including high-performance
memories and new types of DRAMs. A PCMCIA socket controller supports up to two
sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC860 family.
Part II Features
The following list summarizes the key MPC860 features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without
conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets;
4-Kbyte instruction caches are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data
caches are two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit
(4-word) cache blocks.
Table 1. MPC860 Family Functionality
Part
Cache (Kbytes) Ethernet
ATM SCC Ref.
1
1
Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC User’s Manual (MPC860UM/D, Rev. 1).
2. MPC8XX ATM Supplement (MPC860SARUM/AD).
3. MPC860T (Rev. D), Fast Ethernet Controller Supplement (MPC860TREVDSUPP).
4. MPC855T User’s Manual (MPC855TUM/D, Rev. 1).
Instruction
Cache
Data Cache 10T 10/100
MPC860DE 4 4 Up to 2 — — 2 1
MPC860DT 4 4 Up to 2 1 yes 2 1,2,3
MPC860DP 16 8 Up to 2 1 yes 2 1,2,3
MPC860EN 4 4 Up to 4 — — 4 1
MPC860SR 4 4 Up to 4 — yes 4 1,2
MPC860T 4 4 Up to 4 1 yes 4 1,2,3
MPC860P 16 8 Up to 4 1 yes 4 1,2,3
MPC855T 4 4 1 1 yes 1 4
Page 3
MOTOROLA
MPC860 Family Hard ware Specifications
3
Features
– Caches are physically addressed, implement a least recently used (LRU)
replacement algorithm, and are lockable on a cache block basis.
— Instruction and data caches are two-way, set-associative, physically addressed,
LRU replacement, and lockable on-line granularity.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
virtual address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Operates at up to 80 MHz
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS
to support a DRAM bank
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and
other memory devices.
— DRAM controller programmable to support most size and speed memory
interfaces
— Four CAS
lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte to 256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
Page 4
4
MPC860 Family Hard ware Specifications MOT OROLA
Features
— Decrementer, time base, and real-time clock (RTC) from the PowerPC
architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
• 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not
available when using ATM over UTOPIA interface)
• ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables
OAM and software implementation of other protocols).
— A TM pace control (APC) scheduler , providing direct support for constant bit rate
(CBR) and unspecified bit rate (UBR) and providing control mechanisms
enabling software support of available bit rate (ABR)
— Physical interface support for UTOPIA (10/100-Mbps is not supported with this
interface) and byte-aligned serial (for example, T1/E1/ADSL)
— UTOPIA-mode ATM supports level-1 master with cell-level handshake,
multi-PHY (up to 4 physical layer devices), connection to 25-, 51-, or 155-Mbps
framers, and UTOPIA/system clock ratios of 1/2 or 1/3.
— Serial-mode ATM connection supports transmission con v ergence (TC) function
for T1/E1/ADSL lines; cell delineation; cell payload scrambling/descrambling;
automatic idle/unassigned cell insertion/stripping; header error control (HEC)
generation, checking, and statistics.
• Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example,
GRACEFUL
STOP
TRANSMIT
,
ENTER
HUNT
MODE
, and
RESTART
TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
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MOTOROLA
MPC860 Family Hard ware Specifications 5
Features
— Three parallel I/O registers with open-drain capability
• Four baud-rate generators (BRGs)
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
• Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
(available only on specially programmed devices).
— HDLC/SDLC
(all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
• One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
• One I
2
C (inter-integrated circuit) port
— Supports master and slave modes
— Multiple-master environment support
• Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplex ed and/or non-multiplex ed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user
defined
— 1- or 8-bit resolution
Page 6
6
MPC860 Family Hard ware Specifications MOT OROLA
Maximum Tolerated Ratings
— Allows independent transmit and receive routing, frame synchronization,
clocking
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)
• Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on the MPC860 or the
MC68360
• PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— Eight memory or I/O windows supported
• Low power support
— Full on—all units fully powered
— Doze—core functional units disabled, except time base decrementer, PLL,
memory controller, RTC, and CPM in low-power standby
— Sleep—all units disabled, except RTC and PIT, PLL active for fast wake up
— Deep sleep—all units disabled including PLL, except RTC and PIT
— Power down mode— all units po wered do wn, e xcept PLL, RTC, PIT, time base,
and decrementer
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
— Supports conditions: =
≠
<>
— Each watchpoint can generate a break-point internally
• 3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK
• 357-pin ball grid array (BGA) package
Part III Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the
MPC860. Table 3-2 provides the maximum ratings.
This device contains circuitry protecting against damage due to high-static voltage or
electrical fields; howev er , it is advised that normal precautions be taken to av oid application
of any voltages higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced, if unused inputs are tied to an appropriate logic voltage
level (for example, either GND or V
dd
).
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MOTOROLA
MPC860 Family Hard ware Specifications 7
Thermal Characteristics
Part IV Thermal Characteristics
Table 4-3 shows the thermal characteristics for the MPC860.
Table 3-2. Maximum Tolerated Ratings
(GND = 0 V)
Rating Symbol Value Unit
Supply V oltage
1
1
The power supply of the device must start its ramp from 0.0 V.
V
DDH
–0.3 to 4.0 V
V
DDL
–0.3 to 4.0 V
KAPWR –0.3 to 4.0 V
VDDSYN –0.3 to 4.0 V
Input V oltage
2
2
Functional operating conditions are provided with the DC electrical specifications in Table 6-5. Absolute maximum
ratings are stress ratings only; functional oper ation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution : All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage . This restriction applies
to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be
applied to its inputs).
V
in
GND – 0.3 to VDDH V
Temperature
3
(Standard)
3
Minimum temperatures are guaranteed as ambient temperature, T
A
. Maximum temperatures are guaranteed as
junction temperature, T
j
.
T
A(min)
0˚C
T
j(max)
95 ˚C
Temperature
3
(Extended) T
A(min)
–40 ˚C
T
j(max)
95 ˚C
Storage Temperature Range T
stg
–55 to 150 ˚C
Table 4-3. MPC860 Thermal Resistance Data
Rating Environment Symbol Rev A
Rev
B, C, D
Unit
Junction to Ambient
1
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Natural Convection Single layer board (1s) R
θ
JA
2
31 40 °C/W
Four layer board (2s2p) R
θ
JMA
3
20 25
Air Flow (200 ft/min) Single layer board (1s) R
θ
JMA
3
26 32
Four layer board (2s2p) R
θ
JMA
3
16 21
Junction to Board
4
R
θ
JB
815
Junction to Case
5
R
θ
JC
57
Junction to Pac kage Top
6
Natural Convection
Ψ
JT
12
Air Flow (200 ft/min) 2 3
Page 8
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MPC860 Family Hard ware Specifications MOT OROLA
Power Dissipation
Part V Power Dissipation
Table 5-4 provides power dissipation information. The modes are 1:1, where CPU and bus
speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed.
NOTE
Values in Table 5-4” represent V
DDL
-based power dissipation
and do not include I/O power dissipation ov er V
DDH
. I/O power
dissipation varies widely by application due to buffer current,
depending on external circuitry.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. F or exposed
pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
Table 5-4. Power Dissipation (P
D
)
Die Revision Frequency (MHz) Typical
1
1
Typical power dissipation is measured at 3.3 V.
Maximum
2
2
Maximum power dissipation is measured at 3.5 V.
Unit
A.3 and Previous 25 450 550 mW
40 700 850 mW
50 870 1050 mW
B.1 and C.1 33 375 TBD mW
50 575 TBD mW
66 750 TBD mW
D.3 and D.4
(1:1 Mode)
50 656 735 mW
66 TBD TBD mW
D.3 and D.4
(2:1 Mode)
66 722 762 mW
80 851 909 mW
Page 9
MOTOROLA
MPC860 Family Hard ware Specifications 9
DC Characteristics
Part VI DC Characteristics
Table 6-5 provides the DC electrical characteristics for the MPC860.
Table 6-5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating Voltage at 40 MHz or Less V
DDH
, V
DDL
, VDDSYN 3.0 3.6 V
KAPWR
(power-down mode)
2.0 3.6 V
KAPWR
(all other operating modes)
V
DDH
– 0.4 V
DDH
V
Operating Voltage Greater than 40 MHz V
DDH
, V
DDL
, KAPWR,
VDDSYN
3.135 3.465 V
KAPWR
(power-down mode)
2.0 3.6 V
KAPWR
(all other operating modes)
V
DDH
– 0.4 V
DDH
V
Input High Voltage (All Inputs Except EXTAL
and EXTCLK)
V
IH
2.0 5.5 V
Input Low Voltage V
IL
GND 0.8 V
EXTAL, EXTCLK Input High Voltage V
IHC
0.7
×
(V
DDH
)V
DDH
+ 0.3 V
Input Leakage Current, V
in
= 5.5 V (Except
TMS, TRST
, DSCK, and DSDI Pins)
I
in
— 100 µA
Input Leakage Current, V
in
= 3.6 V (Except
TMS, TRST
, DSCK, and DSDI Pins)
I
In
—10µA
Input Leakage Current, V
in
= 0 V (Except
TMS, TRST
, DSCK, and DSDI Pins)
I
In
—10µA
Input Capacitance
1
1
Input capacitance is periodically sampled.
C
in
—20pF
Output High Voltage, I
OH
= –2.0 mA,
V
DDH
= 3.0 V (Except XT AL, XFC, and Open
Drain Pins)
V
OH
2.4 — V
Output Low Voltage
IOL = 2.0 mA, CLKOUT
IOL = 3.2 mA
2
IOL = 5.3 mA
3
IOL = 7.0 mA, TXD1/PA14, TXD2/PA12
IOL = 8.9 mA, TS
, T A, TEA, BI, BB,
HRESET
, SRESET
V
OL
— 0.5 V
Page 10
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MPC860 Family Hard ware Specifications MOT OROLA
Thermal Calculation and Measurement
Part VII Thermal Calculation and Measurement
For the following discussions, P
D
= (V
DD
×
I
DD
) + PI/O, where PI/O is the power
dissipation of the I/O drivers.
7.1 Estimation with Junction-to-Ambient Thermal
Resistance
An estimation of the chip junction temperature, T
J
, in °C can be obtained from the equation:
T
J
= TA + (R
θ
JA
× PD)
where:
T
A
= ambient temperature (ºC)
R
θ
JA
= package junction-to-ambient thermal resistance (ºC/W)
P
D
= power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value which provides a
quick and easy estimation of thermal performance. However, the answer is only an
estimate; test cases have demonstrated that errors of a factor of tw o (in the quantity T
J
–
TA)
are possible.
7.2 Estimation with Junction-to-Case Thermal
Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance:
R
θ
JA
= R
θ
JC
+ R
θ
CA
2
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/
VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0,
IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/T
OUT1/CLK2/P A6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
T
OUT2/CLK4/P A4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/
PA1, L1TCLKB/T
OUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29,
BRGO4/SPIMISO/
PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1
/SDACK1/
PB23, SMSYN2
/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/R
TS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0
/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGA
TE1/CD1/PC10, CTS2/PC9, TGA TE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/
L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4,
PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3].
3
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1
/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/
GPL_B1
, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A,
CE
1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30).
Page 11
MOTOROLA MPC860 Family Har dware Specifications 11
Estimation with Junction-to-Board Thermal Resistance
where:
R
θJA
= junction-to-ambient thermal resistance (ºC/W)
R
θJC
= junction-to-case thermal resistance (ºC/W)
R
θCA
= case-to-ambient thermal resistance (ºC/W)
R
θJC
is device related and cannot be influenced by the user. The user adjusts the thermal
environment to affect the case-to-ambient thermal resistance, R
θCA
. For instance, the user
can change the air flow around the device, add a heat sink, change the mounting
arrangement on the printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device. This thermal model is most useful for ceramic
packages with heat sinks where some 90% of the heat flows through the case and the heat
sink to the ambient environment. For most packages, a better model is required.
7.3 Estimation with Junction-to-Board Thermal
Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%)
is a two resistor model consisting of a junction-to-board and a junction-to-case thermal
resistance. The junction-to-case covers the situation where a heat sink is used or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board
thermal resistance describes the thermal performance when most of the heat is conducted
to the printed circuit board. It has been observed that the thermal performance of most
plastic packages and especially PBGA packages is strongly dependent on the board
temperature; see Figure 7-1.
Figure 7-1. Effect of Board Temperature Rise on Thermal Behavior
0
10
20
30
40
50
60
70
80
90
100
0 20406080
Board Temperture Rise Above Ambient Divided by Package
Junction Temperature Rise Above
Ambient Divided by Package Power
Board Temperature Rise Above Ambient Divided by Package Power
Junction Temperature Rise Above
Ambient Divided by Package Power
Page 12
12 MPC860 Family Har dware Specifications MOTOR OLA
Estimation Using Simulation
If the board temperature is known, an estimate of the junction temperature in the
environment can be made using the following equation:
T
J
= TB + (R
θJB
× PD)
where:
R
θJB
= junction-to-board thermal resistance (ºC/W)
T
B
= board temperature (ºC)
P
D
= power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be
ignored, acceptable predictions of junction temperature can be made. For this method to
work, the board and board mounting must be similar to the test board used to determine the
junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground
plane) and vias attaching the thermal balls to the ground plane.
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is
needed. The simple two resistor model can be used with the thermal simulation of the
application [2], or a more accurate and complex model of the package can be used in the
thermal simulation.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are
available, the thermal characterization parameter (Ψ
JT
) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using the following equation:
T
J
= TT + (ΨJT × PD)
where:
Ψ
JT
= thermal characterization parameter
T
T
= thermocouple temperature on top of package
P
D
= power dissipation in package
The thermal characterization parameter is measured per JEDEC JESD51-2 specification
using a 40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and ov er about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
Page 13
MOTOROLA MPC860 Family Har dware Specifications 13
References
7.6 References
Semiconductor Equipment and Materials International (415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956
JEDEC Specifications http://www.jedec.org
1. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA
Within an Automoti ve Engine Controller Module,” Proceedings of SemiTherm, San
Diego, 1998, pp. 47–54.
2. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board
Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of
SemiTherm, San Diego, 1999, pp. 212–220.
Part VIII Layout Practices
Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground.
The power supply pins driv e distinct groups of logic on chip. The V
DD
power supply should
be bypassed to ground using at least four 0.1 µF-bypass capacitors located as close as
possible to the four sides of the package. The capacitor leads and associated printed circuit
traces connecting to chip V
DD
and GND should be kept to less than half an inch per
capacitor lead. A four-layer board is recommended, emplo ying two inner layers as V
CC
and
GND planes.
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and
reflections caused by these fast output switching times. This recommendation particularly
applies to the address and data busses. Maximum PC trace lengths of 6 inches are
recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing
becomes especially critical in systems with higher capacitive loads because these loads
create higher transient currents in the V
CC
and GND circuits. Pull up all unused inputs or
signals that will be inputs during reset. Special care should be taken to minimize the noise
levels on the PLL supply pins.
Part IX Bus Signal Timing
Table 9-6 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.
The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must
be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be
configured for a 40 MHz bus).
Page 14
14 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a
0-pF load for minimum delays.
Table 9-6. Bus Operation Timings
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B1 CLKOUT period 30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns
B1a EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)
–0.90 0.90 –0.90 0.90 –0.90 0.90 –0.90 0.90 ns
B1b EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)
–2.30 2.30 –2.30 2.30 –2.30 2.30 –2.30 2.30 ns
B1c CLKOUT phase jitter (EXTCLK >
15 MHz and MF <= 2)
1
–0.60 0.60 –0.60 0.60 –0.60 0.60 –0.60 0.60 ns
B1d CLKOUT phase jitter
1
–2.00 2.00 –2.00 2.00 –2.00 2.00 –2.00 2.00 ns
B1e CLKOUT frequency jitter (MF < 10) 1— 0.50 — 0.50 — 0.50 — 0.50 %
B1f CLKOUT frequency jitter (10 < MF
< 500)
1
— 2.00 — 2.00 — 2.00 — 2.00 %
B1g CLKOUT frequency jitter (MF > 500)
1
— 3.00 — 3.00 — 3.00 — 3.00 %
B1h Frequency jitter on EXTCLK
2
— 0.50 — 0.50 — 0.50 — 0.50 %
B2 CLKOUT pulse width low 12.12 — 10.00 — 8.00 — 6.06 — ns
B3 CLKOUT width high 12.12 — 10.00 — 8.00 — 6.06 — ns
B4 CLKOUT rise time
3
— 4.00 — 4.00 — 4.00 — 4.00 ns
B533CLKOUT fall time
3
— 4.00 — 4.00 — 4.00 — 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR
, BURST, D(0:31), DP(0:3)
invalid
7.58 — 6.25 — 5.00 — 3.80 — ns
B7a CLKOUT to TSIZ(0:1), REG
, RSV,
AT(0:3), BDIP
, PTR invalid
7.58 — 6.25 — 5.00 — 3.80 — ns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS
invalid
4
7.58 — 6.25 — 5.00 — 3.80 — ns
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR
, BURST, D(0:31), DP(0:3)
valid
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B8a CLKOUT to TSIZ(0:1), REG
, RSV,
AT(0:3) BDIP
, PTR valid
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B8b CLKOUT to BR, BG, VFLS(0:1),
VF(0:2), IWP(0:2), FRZ, LWP(0:1),
STS
valid
4
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR
, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG
, RSV, AT(0:3), PTR
High-Z
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
Page 15
MOTOROLA MPC860 Family Har dware Specifications 15
Bus Signal Timing
B11 CLKOUT to TS, BB assertion 7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns
B11a CLKOUT to TA, BI assertion (when
driven by the memory controller or
PCMCIA interface)
2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns
B12 CLKOUT to TS
, BB negation 7.58 14.33 6.25 13.00 5.00 11.75 3.80 8.54 ns
B12a CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface)
2.50 11.00 2.50 11.00 2.50 11.00 2.50 9.00 ns
B13 CLKOUT to TS
, BB High-Z 7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns
B13a CLKOUT to TA, BI High-Z (when
driven by the memory controller or
PCMCIA interface)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B14 CLKOUT to TEA
assertion 2.50 10.00 2.50 10.00 2.50 10.00 2.50 9.00 ns
B15 CLKOUT to TEA High-Z 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time) 9.75 — 9.75 — 9.75 — 6.00 — ns
B16a TEA, KR, RETRY, CR valid to
CLKOUT (setup time)
10.00 — 10.00 — 10.00 — 4.50 — ns
B16b BB
, BG, BR, valid to CLKOUT (setup
time)
5
8.50 — 8.50 — 8.50 — 4.00 — ns
B17 CLKOUT to T
A, TEA, BI, BB, BG, BR
valid (hold time)
1.00 — 1.00 — 1.00 — 2.00 — ns
B17a CLKOUT to KR
, RETRY, CR valid
(hold time)
2.00 — 2.00 — 2.00 — 2.00 — ns
B18 D(0:31), DP(0:3) valid to CLKOUT
rising edge (setup time)
6
6.00 — 6.00 — 6.00 — 6.00 — ns
B19 CLKOUT rising edge to D(0:31),
DP(0:3) valid (hold time)
6
1.00 — 1.00 — 1.00 — 2.00 — ns
B20 D(0:31), DP(0:3) valid to CLKOUT
falling edge (setup time)
7
4.00 — 4.00 — 4.00 — 4.00 — ns
B21 CLKOUT falling edge to D(0:31),
DP(0:3) valid (hold time)
7
2.00 — 2.00 — 2.00 — 2.00 — ns
B22 CLKOUT rising edge to CS
asserted
GPCM ACS = 00
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B22a CLKOUT f alling edge to CS
asserted
GPCM ACS = 10, TRLX = 0
— 8.00 — 8.00 — 8.00 — 8.00 ns
B22b CLKOUT f alling edge to CS
asserted
GPCM ACS = 11, TRLX = 0,
EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 16
16 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0,
EBDF = 1
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
B23 CLKOUT rising edge to CS
negated
GPCM read access, GPCM write
access ACS = 00, TRLX = 0, and
CSNT = 0
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
5.58 — 4.25 — 3.00 — 1.79 — ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 0
13.15 — 10.50 — 8.00 — 5.58 — ns
B25 CLKOUT rising edge to OE
, WE(0:3)
asserted
— 9.00 — 9.00 — 9.00 — 9.00 ns
B26 CLKOUT rising edge to OE
negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
35.88 — 29.25 — 23.00 — 16.94 — ns
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
43.45 — 35.50 — 28.00 — 20.73 — ns
B28 CLKOUT rising edge to WE
(0:3)
negated GPCM write access
CSNT = 0
— 9.00 — 9.00 — 9.00 — 9.00 ns
B28a CLKOUT falling edge to WE
(0:3)
negated GPCM write access
TRLX = 0, CSNT = 1, EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B28b CLKOUT falling edge to CS
negated
GPCM write access TRLX = 0, CSNT
= 1, ACS = 10, or ACS = 11, EBDF =
0
— 14.33 — 13.00 — 11.75 — 10.54 ns
B28c CLKOUT falling edge to WE
(0:3)
negated GPCM write access
TRLX = 0, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
B28d CLKOUT falling edge to CS
negated
GPCM write access TRLX = 0, CSNT
= 1, ACS = 10, or ACS = 11, EBDF =
1
— 17.99 — 16.00 — 14.13 — 12.31 ns
B29 WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access
CSNT = 0, EBDF = 0
5.58 — 4.25 — 3.00 — 1.79 — ns
B29a WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 0
13.15 — 10.5 — 8.00 — 5.58 — ns
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 17
MOTOROLA MPC860 Family Har dware Specifications 17
Bus Signal Timing
B29b CS negated to D(0:31), DP(0:3),
High-Z GPCM write access,
ACS = 00, TRLX = 0, and CSNT = 0
5.58 — 4.25 — 3.00 — 1.79 — ns
B29c CS
negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
13.15 — 10.5 — 8.00 — 5.58 — ns
B29d WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 0
43.45 — 35.5 — 28.00 — 20.73 — ns
B29e CS
negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
43.45 — 35.5 — 28.00 — 29.73 — ns
B29f WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1
8.86 — 6.88 — 5.00 — 3.18 — ns
B29g CS
negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1
8.86 — 6.88 — 5.00 — 3.18 — ns
B29h WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 1
38.67 — 31.38 — 24.50 — 17.83 — ns
B29i CS
negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1
38.67 — 31.38 — 24.50 — 17.83 — ns
B30 CS
, WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access
8
5.58 — 4.25 — 3.00 — 1.79 — ns
B30a WE
(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1,
CS
negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT =1
ACS = 10, or ACS = 11, EBDF = 0
13.15 — 10.50 — 8.00 — 5.58 — ns
B30b WE
(0:3) negated to A(0:31),
invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS
negated to A(0:31),
Invalid GPCM, write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
43.45 — 35.50 — 28.00 — 20.73 — ns
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 18
18 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
B30c WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1.
CS
negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT = 1,
ACS = 10, ACS = 11, EBDF = 1
8.36 — 6.38 — 4.50 — 2.68 — ns
B30d WE
(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 1, CSNT =1.
CS
negated to A(0:31) invalid GPCM
write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
38.67 — 31.38 — 24.50 — 17.83 — ns
B31 CLKOUT falling edge to CS
valid—as
requested by control bit CST4 in the
corresponding word in UPM
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B31a CLKOUT f alling edge to CS
valid—as
requested by control bit CST1 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B31b CLKOUT rising edge to CS
valid—as
requested by control bit CST2 in the
corresponding word in UPM
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B31c CLKOUT rising edge to CS
valid—as
requested by control bit CST3 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B31d CLKOUT f alling edge to CS
valid—as
requested by control bit CST1 in the
corresponding word in UPM, EBDF =
1
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
B32 CLKOUT falling edge to BS
valid—as
requested by control bit BST4 in the
corresponding word in UPM
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B32a CLKOUT f alling edge to BS
valid—as
requested by control bit BST1 in the
corresponding word in UPM, EBDF =
0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B32b CLKOUT rising edge to BS
valid—as
requested by control bit BST2 in the
corresponding word in UPM
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B32c CLKOUT rising edge to BS
valid—as
requested by control bit BST3 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B32d CLKOUT f alling edge to BS
valid—as
requested by control bit BST1 in the
corresponding word in UPM, EBDF =
1
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 19
MOTOROLA MPC860 Family Har dware Specifications 19
Bus Signal Timing
B33 CLKOUT falling edge to GPL
valid—as requested by control bit
GxT4 in the corresponding word in
UPM
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B33a CLKOUT rising edge to GPL
valid—as requested by control bit
GxT3 in the corresponding word in
UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B34 A(0:31), BADDR(28:30), and D(0:31)
to CS
valid—as requested by control
bit CST4 in the corresponding word in
UPM
5.58 — 4.25 — 3.00 — 1.79 — ns
B34a A(0:31), BADDR(28:30), and D(0:31)
to CS
valid—as requested by control
bit CST1 in the corresponding word in
UPM
13.15 — 10.50 — 8.00 — 5.58 — ns
B34b A(0:31), BADDR(28:30), and D(0:31)
to CS
valid—as requested by control
bit CST2 in the corresponding word in
UPM
20.73 — 16.75 — 13.00 — 9.36 — ns
B35 A(0:31), BADDR(28:30) to CS
valid—as requested by control bit
BST4 in the corresponding word in
UPM
5.58 — 4.25 — 3.00 — 1.79 — ns
B35a A(0:31), BADDR(28:30), and D(0:31)
to BS
valid—as requested by control
bit BST1 in the corresponding word in
UPM
13.15 — 10.50 — 8.00 — 5.58 — ns
B35b A(0:31), BADDR(28:30), and D(0:31)
to BS
valid—as requested by control
bit BST2 in the corresponding word in
UPM
20.73 — 16.75 — 13.00 — 9.36 — ns
B36 A(0:31), BADDR(28:30), and D(0:31)
to GPL
valid—as requested by
control bit GxT4 in the corresponding
word in UPM
5.58 — 4.25 — 3.00 — 1.79 — ns
B37 UPWAIT valid to CLKOUT falling
edge
9
6.00 — 6.00 — 6.00 — 6.00 — ns
B38 CLKOUT falling edge to UPWAIT
valid
9
1.00 — 1.00 — 1.00 — 1.00 — ns
B39 AS
valid to CLKOUT rising edge
10
7.00 — 7.00 — 7.00 — 7.00 — ns
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge
7.00 — 7.00 — 7.00 — 7.00 — ns
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 20
20 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-2 is the control timing diagram.
B41 TS valid to CLKOUT rising edge
(setup time)
7.00 — 7.00 — 7.00 — 7.00 — ns
B42 CLKOUT rising edge to TS
valid (hold
time)
2.00 — 2.00 — 2.00 — 2.00 — ns
B43 AS
negation to memory controller
signals negation
— TBD — TBD — TBD — TBD ns
1
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
2
If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not sta y at an e xtreme v alue f or a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
3
The timings specified in B4 and B5 are based on full strength clock.
4
The timing for BR output is relev ant when the MPC860 is selected to work with external bus arbiter . The timing f or BG
output is relevant when the MPC860 is selected to work with internal bus arbiter.
5
The timing required for BR input is relev ant when the MPC860 is selected to work with internal bus arbiter . The timing
for BG
input is relevant when the MPC860 is selected to work with external bus arbiter.
6
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
7
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller, f or data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 9-17.
10
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allo w the behavior
specified in Figure 9-20.
Table 9-6. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
Page 21
MOTOROLA MPC860 Family Har dware Specifications 21
Bus Signal Timing
Figure 9-2. Control Timing
Figure 9-3 provides the timing for the external clock.
Figure 9-3. External Clock Timing
CLKOUT
Outputs
A
B
2.0 V
0.8 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
2.0 V
0.8 V
2.0 V
0.8 V
B
A
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
D
C
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
C
D
A Maximum output delay specification.
B Minimum output hold time.
C Minimum input setup time specification.
D Minimum input hold time specification.
CLKOUT
B1
B5
B3
B4
B1
B2
Page 22
22 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-4 provides the timing for the synchronous output signals.
Figure 9-4. Synchronous Output Signals Timing
Figure 9-5 provides the timing for the synchronous active pull-up and open-drain output
signals.
Figure 9-5. Synchr onous Active Pull-Up Resistor and Open-Drain Outputs Signals
Timing
CLKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7 B9
B8a
B9B7a
B8b
B7b
CLKOUT
TS
, BB
TA, BI
TEA
B13
B12B11
B11a B12a
B13a
B15
B14
Page 23
MOTOROLA MPC860 Family Har dware Specifications 23
Bus Signal Timing
Figure 9-6 provides the timing for the synchronous input signals.
Figure 9-6. Synchronous Input Signals Timing
Figure 9-7 provides normal case timing for input data. It also applies to normal read
accesses under the control of the UPM in the memory controller.
Figure 9-7. Input Data Timing in Normal Case
Figure 9-8 provides the timing for the input data controlled by the UPM for data beats
where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on
the falling edge of CLKOUT.)
CLKOUT
T
A, BI
TEA, KR,
RETR
Y, CR
BB, BG, BR
B16
B17
B16a
B17a
B16b
B17
CLKOUT
T
A
D[0:31],
DP[0:3]
B16
B17
B19
B18
Page 24
24 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-8. Input Data Timing when Controlled by UPM in the Memory Controller
and DLT3 = 1
Figure 9-9 through Figure 9-12 provide the timing for the external bus read controlled by
various GPCM factors.
Figure 9-9. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
T
A
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28
Page 25
MOTOROLA MPC860 Family Har dware Specifications 25
Bus Signal Timing
Figure 9-10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
Figure 9-11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a
B23
B26
B19B18
B25B24
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B22b
B8
B22c
B23
B24a
B25 B26
B19B18
Page 26
26 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10,
ACS = 11)
Figure 9-13 through Figure 9-15 provide the timing for the external bus write controlled by
various GPCM factors.
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a
B27
B27a
B22bB22c
B19B18
B26
B23
Page 27
MOTOROLA MPC860 Family Har dware Specifications 27
Bus Signal Timing
Figure 9-13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
CLKOUT
A[0:31]
CSx
WE[0:3]
OE
TS
D[0:31],
DP[0:3]
B11
B8
B22 B23
B12
B30
B28B25
B26
B8 B9
B29
B29b
Page 28
28 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
B23
B30aB30c
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11
B8
B22
B12
B28bB28d
B25
B26
B8
B28aB9B28c
B29cB29g
B29a
B29f
Page 29
MOTOROLA MPC860 Family Har dware Specifications 29
Bus Signal Timing
Figure 9-15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
Figure 9-16 provides the timing for the external bus controlled by the UPM.
B23B22
B8
B12B11
CLKOUT
A[0:31]
CSx
WE[0:3]
TS
OE
D[0:31],
DP[0:3]
B30dB30b
B28bB28d
B25
B29e B29i
B26
B29dB29h
B28aB28c
B9B8
B29b
Page 30
30 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-16. External Bus Timing (UPM Controlled Signals)
Figure 9-17 provides the timing for the asynchronous asserted UPWAIT signal controlled
by the UPM.
CLKOUT
CSx
B31d
B8
B31
B34
B32b
GPL_A[0:5],
GPL_B
[0:5]
BS_A
[0:3],
BS_B
[0:3]
A[0:31]
B31c
B31b
B34a
B32
B32aB32d
B34b
B36
B35b
B35a
B35
B33
B32c
B33a
B31a
Page 31
MOTOROLA MPC860 Family Har dware Specifications 31
Bus Signal Timing
Figure 9-17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles
Timing
Figure 9-18 provides the timing for the asynchronous negated UPWAIT signal controlled
by the UPM.
Figure 9-18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles
Timing
Figure 9-19 provides the timing for the synchronous external master access controlled by
the GPCM.
CLKOUT
CSx
UPWAIT
GPL_A
[0:5],
GPL_B
[0:5]
BS_A[0:3],
BS_B
[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
GPL_A
[0:5],
GPL_B
[0:5]
BS_A[0:3],
BS_B
[0:3]
B37
B38
Page 32
32 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-19. Synchronous External Master Access Timing (GPCM Handled ACS =
00)
Figure 9-20 provides the timing for the asynchronous external master memory access
controlled by the GPCM.
Figure 9-20. Asynchronous External Master Memory Access Timing
(GPCM Controlled—ACS = 00)
Figure 9-21 provides the timing for the asynchronous external master control signals
negation.
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W
, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
Page 33
MOTOROLA MPC860 Family Har dware Specifications 33
Bus Signal Timing
Figure 9-21. Asynchronous External Master—Control Signals Negation Timing
Table 9-7 provides interrupt timing for the MPC860.
Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines.
Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines.
Table 9-7. Interrupt Timing
Num Characteristic
1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC860 is able to support.
All Frequencies
Unit
Min Max
I39 IRQ
x valid to CLKOUT rising edge (setup time) 6.00 — ns
I40 IRQ
x hold time after CLKOUT 2.00 — ns
I41 IRQ
x pulse width low 3.00 — ns
I42 IRQ
x pulse width high 3.00 — ns
I43 IRQ
x edge-to-edge time 4 × T
CLOCKOUT
——
AS
CSx, WE[0:3],
OE
, GPLx,
BS
[0:3]
B43
CLKOUT
IRQ
x
I39
I40
Page 34
34 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 9-8 shows the PCMCIA timing for the MPC860.
Table 9-8. PCMCIA Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
P44 A(0:31), REG
valid to PCMCIA
Strobe asserted
1
20.73 — 16.75 — 13.00 — 9.36 — ns
P45 A(0:31), REG
valid to ALE negation 128.30 — 23.00 — 18.00 — 13.15 — ns
P46 CLKOUT to REG
valid 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns
P47 CLKOUT to REG
invalid 8.58 — 7.25 — 6.00 — 4.84 — ns
P48 CLKOUT to CE1
, CE2 asserted 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns
P49 CLKOUT to CE1
, CE2 negated 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns
P50 CLKOUT to PCOE
, IORD, PCWE,
IO
WR assert time
— 11.00 11.00 — 11.00 — 11.00 ns
P51 CLKOUT to PCOE
, IORD, PCWE,
IO
WR negate time
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
P52 CLKOUT to ALE assert time 7.58 15.58 6.25 14.25 5.00 13.00 3.79 10.04 ns
P53 CLKOUT to ALE negate time — 15.58 14.25 — 13.00 — 11.84 ns
P54 PCWE
, IOWR negated to D(0:31)
invalid
1
5.58 — 4.25 — 3.00 — 1.79 — ns
P55 W
AITA and WAITB valid to CLKOUT
rising edge
1
8.00 — 8.00 — 8.00 — 8.00 — ns
P56 CLKOUT rising edge to W
AITA and
W
AITB invalid
1
2.00 — 2.00 — 2.00 — 2.00 — ns
CLKOUT
IRQ
x
I41 I42
I43
I43
Page 35
MOTOROLA MPC860 Family Har dware Specifications 35
Bus Signal Timing
Figure 9-24 provides the PCMCIA access cycle timing for the external bus read.
Figure 9-24. PCMCIA Access Cycles Timing External Bus Read
Figure 9-25 provides the PCMCIA access cycle timing for the external bus write.
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze
(or relieve) the PCMCIA current cycle. The W
AITx assertion will be effective only if it is
detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC860
PowerQUICC User s Manual.
CLKOUT
A[0:31]
REG
CE1/CE2
PCOE, IORD
TS
D[0:31]
ALE
B19B18
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
Page 36
36 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-25. PCMCIA Access Cycles Timing External Bus Write
Figure 9-26 provides the PCMCIA WAIT signals detection timing.
Figure 9-26. PCMCIA WAIT Signals Detection Timing
Table 9-9 shows the PCMCIA port timing for the MPC860.
CLKOUT
A[0:31]
REG
CE1/CE2
CWE, IOWR
TS
D[0:31]
ALE
B9B8
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
P54
CLKOUT
W
AITx
P55
P56
Page 37
MOTOROLA MPC860 Family Har dware Specifications 37
Bus Signal Timing
Figure 9-27 provides the PCMCIA output port timing for the MPC860.
Figure 9-27. PCMCIA Output Por t Timing
Figure 9-28 provides the PCMCIA output port timing for the MPC860.
Figure 9-28. PCMCIA Input Por t Timing
Table 9-10 shows the debug port timing for the MPC860.
Table 9-9. PCMCIA Port Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 — 19.00 ns
P58 HRESET
negated to OPx drive
1
1
OP2 and OP3 only.
25.73 — 21.75 — 18.00 — 14.36 — ns
P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — 5.00 — ns
P60 CLKOUT rising edge to IP_Xx
invalid
1.00 — 1.00 — 1.00 — 1.00 — ns
CLKOUT
HRESET
Output
Signals
OP2, OP3
P57
P58
CLKOUT
Input
Signals
P59
P60
Page 38
38 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-29 provides the input timing for the debug port clock.
Figure 9-29. Debug Port Clock Input Timing
Figure 9-30 provides the timing for the debug port.
Figure 9-30. Debug Port Timings
Table 9-10. Debug Port Timing
Num Characteristic
All Frequencies
Unit
Min Max
P61 DSCK cycle time 3 × T
CLOCKOUT
——
P62 DSCK clock pulse width 1.25 × T
CLOCKOUT
——
P63 DSCK rise and fall times 0.00 3.00 ns
P64 DSDI input data setup time 8.00 — ns
P65 DSDI data hold time 5.00 — ns
P66 DSCK low to DSDO data valid 0.00 15.00 ns
P67 DSCK low to DSDO invalid 0.00 2.00 ns
DSCK
D61
D61
D63
D62
D62
D63
DSCK
DSDI
DSDO
D64
D65
D66
D67
Page 39
MOTOROLA MPC860 Family Har dware Specifications 39
Bus Signal Timing
Table 9-11 shows the reset timing for the MPC860.
Figure 9-31 shows the reset timing for the data bus configuration.
Table 9-11. Reset Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
R69 CLKOUT to HRESET
high
impedance
— 20.00 — 20.00 — 20.00 — 20.00 ns
R70 CLKOUT to SRESET
high
impedance
— 20.00 — 20.00 — 20.00 — 20.00 ns
R71 RSTCONF
pulse width 515.15 — 425.00 340.00 — 257.58 — ns
R72— ————————
R73 Configuration data to HRESET rising
edge setup time
504.55 — 425.00 — 350.00 — 277.27 — ns
R74 Configuration data to RSTCONF
rising edge setup time
350.00 — 350.00 — 350.00 — 350.00 — ns
R75 Configuration data hold time after
RSTCONF
negation
0.00 — 0.00 — 0.00 — 0.00 — ns
R76 Configuration data hold time after
HRESET
negation
0.00 — 0.00 — 0.00 — 0.00 — ns
R77 HRESET
and RSTCONF asserted to
data out drive
— 25.00 25.00 — 25.00 — 25.00 ns
R78 RSTCONF
negated to data out high
impedance
— 25.00 — 25.00 — 25.00 — 25.00 ns
R79 CLKOUT of last rising edge before
chip three-state HRESET
to data out
high impedance
— 25.00 — 25.00 — 25.00 — 25.00 ns
R80 DSDI, DSCK setup 90.91 — 75.00 — 60.00 — 45.45 — ns
R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — 0.00 — ns
R82 SRESET
negated to CLKOUT rising
edge for DSDI and DSCK sample
242.42 — 200.00 — 160.00 — 121.21 — ns
Page 40
40 MPC860 Family Hardware Specifications MOT OROLA
Bus Signal Timing
Figure 9-31. Reset Timing—Configuration from Data Bus
Figure 9-32 provides the reset timing for the data bus weak drive during configuration.
Figure 9-32. Reset Timing—Data Bus Weak Drive During Configuration
Figure 9-33 provides the reset timing for the debug port configuration.
HRESET
RSTCONF
D[0:31] (IN)
R71
R74
R73
R75
R76
CLKOUT
HRESET
D[0:31] (OUT)
(Weak)
RSTCONF
R69
R79
R77 R78
Page 41
MOTOROLA MPC860 Family Har dware Specifications 41
IEEE 1149.1 Electrical Specifications
Figure 9-33. Reset Timing—Debug Port Configuration
Part X IEEE 1149.1 Electrical Specifications
Table 10-12 provides the JTAG timings for the MPC860 shown in Figure 10-34 through
Figure 10-37.
Table 10-12. JTAG Timing
Num Characteristic
All Frequencies
Unit
Min Max
J82 TCK cycle time 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — ns
J86 TMS, TDI data hold time 25.00 — ns
J87 TCK low to TDO data valid — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 ns
J90 TRST
assert time 100.00 — ns
J91 TRST
setup time to TCK low 40.00 — ns
J92 TCK falling edge to output valid — 50.00 ns
J93 TCK falling edge to output valid out of high impedance — 50.00 ns
J94 TCK falling edge to output high impedance — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81
R81
Page 42
42 MPC860 Family Hardware Specifications MOT OROLA
IEEE 1149.1 Electrical Specifications
Figure 10-34. JTAG Test Clock Input Timing
Figure 10-35. JTAG Test Access Port Timing Diagram
Figure 10-36. JTAG TRST
Timing Diagram
TCK
J82 J83
J82 J83
J84 J84
TCK
TMS, TDI
TDO
J85
J86
J87
J88 J89
TCK
TRST
J91
J90
Page 43
MOTOROLA MPC860 Family Har dware Specifications 43
CPM Electrical Characteristics
Figure 10-37. Boundary Scan (JTAG) Timing Diagram
Part XI CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications
processor module (CPM) of the MPC860.
11.1 PIP/PIO AC Electrical Specifications
Table 11-13 provides the PIP/PIO AC timings as shown in Figure 11-38 through
Figure 11-42.
Table 11-13. PIP/PIO Timing
Num Characteristic
All Frequencies
Unit
Min Max
21 Data-in setup time to STBI low 0 — ns
22 Data-In hold time to STBI high 2.5 – t3
1
1
t3 = Specification 23.
— CLK
23 STBI pulse width 1.5 — CLK
24 STBO pulse width 1 CLK – 5 ns — ns
25 Data-out setup time to STBO low 2 — CLK
26 Data-out hold time from STBO high 5 — CLK
27 STBI low to STBO low (Rx interlock) — 2 CLK
28 STBI low to STBO high (Tx interlock) 2 — CLK
29 Data-in setup time to clock high 15 — ns
30 Data-in hold time from clock high 7.5 — ns
31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns
TCK
Output
Signals
Output
Signals
Output
Signals
J92 J94
J93
J95 J96
Page 44
44 MPC860 Family Hardware Specifications MOT OROLA
PIP/PIO AC Electrical Specifications
Figure 11-38. PIP Rx (Interlock Mode) Timing Diagram
Figure 11-39. PIP Tx (Interlock Mode) Timing Diagram
Figure 11-40. PIP Rx (Pulse Mode) Timing Diagram
DATA-IN
STBI
23
24
22
STBO
27
21
DATA-OUT
24
23
26
28
25
STBO
(Output)
STBI
(Input)
DATA-IN
23
2221
STBI
(Input)
STBO
(Output)
24
Page 45
MOTOROLA MPC860 Family Har dware Specifications 45
IDMA Controller AC Electrical Specifications
Figure 11-41. PIP TX (Pulse Mode) Timing Diagram
Figure 11-42. Parallel I/O Data-In/Data-Out Timing Diagram
11.2 IDMA Controller AC Electrical Specifications
Table 11-14 provides the IDMA controller timings as shown in Figure 11-43 through
Figure 11-46.
Table 11-14. IDMA Controller Timing
Num Characteristic
All Frequencies
Unit
Min Max
40 DREQ
setup time to clock high 7 — ns
41 DREQ hold time from clock high 3 — ns
42 SDACK assertion delay from clock high — 12 ns
DATA-OUT
24
2625
STBO
(Output)
STBI
(Input)
23
CLKO
DATA-IN
29
31
30
DATA-OUT
Page 46
46 MPC860 Family Hardware Specifications MOT OROLA
IDMA Controller AC Electrical Specifications
Figure 11-43. IDMA External Requests Timing Diagram
Figure 11-44. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
43 SDACK negation delay from clock low — 12 ns
44 SDACK negation delay from TA low — 20 ns
45 SDACK negation delay from clock high — 15 ns
46 TA assertion to falling edge of the clock setup time (applies to
external T
A)
7—ns
Table 11-14. IDMA Controller Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
41
40
DREQ
(Input)
CLKO
(Output)
DA TA
42
46
43
CLKO
(Output)
TS
(Output)
R/W
(Output)
T
A
(Input)
SD
ACK
Page 47
MOTOROLA MPC860 Family Har dware Specifications 47
IDMA Controller AC Electrical Specifications
Figure 11-45. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
Figure 11-46. SD
ACK Timing Diagram—Peripheral Read, Internally-Generated TA
DA TA
42 44
CLKO
(Output)
TS
(Output)
R/W
(Output)
T
A
(Output)
SD
ACK
DA TA
42 45
CLKO
(Output)
TS
(Output)
R/W
(Output)
T
A
(Output)
SD
ACK
Page 48
48 MPC860 Family Hardware Specifications MOT OROLA
Baud Rate Generator AC Electrical Specifications
11.3 Baud Rate Generator A C Electrical Specifications
Table 11-15 provides the baud rate generator timings as shown in Figure 11-47.
Figure 11-47. Baud Rate Generator Timing Diagram
11.4 Timer AC Electrical Specifications
Table 11-16 provides the general-purpose timer timings as shown in Figure 11-48.
Table 11-15. Baud Rate Generator Timing
Num Characteristic
All Frequencies
Unit
Min Max
50 BRGO rise and fall time — 10 ns
51 BRGO duty cycle 40 60 %
52 BRGO cycle 40 — ns
Table 11-16. Timer Timing
Num Characteristic
All Frequencies
Unit
Min Max
61 TIN/TGA
TE rise and fall time 10 — ns
62 TIN/TGATE low time 1 — CLK
63 TIN/TGATE high time 2 — CLK
64 TIN/TGATE cycle time 3 — CLK
65 CLKO low to TOUT valid 3 25 ns
52
50
51
BRGOX
50
51
Page 49
MOTOROLA MPC860 Family Har dware Specifications 49
Serial Interface AC Electrical Specifications
Figure 11-48. CPM General-Purpose Timers Timing Diagram
11.5 Serial Interface AC Electrical Specifications
Table 11-17 provides the serial interface timings as shown in Figure 11-49 through
Figure 11-53.
Table 11-17. SI Timing
Num Characteristic
All Frequencies
Unit
Min Max
70 L1RCLK, L1TCLK frequency (DSC = 0)
1, 2
— SYNCCLK/2.5 MHz
71 L1RCLK, L1TCLK width low (DSC = 0)
2
P + 10 — ns
71a L1RCLK, L1TCLK width high (DSC = 0)
3
P + 10 — ns
72 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time — 15.00 ns
73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) 20.00 — ns
74 L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 35.00 — ns
75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns
76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns
77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns
78 L1CLK edge to L1ST(1–4) valid
4
10.00 45.00 ns
78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns
79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns
80 L1CLK edge to L1TXD valid 10.00 55.00 ns
80A L1TSYNC valid to L1TXD valid
4
10.00 55.00 ns
81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns
82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or
SYNCCLK/2
MHz
CLKO
TIN/TGA
TE
(Input)
TOUT
(Output)
64
65
61
626361
60
Page 50
50 MPC860 Family Hardware Specifications MOT OROLA
Serial Interface AC Electrical Specifications
Figure 11-49. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns
83a L1RCLK, L1TCLK width high (DSC = 1)
3
P + 10 — ns
84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns
85 L1RQ valid before falling edge of L1TSYNC
4
1.00 — L1TCL
K
86 L1GR setup time
2
42.00 — ns
87 L1GR hold time 42.00 — ns
88 L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
— 0.00 ns
1
The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
Table 11-17. SI Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
L1RXD
(Input)
L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
L1ST(4-1)
(Output)
71
72
70 71a
RFSD=1
75
73
74 77
78
76
79
BIT0
Page 51
MOTOROLA MPC860 Family Har dware Specifications 51
Serial Interface AC Electrical Specifications
Figure 11-50. SI Receive Timing with Double-Speed Clocking (DSC = 1)
L1RXD
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RCLK
(FE=0, CE=0)
(Input)
L1RSYNC
(Input)
L1ST(4-1)
(Output)
72
RFSD=1
75
73
74 77
78
76
79
83a
82
L1CLKO
(Output)
84
BIT0
Page 52
52 MPC860 Family Hardware Specifications MOT OROLA
Serial Interface AC Electrical Specifications
Figure 11-51. SI Transmit Timing Diagram (DSC = 0)
L1TXD
(Output)
L1TCLK
(FE=0, CE=0)
(Input)
L1TCLK
(FE=1, CE=1)
(Input)
L1TSYNC
(Input)
L1ST(4-1)
(Output)
71 70
72
73
75
74
80a
80
78
TFSD=0
81
79
BIT0
Page 53
MOTOROLA MPC860 Family Har dware Specifications 53
Serial Interface AC Electrical Specifications
Figure 11-52. SI Transmit Timing with Double Speed Clocking (DSC = 1)
L1TXD
(Output)
L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
L1ST(4-1)
(Output)
72
TFSD=0
75
73
74
78a
80
79
83a
82
L1CLKO
(Output)
84
BIT0
78
81
Page 54
54 MPC860 Family Hardware Specifications MOT OROLA
Serial Interface AC Electrical Specifications
Figure 11-53. IDL Timing
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
L1RXD
(Input)
L1TXD
(Output)
L1ST(4-1)
(Output)
L1RQ
(Output)
73
77
12345678910 11 12 13 14 15 16 17 18 19 20
74
80
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
71
71
L1GR
(Input)
78
85
72
76
87
86
L1RSYNC
(Input)
L1RCLK
(Input)
81
Page 55
MOTOROLA MPC860 Family Har dware Specifications 55
SCC in NMSI Mode Electrical Specifications
11.6 SCC in NMSI Mode Electrical Specifications
Table 11-18 provides the NMSI external clock timing.
Table 11-19 provides the NMSI internal clock timing.
Figure 11-54 through Figure 11-56 show the NMSI timings.
Table 11-18. NMSI External Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLK1 and TCLK1 width high
1
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
1/SYNCCLK — ns
101 RCLK1 and TCLK1 width low 1/SYNCCLK + 5 — ns
102 RCLK1 and TCLK1 rise/fall time — 15.00 ns
103 TXD1 active delay (from TCLK1 falling edge) 0.00 50.00 ns
104 R
TS1 active/inactive delay (from TCLK1 falling edge) 0.00 50.00 ns
105 CTS1 setup time to TCLK1 rising edge 5.00 — ns
106 RXD1 setup time to RCLK1 rising edge 5.00 — ns
107 RXD1 hold time from RCLK1 rising edge
2
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
5.00 — ns
108 CD1
setup Time to RCLK1 rising edge 5.00 — ns
Table 11-19. NMSI Internal Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLK1 and TCLK1 frequency
1
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLK1 and TCLK1 rise/fall time — — ns
103 TXD1 active delay (from TCLK1 falling edge) 0.00 30.00 ns
104 R
TS1 active/inactive delay (from TCLK1 falling edge) 0.00 30.00 ns
105 CTS1 setup time to TCLK1 rising edge 40.00 — ns
106 RXD1 setup time to RCLK1 rising edge 40.00 — ns
107 RXD1 hold time from RCLK1 rising edge
2
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
0.00 — ns
108 CD1
setup time to RCLK1 rising edge 40.00 — ns
Page 56
56 MPC860 Family Hardware Specifications MOT OROLA
SCC in NMSI Mode Electrical Specifications
Figure 11-54. SCC NMSI Receive Timing Diagram
Figure 11-55. SCC NMSI Transmit Timing Diagram
RCLK1
CD1
(Input)
102
100
107
108
107
RxD1
(Input)
CD1
(SYNC Input)
102 101
106
TCLK1
CTS1
(Input)
102
100
104
107
TxD1
(Output)
CTS1
(SYNC Input)
102 101
RTS1
(Output)
105
103
104
Page 57
MOTOROLA MPC860 Family Har dware Specifications 57
Ethernet Electrical Specifications
Figure 11-56. HDLC Bus Timing Diagram
11.7 Ethernet Electrical Specifications
Table 11-20 provides the Ethernet timings as shown in Figure 11-57 through Figure 11-61.
Table 11-20. Ethernet Timing
Num Characteristic
All Frequencies
Unit
Min Max
120 CLSN width high 40 — ns
121 RCLK1 rise/fall time — 15 ns
122 RCLK1 width low 40 — ns
123 RCLK1 clock period
1
80 120 ns
124 RXD1 setup time 20 — ns
125 RXD1 hold time 5 — ns
126 RENA active delay (from RCLK1 rising edge of the last data bit) 10 — ns
127 RENA width low 100 — ns
128 TCLK1 rise/fall time — 15 ns
129 TCLK1 width low 40 — ns
130 TCLK1 clock period
1
99 101 ns
131 TXD1 active delay (from TCLK1 rising edge) 10 50 ns
132 TXD1 inactive delay (from TCLK1 rising edge) 10 50 ns
133 TENA active delay (from TCLK1 rising edge) 10 50 ns
TCLK1
CTS1
(Echo Input)
102
100
104
TxD1
(Output)
102 101
RTS1
(Output)
103
104107
105
Page 58
58 MPC860 Family Hardware Specifications MOT OROLA
Ethernet Electrical Specifications
Figure 11-57. Ethernet Collision Timing Diagram
Figure 11-58. Ethernet Receive Timing Diagram
134 TENA inactive delay (from TCLK1 rising edge) 10 50 ns
135 RSTRT active delay (from TCLK1 falling edge) 10 50 ns
136 RSTRT inactive delay (from TCLK1 falling edge) 10 50 ns
137 REJECT width low 1 — CLK
138 CLKO1 low to SDACK asserted
2
—20ns
139 CLKO1 low to SDACK negated
2
—20ns
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 11-20. Ethernet Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
CLSN(CTS1)
120
(Input)
RCLK1
121
RxD1
(Input)
121
RENA(CD1)
(Input)
125
124 123
127
126
Last Bit
Page 59
MOTOROLA MPC860 Family Har dware Specifications 59
Ethernet Electrical Specifications
Figure 11-59. Ethernet Transmit Timing Diagram
Figure 11-60. CAM Interface Receive Start Timing Diagram
Figure 11-61. CAM Interface REJECT
Timing Diagram
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD1)
(Input)
133 134
132
131 121
129
(NOTE 2)
RCLK1
RxD1
(Input)
RSTRT
(Output)
0
136
125
1 1 BIT1 BIT2
Start Frame
REJECT
137
Page 60
60 MPC860 Family Hardware Specifications MOT OROLA
SMC Transparent AC Electrical Specifications
11.8 SMC Transparent AC Electrical Specifications
Table 11-21 provides the SMC transparent timings as shown in Figure 11-62.
Figure 11-62. SMC Transparent Timing Diagram
11.9 SPI Master AC Electrical Specifications
Table 11-22 provides the SPI master timings as shown in Figure 11-63 and Figure 11-64.
T able 11-21. SMC Transparent Timing
Num Characteristic
All Frequencies
Unit
Min Max
150 SMCLK clock period
1
1
SYNCCLK must be at least twice as fast as SMCLK.
100 — ns
151 SMCLK width low 50 — ns
151A SMCLK width high 50 — ns
152 SMCLK rise/fall time — 15 ns
153 SMTXD active delay (from SMCLK falling edge) 10 50 ns
154 SMRXD/SMSYNC setup time 20 — ns
155 RXD1/SMSYNC hold time 5 — ns
SMCLK
SMRXD
(Input)
152
150
SMTXD
(Output)
152 151
SMSYNC
151
154 153
155
154
155
NOTE
NOTE:
This delay is equal to an integer number of character-length clocks.1.
Page 61
MOTOROLA MPC860 Family Har dware Specifications 61
SPI Master AC Electrical Specifications
Figure 11-63. SPI Master (CP = 0) Timing Diagram
Table 11-22. SPI Master Timing
Num Characteristic
All Frequencies
Unit
Min Max
160 MASTER cycle time 4 1024 t
cyc
161 MASTER clock (SCK) high or low time 2 512 t
cyc
162 MASTER data setup time (inputs) 50 — ns
163 Master data hold time (inputs) 0 — ns
164 Master data valid (after SCK edge) — 20 ns
165 Master data hold time (outputs) 0 — ns
166 Rise time output — 15 ns
167 Fall time output — 15 ns
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
Page 62
62 MPC860 Family Hardware Specifications MOT OROLA
SPI Slave AC Electrical Specifications
Figure 11-64. SPI Master (CP = 1) Timing Diagram
11.10SPI Slave AC Electrical Specifications
Table 11-23 provides the SPI slave timings as shown in Figure 11-65 and Figure 11-66.
Table 11-23. SPI Slave Timing
Num Characteristic
All Frequencies
Unit
Min Max
170 Slave cycle time 2 — t
cyc
171 Slave enable lead time 15 — ns
172 Slave enable lag time 15 — ns
173 Slave clock (SPICLK) high or low time 1 — t
cyc
174 Slave sequential transfer delay (does not require deselect) 1 — t
cyc
175 Slave data setup time (inputs) 20 — ns
176 Slave data hold time (inputs) 20 — ns
177 Slave access time — 50 ns
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
162
Page 63
MOTOROLA MPC860 Family Har dware Specifications 63
SPI Slave AC Electrical Specifications
Figure 11-65. SPI Slave (CP = 0) Timing Diagram
Figure 11-66. SPI Slave (CP = 1) Timing Diagram
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182173
173 170
msb lsb msb
181
177 182
175 179
SPISEL
(Input)
171172
174
Datamsb lsb msbUndef
181
178
176 182
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182
msb lsb
181
177 182
175 179
SPISEL
(Input)
174
Data
msb
lsbUndef
178
176 182
msb
msb
172
173
173
171 170
181
Page 64
64 MPC860 Family Hardware Specifications MOT OROLA
I2C AC Electrical Specifications
11.11I2C AC Electrical Specifications
Table 11-24 provides the I2C (SCL < 100 kHz) timings.
Table 11-25 provides the I
2
C (SCL > 100 kHz) timings.
Table 11-24. I2C Timing (SCL < 100 kHZ)
Num Characteristic
All Frequencies
Unit
Min Max
200 SCL clock frequency (slave) 0 100 kHz
200 SCL clock frequency (master)
1
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.
1.5 100 kHz
202 Bus free time between transmissions 4.7 — µs
203 Low period of SCL 4.7 — µs
204 High period of SCL 4.0 — µs
205 Start condition setup time 4.7 — µs
206 Start condition hold time 4.0 — µs
207 Data hold time 0 — µs
208 Data setup time 250 — ns
209 SDL/SCL rise time — 1 µs
210 SDL/SCL fall time — 300 ns
211 Stop condition setup time 4.7 — µs
Table 11-25. . I2C Timing (SCL > 100 kHZ)
Num Characteristic Expression
All Frequencies
Unit
Min Max
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master)
1
fSCL BRGCLK/16512 BRGCLK/48 Hz
202 Bus free time between transmissions 1/(2.2 * fSCL) — s
203 Low period of SCL 1/(2.2 * fSCL) — s
204 High period of SCL 1/(2.2 * fSCL) — s
205 Start condition setup time 1/(2.2 * fSCL) — s
206 Start condition hold time 1/(2.2 * fSCL) — s
207 Data hold time 0 — s
208 Data setup time 1/(40 * fSCL) — s
209 SDL/SCL rise time — 1/(10 * fSCL) s
210 SDL/SCL fall time — 1/(33 * fSCL) s
211 Stop condition setup time 1/2(2.2 * fSCL) — s
Page 65
MOTOROLA MPC860 Family Har dware Specifications 65
UTOPIA AC Electrical Specifications
Figure 11-67 shows the I2C bus timing.
Figure 11-67. I2C Bus Timing Diagram
Part XII UTOPIA AC Electrical Specifications
Table 12-26 shows the AC electrical specifications for the UTOPIA interface.
Figure 12-68 shows signal timings during UTOPIA receive operations.
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.
Table 12-26. UTOPIA AC Electrical Specifications
Num Signal Characteristic Direction Min Max Unit
U1 UtpClk rise/fall time (Internal clock option) Output — 3.5 ns
Duty cycle 50 50 %
Frequency — 50 MHz
U1a UtpClk rise/fall time (external clock option) Input — 3.5 ns
Duty cycle 40 60 %
Frequency — 50 MHz
U2 RxEnb
and TxEnb active delay Output 2 16 ns
U3 UTPB, SOC, Rxclav and Txclav setup time Input 8 — ns
U4 UTPB, SOC, Rxclav and Txclav hold time Input 1 — ns
U5 UTPB, SOC active delay (and PHREQ and PHSEL active delay
in MPHY mode)
Output 2 16 ns
SCL
202
205
203
207
204
208
206 209 211210
SDA
Page 66
66 MPC860 Family Hardware Specifications MOT OROLA
FEC Electrical Characteristics
Figure 12-68. UTOPIA Receive Timing
Figure 12-69 shows signal timings during UTOPIA transmit operations.
Figure 12-69. UTOPIA T ransmit Timing
Part XIII FEC Electrical Characteristics
This section provides the AC electrical specifications for the F ast Ethernet controller (FEC).
Note that the timing specifications for the MII signals are independent of system clock
frequency (part speed designation). Also, MII signals use TTL signal levels compatible
with devices operating at either 5.0 V or 3.3 V.
UtpClk
UTPB
RxEnb
U1
3
2
SOC
4
RxClav
PHREQn
3
4
HighZ at MPHY
HighZ at MPHY
U1
U5
U3 U4
U4
U3
U2
UtpClk
UTPB
TxEnb
1
2
SOC
5
TxClav
PHSELn
3
4
5
HighZ at MPHY
HighZ at MPHY
U1
U1
U5
U5
U2
U3 U4
Page 67
MOTOROLA MPC860 Family Har dware Specifications 67
MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK)
13.1 MII Receive Signal Timing (MII_RXD[3:0],
MII_RX_DV, MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz
+1%. There is no minimum frequency requirement. In addition, the processor clock
frequency must exceed the MII_RX_CLK frequency – 1%.
Table 13-27 provides information on the MII receive signal timing.
Figure 13-70 shows MII receive signal timing.
Figure 13-70. MII Receive Signal Timing Diagram
13.2 MII T ransmit Signal Timing (MII_TXD[3:0],
MII_TX_EN, MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of
25 MHz +1%. There is no minimum frequency requirement. In addition, the processor
clock frequency must exceed the MII_TX_CLK frequency – 1%.
Table 13-28 provides information on the MII transmit signal timing.
Table 13-27. MII Receive Signal Timing
Num Characteristic Min Max Unit
M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns
M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns
M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK
period
M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK
period
M1
M2
MII_RX_CLK (Input)
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M3
M4
Page 68
68 MPC860 Family Hardware Specifications MOT OROLA
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Figure 13-71 shows the MII transmit signal timing diagram.
Figure 13-71. MII Transmit Signal Timing Diagram
13.3 MII Async Inputs Signal Timing (MII_CRS,
MII_COL)
Table 13-29 provides information on the MII async inputs signal timing.
Figure 13-72 shows the MII asynchronous inputs signal timing diagram.
Figure 13-72. MII Async Inputs Timing Diagram
Table 13-28. MII Transmit Signal Timing
Num Characteristic Min Max Unit
M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns
M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25
M7 MII_TX_CLK pulse width high 35 65% MII_TX_CLK
period
M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK
period
Table 13-29. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK
period
M6
MII_TX_CLK (Input)
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
MII_CRS, MII_COL
M9
Page 69
MOTOROLA MPC860 Family Har dware Specifications 69
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
13.4 MII Serial Management Channel Timing
(MII_MDIO, MII_MDC)
T able 13-30 provides information on the MII serial management channel signal timing. The
FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The e xact
upper bound is under investigation.
Figure 13-73 shows the MII serial management channel timing diagram.
Figure 13-73. MII Serial Management Channel Timing Diagram
Table 13-30. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0—ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns
M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns
M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns
M14 MII_MDC pulse width high 40% 60% MII_MDC
period
M15 MII_MDC pulse width low 40% 60% MII_MDC
period
M11
MII_MDC (Output)
MII_MDIO (Output)
M12
M13
MII_MDIO (Input)
M10
M14
MM15
Page 70
70 MPC860 Family Hardware Specifications MOT OROLA
Mechanical Data and Ordering Information
Part XIV Mechanical Data and Ordering
Information
Table 14-31 provides information on the MPC860 revision D.3 and D.4 deri v ati v e de vices.
Table 14-32 identifies the packages and operating frequencies available for the MPC860.
Table 14-31. MPC860 Family Revision D.3 and D.4 Derivatives
Device
Number of
SCCs
1
1
Serial communications controller (SCC).
Ethernet Support
2
(Mbps)
2
Up to 4 channels at 40 MHz or 2 channels at 25 MHz.
Multi-Channel
HDLC Support
ATM
Support
MPC855T 1 10/100 yes yes
MPC860DE 2 10 N/A N/A
MPC860DT 10/100 Yes Yes
MPC860DP 10/100 Yes Yes
MPC860EN 4 10 N/A N/A
MPC860SR 10 Yes Yes
MPC860T 10/100 Yes Yes
MPC860P 10/100 Yes Yes
Table 14-32. MPC860 Family Package/Frequency Availability
Package T ype
Frequency
(MHz)
Temperature
(Tj)
Order Number
Page 71
MOTOROLA MPC860 Family Har dware Specifications 71
Mechanical Data and Ordering Information
Table 14-33 identifies the packages and operating frequencies available for the MPC860P.
Ball grid array
(ZP suffix)
50 0° to 95°C XPC860DEZP50nn
1
XPC860DTZP50nn
XPC860ENZP50nn
XPC860SRZP50nn
XPC860TZP50nn
XPC855TZP50D4
66 0° to 95°C XPC860DEZP66nn
XPC860DTZP66nn
XPC860ENZP66nn
XPC860SRZP66nn
XPC860TZP66nn
XPC855TZP66D4
80 0° to 95°C XPC860DEZP80nn
XPC860DTZP80nn
XPC860ENZP80nn
XPC860SRZP80nn
XPC860TZP80nn
XPC855TZP80D4
Ball grid array
(CZP suffix)
50 –40° to 95°C XPC860DECZP50nn
XPC860DTCZP50nn
XPC860ENCZP50nn
XPC860SRCZP50nn
XPC860TCZP50nn
XPC855TCZP50D4
66 –40° to 95°C XPC860DECZP66nn
XPC860DTCZP66nn
XPC860ENCZP66nn
XPC860SRCZP66nn
XPC860TCZP66nn
XPC855TCZP66D4
1
Where nn specifies version D.3 (as D3) or D.4 (as D4).
Table 14-33. MPC860P Package/Frequency Availability
Package T ype
Frequency
(MHz)
Temperature
(Tj)
Order Number
Ball grid array
(ZP suffix)
50 0° to 95°C XPC860DPZP50nn
1
XPC860PZP50nn
1
Where nn specifies version D.3 (as D3) or D.4 (as D4).
66 0° to 95°C XPC860DPZP66nn
XPC860PZP66nn
80 0° to 95°C XPC860DPZP80nn
XPC860PZP80nn
Ball grid array
(CZP suffix)
50 –40° to 95°C XPC860DPCZP50nn
XPC860PCZP50nn
66 –40° to 95°C XPC860DPCZP66nn
XPC860PCZP66nn
Table 14-32. MPC860 Family Package/Frequency Availability (continued)
Page 72
72 MPC860 Family Hardware Specifications MOT OROLA
Pin Assignments
14.1 Pin Assignments
Figure 14-74 shows the top view pinout of the PBGA package. For additional information,
see the MPC860 PowerQUICC User’s Manual, or the MPC855T User’s Manual.
NOTE: This is the top view of the device.
Figure 14-74. Pinout of the PBGA Package
PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 CLKOUT IPA3DP2
A2 A7 A14 A27 A29 A30 A28 A31 VDDL BSA2
WE1 WE3 CE2A CS1CS4A5 A11
18 16 141312111098765 32417 15 119
A1 A6 A13 A17 A21 A23 A22 TSIZ0 BSA3
M_CRS WE2 GPLA2 CE1A WRCS5A4 A10 GPLB4A0
PA15 A3 A12 A16 A20 A24 A26 TSIZ1 BSA1
WE0 GPLA1 GPLA3 CS0 TACS7PB31 A9 GPLA4PB30
PC14 PC15 N/C N/C A15 A19 A25 A18 BSA0
GPLA0 N/C CS6 GPLA5 BDIPCS2PA14 A8 TEAPB28
PC13 PB29
VDDH VDDH
BI
BGCS3PA13 BBPB27
PC12 VDDL
GND GND
TS
IRQ3VDDLPA12 BURSTPB26
TMS PA11 IRQ6
IPB4BRTDO IPB3TRST
M_MDIO
TCK IRQ2 IPB0M_COLTDI IPB7VDDL
PB24 PB25 IPB1 IPB2IPB5PA10 ALEBPC11
PA9 PB21 GND IPB6 ALEABADDR30PB23 IRQ4
PC10
PC9 PB20 AS
OP1OP0PA8 MODCK1PB22
PC8 PC7
BADDR28
BADDR29
MODCK2
PA6
VDDL
PA7
PA5 PB16
TEXP
EXTCLK
HRESET
PB18 EXTALPB19
PB17 VDDL GND
RSTCONF
SRESET
VDDLPA3 GND XT ALPA4
PA2 PD12
VDDH
WAIT_A
PORESET
WAIT_B
PB15
VDDH
KAPWRPC6
PC5 PD11 VDDH D12 D17 D9 D15 D22 D25 D31 IPA6 IPA0 IPA7 XFCIPA1PC4 PD7 VDDSYNPA1
PB14 PD4 IRQ1
D8 D23 D11 D16 D19 D21 D26 D30 IPA5 IPA2 N/CIPA4PD15 PD5 VSSSYNPA0
PD13 PD6 IRQ0
D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP0 N/CDP3PD9 M_Tx_ E N
VSSSYN1
PD14
B
A
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
PD10 PD8
Page 73
MOTOROLA MPC860 Family Har dware Specifications 73
Mechanical Dimensions of the PBGA Package
14.2 Mechanical Dimensions of the PBGA Package
For more information on the printed circuit board layout of the PBGA package, including
thermal via design and suggested pad layout, please refer to Motorola Application Note,
Plastic Ball Grid Array (order number: AN1231/D), available from your local Motorola
sales office. Figure 14-75 shows the mechanical dimensions of the PBGA package.
Figure 14-75. Mechanical Dimensions and Bottom Surface Nomenclature
of the PBGA Package
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12345678910111213141516171819
SIDE VIEW
BOTTOM VIEW
18X
4X
357X b
TOP VIEW
A2
A3
e
0.3
M
C
D
A
A1
D2
0.15MC
EE2
0.2 C
A
B
0.2
D1
E1
AB
0.25 C
0.35 C
C
NOTES:
1. Dimensions and tolerancing per ASME Y14.5M, 1994.
2. Dimensions in millimeters.
3. Dimension b is the maximum solder ball diameter
measured parallel to datum C.
DIM MIN MAX
MILLIMETERS
A --- 2.05
0.50 0.70
A2 0.95 1.35
A3 0.70 0.90
b 0.60 0.90
D 25.00 BSC
D1 22.86 BSC
D2 22.40 22.60
e 1.27 BSC
E 25.00 BSC
E1 22.86 BSC
E2 22.40 22.60
A1
Case No. 1103-01
Page 74
74 MPC860 Family Hardware Specifications MOT OROLA
Document Revision History
Part XV Document Revision History
Table 15-34 lists significant changes between revisions of this document.
Table 15-34. Document Revision History
Revision Date Change
5.1 11/2001 Revised template format, removed references to MAC functionality, changed Table 9-6
B23 max value @ 66 Mhz from 2ns to 8ns, added this revision history table
6 10/2002 Added the MPC855T. Corrected Figure 9-25 on page 36.
6.1 11/2002 Corrected UTOPIA RXenb* and TXenb* timing values. Changed incorrect usage of Vcc
to Vdd. Corrected dual port RAM to 8Kbytes.
Page 75
MOTOROLA MPC860 Family Har dware Specifications 75
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
Page 76
MPC860EC/D
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