Datasheet XC95144-15PQ100I, XC95144-15PQ100C, XC95144-10TQ100I, XC95144-10TQ100C, XC95144-10PQ160I Datasheet (XILINX)

December 4, 1998 (Version 4.0) 1

Features

• 7.5 ns pin-to-pin logic delays on all pins

•f

CNT

to 111 MHz

• 144 macrocells with 3,200 usable gates

• Up to 133 user I/O pins

• 5 V in-system programmable

- Endurance of 10,000 program/erase cycles

- Program/erase over full commercial voltage and
temperature range

• Enhanced pin-locking architecture

• Flexible 36V18 Function Block

- 90 product terms drive any or all of 18 macrocells
within Function Block

- Global and product term clocks, output enables, set
and reset signals

• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support

• Programmable power reduction mode in each
macrocell

• Slew rate control on individual outputs

• User programmable ground pin capability

• Extended pattern security features for design protection

• High-drive 24 mA outputs

• 3.3 V or 5 V I/O capability

• Advanced CMOS 5V FastFLASH technology

• Supports parallel programming of more than one
XC9500 concurrently

• Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages

Description

The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure2 for the architec­ture overview.

Power Management

Power dissipation can be reduced in the XC95144 by con­figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.

Operating current for each design can be approximated for
specific operating conditions using the following equation:

I

CC

(mA) =

MC

HP

(1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MC

HP

= Macrocells in high-performance mode
MC

LP

= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)

Figure1 shows a typical calculation for the XC95144

device.

Figure 1: Typical I

cc

vs. Frequency for XC95144

1

XC95144 In-System Programmable
CPLD

December 4, 1998 (Version 4.0)

11*

Product Specification



Clock Frequency (MHz)

Typical I

CC

(mA)

050

200

(480)

(320)

400

600

100

High Performance

Low Power

X5898B

(160)

(300)

XC95144 In-System Programmable CPLD

2 December 4, 1998 (Version 4.0)

In-System Programming Controller

JTAG

Controller

I/O

Blocks

Function

Block 1

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

JTAG Port

3

36

I/O/GTS

I/O/GSR

I/O/GCK

I/O

I/O

I/O

I/O

2

1

I/O

I/O

I/O

I/O

3

X5922

1

Function

Block 2

36

Function

Block 3

36

Function

Block 4

36

Macrocells

1 to 18

Function

Block 8

36

18

18

18

18

18

FastCONNECT Switch Matrix

Figure 2: XC95144 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

December 4, 1998 (Version 4.0) 3

XC95144 In-System Programmable CPLD

Absolute Maximum Ratings

Warning:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.

Recommended Operation Conditions

1

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol Parameter Value Units

V

CC

Supply voltage relative to GND -0.5 to 7.0 V

V

IN

DC input voltage relative to GND -0.5 to VCC + 0.5 V

V

TS

Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V

T

STG

Storage temperature -65 to +150 °C

T

SOL

Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260 °C

Symbol Parameter Min Max Units

V

CCINT

Supply voltage for internal logic and input buffer 4.75

(4.5)

5.25
(5.5)

V

V

CCIO

Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V

V

IL

Low-level input voltage 0 0.80 V

V

IH

High-level input voltage 2.0 V

CCINT

+0.5 V

V

O

Output voltage 0 V

CCIO

V

Symbol Parameter Min Max Units

t

DR

Data Retention 20 - Years

N

PE

Program/Erase Cycles 10,000 - Cycles

XC95144 In-System Programmable CPLD

4 December 4, 1998 (Version 4.0)

DC Characteristics Over Recommended Operating Conditions

AC Characteristics

Note: 1. f

CNT

is the fastest 16-bit counter frequency available, using the local feedback when applicable.

f

CNT

is also the Export Control Maximum flip-flop toggle rate, f

TOG

.

2. f

SYSTEM

is the internal operating frequency for general purpose system designs spanning multiple FBs.

Symbol Parameter Test Conditions Min Max Units

V

OH

Output high voltage for 5 V operation IOH = -4.0 mA

V

CC

= Min

2.4 V

Output high voltage for 3.3 V operation I

OH

= -3.2 mA

V

CC

= Min

2.4 V

V

OL

Output low voltage for 5 V operation IOL = 24 mA

V

CC

= Min

0.5 V

Output low voltage for 3.3 V operation I

OL

= 10 mA

V

CC

= Min

0.4 V

I

IL

Input leakage current VCC = Max

V

IN

= GND or V

CC

±10.0 µA

I

IH

I/O high-Z leakage current VCC = Max

V

IN

= GND or V

CC

±10.0 µA

C

IN

I/O capacitance VIN = GND

f = 1.0 MHz

10.0 pF

I

CC

Operating Supply Current
(low power mode, active)

VI = GND, No load
f = 1.0 MHz

160 (Typ) ma

Symbol Parameter

XC95144-7 XC95144-10XC95144-15

Units

Min Max Min Max Min Max

t

PD

I/O to output valid 7.5 10.0 15.0 ns

t

SU

I/O setup time before GCK 4.5 6.0 8.0 ns

t

H

I/O hold time after GCK 0.0 0.0 0.0 ns

t

CO

GCK to output valid 4.5 6.0 8.0 ns

f

CNT

1

16-bit counter frequency 125.0 111.1 95.2 MHz

f

SYSTEM

2

Multiple FB internal operating frequency 83.3 66.7 55.6 MHz

t

PSU

I/O setup time before p-term clock input 0.5 2.0 4.0 ns

t

PH

I/O hold time after p-term clock input 4.0 4.0 4.0 ns

t

PCO

P-term clock to output valid 8.5 10.0 12.0 ns

t

OE

GTS to output valid 5.5 6.0 11.0 ns

t

OD

GTS to output disable 5.5 6.0 11.0 ns

t

POE

Product term OE to output enabled 9.5 10.0 14.0 ns

t

POD

Product term OE to output disabled 9.5 10.0 14.0 ns

t

WLH

GCK pulse width (High or Low) 4.0 4.5 5.5 ns

December 4, 1998 (Version 4.0) 5

XC95144 In-System Programmable CPLD

Internal Timing Parameters

Note: 3. t

PTA

is multiplied by the span of the function as defined in the family data sheet.

Symbol Parameter

XC95144-7 XC95144-10XC95144-15

Units

Min Max Min Max Min Max

Buffer Delays

t

IN

Input buffer delay 2.5 3.5 4.5 ns

t

GCK

GCK buffer delay 1.5 2.5 3.0 ns

t

GSR

GSR buffer delay 4.5 6.0 7.5 ns

t

GTS

GTS buffer delay 5.5 6.0 11.0 ns

t

OUT

Output buffer delay 2.5 3.0 4.5 ns

t

EN

Output buffer enable/disable delay 0.0 0.0 0.0 ns

Product Term Control Delays

t

PTCK

Product term clock delay 3.0 3.0 2.5 ns

t

PTSR

Product term set/reset delay 2.0 2.5 3.0 ns

t

PTTS

Product term 3-state delay 4.5 3.5 5.0 ns

Internal Register and Combinatorial delays

t

PDI

Combinatorial logic propagation delay 0.5 1.0 3.0 ns

t

SUI

Register setup time 1.5 2.5 3.5 ns

t

HI

Register hold time 3.0 3.5 4.5 ns

t

COI

Register clock to output valid time 0.5 0.5 0.5 ns

t

AOI

Register async. S/R to output delay 6.5 7.0 8.0 ns

t

RAI

Register async. S/R recovery before clock 7.5 10.0 10.0 ns

t

LOGI

Internal logic delay 2.0 2.5 3.0 ns

t

LOGILP

Internal low power logic delay 10.0 11.0 11.5 ns

Feedback Delays

t

F

FastCONNECT matrix feedback delay 8.0 9.5 11.0 ns

t

LF

Function Block local feedback delay 4.0 3.5 3.5 ns

Time Adders

t

PTA

3

Incremental Product Term Allocator delay 1.0 1.0 1.0 ns

t

SLEW

Slew-rate limited delay 4.0 4.5 5.0 ns

R

1

V

TEST

C

L

R

2

Device Output

Output Type V

TEST

5.0 V

3.3 V

R

1

160 Ω
260 Ω

R

2

120 Ω
360 Ω

C

L

35 pF
35 pF

X5906

V

CCIO

5.0 V

3.3 V

Figure 3: AC Load Circuit

XC95144 In-System Programmable CPLD

6 December 4, 1998 (Version 4.0)

XC95144 I/O Pins

Notes: [1] Global control pin.

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.

Function

Block

Macrocell

TQ

100PQ100PQ160

BScan

Order

Notes

Function

Block

Macrocell

TQ

100PQ100PQ160

BScan

Order

Notes

1 1 – – 25 429 3 1 – – 43 321
1 2 11 13 18 426 3 2 23 25 35 318 [1]
1 3 12 14 19 423 3 3 – – 45 315
1 4 – – 27 420 3 4 – – 48 312
1 5 13 15 21 417 3 5 24 26 36 309
1 6 14 16 22 414 3 6 25 27 37 306
1 7 – – 32 411 3 7 – – 50 303
1 8 15 17 23 408 3 8 27 29 42 300 [1]
1 9 16 18 24 405 3 9 28 30 44 297
1 10 – – 34 402 3 10 – – 52 294
1 11 17 19 26 399 3 11 29 31 47 291
1 12 18 20 28 396 3 12 30 32 49 288
1 13 – – 38 393 3 13 – – 53 285
1 14 19 21 29 390 3 14 32 34 54 282
1 15 20 22 30 387 3 15 33 35 56 279
1 16 – – 39 384 3 16 – – 55 276
1 17 22 24 33 381 [1] 3 17 34 36 57 273
1 18 – – – 378

3 18 – – – 270
2 1 – – 158 375 4 1 – – 132 267
2 2 99 1 159 372 [1] 4 2 87 89 140 264
2 3 – – 3 369 4 3 – – 147 261
2 4 – – 5 366 4 4 – – 149 258
2 5 1 3 2 363 [1] 4 5 89 91 142 255
2 6 2 4 4 360 [1] 4 6 90 92 143 252
2 7 – – 7 357 4 7 – – 150 249
2 8 3 5 6 354 [1] 4 8 91 93 144 246
2 9 4 6 8 351 [1] 4 9 92 94 145 243
2 10 – – 9 348 4 10 – – 151 240
2 11 6 8 11 345 4 11 93 95 146 237
2 12 7 9 12 342 4 12 94 96 148 234
2 13 – – 14 339 4 13 – – 153 231
2 14 8 10 13 336 4 14 95 97 152 228
2 15 9 11 15 333 4 15 96 98 154 225
2 16 – – 16 330 4 16 – – 155 222
2 17 10 12 17 327 4 17 97 99 156 219
2 18 – – – 324

4 18 – – – 216

December 4, 1998 (Version 4.0) 7

XC95144 In-System Programmable CPLD

XC95144 I/O Pins (continued)

Function

Block

Macrocell

TQ

100PQ100PQ160

BScan

Order

Notes

Function

Block

Macrocell

TQ

100PQ100PQ160

BScan

Order

Notes

5 1 – – 65 213 7 1 – – – 105
5 2 35 37 58 210 7 2 50 52 79 102
5 3 – – 66 207 7 3 – – 84 99
5 4 – – 67 204 7 4 – – 85 96
5 5 36 38 59 201 7 5 52 54 82 93
5 6 37 39 60 198 7 6 53 55 86 90
5 7 – – 74 195 7 7 – – 87 87
5 8 39 41 62 192 7 8 54 56 88 84
5 9 40 42 63 189 7 9 55 57 90 81
5 10 – – 76 186 7 10 – – 89 78
5 11 41 43 64 183 7 11 56 58 92 75
5 12 42 44 68 180 7 12 58 60 95 72
5 13 – – 78 177 7 13 – – 91 69
5 14 43 45 69 174 7 14 59 61 96 66
5 15 46 48 72 171 7 15 60 62 97 63
5 16 – – 83 168 7 16 – – 93 60
5 17 49 51 77 165 7 17 61 63 98 57
518–––162

718–––54
6 1 – – –159 8 1 – – –51
6 2 74 76 117 156 8 2 63 65 101 48
6 3 – – 119 153 8 3 – – 105 45
6 4 – – 123 150 8 4 – – 107 42
6 5 76 78 122 147 8 5 64 66 102 39
6 6 77 79 124 144 8 6 65 67 103 36
6 7 – – 125 141 8 7 – – 109 33
6 8 78 80 126 138 8 8 66 68 104 30
6 9 79 81 129 135 8 9 67 69 106 27
6 10 – – 128 132 8 10 – – 112 24
6 11 80 82 133 129 8 11 68 70 108 21
6 12 81 83 134 126 8 12 70 72 111 18
6 13 – – 130 123 8 13 – – 114 15
6 14 82 84 135 120 8 14 71 73 113 12
6 15 85 87 138 117 8 15 72 74 115 9
6 16 – – 131 114 8 16 – – 118 6
6 17 86 88 139 111 8 17 73 75 116 3
618–––108

818–––0

XC95144 In-System Programmable CPLD

8 December 4, 1998 (Version 4.0)

XC95144 Global, JTAG and Power Pins

Pin Type TQ100 PQ100 PQ160

I/O/GCK1 22 24 33
I/O/GCK2 23 25 35
I/O/GCK3 27 29 42
I/O/GTS1 3 5 6
I/O/GTS2 4 6 8
I/O/GTS3 1 3 2
I/O/GTS4 2 4 4

I/O/GSR 99 1 159

TCK485075

TDI454771
TDO 83 85 136
TMS474973

V

CCINT

5 V 5, 57, 98 7, 59, 100 10, 46, 94, 157

V

CCIO

3.3 V/5 V 26, 38, 51, 88 28, 40, 53, 90 1, 41, 61, 81, 121, 141

GND 100, 21, 31, 44, 62, 69,

75, 84

2, 23, 33, 46, 64, 71,

77, 86

20, 31, 40, 51, 70, 80,

99, 100, 110, 120, 127,

137, 160

No Connects –––

December 4, 1998 (Version 4.0) 9

XC95144 In-System Programmable CPLD

Ordering Information

Component Availability

C = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C

Revision Control

Speed Options

-1515 ns pin-to-pin delay

-1010 ns pin-to-pin delay

-7 7 ns pin-to-pin delay

Packaging Options

PQ100100-Pin Plastic Quad Flat Pack (PQFP)
TQ100100-Pin Very Thin Quad Flat Pack (TQFP)
PQ160160-Pin Plastic Quad Flat Pack (PQFP)

Temperature Options

C Commercial 0°C to 70°C
I Industrial –40°C to 85°C

XC95144 -7 PQ 160 C

Device Type

Speed

Package Type

Number of Pins

Temperature Range

Pins 100 160
Type Plastic

PQFP

Plastic

TQFP

Plastic

PQFP

Code PQ100 TQ100 PQ160

XC95144

–15 C,I C,I C,I
–10 C,I C,I C,I
–7 C C C

Date Revision

12/04/98 Update AC characteristics and internal parameters.