Datasheet X9418 Datasheet (intersil)

®

www.BDTIC.com/Intersil

X9418

Low Noise/Low Power/2-Wire Bus

Data Sheet FN8194.3October 12, 2006

Dual Digitally Controlled Potentiometers
(XDCP™)

FEATURES

• Two potentiometers in one package

• 2-wire serial interface

• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per

Potentiometer

• Power supplies
—V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V

• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications

• High reliability
—Endurance–100,000 Data Changes per Bit per

—Register Data Retention–100 years

• 8-bytes of nonvolatile memory

•2.5kΩ, 10kΩ resistor array

• Resolution: 64 taps each potentiometer

• 24-pin plastic DIP, 24-lead TSSOP and 24-lead
SOIC packages

• Pb-Free plus anneal available (RoHS compliant)

= 2.7V to 5.5V

CC

Register

DESCRIPTION

The X9418 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

SCL

SDA

A0
A1
A2
A3

V+

V-

WP

1

Interface

and

Control

Circuitry

R0 R1

R2 R3

8

Data

R0 R1

R2 R3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

Wiper

Counter
Register

(WCR)

Wiper

Counter

Register

(WCR)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Resistor

Array

XDCP1

VH0/R

VL0/R

VW0/R

VW1/R

V

H1/RH1

VL1/R

H0

L0

W0

W1

L1

X9418

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMET

ER

V

LIMITS

PART NUMBER PART MARKING

X9418WV24* X9418WV 5 ±10% 10 0 to +70 24 Ld TSSOP (4.4MM) MDP0044
X9418WV24Z* (Note) X9418WV Z 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418WP24I-2.7 X9418WP G 2.7 to 5.5 10 -40 to +85 24 Ld PDIP E24.6
X9418WS24I-2.7 X9418WS G -40 to +85 24 Ld SOIC (300MIL) M24.3
X9418WS24IZ-2.7 (Note) X9418WS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3
X9418WV24-2.7* X9418WV F 0 to +70 24 Ld TSSOP (4.4MM) MDP0044
X9418WV24Z-2.7* (Note) X9418WV ZF 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418WV24I-2.7 X9418WV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044
X9418WV24IZ-2.7 (Note) X9418WV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418YS24-2.7 X9418YS F 2.5 0 to +70 24 Ld SOIC (300MIL) M24.3
X9418YS24Z-2.7 (Note) X9418YS ZF 0 to +70 24 Ld SOIC (300MIL) (Pb-free) M24.3
X9418YS24I-2.7 X9418YS G -40 to +85 24 Ld SOIC (300MIL) M24.3
X9418YS24IZ-2.7 (Note) X9418YS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3
X9418YV24I-2.7* X9418YV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044
X9418YV24IZ-2.7* (Note) X9418YV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CC

(V)

ORGANIZATION

(kΩ)

TEMPERATU

RE RANGE

(°C) PACKAGE PKG . DWG. #

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9418.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

0

- A3)

The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9418. A maximum of 16
devices may occupy the 2-wire serial bus.

Potentiometer Pins

V

H/RH

The V

(VH0/R

H/RH

- VH1/RH1), VL/RL (VL0/R

H0

- VL1/RL1)

L0

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW

(VW0/R

- VW1/RW1)

W0

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when low prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.

2

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

PIN CONFIGURATION

DIP/SOIC

RL0/V

RH0/V

RW0/V

R

L1/VL1

RH1/V

RW1/V

R

L1/VL1

R

H1/VH1

R

W1/VW1

V

WP

SDA

V

SDA

V

SCL

CC

L0

H0

W0

A2

A1

H1

W1

SS

A1

SS

NC
NC
NC

V-

A3

1
2
3
4
5
6
7
8
9

10

11
12

1
2
3
4
5
6
7
8

9
10
11

12

X9418

TSSOP

X9418

24
23
22
21
20
19
18
17
16

5

14

13

24
23
22
21
20
19
18
17
16

15
14
13

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0 - A3 Device Address

V

H0/RH0

V

L0/RL0

V

W0/RW0

V

W1/RW1

WP

- VH1/RH1,

- VL1/R

L1

-

Potentiometer Pins
(terminal equivalent)

Potentiometer Pins
(wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

V

CC

V

SS

System Supply Voltage

System Ground

NC No Connection

V+
NC
NC
NC
A0
NC
A3
SCL
NC
NC

NC

V-

WP
A2
V

W0/RW0

VH0/R
VL0/R
V

CC

NC
NC
NC
V+
A0

NC

L0

H0

PRINCIPLES OF OPERATION

The X9418 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

). The X9418 continuously

HIGH

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

3

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

The X9418 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9418 will respond with a final acknowledge.

Array Description

The X9418 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9418
this is fixed as 0101[B].

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9418
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9418 is still busy with the write operation no ACK will
be returned. If the X9418 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

YES

NO

Issue STOP

Figure 1. Slave Address

Device Type

Identifier

100

1

A3 A2 A1 A0

Device Address

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A

- A3 inputs. The X9418 compares

0

the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9418 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

or VSS.

CC

4

Further

Operation?

YES

Issue

Instruction

Proceed

NO

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9418 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown Figure 2.

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 0 P0

Instructions

Wiper Counter

Register Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P0) select
which one of the two potentiometers is to be affected
by the instruction. Bit 1 is defined to be 0.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the wiper

WRL

counter register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the two potentiometers and one of its

associated registers; or it may occur globally, wherein
the transfer occurs between both of the
potentiometers and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9418; either between the host and
one of the Data Registers or directly between the host
and the wiper counter register. These instructions are:
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9418 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V

H/RH

terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V

terminal. A detailed

L/RL

illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

I3 I2 I1 I0 R1 R0 0 P0 A
C
K

S

C

T

K

O
P

5

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

3I2I1I0R1R0P1P0

1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter Register

pointed to by P

1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter Register

pointed to by P

Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed to by

and R1 - R

P

0

Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed to by

and R1 - R

P

0

XFR Data Register to
Wiper Counter Register

1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register pointed to

and R1 - R0 to its associated Wiper Counter

by P

0

Register

XFR Wiper Counter
Register to Data Register

Global XFR Data
Registers to Wiper
Counter Registers

Global XFR Wiper
Counter Registers to
Data Register

Increment/Decrement
Wiper Counter Register

Note: (7) 1/0 = data is one or zero

1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter Register

pointed to by P

- R

R

1

0

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed

to by R

- R0 of both pots to their respective Wiper

1

Counter Registers

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

Registers to their respective data Registers pointed
to by R

- R0 of both pots

1

0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter

Register pointed to by P

OperationI

0

0

0

0

to the Data Register pointed to by

0

0

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 A
T
A
R
T

I3 I2 I1 I0 R1 R0 0 P0 A
C
K

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 A
T
A
R
T

I3 I2 I1 I0 R0 0 P0 A
C
K

R1

0 0 D5 D4 D3 D2 D1 D0
C
K

XX

I

I

N

C
K

N

C

C

1

2

D

I

E

N

C

C

1

n

A

S

C

T

K

O
P

S

D

T

E

O

C

P

n

6

FN8194.3

October 12, 2006

Figure 6. Increment/Decrement Timing Limits

www.BDTIC.com/Intersil

INC/DEC

CMD

Issued

SCL

SDA

X9418

t

WRID

VW/R

W

Voltage Out

Figure 7. Acknowledge Response from Receiver

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

START

1

89

Acknowledge

7

FN8194.3

October 12, 2006

Figure 8. Detailed Potentiometer Block Diagram

www.BDTIC.com/Intersil

X9418

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

8 6

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

L

H

Modified SCL

DETAILED OPERATION

Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.

Wiper Counter Register

The X9418 contains two wiper counter registers, one
for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.

Serial
Bus

Input

C
o
u
n

t

e

r

D

e
c

o
d
e

UP/DN

Parallel
Bus

Input

Wiper

Counter

Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

(MSB) (LSB)

Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).

VH/R

VL/R

VW/R

H

L

W

The WCR is a volatile register; that is, its contents are
lost when the X9418 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.

8

– {D5~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

Wiper Counter Register, (6-Bit), Volatile One 6-bit wiper counter register for each XDCP. (Four

WP5 WP4 WP3 WP2 WP1 WP0

VVVVVV

(MSB) (LSB)

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

6-bit registers in total.)

– {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S

opcode

A
C

1001000

K

Write Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S
A
C

101

K

opcode

Read Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S

opcode

A
C

1011

K

Write Data Register (DR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1100

WCR

addresses

WCR

addresses

0000

DR and WCR

addresses

R1R

DR and WCR

a

R1R

0

0

ddresses

0P0 00WP

0

S
A
C

P

K

0

S
A
C

P

K

0

P
0

S
A
C
K

wiper position

(sent by slave on SDA)

00WP

5

wiper position

(sent by master on SDA)

00WP

5

wiper position/data

S

(sent by slave on SDA)

A
C

00WP

K

(sent by master on SDA)

5

wiper position/data

5

W

W

S

M

T

W

P

W

P

A

W

O

C

P

P

K

1

0

S

S

T

A

W

O

C

P

P

K

1

0

S

M

T

A

W

W

O

C

P

P

P

K

1

0

S

S

A

T

W

P

W
P

1

0

HIGH-VOLTAGE

C

O

WRITE CYCLE

K

P

W

W

P

P

P

4

3

2

W

W

P

P

P

4

3

2

W

W

W

P

P

P

4

3

2

W

W

W

P

P

P

4

3

2

XFR Data Register (DR) to Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

9

instruction

opcode

1101

DR and WCR

addresses

R1R

0

0

S

S

T

A

O

C

P

P

K

0

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

XFR Wiper Counter Register (WCR) to Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1110

DR and WCR

addresses

R1R

0

0

S

S

T

A

O

C

P

P

K

0

Increment/Decrement Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

instruction

S

opcode

A

C

0010000

K

0

WCR

addresses

P

0

increment/decrement

S

(sent by master on SDA)

A
C

I/DI/

K

D

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

0001

DR

addresses

R1R

00

0

S

S

T

A

O

C

P

K

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addre

sses

A3A2A1A

S
A
C
K

0

instruction

opcodeDRaddresses

1000

R1R

0

00

S

S

T

A
C
K

HIGH-VOLTAGE

O

WRITE CYCLE

P

HIGH-VOLTAGE

WRITE CYCLE

....

I/DI/

S

T
O
P

D

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

120

100

80

60

40

Resistance (K)

20

V

R

R

Min.
Resistance

0

20 40 60 80 100 120

0

Bus Capacitance (pF)

CC MAX

=

MIN

I

OL MIN

t

=

MAX

C

BUS

Max.
Resistance

R

=1.8kΩ

10

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address

input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

......................... -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V

, VL/RL, VW/RW ........................... V- to V+

H/RH

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Lead temperature (soldering, 10 seconds)...... +300°C

(10 seconds)..................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40

°C+85°C

Device Supply Voltage (VCC) Limits

X9418 5V ± 10%

X9418-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

End to end resistance tolerance -20 +20 %
Power rating 50 mW +25

I

W

R

V+ Voltage on V+ pin X9418 +4.5 +5.5 V

V- Voltage on V- pin X9418 -5.5 -4.5 V

V

TERM

C

H/CL/CW

I

AL

Wiper current -3 +3 mA
Wiper resistance 150 250 Ω Wiper current = ± 1mA, V+, V- = ±3V

W

40 100 Ω Wiper current = ± 1mA, V+, V- = ±5V

X9418-2.7 +2.7 +5.5

X9418-2.7 -5.5 -2.7

Voltage on any VH/RH, VL/RL or
V

W/RW

Noise -120 dBV Ref: 1kHz
Resolution
Absolute linearity
Relative linearity
Temperature Coefficient of R
Ratiometric Temperature Coefficient ±20 ppm/°C See Note 4
Potentiometer Capacitances 10/10/25 pF See Circuit #3,

RH, RL, RW Leakage Current 0.1 10 µA VIN = V- to V+. Device is in Stand-by

(4)

(1)

(2)

TOTAL

V- V+ V

1.6 % See Note 4

-1 +1 MI

-0.2 +0.2 MI
±300 ppm/°C See Note 4

(3)

V

(3)

w(n)(actual)

V

w(n + 1 - [Vw(n) + MI

Spice Macromodel

mode.

Test ConditionsMin. Typ. Max. Unit

°C, each pot

- V

w(n)(expected)

(4)

(4)

]

11

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

VCC supply current
(nonvolatile write)

VCC supply current
(move wiper, write, read)

1mAf

Other Inputs = V

100 µA f

Other Inputs = V

VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC + 0.5 V

Input LOW voltage -0.5 VCC x 0.1 V

Output LOW voltage 0.4 V IOL = 3mA

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

- RL)/63, single pot

H

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SCL

SS

= 400kHz, SDA = Open,

SCL

SS

CC

= VSS to V

OUT

CC

SS

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 Years

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(4)

C

I/O

(4)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Typ. Max. Unit

(5)

t

PUR

t

PUW

t

RVCC

(5)

(6)

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC Power up ramp rate 0.2 50 V/msec

Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V
and R

. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate

W

specification should be met, and any glitches or slope changes in the V

powers down, it should be held below 0.1V for more than 1 second before powering up again in order for

If V

CC

proper wiper register recall. Also, V
be complete until V

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

(6) This is a tested or guaranteed parameter and should only be used as a guidance.

and t

PUR

instruction can be issued. These parameters are periodically sampled and not 100% tested.

, V+ and V- reach their final value.

CC

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific

PUW

should not reverse polarity by more than 0.5V. Recall of wiper position will not

CC

, then V+ and V-, and then the potentiometer pins, RH, RL,

CC

line should be held to <100mV if possible.

CC

12

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

CC

x 0.5

Circuit #3 SPICE Macro Model

R

R

H

TOTAL

C

H

C

C

L

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

5V

1533Ω

SDA Output

100pF

25pF

R

W

AC TIMING (over recommended operating conditions)

Symbol Parameter Min. Max. Unit

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock frequency 400 kHz

Clock cycle time 2500 ns

Clock high time 600 ns

Clock low time 1300 ns

Start setup time 600 ns

Start hold time 600 ns

Stop setup time 600 ns

SDA data input setup time 100 ns

SDA data input hold time 30 ns

SCL and SDA rise time 300 ns

SCL and SDA fall time 300 ns

SCL low to SDA data output valid time 900 ns

SDA data output hold time 50 ns

Noise suppression time constant at SCL and SDA inputs 50 ns

Bus free time (prior to any transmission) 1300 ns

WP, A0, A1, A2 and A3 setup time 0 ns

WP, A0, A1, A2 and A3 hold time 0 ns

R

L

13

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

g

SCL

SDA

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs

(START) (STOP)

t

F

t

SU:STO

t

F

t

SU:STA

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

14

FN8194.3

October 12, 2006

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9418

(STOP)

SDA

V

W/RW

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address Inc/Dec Inc/Dec

V

W/RW

SDA

Write Protect and Device Address Pins Timing

LSB

t

WRL

t

WRID

SCL

SDA

WP

A0, A1

A2, A3

15

(START) (STOP)

...

(Any Instruction)

...

...

t

SU:WPA

t

HD:WPA

FN8194.3

October 12, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

X9418

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS

V

S

10kΩ

R

R

1

100kΩ

-12V+12V

+

–

R

1

S

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

317

I

adj

R

2

–

+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

16

FN8194.3

October 12, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

S

}

VO = G V
G = - R2/R

4

All RS = 10kΩ

S

2

}

S

1

–

+

–

+

X9418

C

V

R

2

V

O

V

O

S

R

= 1 + R2/R

G

O

fc = 1/(2πRC)

C

1

V

S

Z

IN

+

–

R

R

1

1

R

2

+

–

R

1

R

3

V

O

2

17

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

FUNCTION GENERATOR

R

–

+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

R

1

, R

A

B

+ R3) >> R

1

C

–

+

2

FN8194.3

October 12, 2006

Dual-In-Line Plastic Packages (PDIP)

www.BDTIC.com/Intersil

X9418

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic­ular to datum .

7. e
e

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

12 3 N/2

-A-

D1

B1

B

e

A

and eC are measured at the lead tips with the leads unconstrained.

B

must be zero or greater.

C

D

e

0.010 (0.25) C AM BS

-C-

E24.6 (JEDEC MS-011-AA ISSUE B)

24 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4

A1 0.015 - 0.39 - 4

A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.150 1.290 29.3 32.7 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

L 0.115 0.200 2.93 5.08 4

N24 249

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

NOTESMIN MAX MIN MAX

Rev. 0 12/93

18

FN8194.3

October 12, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9418

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

E

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

h x 45

o

C

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9

C 0.0091 0.0125 0.23 0.32 -

D 0.5985 0.6141 15.20 15.60 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N24 247

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

19

FN8194.3

October 12, 2006

X9418

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

E

C

SEATING
PLANE

N LEADS

0.25 CAB

M

N

E1

1

B

e

0.10 C

TOP VIEW

b

SIDE VIEW

SEE DETAIL “X”

(N/2)+1

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8194.3

October 12, 2006