The X9401 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
V
V
HOLD
CS
SCK
SO
SI
A0
A1
WP
CC
SS
Interface
and
Control
Circuitry
Data
Pot 0
R0 R1
R2 R3
8
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH0/R
VL0/R
VW0/R
VW1/R
V
H1/RH1
VL1/R
L0
W0
W1
L1
H0
R0 R1
R2 R3
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
Resistor
Array
Pot 3
V
H2/RH2
VL2/R
VW2/R
VW3/R
V
H3/RH3
VL3/R
L2
W2
W3
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Page 2
X9401
www.BDTIC.com/Intersil
Ordering Information
V
PART
PART NUMBER
X9401WS24IZ (Note)X9401WS ZI5 ±10%10-40 to 8524 Ld SOIC (300 mil) (Pb-free)MDP0027
X9401WS24I-2.7*X9401WS G2.7 to 5.510-40 to 8524 Ld SOIC (300 mil)M24.3
X9401WS24IZ-2.7* (Note) X9401WS ZG-40 to 8524 Ld SOIC (300 mil) (Pb-free)MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
MARKING
CC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION (kΩ)
TEMP
RANGE (°C)PACKAGE
PKG. DWG.
#
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
Chip Select (CS
When CS
is HIGH, the X9401 is deselected and the
)
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
LOW enables the X9401, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is
required prior to the start of any operation.
Device Address (A
0
- A1)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9401. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
(V
V
H
R
L(RL0
The V
- VH3), VL (V
H0
- RL3)
and VL/RL inputs are equivalent to the
H/RH
- VL3), RH (R
L0
H0
- RH3),
terminal connections on either end of a mechanical potentiometer.
(VW0 - VW3), RW(R
V
W
W0
- RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP
The WP
pin when LOW prevents nonvolatile writes to
)
the Wiper Counter Registers.
Hold (HOLD
HOLD
)
is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD
may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD
while SCK is LOW. To resume communication, HOLD
must be brought LOW
is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD
should be held HIGH at all
times.
2
FN8190.3
October 12, 2006
Page 3
X9401
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PIN CONFIGURATION
SOIC
13
24
23
22
21
20
19
18
17
16
15
14
NC
V
L3/RL3
VH3/R
VW3/R
A
0
SO
HOLD
SCK
V
L2/RL2
VH2/R
VW2/R
NC
H3
W3
H2
W2
VL0/R
VH0/R
VW0/R
VL1/R
VH1/R
VW1/R
V
V
CC
L0
H0
W0
CS
WP
SI
A
L1
H1
W1
SS
1
2
3
4
5
6
X9401
7
8
1
9
10
11
12
PIN NAMES
SymbolDescription
SCKSerial Clock
SI, SOSerial Data
A
- A
0
V
H0/RH0
V
L0/RL0
V
W0/RW0
1
- VH3/RH3,
- VL3/R
- VW1/R
L3
Device Address
Potentiometers (terminal
equivalent)
Potentiometers (wiper
W1
equivalent)
WP
V
CC
V
SS
Hardware Write Protection
System Supply Voltage
System Ground
NCNo Connection
DEVICE DESCRIPTION
The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS
and the HOLD
and WP pins must be HIGH during the
must be LOW
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
and VL/RL inputs).
H/RH
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
) output. Within each individual array only one
W/RW
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data
registers via the XFR Data Register or Global XFR
Data Register instructions (parallel load); it can be
modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents
of its data register zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powereddown. Although the register is automatically loaded
with the value in R
upon power-up, this may be differ-
0
ent from the value present at power-down. The wiper
position must be stored in R
to insure restoring the
0
wiper position after power-up.
Data Registers
Each potentiometer has four 6-bit nonvolatile data registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.
3
FN8190.3
October 12, 2006
Page 4
X9401
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Data Register Detail
(MSB)(LSB)
D5D4D3D2D1D0
NVNVNVNVNVNV
Write in Process
The contents of the Data Registers are saved to nonvolatile memory when the CS
pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
- A1 input
0
pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A
- A1 inputs
0
can be actively driven by CMOS input signals or tied to
or VSS.
V
CC
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
100
1
00A1A0
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruction and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I1I2I3I0R1R0P1P0
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R
and R0) select
1
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P
) selects which one of the four potenti-
0
ometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register
—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register
—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t
. A transfer from
WRL
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
to complete. The transfer can occur between one
t
WR
of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9401; either between the host and
4
FN8190.3
October 12, 2006
Page 5
X9401
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one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
– Read Wiper Counter Register
— read the current
wiper position of the selected pot,
– Write Wiper Counter Register
—change current
wiper position of the selected pot,
– Read Data Register
—read the contents of the
selected data register;
– Write Data Register
—write a new value to the
selected data register.
– Read Status
—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0Register 1
86
Register 2Register 3
If WCR = 00[H] then VW/RW = VL/R
If WCR = 3F[H] then VW/RW = VH/R
L
H
Modified SCL
The sequence of these operations is shown in Figure 4
and Figure 5.
The final command is Increment/Decrement. It is different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse
) while SI is HIGH, the selected wiper will move
(t
HIGH
one resistor segment towards the V
H/RH
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V
terminal. A detailed illustration of the
L/RL
sequence and timing for this operation are shown in
Figure 6 and Figure 7.
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
UP/DN
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
INC/DEC
Logic
UP/DN
CLK
terminal.
VH/R
H
VL/R
L
5
VW/R
W
FN8190.3
October 12, 2006
Page 6
Figure 3. Two-Byte Command Sequence
www.BDTIC.com/Intersil
CS
SCK
SI
010100A1A0 I3I2I1 I0R1 R0 P1 P0
Figure 4. Three-Byte Command Sequence (Write)
CS
SCL
SI
X9401
0101A1 A0I3 I2I1 I0 R1 R0 P1 P0
00
Figure 5. Three-Byte Command Sequence (Read)
CS
SCL
SI
0101A1 A0I3 I2I1 I0 R1 R0 P1 P0
S0
00
Figure 6. Increment/Decrement Command Sequence
CS
SCK
00D5 D4 D3 D2 D1 D0
Don’t Care
00D5 D4 D3 D2 D1 D0
SI
010100A1A0I3 I2I1 I00
0
P1
6
P0
I
I
N
N
C
C
1
2
D
I
E
N
C
C
1
n
D
E
C
n
FN8190.3
October 12, 2006
Page 7
Figure 7. Increment/Decrement Timing Limits
www.BDTIC.com/Intersil
SCK
SI
X9401
t
WRID
VW/R
W
INC/DEC CMD Issued
Voltage Out
Table 1. Instruction Set
Instruction Set
Instruction
3I2I1I0R1R0P1P0
OperationI
Read Wiper Counter Register 100100P1P0Read the contents of the Wiper Counter Register
pointed to by P
- P
1
0
Write Wiper Counter Register101000P1P0Write new value to the Wiper Counter Register
pointed to by P
- P
1
0
Read Data Register1011R1R0P1P0Read the contents of the Data Register pointed to by
- P0 and R1 - R
P
1
0
Write Data Register1100R1R0P1P0Write new value to the Data Register pointed to by
- P0 and R1 - R
P
XFR Data Register to Wiper
Counter Register
XFR Wiper Counter Register
to Data Register
Global XFR Data Register to
Wiper Counter Register
1
1101R1R0P1P0Transfer the contents of the Data Register pointed to
- R0 to the Wiper Counter Register pointed to by
by R
1
- P
P
1
0
1110R1R0P1P0Transfer the contents of the Wiper Counter Register
pointed to by P
- R
R
1
0
0001R1R000Transfer the contents of the Data Registers pointed to
- R0 of all four pots to their respective Wiper
by R
1
0
- P0 to the Register pointed to by
1
Counter Register
Global XFR Wiper Counter
Register to Data Register
Increment/Decrement Wiper
Counter Register
1000R
1R0
00100 0P
00Transfer the contents of all Wiper Counter Registers
to their respective data Registers pointed to by
- R0 of all four pots
R
1
1P0
Enable Increment/decrement of the Wiper Counter
Register pointed to by P
- P
1
0
Read Status (WIP bit)01010001Read the status of the internal write cycle, by
checking the WIP bit.
7
FN8190.3
October 12, 2006
Page 8
X9401
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Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
100100
0
Write Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
101000
0
Read Data Register (DR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
1011
0
Write Data Register (DR)
WCR
addresses
P1P
WCR
addresses
P1P
DR and WCR
addresses
R1R0P1P
wiper position
(sent by X9401 on SO)
W
00WP
0
(sent by Host on SI)
00WP
0
(sent by X9401 on SO)
00WP
0
P
5
4
Data Byte
W
P
5
4
Data Byte
W
P
5
4
W
W
P
3
P
3
W
P
3
W
W
W
CS
Rising
W
W
P
P
2
1
W
P
P
2
1
W
P
P
2
Edge
P
0
CS
Rising
W
Edge
P
0
CS
Rising
W
Edge
P
1
0
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
1100
0
DR and WCR
addresses
R1R0P1P
(sent by host on SI)
00WP
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
1101
0
DR and WCR
addresses
R1R0P1P
CS
Rising
Edge
0
Data Byte
W
P
5
CS
W
P
1
W
P
0
Rising
Edge
W
W
P
P
4
3
2
HIGH-VOLTAGE
WRITE CYCLE
8
FN8190.3
October 12, 2006
Page 9
X9401
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
1110
0
DR and WCR
addresses
R1R0P1P
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
0010XX
0
WCR
addresses
P1P0I/DI/
increment/decrement
(sent by master on SDA)
....
D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcode
0001
0
DR
addresses
R1R
0
00
CS
Rising
Edge
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
device type
identifier
010100
device
addresses
A1A
instruction
opcodeDRaddresses
1000
0
R1R
0
00
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
I/DI/
D
CS
Rising
Edge
Read Status
device type
CS
Falling
Edge
identifier
010100
device
addresses
A1A
instruction
opcode
010100010000000WI
0
wiper
addresses
Data Byte
(sent by X9401 on SO)
CS
Rising
Edge
P
9
FN8190.3
October 12, 2006
Page 10
X9401
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Lead temperature (soldering, 10s) .................. +300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
TempMin.Max.
Commercial0°C+70°C
Industrial-40°C+85°C
DeviceSupply Voltage (VCC) Limits
X94015V ± 10%
X9401-2.72.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
SymbolParameter
R
TOTAL
I
W
R
W
V
TERM
C
H/CL/CW
I
AL
End to end resistance–20+20%
Power rating50mW+25°C, each pot
Wiper current–6+6mA
Wiper resistance150500ΩWiper Current = ± 3mA
Voltage on any VH or VL PinV
Noise-120dBVRef: 1kHz
Resolution
Absolute linearity
Relative linearity
Temperature coefficient of R
Ratiometric temp. coefficient±20ppm/°C
Potentiometer capacitances10/10/25pFSee Macro model
RH, RL, RW leakage current0.110µAVIN = VSS to VCC. Device is in
(1)
(2)
TOTAL
SS
1.6%
-1+1MI
-0.2+0.2MI
±300ppm/°C
V
CC
VVSS = 0V
(3)
(3)
Test ConditionMin.Typ.Max.Unit
V
w(n)(actual)
V
w(n + 1)
stand-by mode.
- [V
- V
w(n)(expected)
w(n) + MI
]
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V
tiometer pins provided that V
The V
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
power-up spec is always in effect.
CC
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V
is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW.
VCC current (standby)1µASCK = SI = VSS, Addr. = VSS,
Input leakage current10µAVIN = VSS to V
Output leakage current10µAV
Input HIGH voltageVCC x 0.7VCC + 0.5V
Input LOW voltage-0.5VCC x 0.1V
Output LOW voltage0.4VIOL = 3mA
ENDURANCE AND DATA RETENTION
ParameterMin.Unit
Minimum endurance100,000Data changes per bit per register
Data retention100years
SCK
Other Inputs = V
1mAf
SCK
Other Inputs = V
CS = V
OUT
Test ConditionsMin.Typ.Max.Unit
= 2MHz, SO = Open,
SS
= 2MHz, SO = Open,
SS
CC
CC
= VSS to V
CC
CAPACITANCE
SymbolTestMax.UnitTest Condition
(4)
C
OUT
C
IN
(4)
Output capacitance (SO)8pFV
OUT
Input capacitance (A0, A1, SI, and SCK)6pFVIN = 0V
POWER-UP TIMING
SymbolParameter Min.Max.Unit
(6)
tr V
CC
(5)
t
PUR
(5)
t
PUW
A.C. TEST CONDITIONS
Input pulse levelsV
Input rise and fall times10ns
Input and output timing levelV
Notes: (4) This parameter is periodically sampled and not 100%
tested
(5) t
PUR
the (last) power supply (V
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is not a tested or guaranteed parameter and should
be used only as a guideline.
VCC Power-up rate0.250V/ms
Power-up to initiation of read operation1ms
Power-up to initiation of write operation5ms
EQUIVALENT A.C. LOAD CIRCUIT
x 0.1 to VCC x 0.9
and t
CC
x 0.5
CC
are the delays required from the time
PUW
-) is stable until the specific
CC
5V
1533Ω
SDA
Output
100pF
SPICE Macro Model
R
H
C
L
10pF
R
TOTAL
R
C
25pF
W
W
= 0V
C
10pF
R
L
L
11
FN8190.3
October 12, 2006
Page 12
X9401
www.BDTIC.com/Intersil
AC TIMING
SymbolParameterMin.Max.Unit
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
V
t
HO
t
RO
t
FO
t
HOLD
t
HSU
t
HH
t
HZ
t
LZ
T
I
t
CS
t
WPASU
t
WPAH
SSI/SPI clock frequency2.0MHz
SSI/SPI clock cycle rime500ns
SSI/SPI clock high rime200ns
SSI/SPI clock low time200ns
Lead time250ns
Lag time250ns
SI, SCK, HOLD and CS input setup time50ns
SI, SCK, HOLD and CS input hold time50ns
SI, SCK, HOLD and CS input rise time2µs
SI, SCK, HOLD and CS input fall time2µs
SO output disable time0500ns
SO output valid time100ns
SO output hold time0ns
SO output rise time50ns
SO output fall time50ns
HOLD time400ns
HOLD setup time100ns
HOLD hold time100ns
HOLD low to output in high Z100ns
HOLD high to output in low Z100ns
Noise suppression time constant at SI, SCK, HOLD and CS inputs20ns
CS deselect time2µs
WP, A0 and A1 setup time0ns
WP, A0 and A1 hold time0ns
HIGH-VOLTAGE WRITE CYCLE TIMING
SymbolParameterTyp.Max.Unit
t
WR
High-voltage write cycle time (store instructions)510ms
XDCP TIMING
SymbolParameterMin.Max.Unit
t
WRPO
t
WRL
t
WRID
Wiper response time after the third (last) power supply is stable10µs
Wiper response time after instruction issued (all load instructions)10µs
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)450ns
12
October 12, 2006
FN8190.3
Page 13
SYMBOL TABLE
www.BDTIC.com/Intersil
WAVEFORMINPUTSOUTPUTS
X9401
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/ACenter Line
TIMING DIAGRAMS
Input Timing
CS
SCK
t
SU
SI
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
is High
Impedance
t
LEAD
t
H
MSBLSB
t
WL
t
CYC
t
WH
...
...
t
FI
t
CS
t
LAG
t
RI
SO
Output Timing
CS
SCK
SO
SI
High Impedance
ADDR
t
V
MSBLSB
t
HO
...
...
t
DIS
13
FN8190.3
October 12, 2006
Page 14
Hold Timing
www.BDTIC.com/Intersil
CS
SCK
t
RO
SO
SI
HOLD
XDCP Timing (for All Load Instructions)
CS
t
HSU
t
FO
t
t
HOLD
HZ
X9401
t
HH
...
t
LZ
SCK
MSBLSB
VW/R
SI
W
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
V
W/RW
ADDR
SI
Inc/Dec
Inc/Dec
...
t
WRID
...
...
...
...
t
WRL
High Impedance
SO
14
FN8190.3
October 12, 2006
Page 15
Write Protect and Device Address Pins Timing
www.BDTIC.com/Intersil
X9401
CS
t
WP
A0
A1
WPASU
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
V
R
VW/R
W
Three terminal Potentiometer;
Variable voltage divider
(Any Instruction)
t
WPAH
+V
R
I
Two terminal Variable Resistor;
Variable current
15
FN8190.3
October 12, 2006
Page 16
Application Circuits
www.BDTIC.com/Intersil
NONINVERTING AMPLIFIERVOLTAGE REGULATOR
X9401
V
S
VO = (1+R2/R1)V
OFFSET VOLTAGE ADJUSTMENTCOMPARATOR WITH HYSTERESIS
V
S
10kΩ
10kΩ
R
100kΩ
R
1
+
–
1
10kΩ
S
–
+
R
2
R
2
TL072
V
O
V
O
IN
VO (REG) = 1.25V (1+R2/R1)+I
V
S
VUL = {R1/(R1+R2)} VO(max)
V
= {R1/(R1+R2)} VO(min)
LL
317
I
adj
R
2
–
+
}
}
R
R
2
1
R
1
adj R2
VO (REG)V
V
O
V
+5V
S
ATTENUATORFILTER
V
S
R
1
R
3
R
4
VO = G V
-1/2 ≤ G ≤ +1/2
S
R
2
–
+
All RS = 10kΩ
V
O
C
R
G
= 1 + R2/R
O
fc = 1/(2πRC)
+
–
R
R
1
1
V
O
2
16
FN8190.3
October 12, 2006
Page 17
Application Circuits (continued)
www.BDTIC.com/Intersil
INVERTING AMPLIFIEREQUIVALENT L-R CIRCUIT
R
R
V
S
1
}
VO = G V
G = - R2/R
2
}
–
+
S
1
X9401
V
O
FUNCTION GENERATOR
R
C
1
V
S
Z
IN
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R
R
R
+ R3) >> R
1
2
+
–
1
3
2
C
R
–
+
R
}
A
R
}
B
frequency ∝ R1, R2, C
amplitude ∝ R
2
, R
A
R
1
–
+
B
17
FN8190.3
October 12, 2006
Page 18
Small Outline Plastic Packages (SOIC)
www.BDTIC.com/Intersil
X9401
N
INDEX
AREA
123
-A-
E
-B-
SEATING PLANE
D
A
-C-
0.25(0.010)BMM
H
L
h x 45°
α
e
B
0.25(0.010)C AMBS
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)TOLERANCENOTES
A
0.010
Rev. L 2/01
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subs idi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN8190.3
October 12, 2006
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