Datasheet X9400 Datasheet (intersil)

®

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X9400

Low Noise/Low Power/SPI Bus

Data Sheet FN8189.3July 28, 2006

Quad Digitally Controlled Potentiometers
(XDCP™)

FEATURES

• Four potentiometers per package

• 64 resistor taps

• SPI serial interface for write, read, and transfer
operations of the potentiometer

• Wiper resistance, 40Ω typical at 5V.

• Four non-volatile data registers for each
potentiometer

• Non-volatile storage of multiple wiper position

• Power-on recall. Loads saved wiper position on
power-up.

• Standby current < 1µA max

•System V

•Analog V

•10kΩ, 2.5kΩ end to end resistance

• 100 yr. data retention

• Endurance: 100,000 data changes per bit per
register

• Low power CMOS

• 24 Ld SOIC and 24 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

: 2.7V to 5.5V operation

CC

+/V–

: -5V to +5V

DESCRIPTION

The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

V+

V-

HOLD

CS

SCK

WP

SO

SI
A0
A1

Interface

and

Control

Circuitry

Data

Pot 0

R0 R1

R2 R3

8

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter

Register

(WCR)

Resistor

Array
Pot 1

VH0/R

VL0/R

VW0/R

VW1/R

V

H1/RH1

VL1/R

L0

W0

W1

L1

H0

R0 R1

R2 R3

R0 R1

R2 R3

Wiper
Counter
Register

(WCR)

Wiper
Counter
Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array
Pot 3

V

H2/RH2

VL2/R

VW2/R

VW3/R

V

H3/RH3

VL3/R

L2

W2

W3

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

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X9400

POTENTIOMETER

PART

PART NUMBER

X9400WS24* X9400WS 5 ±10% 10 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400WS24ZT1

(Note)
X9400WS24I* X9400WS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400WS24IZ*

(Note)
X9400WV24* X9400WV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24I* X9400WV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24IZ*

(Note)
X9400WV24Z*

(Note)
X9400YS24* X9400YS 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400YS24I* X9400YS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400YV24* X9400YV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24I* X9400YV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24IZ*

(Note)
X9400YV24Z*

(Note)
X9400WS24-2.7* X9400WS F 2.7 to 5.5 10 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400WS24I-2.7* X9400WS G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400WS24IZ-2.7*

(Note)
X9400WV24-2.7* X9400WV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24I-2.7* X9400WV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24IZ-2.7*

(Note)
X9400WV24Z-2.7*

(Note)
X9400YS24-2.7* X9400YS F 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400YS24I-2.7* X9400YS G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400YV24-2.7* X9400YV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24I-2.7* X9400YV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24IZ-2.7*

(Note)
X9400YV24Z-2.7*

(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

X9400WS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free)

X9400WS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WS ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9400YV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

V

CC

LIMITS

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE

(°C) PACKAGE PKG. DWG. #

M24.3

Tape and Reel

2

FN8189.3

July 28, 2006

X9400

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PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the
X9400.

Chip Select (CS

When CS

is HIGH, the X9400 is deselected and the

)

SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS

LOW enables the X9400, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS

is

required prior to the start of any operation.

Hold (HOLD

HOLD

)

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD

may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD

must

be brought LOW while SCK is LOW. To resume
communication, HOLD

is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

Device Address (A

0

- A1)

The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9400. A maximum of 4 devices may occupy the
SPI serial bus.

Potentiometer Pins

V

H/RH

V

L3/RL3

The V

(VH0/R

)

H/RH

- VH3/RH3), VL/RL (VL0/R

H0

L0

-

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW

(VW0/R

- VW3/RW3)

W0

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP

The WP

pin when LOW prevents nonvolatile writes to

)

the Data Registers.

Analog Supplies (V+, V-)

The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.

PIN CONFIGURATION

V

CC

VL0/R

L0

VH0/R

H0

VW0/R

W0

CS

WP

SI

A

1

VL1/R

L1

VH1/R

H1

VW1/R

W1

V

SS

10

1

2

3

4

5

6

7

8

9

11

12

SOIC

X9400

3

13

24

23

22

21

20

19

18

17

16

15

14

V+

V

L3/RL3

VH3/R

VW3/R

A

0

SO

HOLD

SCK

V

L2/RL2

VH2/R

VW2/R

V-

H3

H2

W3

W2

VL1/R

VH1/R

VW1/R

VW2/R

VH2/R

V

L2/RL2

HOLD

A

H1

W1

V

SS

W2

H2

SCK

L1

V-

TSSOP

13

24

23

22

21

20

19

18

17

16

15

14

WP

CS

VW0/R

V

H0/RH0

VL0/R

V

CC

V+

V

L3/RL3

VH3/R

VW3/R

A

0

SO

L0

H3

W0

W3

FN8189.3

July 28, 2006

SI

1

2

1

3

4

5

6

X9400

7

8

9

10

11

12

X9400

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PIN NAMES

Symbol Description

SCK Serial Clock

SI, SO Serial Data

A

- A

0

1

V

H0/RH0

V

L0/RL0

V

W0/RW0

WP

V

CC

V

SS

NC No Connection

- VH3/RH3,

- VL3/R

L3

- VW1/R

Device Address

Potentiometer Pins (terminal
equivalent)

Potentiometer Pins (wiper

W1

equivalent)

Hardware Write Protection

System Supply Voltage

System Ground

DEVICE DESCRIPTION

The X9400 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

Wiper Counter Register (WCR)

The X9400 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of sixty-four
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
global XFR data register instructions (parallel load); it
can be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9400 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.

Data Registers

Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and VL/RL inputs).

H/RH

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

W/RW

switch may be turned on at a time.

These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Data Register Detail

(MSB) (LSB)

D5 D4 D3 D2 D1 D0

NV NV NV NV NV NV

4

FN8189.3

July 28, 2006

Figure 1. Detailed Potentiometer Block Diagram

www.BDTIC.com/Intersil

(One of Four Arrays)

X9400

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = 3F[H] then VW/RW = VH/R

Serial
Bus

Input

8 6

L

H

UP/DN

Modified SCL

Parallel
Bus

Input

Wiper
Counter
Register

(WCR)

INC/DEC

Logic

UP/DN

CLK

C
o

u
n

t

e

r

D

e
c

o
d
e

VH/R

VL/R

VW/R

H

L

W

Write in Process

The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9400 from the host,
following a CS

going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9400 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

- A1 input

0

pins. The X9400 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9400 to successfully

continue the command sequence. The A

- A1 inputs

0

can be actively driven by CMOS input signals or tied to

or VSS.

V

CC

The remaining two bits in the slave byte must be set to 0.

Figure 2. Identification Byte Format

Device Type

Identifier

100

1

0 0 A1 A0

Device Address

Instruction Byte

The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.

5

FN8189.3

July 28, 2006

X9400

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Figure 3. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

The four high order bits of the instruction byte specify
the operation. The next two bits (R
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P
potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:

– XFR Data Register to Wiper Counter Register

– XFR Wiper Counter Register to Data Register

– Global XFR Data Register to Wiper Counter Register

– Global XFR Wiper Counter Register to Data Register

The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register.

and P0) selects which one of the four

1

transfers the contents of one specified Data Register
to the associated Wiper Counter Register.

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.

—This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.

to complete. The transfer can occur

WR

Pot Select

and R0) select

1

—This

—

. A transfer

WRL

Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

– Read Wiper Counter Register

wiper position of the selected pot,

– Write Wiper Counter Register

wiper position of the selected pot,

– Read Data Register

selected data register;

– Write Data Register

selected data register.

– Read Status

of the WIP bit which indicates if the internal write
cycle is in progress.

The sequence of these operations is shown in Figure 5
and Figure 6.

The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse

) while SI is HIGH, the selected wiper will move

(t

HIGH

one resistor segment towards the V
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the V

L/RL

sequence and timing for this operation are shown in
Figure 7 and Figure 8.

—This command returns the contents

terminal. A detailed illustration of the

—read the contents of the

—write a new value to the

—read the current

—change current

terminal.

H/RH

6

FN8189.3

July 28, 2006

Figure 4. Two-Byte Instruction Sequence

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CS

SCK

SI

010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0

Figure 5. Three-Byte Instruction Sequence (Write)

CS

SCK

SI

X9400

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

00

Figure 6. Three-Byte Instruction Sequence (Read)

CS

SCK

SI

0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0

S0

00

Figure 7. Increment/Decrement Instruction Sequence

CS

SCK

SI

0 0 D5 D4 D3 D2 D1 D0

Don’t Care

0 0 D5 D4 D3 D2 D1 D0

010100A1A0 I3 I2 I1 I0 0

0

P1

7

P0

I

I

N

N

C

C

1

2

D

I

E

N

C

C

1

n

D
E
C

n

FN8189.3

July 28, 2006

Figure 8. Increment/Decrement Timing Limits

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SCK

SI

X9400

t

WRID

VW/R

W

INC/DEC CMD Issued

Voltage Out

Table 1. Instruction Set

Instruction Set

Instruction

3I2I1I0R1R0P1P0

OperationI

Read Wiper Counter Register 1 0 0 1 0 0 P1P0Read the contents of the Wiper Counter Register

pointed to by P

- P

1

0

Write Wiper Counter Register 1 0 1 0 0 0 P1P0Write new value to the Wiper Counter Register

pointed to by P

- P

1

0

Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to

- P0 and R1 - R

by P

1

0

Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to by

- P0 and R1 - R

P

XFR Data Register to Wiper
Counter Register

XFR Wiper Counter Register
to Data Register

Global XFR Data Register to
Wiper Counter Register

1

1101R1R0P1P0Transfer the contents of the Data Register pointed to

- R0 to the Wiper Counter Register pointed to by

by R

1

- P

P

1

0

1110R1R0P1P0Transfer the contents of the Wiper Counter

Register pointed to by P
pointed to by R

0001R1R00 0 Transfer the contents of the Data Registers pointed

to by R

- R0 of all four pots to their respective Wiper

1

0

- P0 to the Register

1

- R

1

0

Counter Register

Global XFR Wiper Counter
Register to Data Register

Increment/Decrement Wiper
Counter Register

1000R

1R0

001000P

0 0 Transfer the contents of all Wiper Counter

Registers to their respective data Registers

- R0 of all four pots

1

- P

1

0

1P0

pointed to by R
Enable Increment/decrement of the Wiper Counter

Register pointed to by P

Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by

checking the WIP bit.

8

FN8189.3

July 28, 2006

X9400

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Instruction Format

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register (WCR)

device type

CS

Falling

Edge

identifier

010100

Write Wiper Counter Register (WCR)

device type

identifier

CS

Falling

Edge

010100

Read Data Register (DR)

device type

identifier

CS

Falling

Edge

010100

device

addresses

A1A

device

addresses

A1A

device

addresses

A1A

instruction

opcode

100100

0

instruction

opcode

101000

0

instruction

opcode

1011

0

WCR

addresses

P1P

WCR

addresses

P1P

DR and WCR

addresses

R1R0P1P

(sent by X9400 on SO)

00WP

0

00WP

0

(sent by X9400 on SO)

00WP

0

wiper position

W

W

W

W

P

P

P

P

5

4

3

2

1

Data Byte

(sent by Host on SI)

W

W

W

W

P

P

P

P

5

4

3

2

1

Data Byte

W

W

W

W

P

P

P

P

5

4

3

2

1

W

P
0

W

P
0

W

P
0

CS

Rising

Edge

CS

Rising

Edge

CS

Rising

Edge

Write Data Register (DR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1100

0

DR and WCR

addresses

R1R0P1P

(sent by host on SI)

00WP

0

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1101

0

DR and WCR

addresses

R1R0P1P

CS

Rising

Edge

0

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

device type

identifier

010100

device

addresses

A1A

instruction

opcode

1110

0

DR and WCR

addresses

R1R0P1P

CS

Rising

Edge

0

Data Byte

W

W

P

P

5

4

3

HIGH-VOLTAGE

WRITE CYCLE

W
P

CS

Rising

W

W

Edge

P

P

2

1

0

HIGH-VOLTAGE

WRITE CYCLE

9

FN8189.3

July 28, 2006

X9400

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Increment/Decrement Wiper Counter Register (WCR)

device type

CS

Falling

Edge

identifier

010100

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

device type

CS

Falling

Edge

identifier

010100

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

device type

CS

Falling

Edge

identifier

010100

Read Status

device type

CS

Falling

Edge

identifier

010100

device

addresses

A1A

device

addresses

A1A

device

addresses

A1A

device

addresses

A1A

instruction

opcode

0010XX

0

instruction

opcode

0001

0

instruction

opcodeDRaddresses

1000

0

instruction

opcode

010100010000000WI

0

WCR

addresses

DR

addresses

R1R

0

R1R

00

0

wiper

addresses

increment/decrement

(sent by master on SDA)

P1P0I/DI/

Rising

00

CS

Rising

Edge

(sent by X9400 on SO)

....

D

CS

Edge

HIGH-VOLTAGE

WRITE CYCLE

Data Byte

I/DI/

P

Rising

D

CS

Rising

Edge

CS

Edge

10

FN8189.3

July 28, 2006

X9400

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SCK, SCL or any address

input with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

......................... -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V
Any V

.................................................................... V+

H

...................................................................... V-

L

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Lead temperature (soldering, 10 seconds)........ 300°C

(10 seconds)................................................ ±12mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

Device Supply Voltage (VCC) Limits

X9400 5V ± 10%

X9400-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter

R

TOTAL

I

W

R

W

Vv+ Voltage on V+ Pin X9400 +4.5 +5.5 V

Vv- Voltage on V- Pin X9400 -5.5 -4.5 V

V

TERM

C

H/CL/CW

I

AL

End to end resistance ±20 %

Power rating 50 mW 25°C, each pot

Wiper current ±6 mA

Wiper resistance 150 250 Ω Wiper Current = ± 1mA,

40 100 Ω Wiper Current = ± 1mA,

X9400-2.7 +2.7 +5.5

X9400-2.7 -5.5 -2.7

Voltage on any VH/RH or VL/RL Pin V- V+ V

Noise -120 dBV Ref: 1kHz

Resolution 1.6 %

Absolute linearity

Relative linearity

Temperature coefficient of R

Ratiometric temp. coefficient ±20 ppm/°C

Potentiometer capacitances 10/10/25 pF See Spice Macromodel

RH, RL, RW leakage current 0.1 10 µA VIN = VSS to VCC. Device is in

(1)

(2)

TOTAL

-1 +1 MI

-0.2 +0.2 MI

±300 ppm/°C

(3)

(3)

Test ConditionsMin. Typ. Max. Unit

=3V

V

CC

=5V

V

CC

R

w(n)(actual)

R

w(n + 1)

stand-by mode.

- [R

- R

w(n)(expected)

w(n) + MI

]

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when

used as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R

- RL)/63, single pot

H

11

FN8189.3

July 28, 2006

X9400

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

I

SB

I

I

LO

V

V

V

LI

IH

IL

OL

VCC supply current (Active) 400 µA f

VCC supply current (Nonvolatile
Write)

VCC current (standby) 1 µA SCK = SI = VSS, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

Input HIGH voltage VCC x 0.7 VCC + 0.5 V

Input LOW voltage -0.5 VCC x 0.1 V

Output LOW voltage 0.4 V IOL = 3mA

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

SCK

Other Inputs = V

1mAf

SCK

Other Inputs = V

Test ConditionsMin. Typ. Max. Units

= 2MHz, SO = Open,

SS

= 2MHz, SO = Open,

SS

CC

= VSS to V

OUT

CC

SS

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(4)

C

OUT

C

IN

(4)

Output capacitance (SO) 8 pF V

Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V

OUT

= 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(5)

t

PUR

(5)

t

PUW

(4)

t

R VCC

POWER-UP REQUIREMENTS (Power-up sequencing

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC Power-up ramp 0.2 50 V/msec

EQUIVALENT A.C. LOAD CIRCUIT

can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First

, then the potentiometer pins, RH, RL, and RW.

V

CC

Voltage should not be applied to the potentiometer
pins before V+ or V- is applied. The V

ramp rate

CC

specifi-cation should be met, and any glitches or slope
changes in the V
possible. If V

CC

line should be held to <100mV if

CC

powers down, it should be held below

SDA Output

5V

1533Ω

100pF

0.1V for more than 1 second before powering up again
in order for proper wiper register recall. Also, V

CC

should not reverse polarity by more than 0.5V. Recall
of wiper position will not be complete until V

CC

, V+

and V-reach their final value.

12

FN8189.3

July 28, 2006

X9400

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

nput pulse levels VCC x 0.1 to VCC x 0.9

I

Input rise and fall times 10ns

Input and output timing level V

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

and t

PUR

third (last) power supply (V
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.

are the delays required from the time the

PUW

x 0.5

CC

, V+ or V-) is stable until the

CC

SPICE Macro Model

R

R

H

10pF

TOTAL

C

H

C

W

25pF

R

W

C

L

10pF

R

L

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

AC TIMING

Symbol Parameter Min. Max. Unit

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI clock frequency 2.0 MHz

SSI/SPI clock cycle time 500 ns

SSI/SPI clock high time 200 ns

SSI/SPI clock low time 200 ns

Lead time 250 ns

Lag time 250 ns

SI, SCK, HOLD and CS input setup time 50 ns

SI, SCK, HOLD and CS input hold time 50 ns

SI, SCK, HOLD and CS input rise time 2 µs

SI, SCK, HOLD and CS input fall time 2 µs

SO output disable time 0 500 ns

SO output valid time 100 ns

SO output hold time 0 ns

SO output rise time 50 ns

SO output fall time 50 ns

HOLD time 400 ns

HOLD setup time 100 ns

HOLD hold time 100 ns

HOLD low to output in High Z 100 ns

HOLD high to output in Low Z 100 ns

Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns

CS deselect time 2 µs

WP, A0 and A1 setup time 0 ns

WP, A0 and A1 hold time 0 ns

13

FN8189.3

July 28, 2006

X9400

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

TIMING DIAGRAMS

Input Timing

CS

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns

t

CS

t

LEAD

t

CYC

t

LAG

SCK

SI

SO

Output Timing

CS

SCK

SO

SI

t

SU

MSB LSB

High Impedance

ADDR

t

H

t

WL

t

WH

...

t

FI

t

RI

...

...

t

V

MSB LSB

t

HO

...

t

DIS

14

FN8189.3

July 28, 2006

Hold Timing

www.BDTIC.com/Intersil

CS

SCK

t

RO

SO

SI

HOLD

XDCP Timing (for All Load Instructions)

CS

t

HSU

t

FO

t

HOLD

X9400

t

HH

...

t

HZ

t

LZ

SCK

MSB LSB

VW/R

SI

W

SO

High Impedance

XDCP Timing (for Increment/Decrement Instruction)

CS

SCK

V

W/RW

ADDR

SI

Inc/Dec

Inc/Dec

...

t

WRID

...

...

...

...

t

WRL

High Impedance

SO

15

FN8189.3

July 28, 2006

Write Protect and Device Address Pins Timing

www.BDTIC.com/Intersil

X9400

CS

t

WP

A0

A1

WPASU

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

Three terminal Potentiometer;
Variable voltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

(Any Instruction)

t

WPAH

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysteresis

V

S

10kΩ

R

R

1

100kΩ

-12V+12V

+

–

R

1

S

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

317

I

adj

R

2

–

+

}

}

R

R

2

1

R

1

adj R2

VO (REG)V

V

O

16

FN8189.3

July 28, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

Inverting Amplifier Equivalent L-R Circuit

R

R

1

S

}

4

All RS = 10kΩ

S

2

}

–

+

–

+

X9400

C

V

R

2

V

O

V

O

S

R

G

O

fc = 1/(2πRC)

C

1

V

S

R

= 1 + R2/R

+

–

R

1

1

R

2

+

–

V

O

2

VO = G V
G = - R2/R

R

Z

S

1

Function Generator

R

–

+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

, R

A

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

1

B

1

–

+

1

R

3

+ R3) >> R

C

2

17

FN8189.3

July 28, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9400

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6
N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

18

FN8189.3

July 28, 2006

X9400

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or i t s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

19

FN8189.3

July 28, 2006