Datasheet X9271 Datasheet (intersil)

®

www.BDTIC.com/Intersil

X9271

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet November 22, 2005

Single Digitally-Controlled (XDCP™)
Potentiometer

FEATURES

• 256 Resistor Taps

• SPI Serial Interface for write, read, and transfer
operations of the potentiometer

• Wiper Resistance, 100Ω typical @ V

• 16 Nonvolatile Data Registers

• Nonvolatile Storage of Multiple Wiper Positions

• Power -on Recall. Loads Sa ved Wiper P osition o n
Power-up.

• Standby Current < 3µA Max

: 2.7V to 5.5V Operation

•V

CC

•50kΩ, 100kΩ versions of End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 14-Lead TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

CC

= 5V

FN8174.2

DESCRIPTION

The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two ter minal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

SPI
Bus

Interface

Status

V

CC

Bus

Interface

and Control

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter
Register (WCR)

Data Registers

16 Bytes

R

H

50kΩ and 100kΩ

256-taps

POT

R

R

W

L

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9271

www.BDTIC.com/Intersil

Ordering Information

POTENTIOMETER

V

LIMITS

PART NUMBER PART MARKING

X9271UV14* X9271UV 5 ±10% 50 0 to +70 14 Ld TSSOP (4.4mm)

X9271UV14I* X9271UV I -40 to 85 14 Ld TSSOP (4.4mm)

X9271UV14IZ* (Note) X9271UV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14Z* (Note) X9271UV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14* X9271TV 100 0 to +70 14 Ld TSSOP (4.4mm)

X9271TV14I* X9271TV I -40 to 85 14 Ld TSSOP (4.4mm)

X9271TV14IZ* (Note) X9271TV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14Z* (Note) X9271TV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14-2.7* X9271UV F 2.7 to 5.5 50 0 to +70 14 Ld TSSOP (4.4mm)

X9271UV14I-2.7* X9271UV G -40 to 85 14 Ld TSSOP (4.4mm)

X9271UV14IZ-2.7* (Note) X9271UV ZF -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271UV14Z-2.7* (Note) X9271UV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14-2.7* X9271TV F 100 0 to +70 14 Ld TSSOP (4.4mm)

X9271TV14I-2.7* X9271TV G -40 to 85 14 Ld TSSOP (4.4mm)

X9271TV14IZ-2.7* (Note) X9271TV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)

X9271TV14Z-2.7* (Note) X9271TV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CC

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE (°C) PACKAGE

2

FN8174.2

November 22, 2005

DETAILED FUNCTIONAL DIAGRAM

www.BDTIC.com/Intersil

V

CC

X9271

HOLD

CS

SCK

SO

SI

A0
A1

WP

INTERFACE

AND

CONTROL

CIRCUITRY

V

SS

DATA

Control

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Trim out the offset voltage error in a v oltage am plifier
circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

• Vary the freque n cy an d du ty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

Bank 0
R0R

R2R

Power-on Recall

1

WIPER

COUNTER
REGISTER

(WCR)

3

Bank 1

R0R

R2R

12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits

1

3

Bank 2
R0R

R2R

50kΩ and 100kΩ

Bank 3
R0R

1

R2R

3

256-taps

1

3

R

R

R

SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF
wireless systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

H

L

W

3

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PIN CONFIGURATION

TSSOP

S0

1

A0

2

NC

3

CS

SCK

V

4
5

SI

6
7

SS

PIN ASSIGNMENTS

TSSOP Symbol Function

1 SO Serial Data Output.
2 A0 Device Address.
3 NC No Connect.
4CS
5 SCK Serial Clock.
6 SI Serial Data Input.
7V
8WP

9 A1 Device Address.
10 HOLD
11 R
12 R
13 R
14 V

X9271

SS

W

H

L

CC

14

V

CC

R

13
12
11
10

L

R

H

R

W

HOLD

A1

9

8

WP

Chip Select.

System Ground.
Hardware Write Protect.

Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.

4

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL OUTPUT (SO)

S

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL INPUT

S

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL CLOCK (SCK)

S

The SCK input is used to clock data into and out of the
X9271.

OLD (HOLD)

H

HOLD

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
serial communication with the controller without resetting
the serial sequence. To pause, HOLD
LOW while SCK is LOW. To resume communication,

is brought HIGH, again while SCK is LOW. If the

HOLD
pause feature is not u se d, HO L D
all times. CMOS level input.

may be used to pause the

must be brought

should be held HIGH at

Potentiometer Pins

, RL

R

H

The R
connections on a mechanical potentiometer.

R

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.

Supply Pins

S
G

The V
pin is the system ground.

Other Pins

H

The WP
the Data Registers.

N

No connect pins should be left floating . This pins are
used for Intersil man uf acturing and test ing purposes.

and RL pins are equivalent to the terminal

H

W

YSTEM SUPPLY VOLTAGE (V
ROUND (V

CC

ARDWARE WRITE PROTECT INPUT (WP)

O CONNECT.

)

SS

pin is the system supply voltage. The V

pin when LOW prevents nonvolatile writes to

) AND SUPPLY

CC

SS

EVICE ADDRESS (A1 - A0)

D

The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9271.

HIP SELECT (CS)

C

When CS
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
required prior to the start of any operati on.

is HIGH, the X9271 is deselected and the

LOW enables the X9271, placing it

is

5

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

PRINCIPLES OF OPERATION

Device Description

ERIAL INTERFACE

S

The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.
The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce
system pin count.

RRAY DESCRIPTION

A

The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in

Figure 1. Detailed Potentiometer Block Diagram

series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer

and RL inputs).

(R

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time.
These switches are controlled by a Wiper Counter

Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

OWER-UP AND DOWN RECOMMENDATIONS.

P

There are no restrictions on the power-up or power­down conditions of V
the potentiometer pins provided that V
more positive than or equal to V

≥ VH, VL, VW. The VCC ramp rate specification is

V

CC

and the voltages applied to

CC

, VL, and VW, i.e.,

H

is always

CC

always in effect.

SERIAL DATA PATH
FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0 REGISTER 1

(DR0) (DR1)

8 8

BANK_0 Only

REGISTER 2

(DR2) (DR3)

L

H

REGISTER 3

MODIFIED SCK

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN
CLK

R

H

C
O

U
N

T
E
R

D
E
C
O
D
E

R

L

R

W

6

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the R0 value into the WCR. The
DR0 value of Bank 0 is the def ault va lue.

Data Registers (DR3–DR0)

The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user pref erence d ata.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-v oltage write cycle

is in progress.

– When WIP=0, indicates that no high-voltage write

cycle is in progress

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

Table 3. Status Register, SR (WIP is 1-bit)

WIP

(LSB)

7

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

DEVICE DESCRIPTION

Instructions

DENTIFICATION BYTE (ID AND A)

I

The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9271; this is fixed as
0101[B] (refer to Table 4).

The A1 - A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A1 - A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both address bits is required f or
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driv en by CMOS input signals or tied to

or VSS.

V

CC

NSTRUCTION BYTE (I[3:0])

I

The next byte sent to the X9271 contains the
instruction and register po inter information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bit s po int t o one o f th e
four Data Registers. P0 is the POT selection; since th e
X9271 is single POT, the P0=0. The format is shown in
Table 5.

EGISTER BANK SELECTION (R1, R0, P1, P0)

R

Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Reg ister.

Register Selection (DR0 to DR3) Table

Register

RB RA

0 0 0 Data Register Read and Write;

0 1 1 Data Register Read and Write;

1 0 2 Data Register Read and Write;

1 1 3 Data Register Read and Write;

Selection Operations

Wiper Counter Register
Operations

Wiper Counter Register
Operations

Wiper Counter Register
Operations

Wiper Counter Register
Operations

Register Bank Selection (Bank 0 to Bank 3) Table

Bank

P1 P0

0 0 0 Data Register Read and Write;

0 1 1 Data Register Read and Write

1 0 2 Data Register Read and Write

1 1 3 Data Register Read and Write

Selection Operations

Wiper Counter Register
Operations

Only

Only

Only

There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.

Table 4. Identification Byte Format

Device Type

Identifier

ID3 ID2 ID1 ID0 0 0 A1 A0

0101

(MSB) (LSB)

8

Set to 0

for proper operation

Internal

Slave Address

FN8174.2

November 22, 2005

Table 5. Instruction Byte Format

www.BDTIC.com/Intersil

X9271

P1 and P0 are used also for register Bank Selection
for SPI Register Write and Read operations

Instruction Opcode

I3 I2 I1 P0 RB RA P1 P0

(MSB) (LSB)

DEVICE DESCRIPTION

Instructions

Five of the eight instructions are three bytes in length.
These instructions are:

– Read Wiper Counter Register – read the current

wiper position of the potentiometer;

– Write Wiper Counter Register – change current

wiper position of the potentiometer;

– Read Data Register – read the contents of the

selected Data Register;

– Write Data Register – write a new value to the

selected Data Register.

– Read Status - This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and t akes a
minimum of t
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique fo rmat (See Figure 4).

to complete. The transfer can occur

WR

WRL

. A transfer

Register Selection

Two instructions require a two-byte sequence to
complete (Figure 2). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

The final command is Increment/Decrement (Figure 5
and 6). It is different from the other commands,
because it’s length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (t
the selected wiper will move one resistor segment
towards the R
pulse while SI is LOW, the selected wiper will move
one resistor segment tow ards the R

See Instruction format for more details.

Write in Process (WIP bit)

The contents of the Data Registers are saved to
nonvolatile memory when the CS
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.

Pot Selection (WCR Selection)
Set to P0=0 for potentiometer operations

terminal. Similarly, for each SCK clock

H

) while SI is HIGH,

HIGH

terminal.

L

pin goes from LOW

9

FN8174.2

November 22, 2005

Figure 2. Two-Byte Instruction Sequence

www.BDTIC.com/Intersil

CS

SCK

X9271

SI

0101

ID3 ID2 ID1 ID0 0

Device ID

0

0

A1 A0

0

Internal
Address

Figure 3. Three-Byte Instruction Sequence (Write)

CS

SCL

SI

ID3 ID2 ID1 ID0

0101

Device ID

00
00

A1 A0

Internal
Address

I3 I2

Instruction
Opcode

I1

I3

I2

Instruction

Opcode

RB RA P0

I0

Register
Address

0

0

I0

I1

P1

RB RA P0

Register
Address

These commands only valid when P1 = P0 = 0

Pot/Bank
Address

Data Register Bit [7:0] for all values of P1 and P0

P1

Pot/Bank
Address

D7 D6 D5 D4 D3 D2 D1 D0

WCR[7:0] valid only when P1 = P0 = 0;

or

Figure 4. Three-Byte Instruction Sequence (Read)

CS

SCL

SI

ID3 ID2 ID1 ID0

S0

0101

Device ID

00
00

A1 A0

Internal
Address

I3

Instruction
Opcode

I2

X

X

XX

Don’t Care

or

XX

X

X

I1

RB RA P0

I0

Register
Address

P1

Pot/Bank
Address

D7 D6 D5 D4 D3 D2 D1 D0

WCR[7:0] valid only when P1 = P0 = 0;

Data Register Bit [7:0] for all values of P1 and P0

10

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

Figure 5. Increment/Decrement Instruction Sequence

CS

SCL

SI

0101

ID3 ID2 ID1 ID0

Device ID

Figure 6. Increment/Decrement Timing Limits

SCK

00
00

A1 A0

Internal
Address

I3 I2

Instruction

Opcode

I1

I0

0

RA RB P0

Register
Address

P1

Pot/Bank

Address

0

I

t

WRID

I

N

N

C

C

1

2

D

I

E

N

C

C

1

n

D
E

C

n

SI

V

W

INC/DEC CMD ISSUED

VOLTAGE OUT

Table 6. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Coun ter
Register

0

100100 01/0Read the contents of the Wiper Counter

Register

101000 01/0Write new value to the Wiper Counter

Register

OperationI3 I2 I1 I0 RB RA P1P

Read Data Register 10111/01/01/01/0Read the contents of the Data Register

pointed to by P1 - P0 and RB - RA

Write Data Register 11001/01/01/01/0Write new value to the Data Register

pointed to by P1 - P0 and RB - RA

XFR Data Register to
Wipe r Counter Register

11011/01/00 0Transfer the contents of the Data Register

pointed to by RB - RA (Bank 0 only) to the
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

11101/01/00 0Transfer the contents of the Wiper Counter

Regi s t er to the Register pointed to by RB-RA
(Bank 0 only)

Increment/Decrement
Wiper Counter Register

001000 0 0Enable Increment/decrement of the Wiper

Counter Register

Read Status (WIP bit) 010100 0 1Read the status of the internal write cycle, by

checking the WIP bit.

Note: 1/0 = data is one or zero

11

FN8174.2

November 22, 2005

INSTRUCTION FORMAT

www.BDTIC.com/Intersil

Read Wiper Counter Register (WCR)

X9271

CS

Falling

Edge

Device Type

Identifier

010100A1A010010000

Device

Addresses

Write Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A1A010100000

Device

Addresses

Read Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

01 0100A1A01011RBRAP1 P0 D7D 6D5D4D3D2D1D0

Device

Addresses

Write Data Register (DR)

Instruction

Opcode

Instruction

Opcode

Instruction

Opcode

DR/Bank

Addresses

DR/Bank

Addresses

DR/Bank

Addresses

Wiper Position

(Sent by X9271 on SO)

W

W

W

W

W

W
C
R

C
R
4

W
C
R

4

W

C

C

R

R

3

2

W

C
R

3

2

Data Byte

C

C

C

R

R

R

7

5

6

Data Byte

(Sent by Host on SI)

W

W

W

C

C

C

R

R

R

7

5

6

(Sent by X9271 on SO)

W
C
R

W
C
R

1

CS

W

Rising

C

Edge

R

1

0

CS

W

Rising

C

Edge

R

0

CS

Rising

Edge

CS

Falling

Edge

Device Type

Identifier

0 1 0 1 0 0A1A01 1 0 0RBRAP1 P0 D7D 6D5D4D3D2D1D0

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

01 0 100A1A01110RB RA0 0

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Data Byte

(Sent by Host on SI)

CS

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

CS

Rising

Edge

WRITE CYCLE

HIGH-VOLTAGE

12

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01101RBRA00

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Increment/Decrement Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

Read Status Register (SR)

CS

Falling

Edge

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

Identifier

010100A1A0010100010000000 WIP

(2) WCRx refers to wiper position data in the Wiper Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
(4) “X:”: Don’t Care.

Device Type

Device

Addresses

Instruction

Opcode

DR/Bank

Addresses

CS

Rising

Edge

Increment/Decrement

(Sent by Master on SDA)

Data Byte

(Sent by X9271 on SO)

CS

Rising

Edge

CS

Rising

Edge

13

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias..................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

V oltage on SCK any addr ess input

with respect to V

∆V = |(V

- VL)|.....................................................5.5V

H

................................. -1V to +7V

SS

Lead temperature (soldering, 10 seconds)........ 300°C

(10 seconds)..................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

ANALOG CHARACTERISTICS

(Over recommended industrial operating conditions unless otherwise stated.)

Symbol Parameter

R

TOTAL

R

TOTAL

End to End Resistance 100 kΩ T version
End to End Resistance 50 kΩ U version
End to End Resistance

Tolerance
Power Rating 50 mW 25°C, each pot

I

W

R

W

R

W

V

TERM

Wiper Current ±3 mA
Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V
Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V
Voltage on any RH or RL Pin V

SS

Noise -120 dBV/√
Resolution
Absolute Linearity

(1)

COMMENT

Stresses above those liste d under “Abso lute Maxim um
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect de vice reliabi lity.

Device Supply Voltage (VCC)

X9271 5V ± 10%

X9271-2.7 2.7V to 5.5V

Limits

Test ConditionsMin. Typ. Max. Units

±20 %

V

CC

VV

SS

= 0V

Hz Ref: 1V

0.4 %
±1 MI

(3)

R

w(n)(actual) - Rw(n)(expected)

(4)

Limits

(5)

Relative Linearity

Temperature Coefficient of
R

TOTAL

(2)

±0.2 MI

±300 ppm/°C

Ratiometric Temp. Coefficient 20 ppm/°C

C

H/CL/CW

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

(3) MI = RTO T / 255 or (R
(4) During power-up V
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.

Potentiometer Capacitancies 10/10/25 pF See Macro model

potentiometer.

potentiometer. It is a measure of the error in step size.

- RL) / 255, single pot

H

> VH, VL, and VW.

CC

14

(3)

R

w(n + 1)

- [R

w(n) + MI

(5)

]

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

VCC supply current
(active)

I

CC2

VCC supply current
(nonvolatile write)

I

I
I
V
V
V
V
V

SB

LI
LO

IH
IL
OL
OH
OH

VCC current (standby) 3 µASCK = SI = VSS, Addr. = VSS,

Input leakage current 10 µAVIN = VSS to V
Output leakage current 10 µAV
Input HIGH voltage VCC x 0.7 VCC + 1 V
Input LOW voltage -1 VCC x 0.3 V
Output LOW voltage 0.4 V IOL = 3mA
Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V
Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V

ENDURANCE AND DATA RETENTION

400 µAf

SCK

Other Inputs = V

15mAf

SCK

Other Inputs = V

CS

= VCC = 6V

OUT

Test ConditionsMin. Typ. Max. Units

= 2.5 MHz, SO = Open, V

SS

= 2.5MHz, SO = Open, V

SS

CC

= VSS to V

CC

CC

CC

= 6V

= 6V

Parameter Min. Units

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

CAPACITANCE

Symbol Test Max. Units Test Conditions

IN/OUT

(6)

OUT

(6)

IN

(6)

Input / Output capacitance (SI) 8 pF V
Output capacitance (SO) 8 pF V
Input capacitance (A0, CS, WP, HOLD, and

6pFV

OUT
OUT

IN

= 0V

C
C
C

SCK)

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(6)

tr V
t

PUR

t

PUW

CC

(7)

(7)

VCC Power-up rate 0.2 50 V/ms
Power-up to initiation of read operation 1 ms
Power-up to initiation of write operation 50 ms

A.C. TEST CONDITIONS

Input Pulse Levels V

x 0.1 to VCC x 0.9

CC

Input rise and fall times 10ns
Input and output timing level V

Notes: (6) This parameter is not 100% tested

(7) t

and t

PUR

These parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.

PUW

CC

x 0.5

= 0V
= 0V

15

FN8174.2

November 22, 2005

EQUIVALENT A.C. LOAD CIRCUIT

www.BDTIC.com/Intersil

X9271

SPICE Macromodel

R

TOTAL

C

L

10pF

R

W

C

W

25pF

C

L

10pF

SO pin

2714Ω

5V

1462Ω

100pF

SO pin

1217Ω

3V

1382Ω

100pF

R

H

AC TIMING

Symbol Parameter Min. Max. Units

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI clock frequency 2.5 MHz
SSI/SPI clock cycle time 500 ns
SSI/SPI clock high time 200 ns
SSI/SPI clock low time 200 ns
Lead time 250 ns
Lag time 250 ns
SI, SCK, HOLD and CS input setup time 50 ns
SI, SCK, HOLD and CS input hold time 50 ns
SI, SCK, HOLD and CS input rise time 2 µs
SI, SCK, HOLD and CS input fall time 2 µs
SO output disable time 0 250 ns
SO output valid time 200 ns
SO output hold time 0 ns
SO output rise time 100 ns
SO output fall time 100 ns
HOLD time 400 ns
HOLD setup time 100 ns
HOLD hold time 100 ns
HOLD low to output in high Z 100 ns
HOLD high to output in low Z 100 ns
Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
CS deselect time 2 µs
WP, A0 setup time 0 ns
WP, A0 hold time 0 ns

R

L

16

FN8174.2

November 22, 2005

X9271

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 5 10 µs
Wiper response time after instruction issued (all load instructions) 5 10 µs

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

17

FN8174.2

November 22, 2005

TIMING DIAGRAMS

www.BDTIC.com/Intersil

Input Timing

CS

SCK

t

SU

SI

X9271

t

LEAD

t

H

MSB LSB

t

WL

t

CYC

t

...

WH

...

t

FI

t

CS

t

LAG

t

RI

SO

Output Timing

CS

SCK

SO

ADDR

SI

Hold Timing

CS

SCK

t

RO

SO

High Impedance

t

V

MSB

t

HSU

t

FO

t

HZ

t

HO

...

...

t

HH

...

t

LSB

LZ

t

DIS

SI

t

HOLD

HOLD

18

FN8174.2

November 22, 2005

XDCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

CS

X9271

SCK

MSB LSB

VWx

SO

SI

High Impedance

Write Protect and Device Address Pins Timing

CS

t

WP

A0
A1

WPASU

...

...

(Any Instruction)

t

WPAH

t

WRL

19

FN8174.2

November 22, 2005

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

RW

Three terminal Potentiometer;
Variable v oltage divider

Application Circuits

Noninverting Amplifier Voltage Regulator

X9271

+V

R

I

Two terminal Variable Resistor;
Variable current

V

S

VO = (1+R2/R1)V

+
–

R

R

1

S

V

O

2

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

I

adj

R

2

Offset Voltage Adjustment Comparator with Hysterisis

–
+

R

2

TL072

V

S

V

O

VUL = {R1/(R1+R2)} VO(max)
RL

= {R1/(R1+R2)} VO(min)

L

–
+

}

}

R

R

2

1

V

S

10kΩ

R

1

100kΩ

-12V+12V

10kΩ10kΩ

1

adj R2

VO (REG)V

V

O

20

FN8174.2

November 22, 2005

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

R

–
+

R1 = R2 = R3 = R4 = 10kΩ

S

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

2

1

}

}

–
+

X9271

C

V

S

2

V

O

V

V

O

S

R

C

1

G

= 1 + R2/R

O

fc = 1/(2πRC)

+
–

R

R

1

1

R

2

+
–

V

O

2

VO = G V
G = - R2/R

S

1

Function Generator

–
+

frequency ∝ R1, R2, C
amplitude ∝ R

, R

A

B

R

Z

IN

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

1

–
+

1

R

3

+ R3) >> R

C

2

21

FN8174.2

November 22, 2005

PACKAGING INFORMATION

www.BDTIC.com/Intersil

X9271

14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V

.025 (.65) BSC

0° - 8 °

.0075 (.19)
.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

DetailA (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Seating Plane

.252 (6.4) BSC

Gage Plane

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

22

FN8174.2

November 22, 2005