Datasheet X9261 Datasheet (intersil)

®

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X9261

Single Supply/Low Power/256-Tap/SPI Bus

Data Sheet October 12, 2006

Dual Digitally-Controlled (XDCP™)
Potentiometers

FEATURES

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/pot–0.4% Resolution

• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer Single Supply
Device

• Wiper Resistance, 100Ω typical @ V

• 4 Nonvolatile Data Registers for Each
Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall Loads Saved Wiper Position on
Power-up.

• Standby Current < 5µA Max

•50kΩ, 100kΩ Versions of End to End Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per
Register

• 24 Ld SOIC, 24 Ld TSSOP

• Low Power CMOS

• Power Supply V

= 5V ±10%

CC

• Pb-Free Plus Anneal Available (RoHS Compliant)

CC

= 5V

FN8171.4

DESCRIPTION

The X9261 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

Address

Data

SPI
Bus

Interface

Status

V

CC

Bus

Interface

and Control

V

SS

Write
Read

Transfer

Inc/Dec

Control

Power-on Recall

Wiper Counter

Register (WCR)

Data Registers

(DR0-DR3)

R

H0

W0

R

L0

R

R

H1

R

R

W1

50kΩ or 100kΩ versions

L1

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9261

PART

PART NUMBER

X9261US24 X9261US 5 ±10% 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9261US24Z (Note) X9261US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9261UV24 X9261UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9261UV24Z (Note) X9261UV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

V

CC

LIMITS

(V) R

(kΩ) TEMP RANGE (°C) PACKAGE

TOTAL

PKG.

DWG. #

DETAILED FUNCTIONAL DIAGRAM

R

R

R

H0

L0

W0

V

CC

Power-on

HOLD

CS

SCK

SO

A0
A1

WP

Recall

R0R

1

Wiper

Counter

INTERFACE

AND

SI

CONTROL

CIRCUITRY

8

Data

R2R

Power-on
Recall

R0R

R2R

3

1

3

Register

(WCR)

Wiper
Counter
Register

(WCR)

Pot 0

Ω

50k

256-taps

Resistor

Array
Pot 1

and 100k

Ω

V

SS

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Provide programmable dc reference voltages for
comparators and detectors

• Control the volume in audio circuits

• Vary the frequency and duty cycle of timer ICs

• Vary the dc biasing of a pin diode attenuator in RF
circuits

• Provide a control variable (I, V, or R) in feedback
circuits

• Trim out the offset voltage error in a voltage ampli­fier circuit

• Set the output voltage of a voltage regulator

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and
Q-factor in filter circuits

• Set the scale factor and zero point in sensor signal
conditioning circuits

2

R

R

R

H1

L1

W1

FN8171.4

October 12, 2006

X9261

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SYSTEM LEVEL APPLICATIONS

• Adjust the contrast in LCD displays

• Control the power level of LED transmitters in
communication systems

• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems

• Control the gain in audio and home entertainment
systems

• Provide the variable DC bias for tuners in RF wire­less systems

• Set the operating points in temperature control
systems

• Control the operating point for sensors in industrial
systems

• Trim offset and gain errors in artificial intelligent
systems

PIN CONFIGURATION

SOIC/TSSOP

HOLD

SCK

NC

NC

NC

NC

V

SS

R

W1

R

H1

R

L1

A1

SI

V

R

R

SO

A0

NC

NC

NC

NC

CC

R

H0

W0

CS

WP

1

2

3

4

5

6

X9261

7

L0

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PIN ASSIGNMENTS

Pin

(SOIC/

TSSOP) Symbol Function

1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus.
3 NC No Connect.
4 NC No Connect.
5 NC No Connect.
6 NC No Connect.
7V
8R

9R
10 R
11 CS
12 WP
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus.
15 R
16 R
17 R
18 V
19 NC No Connect
20 NC No Connect
21 NC No Connect
22 NC No Connect
23 SCK Serial Clock for SPI bus
24 HOLD

System Supply Voltage

CC

Low Terminal for Potentiometer 0.

L0

High Terminal for Potentiometer 0.

H0

Wiper Terminal for Potentiometer 0.

W0

Device Address for SPI bus.
Hardware Write Protect

Low Terminal for Potentiometer 1.

L1

High Terminal for Potentiometer 1.

H1

Wiper Terminal for Potentiometer 1.

W1

System Ground

SS

Device select. Pause the SPI serial bus.

PIN DESCRIPTIONS

Bus Interface Pins

S

ERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL INPUT

S

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL CLOCK (SCK)

S

The SCK input is used to clock data into and out of the
X9261.

3

FN8171.4

October 12, 2006

X9261

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HOLD (HOLD)

HOLD

is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD

may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD

must
be brought LOW while SCK is LOW. To resume
communication, HOLD

is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

EVICE ADDRESS (A1 - A0)

D

The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9261.

HIP SELECT (CS)

C

When CS

is HIGH, the X9261 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS

LOW enables the X9261, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS

is

required prior to the start of any operation.

Potentiometer Pins

, RL

R

H

The R

and RL pins are equivalent to the terminal

H

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R

such that RH0 and RL0 are the terminals of POT 0

R

L

H

and

and so on.

R

W

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of R

such that R

W

W0

is the terminals of POT 0 and so on.

Supply Pins

YSTEM SUPPLY VOLTAGE (V

S

ROUND (V

G

The V

CC

)

SS

pin is the system supply voltage. The V

) AND SUPPLY

CC

SS

pin is the system ground.

Other Pins

O CONNECT

N

No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.

ARDWARE WRITE PROTECT INPUT (WP)

H

The WP

pin when LOW prevents nonvolatile writes to

the Data Registers.

PRINCIPLES OF OPERATION

Serial Interface

The X9261 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
LOW and the HOLD

and WP pins must be HIGH

must be

during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9261 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer

and RL inputs).

(R

H

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(R

W

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

Power-up and Down Requirements.

There are no restrictions on the power-up or power­down conditions of V
the potentiometer pins provided that V
more positive than or equal to V

, VH, VL, VW. The VCC ramp rate specification is

V

CC

and the voltages applied to

CC

, VL, and VW, i.e.,

H

is always

CC

always in effect.

4

FN8171.4

October 12, 2006

Figure 1. Detailed Potentiometer Block Diagram

www.BDTIC.com/Intersil

One of Two Potentiometers

X9261

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

IF WCR = 00[H] THEN RW = R
IF WCR = FF[H] THEN RW = R

REGISTER 0

(DR0)

REGISTER 2 REGISTER 3

(DR2)

L

H

REGISTER 1

(DR1)

8 8

(DR3)

MODIFIED SCK

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9261 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9261 is powered­down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.

UP/DN

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

WIPER
COUNTER
REGISTER

(WCR)

INC/DEC

LOGIC

UP/DN

CLK

C
O
U
N
T
E
R

D
E
C
O
D
E

R

H

R

L

R

W

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.

– When WIP=1, indicates that high-voltage write cycle

is in progress.

– When WIP=0, indicates that no high-voltage write

cycle is in progress.

5

FN8171.4

October 12, 2006

X9261

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Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0

VVVVVVVV

(MSB) (LSB)

Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

NV NV NV NV NV NV NV NV

MSB LSB

DEVICE DESCRIPTION

input state; a successful compare of both address bits
is required for the X9261 to successfully continue the

Instructions

command sequence. Only the device which slave
address matches the incoming device address sent

DENTIFICATION BYTE ( ID AND A )

I

The first byte sent to the X9261 from the host,
following a CS

going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9261; this is fixed as
0101[B] (refer to Table 3).

The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9261
compares the serial data stream with the address

by the master executes the instruction. The A3-A0
inputs can be actively driven by CMOS input signals
or tied to V

NSTRUCTION BYTE ( I[3:0] )

I

or VSS.

CC

The next byte sent to the X9261 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.

Table 3. Identification Byte Format

Device Type

Identifier Slave Address

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Table 4. Instruction Byte Format

Data

Instruction

Opcode

I3 I2 I1 I0 RB RA 0 P0

(MSB) (LSB)

6

Register

Selection

Pot Selection

(WCR Selection)

FN8171.4

October 12, 2006

X9261

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Register Selection

Register Selected RB RA

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

DEVICE DESCRIPTION

Instructions

Four of the ten instructions are three bytes in length.
These instructions are:

– Read Wiper Counter Register – read the current

wiper position of the selected potentiometer,

– Write Wiper Counter Register – change current

wiper position of the selected potentiometer,

– Read Data Register – read the contents of the

selected Data Register;

– Write Data Register – write a new value to the

selected Data Register.

– Read Status - This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 5).

to complete. The transfer can occur

WR

. A transfer

WRL

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

– Global XFR Data Register to Wiper Counter

Register – This transfers the contents of all speci­fied Data Registers to the associated Wiper Counter
Registers.

– Global XFR Wiper Counter Register to Data

Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (See
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9261 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
the selected wiper will move one resistor segment
towards the R
pulse while SI is LOW, the selected wiper will move
one resistor segment towards the R
detailed illustration of the sequence and timing for this
operation are shown. See Instruction format for more
details.

terminal. Similarly, for each SCL clock

H

) while SI is HIGH,

HIGH

terminal. A

L

Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9261; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:

7

FN8171.4

October 12, 2006

Figure 2. Two-Byte Instruction Sequence

www.BDTIC.com/Intersil

CS

SCK

X9261

SI

0101

ID3 ID2 ID1 ID0 0

Device ID

0

0

A1 A0

0

Internal

Address

Figure 3. Three-Byte Instruction Sequence (Write)

CS

SCL

SI

ID3 ID2 ID1 ID0

0101

Device ID

00

00

A1 A0

Internal
Address

I3 I2

Instruction

Opcode

I1

Figure 4. Three-Byte Instruction Sequence (Read)

I3

Instruction

RB RA P0

I0

Register
Address

I2

I1

Opcode

0

Pot/WCR

Address

RB RA P0

I0

Register

Address

D7 D6 D5 D4 D3 D2 D1 D0

0

Pot/WCR

Address

WCR[7:0]

Data Register Bit [7:0]

or

CS

SCL

SI

S0

0101

ID3 ID2 ID1 ID0

Device ID

00

00

A1 A0

Internal
Address

I3

I1

I2

Instruction
Opcode

RB RA P0

I0

Register
Address

0

Pot/WCR

Address

8

X

D7 D6 D5 D4 D3 D2 D1 D0

X

X

XX

Don’t Care

WCR[7:0]

Data Register Bit [7:0]

XX

or

X

October 12, 2006

FN8171.4

X9261

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Figure 5. Three-Byte Instruction Sequence (Read Status Register)

CS

SCL

SI

ID3 ID2 ID1 ID0

0101

Device ID

00

00

A1 A0

Internal
Address

101

I3

I2

Instruction
Opcode

I1

I0

Figure 6. Increment/Decrement Instruction Sequence

CS

SCL

SI

ID3 ID2 ID1 ID0

0101

Device ID

00

00

A1 A0

Internal
Address

I3I2

I1

Instruction
Opcode

Figure 7. Increment/Decrement Timing Limits

1

RB RA

Register
Address

I0

RB RA P0

Register
Address

0

P0

Pot/WCR
Address

0

Pot/WCR
Address

0

0

I
N
C
2

00

D

I

E

N

C

C

1

n

00

WIP

Status

Bit

D
E

C

n

0

I
N
C
1

SCK

SI

R

W

INC/DEC CMD ISSUED

9

VOLTAGE OUT

t

WRID

FN8171.4

October 12, 2006

X9261

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Table 5. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register

Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register

XFR Data Register to
Wiper Counter Register

XFR Wiper Counter
Register to Data Register

Global XFR Data Registers
to Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

Increment/Decrement
Wiper Counter Register

Note: 1/0 = data is one or zero

1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter

Register pointed to by P0

1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter

Register pointed to by P0

pointed to by P0 and RB - RA

pointed to by P0 and RB - RA

1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register

pointed to by P0 and RB - RA to its
associated Wiper Counter Register

1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter

Register pointed to by P0 to the Data
Register pointed to by RB - RA

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers

pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

Registers to their respective data Registers
pointed to by RB - RA of all four pots

0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Control

Latch pointed to by P0

OperationI3 I2 I1 I0 RB RA 0 P0

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

01 0100A1A01001000P0

Device

Addresses

Write Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01010000P0

Device

Addresses

Read Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010100A1A01011RBRA 0 P0

Device

Addresses

Instruction

Opcode

Instruction

Opcode

Instruction

Opcode

WCR

Addresses

WCR

Addresses

DR and WCR

Addresses

Wiper Position

(Sent by X9261 on SO)

W

W

W

W

W

C

C

C

R

R

R

7

5

6

Data Byte

(Sent by Host on SI)

W

W

W

W

C

C

C

R

R

R

7

5

6

Data Byte

(Sent by X9271 on SO)

D

D 6D5D4D3D2D1D

7

W

C

C

C

R

R

R

4

3

2

W

W

C

C

C

R

R

R

4

3

2

W

C
R

W

1

CS

W

Rising

C

C
R

0

W
C
R

0

Edge

CS

Rising

Edge

Rising

0

CS

Edge

R
1

10

FN8171.4

October 12, 2006

Write Data Register (DR)

www.BDTIC.com/Intersil

X9261

CS

Falling

Edge

Device Type

Identifier

010 100A1A01100RBRA 0 P0

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

(Sent by Host on SI)

D

D 6D5D4D3D2D1D

7

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

010100A1A00001RBRA00

Device

Addresses

Instruction

Opcode

DR

Addresses

CS

Rising

Edge

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010 100A1A01000RBRA00

Device

Addresses

Instruction

Opcode

DR

Addresses

CS

Rising

Edge

Transfer Wiper Counter Register (WCR) to Data Register (DR)

CS

Falling

Edge

Device Type

Identifier

010 100A1A01110RBRA0P0

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

CS

Rising

Edge

Data Byte

HIGH-VOLTAGE

WRITE CYCLE

HIGH-VOLTAGE

WRITE CYCLE

0

CS

Rising

Edge

WRITE CYCLE

HIGH-VOLTAGE

Transfer Data Register (DR) to Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

0 1 0 100A1A01101RBRA0P0

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Increment/Decrement Wiper Counter Register (WCR)

CS

Falling

Edge

Device Type

Identifier

0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D

Device

Addresses

Instruction

Opcode

WCR

Addresses

Read Status Register (SR)

Device Type

CS

Falling

Edge

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.

Identifier

0 10 100A1A00101000100 000 00 WIP

(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).

Device

Addresses

Instruction

Opcode

WCR

Addresses

CS

Rising

Edge

Increment/Decrement

(Sent by Master on SDA)

Data Byte

(Sent by X9261 on SO)

CS

Rising

Edge

CS

Rising

Edge

11

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SCK any address input

with respect to V

ΔV = | (V

- VL) |................................................... 5.5V

H

................................. -1V to +7V

SS

Lead temperature (soldering, 10s) .................... 300°C

(10s) ..............................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

POTENTIOMETER CHARACTERISTICS

(Over recommended industrial operating conditions unless otherwise stated.)

Parameter Limits

Symbol

R

TOTAL

R

TOTAL

End to End Resistance 100 kΩ T version

End to End Resistance 50 kΩ U version

End to End Resistance Tolerance ±20 %

Power Rating 50 mW 25°C, each pot

I

W

R

W

R

W

V

TERM

Wiper Current ±3 mA

Wiper Resistance 300 Ω IW = ±3mA @ V+ = 3V

Wiper Resistance 150 Ω IW = ±3mA @ V+ = 5V

Voltage on any RH or RL Pin V

SS

Noise -120 dBV Ref: 1V

Resolution

Absolute Linearity

(1)

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

Device Supply Voltage (VCC)

(4)

Limits

X9261 5V ± 10%

Test ConditionsMin. Typ. Max. Units

V

CC

VV

SS

= 0V

0.4 %

±1 MI

(3)

R

w(n)(actual)

- R

w(n)(expected)

(5)

Relative Linearity

(2)

Temperature Coefficient of R

TOTAL

±0.6 MI

±300 ppm/°C

(3)

R

w(n + 1)

- [R

w(n) + MI

(5)

]

Ratiometric Temp. Coefficient 20 ppm/°C

C

H/CL/CW

I

al

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

(3) MI = RTOT / 255 or (R
(4) During power-up V
(5) n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.

Potentiometer Capacitances 10/10/25 pF See Macro model

RW, RH, RL Leakage 0.1 10.0 µA Device in stand by.

potentiometer.

potentiometer. It is a measure of the error in step size.

- RL) / 255, single pot

H

> VH, VL, and VW.

CC

12

Vin = V

SS

to V

CC

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

VCC supply current
(active)

I

CC2

VCC supply current
(nonvolatile write)

I

I

I

V

V

V

V

V

SB

LI

LO

IH

IL

OL

OH

OH

VCC current (standby) 5 μASCK = SI = VSS, Addr. = VSS,

Input leakage current 10 μAVIN = VSS to V

Output leakage current 10 μAV

Input HIGH voltage VCC x 0.7 VCC + 1 V

Input LOW voltage -1 VCC x 0.3 V

Output LOW voltage 0.4 V IOL = 3mA

Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V

Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V

ENDURANCE AND DATA RETENTION

Parameter Min. Units

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

400 μAf

SCK

Other Inputs = V

15mAf

SCK

Other Inputs = V

CS

= VCC = 6V

OUT

Test ConditionsMin. Typ. Max. Units

= 2.5 MHz, SO = Open, V

SS

= 2.5MHz, SO = Open, V

SS

CC

= VSS to V

CC

CC

CC

= 6V

= 6V

CAPACITANCE

Symbol Test Max. Units Test Conditions

(6)

C

C

OUT

(6)

IN

Output capacitance (SO) 8 pF V

OUT

= 0V

Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Units

(6)

tr V

t

PUR

CC

(7)

VCC Power-up rate 0.2 50 V/ms

Power-up to initiation of read operation 1 ms

POWER-UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of V
tiometer pins provided that V

power-up timing spec is always in effect.

V

CC

is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The

CC

and the voltages applied to the poten-

CC

A.C. TEST CONDITIONS

Input Pulse Levels V

x 0.1 to VCC x 0.9

CC

Input rise and fall times 10ns

Input and output timing level V

Notes: (6) This parameter is not 100% tested

(7) t

and t

PUR

These parameters are periodically sampled and not 100% tested.

are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.

PUW

CC

x 0.5

13

FN8171.4

October 12, 2006

EQUIVALENT A.C. LOAD CIRCUIT

www.BDTIC.com/Intersil

X9261

SO pin

2714Ω

5V

1462Ω

SO pin

100pF

1217Ω

3V

1382Ω

100pF

SPICE Macromodel

R

R

H

10pF

TOTAL

C

L

C

W

25pF

R

W

C

L

10pF

AC TIMING

Symbol Parameter Min. Max. Units

f

SCK

t

CYC

t

WH

t

WL

t

LEAD

t

LAG

t

SU

t

H

t

RI

t

FI

t

DIS

t

V

t

HO

t

RO

t

FO

t

HOLD

t

HSU

t

HH

t

HZ

t

LZ

T

I

t

CS

t

WPASU

t

WPAH

SSI/SPI clock frequency 2 MHz

SSI/SPI clock cycle rime 500 ns

SSI/SPI clock high rime 200 ns

SSI/SPI clock low time 200 ns

Lead time 250 ns

Lag time 250 ns

SI, SCK, HOLD and CS input setup time 50 ns

SI, SCK, HOLD and CS input hold time 50 ns

SI, SCK, HOLD and CS input rise time 2 μs

SI, SCK, HOLD and CS input fall time 2 μs

SO output disable time 0 250 ns

SO output valid time 200 ns

SO output hold time 0 ns

SO output rise time 100 ns

SO output fall time 100 ns

HOLD time 400 ns

HOLD setup time 100 ns

HOLD hold time 100 ns

HOLD low to output in high Z 100 ns

HOLD high to output in low Z 100 ns

Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns

CS deselect time 2 μs

WP, A0, A1 setup time 0 ns

WP, A0, A1 hold time 0 ns

R

L

14

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Units

t

WR

XDCP TIMING

Symbol Parameter Min. Max. Units

t

WRPO

t

WRL

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

High-voltage write cycle time (store instructions) 5 10 ms

Wiper response time after the third (last) power supply is stable 5 10 μs

Wiper response time after instruction issued (all load instructions) 5 10 μs

TIMING DIAGRAMS

Input Timing

CS

SCK

t

SU

SI

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

t

LEAD

MSB LSB

t

H

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

t

WL

t

CYC

t

...

WH

...

t

FI

t

CS

t

LAG

t

RI

SO

High Impedance

15

FN8171.4

October 12, 2006

Output Timing

www.BDTIC.com/Intersil

CS

X9261

SCK

SO

ADDR

SI

Hold Timing

CS

SCK

SO

SI

HOLD

t

RO

t

V

MSB LSB

t

HSU

t

FO

t

HZ

t

HOLD

t

HO

t

HH

...

...

...

t

LZ

t

DIS

XDCP Timing (for All Load Instructions)

CS

SCK

SI

VWx

SO

High Impedance

MSB

Write Protect and Device Address Pins Timing

CS

t

WP

A0

A1

WPASU

...

...

(Any Instruction)

t

WPAH

t

WRL

LSB

16

FN8171.4

October 12, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

RW

X9261

+V

R

I

Three terminal Potentiometer;

Application Circuits

Noninverting Amplifier Voltage Regulator

V

S

VO = (1+R2/R1)V

Offset Voltage Adjustment Comparator with Hysterisis

Variable voltage divider

+

–

R

2

R

1

S

Two terminal Variable Resistor;

Variable current

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

317

R

1

I

adj

R

2

VO (REG)V

adj R2

–

+

R

2

TL072

V

S

V

O

}
R

VUL = {R1/(R1+R2)} VO(max)
V

= {R1/(R1+R2)} VO(min)

LL

V

S

10kΩ

R

1

100kΩ

-12V+12V

10kΩ10kΩ

17

–

+

}
R

2

1

V

O

FN8171.4

October 12, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

Attenuator Filter

R

1

V

S

R

3

R

4

VO = G V

-1/2 ≤ G ≤ +1/2

S

R

–

+

R1 = R2 = R3 = R4 = 10kΩ

Inverting Amplifier Equivalent L-R Circuit

R

R

V

S

1

}

VO = G V
G = - R2/R

2

}

–

+

S

1

X9261

C

V

S

2

V

O

V

V

O

S

Z

IN

R

C

1

= 1 + R2/R

G

O

fc = 1/(2πRC)

+

–

R

R

1

1

R

2

+

–

R

1

R

3

V

O

2

Function Generator

–

+

frequency ∝ R1, R2, C

18

, R

A

B

amplitude ∝ R

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

R

2

R

}

A

R

}

B

R

1

+ R3) >> R

1

C

–

+

2

FN8171.4

October 12, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9261

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

19

FN8171.4

October 12, 2006

X9261

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8171.4

October 12, 2006