Datasheet X9258 Datasheet (intersil)

®

www.BDTIC.com/Intersil

X9258

Low Noise/Low Power/2-Wire Bus/256 Taps

Data Sheet FN8168.4August 30, 2006

Quad Digital Controlled Potentiometers
(XDCP™)

FEATURES

• Four potentiometers in one package

• 256 resistor taps/pot–0.4% resolution

• 2-wire serial interface

• Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current <5µA max (total package)

• Power supplies
—V
—V+ = 2.7V to 5.5V
—V- = -2.7V to -5.5V

• 100kΩ, 50kΩ total pot resistance

• High reliability
—Endurance – 100,000 data changes per bit per

—Register data retention – 100 years

• 24 Ld SOIC, 24 Ld TSSOP

• Dual supply version of X9259

• Pb-free plus anneal available (RoHS compliant)

= 2.7V to 5.5V

CC

register

DESCRIPTION

The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

CC

V

SS

V+
V-

WP

SCL

SDA

A0
A1

A2
A3

Interface

and

Control

Circuitry

Data

Pot 0

R0R

1

Wiper
Counter
Register

3

1

3

(WCR)

Wiper

Counter
Register

(WCR)

Resistor

Array
Pot 1

R2R

8

R0R

R2R

VH0/R

VL0/R

VW0/R

VW1/R

V

H1/RH1

VL1/R

W0

W1

L0

L1

H0

R0R

R2R

R0R

R2R

1

3

1

3

Wiper
Counter
Register

(WCR)

Wiper

Counter

Register

(WCR)

Resistor

Array
Pot 2

Resistor

Array

Pot 3

V

H2/RH2

VL2/R

VW2/R

VW3/R

V

H3/RH3

VL3/R

L2

W2

W3

L3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

X9258

POTENTIOMETER

PART

PART NUMBER

X9258US24* X9258US 5 ±10 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258US24Z* (Note) X9258US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258US24I* X9258US I -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258US24IZ* (Note) X9258US ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258UV24 X9258UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24I X9258UV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24IZ (Note) X9258UV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TS24 X9258TS 100 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258TS24Z (Note) X9258TS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TS24I X9258TS I -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ (Note) X9258TS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TV24I X9258TV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258US24-2.7* X9258US F 2.7 to 5.5 50 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258US24Z-2.7* (Note) X9258US ZF 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258US24I-2.7* X9258US G -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258US24IZ-2.7*

(Note)
X9258UV24-2.7 X9258UV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24I-2.7 X9258UV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258UV24IZ-2.7 (Note) X9258UV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258UV24Z-2.7 (Note) X9258UV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TS24-2.7* X9258TS F 100 0 to 70 24 Ld SOIC (300 mil) M24.3
X9258TS24Z-2.7* (Note) X9258TS ZF 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258TS24I-2.7* X9258TS G -40 to 85 24 Ld SOIC (300 mil) M24.3
X9258TS24IZ-2.7*

(Note)
X9258TV24-2.7 X9258TV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9258TV24I-2.7 X9258TV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9258TV24IZ-2.7 (Note) X9258TV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TV24Z-2.7 (Note) X9258TV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

X9258US ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3

X9258TS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) M24.3

V

LIMITS

CC

(V)

ORGANIZATION

(kΩ)

TEMPERATURE

RANGE

(°C) PACKAGE

PKG.

DWG. #

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August 30, 2006

X9258

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PIN DESCRIPTIONS

Host Interface Pins

ERIAL CLOCK (SCL)

S

The SCL input is used to clock data into and out of the
X9258.

ERIAL DATA (SDA)

S

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

EVICE ADDRESS (A

D

0

- A3)

The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the address input in order to initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.

Potentiometer Pins

V

H/RH

V

L3/RL3

The V

(VH0/R

)

H/RH

- VH3/RH3), VL/RL (VL0/R

H0

L0

-

and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.

V

W/RW (VW0/RW0

- VW3/RW3)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages
for the DCP analog section.

PIN CONFIGURATION

SOIC/TSSOP

A3

SCL

V

L2/RL2

VH2/R

VW2/R

V–

V

SS

VW1/R

VH1/R

VL1/R

A1

SDA

H2

W2

W1

H1

L1

V

W3/RW3

VH3/R

V

L3/RL3

VL0/R

VH0/R

VW0/R

V

NC

A0

H3

V+

CC

H0

W0

A2

WP

1

2

3

4

5

6

X9258

7

L0

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PIN NAMES

Symbol Description

SCL Serial Clock

SDA Serial Data

A0-A3 Device Address

V

H0/RH0

V

L0/RL0

V

W0/RW0

- VH3/RH3,

- VL3/R

L3

- VW3/R

Potentiometer Pins
(terminal equivalent)

Potentiometers Pins

W3

(wiper equivalent)

WP

Hardware Write Protection

V+,V- Analog Supplies

V

CC

V

SS

System Supply Voltage

System Ground

NC No Connection (Allowed)

PRINCIPLES OF OPERATION

The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the DCP potentiometers.

Serial Interface—2-Wire

The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers

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X9258

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and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9258 will respond with a final acknowledge.

Array Description

The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that
are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (V

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

(V

W

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
8 bits of the WCR are decoded to select, and enable,
one of 256 switches.

). SDA state changes during

LOW

). The X9258 continuously

HIGH

and VL/RL inputs).

H/RH

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1). For the X9258 this is
fixed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

100

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9258 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9258 to respond with an acknowledge. The

- A3 inputs can be actively driven by CMOS input

A

0

signals or tied to V

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9258
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9258 is still busy with the write operation no ACK will
be returned. If the X9258 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

or VSS.

CC

1

A3 A2 A1 A0

Device Address

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X9258

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ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Yes

Further

Operation?

Yes

Issue

Instruction

Proceed

No

No

Issue STOP

Issue STOP

Proceed

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9258; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data
register). The sequence of operations is shown in
Figure 4.

Instruction Structure

The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.

Figure 2. Instruction Byte Format

Register

Select

I1I2I3 I0 R1 R0 P1 P0

Instructions

Wiper Counter

Register Select

The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.

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August 30, 2006

Figure 3. Two-Byte Instruction Sequence

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SCL

SDA

S

0101A3A2A1A0A
T
A
R
T

X9258

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

S

C

T

K

O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9258 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of

L/RL

the sequence and timing for this operation are shown
in Figures 5 and 6 respectively.

tuning capability to the host. For each SCL clock pulse

) while SDA is HIGH, the selected wiper will

(t

HIGH

move one resistor segment towards the V

terminal.

H

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter
Register

Write Wiper Counter
Register

0

1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P

1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register

pointed to by P

OperationI3I2I1I0R1R0P1P

- P

1

0

- P

1

0

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed

to by P

- P0 and R1 - R

1

0

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to

- P0 and R1 - R

by P

XFR Data Register to
Wiper Counter Register

1

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed

to by P

- P0 and R1 - R0 to its associated Wiper

1

0

Counter Register

XFR Wiper Counter
Register to Data
Register

Global XFR Data
Registers to Wiper
Counter Registers

Global XFR Wiper
Counter Registers
to Data Register

Increment/Decrement
Wiper Counter Register

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Reg-

ister pointed to by P
pointed to by R

- P0 to the Data Register

1

- R

1

0

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers

pointed to by R

- R0 of all four pots to their re-

1

spective Wiper Counter Registers

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter

Registers to their respective data Registers
pointed to by R

- R0 of all four pots

1

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch

pointed to by P

- P

1

0

Note: (1) 1/0 = data is one or zero

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August 30, 2006

X9258

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Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

0 1 0 1 A3 A2 A1 A0 A
T
A
R
T

Figure 5. Increment/Decrement Instruction Sequence

F

SCL

SDA

I3 I2 I1 I0 R1 R0 P1 P0 A
C
K

D7 D6 D5 D4 D3 D2 D1 D0
C
K

A

S

C

T

K

O
P

S

0 1 0 1 A3 A2 A1 A0 A
T
A
R
T

C
K

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

SCL

SDA

VW/R

W

Voltage Out

I3 I2 I1 I0 R0 P1 P0 A

R1

I
N
C
1

t

WRID

I
N
C

2

C
K

D

I

E

N

C

C

1

n

S

D

T

E

O

C

P

n

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August 30, 2006

Figure 7. Acknowledge Response from Receiver

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SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

1

X9258

89

START

Figure 8. Detailed Potentiometer Block Diagram Detailed Operation

Serial Data Path

From Interface

Circuitry

Register 0 Register 1

Register 2 Register 3

If WCR = 00[H] then VW/RW = VL/R

If WCR = FF[H] then VW/RW = VH/R

8 8

L

H

UP/DN

Modified SCL

Serial
BUS
Input

Parallel

BUS
Input

UP/DN

CLK

Wiper

Counter

Register

(WCR)

INC/DEC

Logic

Acknowledge

C

o
u

n
t
e
r

D

e

c

o
d

e

VH/R

VL/R

H

L

All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and four Data Registers. A
detailed discussion of the register organization and
array operation follows.

one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data

Wiper Counter Register

The X9258 contains four Wiper Counter Registers,
one for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and

Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.

serial load counter with its outputs decoded to select

8

VW/R

W

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X9258

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The WCR is a volatile register; that is, its contents are

REGISTER DESCRIPTIONS

lost when the X9258 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.

Data Registers

Data Registers, (8-Bit), Nonvolatile

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

NV NV NV NV NV NV NV NV

(MSB) (LSB)

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.

If the application does not require storage of multiple

Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).

– {D7~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the wiper counter
register on power-up.

settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Wiper Counter Register, (8-Bit), Volatile

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S

opcode

A

C

100100

K

Write Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S
A
C

101

K

opcode

Read Data Register (DR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

0

instruction

S

opcode

A
C

1011

K

WCR

addresses

WCR

addresses

000

DR and WCR

addresses

R1R0P1P

P1P

P1P

S
A
C
K

0

S
A
C
K

0

S
A
C
K

0

wiper position

(sent by slave on SDA)

W

W

W

P

P

P

7

6

5

Data Byte

(sent by master on SDA)

W

W

W

P

P

P

7

6

5

(sent by slave on SDA)

W

W

W

P

P

P

7

6

5

W

W

W

P

P

P

4

3

2

W

W

W

P

P

P

4

3

2

Data Byte

W

W

P

P

4

3

W

P

S

M

T

W

W

2

A

W

O

C

P

P

P

K

1

0

S

S

T

A

W

O

C

P

P

P

K

1

0

S

M

T

A

W

W

O

C

P

P

P

K

1

0

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August 30, 2006

Write Data Register (WR)

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X9258

device type

S

identifier

T
A

R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1100

DR and WCR

addresses

R1R0P1P

0

XFR Data Register (DR) to Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1101

DR and WCR

addresses

R1R0P1P

0

XFR Wiper Counter Register (WCR) to Data Register (DR)

d WCR

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcode

1110

DR an

addresses

R1R0P1P

0

Increment/Decrement Wiper Counter Register (WCR)

S

(sent by master on SDA)

A

W

C
K

S
A

O

C
K

S
A
C
K

Data Byte

W

W

W

P

P

P

P

7

6

5

4

S
T

P

S
T

HIGH-VOLTAGE

O

WRITE CYCLE

P

W

W

P

P

3

2

W

S

S

T

A

W

P

P

1

0

HIGH-VOLTAGE

O

C
K

WRITE CYCLE

P

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A1A

instruction

S

opcode

A
C

00100 0

K

0

WCR

addresses

P1P

S

(sent by master on SDA)

A
C

I/DI/

K

0

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

device type

S

identifier

T
A
R

0101

T

device

addresses

A3A2A

1A0

S
A

C

K

00

instruction

opcode

01

DR

addresses

R1R

0

00

S

S

T

A

O

C

P

K

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

device type

T

identifier
A
R

0101

T

device

addresses

A3A2A1A

S
A
C
K

0

instruction

opcodeDRaddresses

1000

R1R

0

00

S

S

T

A
C
K

HIGH-VOLTAGE

O

WRITE CYCLE

P

increment/decrement

....

D

I/DI/

S
T

O

P

D

10

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

SYMBOL TABLE Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM INPUTS OUTPUTS

Must be
steady

May change
from Low to
High

May change
from High to
Low

Don’t Care:
Changes
Allowed

N/A Center Line

Will be
steady

Will change
from Low to
High

Will change
from High to
Low

Changing:
State Not
Known

is High
Impedance

120

100

80

60

40

Resistance (K)

20

V

R

R

Min.
Resistance

0

20 40 60 80 100 120

0

Bus Capacitance (pF)

CC MAX

=

MIN

IOL MIN

t

=

MAX

C

BUS

Max.
Resistance

R

=1.8kΩ

11

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address input

with respect to V
Voltage on V+ (referenced to V
Voltage on V- (referenced to V

................................. -1V to +7V

SS

)........................ 10V

SS

)........................-10V

SS

(V+) - (V-) .............................................................. 12V

Any V
Any V

..............................................................V+

H/RH

.................................................................V-

L/RL

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Lead temperature (soldering, 10s) .................. +300°C

(10s) ............................................................±15mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max.

Commercial 0°C+70°C

Industrial -40°C+85°C

X9258-2.7 2.7V to 5.5V

ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)

Device Supply Voltage (VCC) Limits

X9258 5V ± 10%

Limits

Symbol Parameter

End to end resistance tolerance ±20 %

Power rating 50 mW 25°C, each pot

I

W

R

W

R

W

V+ Voltage on V+ Pin X9258 +4.5 +5.5 V

V- Voltage on V- Pin X9258 -5.5 -4.5 V

V

TERM

C

H/CL/CW

Wiper current ±7.5 mA Wiper current = ± 1mA

Wiper resistance 150 250 Ω IW = ± 1mA @ V+ = 3V, V- = -3V

Wiper resistance 40 100 Ω IW = ± 1mA @ V+ = 5V, V- = -5V

X9258-2.7 +2.7 +5.5

X9258 -2.7 -5.5 -2.7

Voltage on any VH/RH or VL/RL pin V- V+ V

Noise -120 dBV Ref: 1kHz

Resolution

Absolute linearity

Relative linearity

Temperature coefficient of R

Ratiometric Temperature Coefficient ±20 ppm/°C

Potentiometer Capacitance 10/10/25 pF See Circuit #3

(4)

(1)

(2)

TOTAL

0.6 %

±1 MI

±0.6 MI

±300 ppm/°C

(3)

(3)

V

w(n)(actual)

V

w(n + 1)

Test ConditionsMin. Typ. Max. Unit

- [V

- V

w(n) + MI

w(n)(expected)

]

12

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol Parameter

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

IH

V

IL

V

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

VCC supply current (Nonvol­atile Write)

VCC supply current (move
wiper, write, read)

1mAf

SCL

Other Inputs = V

100 µA f

SCL

Other Inputs = V

VCC current (standby) 5 µA SCL = SDA = VCC, Addr. = V

Input leakage current 10 µA VIN = VSS to V

Output leakage current 10 µA V

OUT

Input HIGH voltage VCC x 0.7 VCC + 0.1 V

Input LOW voltage -0.5 VCC x 0.3 V

Output LOW voltage 0.4 V IOL = 3mA

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.
(3) MI = RTOT/255 or (V
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

H/RH—VL/RL

)/255, single pot

Test ConditionsMin. Typ. Max. Unit

= 400kHz, SDA = Open,

SS

= 400kHz, SDA = Open,

SS

CC

= VSS to V

CC

SS

ENDURANCE AND DATA RETENTION

Parameter Min. Unit

Minimum endurance 100,000 Data changes per bit per register

Data retention 100 years

CAPACITANCE

Symbol Test Max. Unit Test Conditions

(5)

C

I/O

(5)

C

IN

Input/output capacitance (SDA) 8 pF V

I/O

= 0V

Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V

POWER-UP TIMING

Symbol Parameter Min. Max. Unit

(6)

t

PUR

t

PUW

t

R VCC

(6)

(7)

Power-up to initiation of read operation 1 ms

Power-up to initiation of write operation 5 ms

VCC Power up ramp 0.2 50 V/ms

POWER UP AND DOWN REQUIREMENT

The are no restrictions on the sequencing of the bias supplies V

, V+, and V- provided that all three supplies reach

CC

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

PUR

instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.

ramp rate spec is always in effect.

CC

and t

are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific

PUW

13

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

A.C. TEST CONDITIONS

I

nput pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing level V

CC

x 0.5

EQUIVALENT A.C. LOAD CIRCUIT

5V

1533Ω

SDA Output

100pF

2.7V

100pF

Test Circuit #3 SPICE Macro Model

Macro Model

R

R

H

10pF

TOTAL

C

H

C

W

25pF

R

W

C

L

10pF

AC TIMING (Over recommended operating condition)

Symbol Parameter Min. Max. Unit

f

SCL

t

CYC

t

HIGH

t

LOW

t

SU:STA

t

HD:STA

t

SU:STO

t

SU:DAT

t

HD:DAT

t

R

t

F

t

AA

t

DH

T

I

t

BUF

t

SU:WPA

t

HD:WPA

Clock frequency 400 kHz

Clock cycle time 2500 ns

Clock high time 600 ns

Clock low time 1300 ns

Start setup time 600 ns

Start hold time 600 ns

Stop setup time 600 ns

SDA data input setup time 100 ns

SDA data input hold time 30 ns

SCL and SDA rise time 300 ns

SCL and SDA fall time 300 ns

SCL low to SDA data output valid time 900 ns

SDA data output hold time 50 ns

Noise suppression time constant at SCL and SDA inputs 50 ns

Bus free rime (prior to any transmission) 1300 ns

WP, A0, A1, A2 and A3 setup time 0 ns

WP, A0, A1, A2 and A3 hold time 0 ns

R

L

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol Parameter Typ. Max. Unit

t

WR

High-voltage write cycle time (store instructions) 5 10 ms

14

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

DCP TIMING

Symbol Parameter Min. Max. Unit

t

WRPO

t

WRL

t

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

TIMING DIAGRAMS 2-WIRE INTERFACE

START and STOP Timing

Wiper response time after the third (last) power supply is stable 10 µs

Wiper response time after instruction issued (all load instructions) 10 µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs

edge of SCL.

(START) (STOP)

t

F

t

SU:STO

t

F

SCL

SDA

t

SU:STA

t

HD:STA

t

R

t

R

Input Timing

SCL

SDA

Output Timing

SCL

SDA

t

CYC

t

SU:DAT

t

HIGH

t

LOW

t

HD:DAT

t

AA

t

DH

t

BUF

15

FN8168.4

August 30, 2006

DCP Timing (for All Load Instructions)

www.BDTIC.com/Intersil

SCL

X9258

(STOP)

SDA

VWx

DCP Timing (for Increment/Decrement Instruction)

SCL

SDA

VWx

Wiper Register Address Inc/Dec Inc/Dec

Write Protect and Device Address Pins Timing

(START) (STOP)

SCL

SDA

LSB

t

WRL

...

(Any Instruction)

...

...

t

WRID

WP

A0, A1

A2, A3

16

t

SU:WPA

t

HD:WPA

FN8168.4

August 30, 2006

APPLICATIONS INFORMATION

www.BDTIC.com/Intersil

Basic Configurations of Electronic Potentiometers

V

R

VW/R

W

X9258

+V

R

I

THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER

Application Circuits

NONINVERTING AMPLIFIER VOLTAGE REGULATOR

V

S

VO = (1+R2/R1)V

OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS

V

S

100kΩ

10kΩ

-12V+12V

TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT

+

–

R

R

1

S

R

1

–

+

TL072

10kΩ10kΩ

V

O

2

R

2

V

O

IN

VO (REG) = 1.25V (1+R2/R1)+I

V

S

VUL = {R1/(R1+R2)} VO(max)

= {R1/(R1+R2)} VO(min)

V

LL

317

R

1

I

adj

R

2

–

+

}

}

R

R

2

1

adj R2

VO (REG)V

V

O

17

FN8168.4

August 30, 2006

Application Circuits (continued)

www.BDTIC.com/Intersil

ATTENUATOR FILTER

R

1

V

S

V

R

3

R

VO = G V

-1/2 ≤ G ≤ +1/2

INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT

R

R

1

S

}

VO = G V
G = - R2/R

4

All RS = 10kΩ

S

2

}

–

+

–

+

S

1

X9258

C

V

R

2

V

O

V

O

S

R

= 1 + R2/R

G

O

fc = 1/(2πRC)

C

1

V

S

Z

IN

+

–

R

R

1

1

R

2

+

–

R

1

R

3

V

O

2

18

ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R

FUNCTION GENERATOR

R

–

+

R

}

A

R

}

B

frequency ∝ R1, R2, C
amplitude ∝ R

2

R

1

, R

A

B

+ R3) >> R

1

C

–

+

2

FN8168.4

August 30, 2006

X9258

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

C

SEATING
PLANE

N LEADS

0.25 CAB

M

E

E1

B

0.10 C

N

1

TOP VIEW

e

b

SEE DETAIL “X”

(N/2)+1

SIDE VIEW

(N/2)

0.10 CABM

AD

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

H

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

A2

A

A1

END VIEW

DETAIL X

L1

GAUGE
PLANE

0.25

L

0° - 8°

19

FN8168.4

August 30, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

X9258

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6
N24 247

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8168.4

August 30, 2006